TWI801412B - Debug method - Google Patents

Abstract

A debug method is used for a CPU and a memory and includes: performing a POST by executing a code of a BIOS by the CPU; providing a driver so that multiple debug information can be output to the memory correspondingly by the code of the BIOS; after the memory is initialized, storing the debug information to the memory by the CPU in an initial stage of the POST; after the POST, reading the debug information stored in the memory by an application software. This disclosure uses the debug method of storing the debug information in the memory to greatly improve the execution efficiency of the POST and thereby to shorten the development time.

Description

Debugging method

The present invention relates to an error detection method, in particular to a basic input output system error detection method.

Referring to Fig. 1, the known mainframe computer 9 comprises a central processing unit (CPU) 91, a chip set (PCH) 92 electrically connected to the central processing unit, a basic input output system (BIOS) 93 electrically connected to the chip set , and a Universal Asynchronous Receiver/Transmitter (UART) 94 electrically connected to the chipset. The boot process of the BIOS 93 operates between a normal mode (Release Mode) and a debug mode (Debug Mode). When the BIOS 93 is operating in the debug mode, the chipset 92 sends the debug information of the BIOS 93 through the USB 94 via a device supporting the USB The standard connection port of the device 94, such as COM1, is sent to another computer host 8, so that a program developer can obtain the relevant debugging information of the debug mode through the computer host 8, and then modify the basic input output system accordingly 93 code.

Because the transmission speed of the standard connection port supporting the UART 94 is quite slow, when the BIOS 93 is in the normal mode and the error detection mode, the booting program is executing the power-on self-test (Power ON) Self Test; POST) time difference is quite large. For example, in the normal mode, the POST time is about 78 seconds, but in the debug mode, the POST time is about 264 seconds. Such a time difference shows that the debugging efficiency is not good, which leads to a longer development time of the BIOS, so it becomes a problem to be solved.

Therefore, the object of the present invention is to provide a debugging method that can improve efficiency.

Therefore, the error detection method of the present invention is applicable to a computer host including a central processing unit and a memory and includes steps (a)-(d).

In step (a), a BIOS code is executed by the CPU to execute a power-on self-test (POST).

In step (b), the program code of the BIOS provides a driver so that a plurality of debugging information can be correspondingly output to an address block of the memory.

In step (c), at the initial stage of the POST, after the memory is initialized, the CPU stores the error detection information in the address block of the memory.

In step (d), after the POST is finished, the central processing unit executes an application software to read the debug information stored in the address block of the memory.

In some implementation aspects, the central processing unit includes a cache memory, and the error detection method further includes a step (e), in the initial stage of the power-on self-test, after the cache memory is initialized, and Before the memory is initialized, the cache memory is virtualized as the address block of the memory, so that the central processing unit stores the debugging information in the cache memory.

In some implementation aspects, wherein, in step (c), after the memory is initialized, the central processing unit first stores the debugging information stored in the cache memory in the memory the address block.

In some other implementations, the error detection method is also applicable to a computer host, and further includes a step (f), in the process of the power-on self-test, through the computer host through an extended error detection port ( Extended Debug Port; XDP) is connected with the central processing unit, so that the BIOS stored in the address block of the memory can be read during the process of the BIOS executing the power-on self-test (POST). Wait for debugging information.

The effect of the present invention is: by storing the error detection information generated during the POST process into the memory, the execution time of the POST is greatly shortened compared with the prior art, thereby enabling development The error detection efficiency of the operator is greatly improved. In this way, not only can the development time be effectively shortened, but also because the execution time of the debug mode and the normal mode is almost the same, the developer does not need to develop two versions of the basic input output system for the debug mode and the normal mode respectively That is to say, the developer only needs to provide one version of the code, that is, the normal mode that already includes the function of the debug mode, thereby effectively improving the development efficiency of the basic input output system.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numerals.

Referring to Fig. 2 and Fig. 3, the error detection method of the present invention is applicable to a computer mainframe 5, and this computer mainframe 5 comprises a central processing unit (CPU) 1, a chipset (PCH) 3 electrically connected to the central processing unit 1, a It is electrically connected to a basic input output system (BIOS) 4 of the chipset 3 and a memory 2 electrically connected to the CPU 1 . The central processing unit 1 includes a cache memory (Cache) 11, and the memory memory 2 is the system memory of the computer host 5, such as DDR SDRAM. The debugging method includes steps S1-S6.

In step S1, when the host computer 5 is turned on, the CPU 1 executes the program code of the BIOS 4 through the chipset 3 to perform a power-on self-test (POST).

In step S2, the program code of the BIOS 4 provides a driver, so that a plurality of debugging information can be correspondingly output to an address block of the memory 2 .

In step S3, in the initial stage of the power-on self-test, after the cache memory 11 is initialized and before the memory 2 is initialized, the cache memory 11 is virtualized as a part of the memory 2 The address block enables the central processing unit 1 to store the debugging information in the cache memory 11 .

In step S4, in the initial stage of the POST, after the memory 2 is initialized, the central processing unit 1 first stores the debugging information stored in the cache memory 11 into the memory 2 The address block, and then store the subsequently generated error detection information in the address block of the memory 2 .

In step S5, after the POST is finished, the central processing unit 1 executes an application software to read the debug information stored in the address block of the memory 2 . More specifically, the CPU 1 executes the program code of the BIOS 4 to complete a boot process, so that the user can execute the application software through the CPU 1 . The application software is, for example, UltraEdit, as long as it has the function of reading out the data stored in the memory 2, such as displaying in the form of converted ASCII code.

In step S6, in the process of the power-on self-test, another host computer 7 is connected to the central processing unit 1 through an extended debug port (Extended Debug Port; XDP), so that the basic input and output system During the process of executing the power-on self-test (POST), the debug information stored in the address block of the memory 2 can be read. In other words, reading the debug information through the extended debug port has the property of real-time processing, which can meet the needs of developers for real-time updated debug information. For example, when the POST process is abnormal, causing the system to be stuck in the POST process and unable to complete the boot process, the host computer 7 can read the memory 2 in real time. Debugging information enables developers to further grasp the abnormal conditions of the code.

In this embodiment, the error detection information is, for example, which location or stage the program code is executed to, such as which device is detected, or any relevant register value in the program, etc., such as register PPI Notify: EfiPeiSecurity2 , Install PPI: EfiPeiLoadFile, StatusCodePei.Entry(FFF 39594), PcdPeim.Entry(FFF51320), Size: 90, Power Failure PWR_FLR bit: 1... etc. are not limited here. In addition, due to the development trend of hardware, the capacities of the cache memory 11 and the memory 2 are capable of completely storing the correspondingly generated error detection information in different execution stages.

In summary, after the cache memory 11 is initialized, the cache memory 11 stores the error detection information generated during POST, and after the memory 2 is initialized, the The debugging information in the cache memory 11 is copied to the memory 2, and the newly generated debugging information is stored in the memory 2, which not only makes the present invention not need to use the conventional low-speed The UART connection port is used to transmit the debugging information, so as to achieve the advantage of greatly shortening the execution time of the debugging mode. Furthermore, because the execution time of the debug mode and the normal mode is almost the same, the debug mode and the normal mode can be combined into one, so that developers only need to develop a version of the program code of the basic input output system 4, It can greatly improve the development efficiency, so the purpose of the present invention can indeed be achieved.

But the above-mentioned ones are only embodiments of the present invention, and should not limit the scope of the present invention. All simple equivalent changes and modifications made according to the patent scope of the present invention and the content of the patent specification are still within the scope of the present invention. Within the scope covered by the patent of the present invention.

1: central processing unit 11: cache memory 2: memory 3: chip set 4: basic input output system 5: mainframe computer 7: mainframe computer 8: mainframe computer 9: mainframe computer 91: central processing unit 92: chip set 93: Basic input and output system 94: Universal asynchronous transceiver transmitter S1~S6: steps

Other features and functions of the present invention will be clearly presented in the implementation manner with reference to the drawings, wherein: FIG. 1 is a block diagram illustrating a conventional computer host and another computer host; FIG. 2 is a block diagram , illustrating a host computer to which the error detection method of the present invention is applicable; and FIG. 3 is a flow chart illustrating an embodiment of the error detection method of the present invention.

S1~S6: steps

Claims (2)

A kind of error detection method is applicable to a computer mainframe including a central processing unit and a memory, the central processing unit includes a cache memory, and the error detection method includes the following steps: (a) executing by the central processing unit A BIOS code to perform a power-on self-test (POST) in a debug mode; (b) the BIOS code provides a driver so that a plurality of debug information can be correspondingly output to An address block of the memory; (e) in the initial stage of the power-on self-test, after the cache memory is initialized and before the memory is initialized, the cache memory is virtualized as the memory the address block, so that the central processing unit stores the debugging information in the cache memory; (c) in the initial stage of the boot self-test, after the memory is initialized, the central processing unit storing the debug information in the address block of the memory, and the central processing unit first stores the debug information stored in the cache memory in the address block of the memory and (d) after the power-on self-test is completed, execute an application software by the central processing unit to read the debug information stored in the address block of the memory. The error detection method as described in claim 1 is also applicable to a computer host, and the error detection method also includes a step (f), in the process of the self-test after power-on, the computer host uses an amplification to detect errors Port (Extended Debug Port; XDP) is connected with the central processing unit, so that the BIOS stored in the address block of the memory can be read during the process of executing the power-on self-test (POST) in the BIOS. Debug information.

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