TWI899869B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A manufacturing method of a semiconductor device includes forming a epitaxial layer over the substrate, forming a well region and a source region in the epitaxial layer, forming a first trench in the epitaxial layer, in which the first trench has a round corner protruding to the well region, forming a second trench in the epitaxial layer, in which the bottom of the second trench is higher than the bottom of the first trench and the width of the second trench is greater than the width of the first trench, and forming a gate structure in the first trench and the second trench.

Description

Semiconductor device and manufacturing method thereof

Some embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing the same.

To increase the channel density of metal oxide semiconductor field effect transistors (MOSFETs), MOSFETs may have a gate trench structure and a vertical channel. However, the corners of the gate trench structure may cause excessive electric field concentration, resulting in excessively high on-resistance.

Some embodiments of the present disclosure provide a method for fabricating a semiconductor device, comprising forming an epitaxial layer on a substrate, forming a well region and a source region in the epitaxial layer, forming a first trench in the epitaxial layer, wherein corners of the first trench have rounded corners protruding toward the well region, forming a second trench in the epitaxial layer, wherein a bottom of the second trench is higher than a bottom of the first trench and a width of the second trench is greater than a width of the first trench, and forming gate structures in the first trench and the second trench.

In some embodiments, forming a first trench in the epitaxial layer includes forming vertical sidewalls of the first trench in the epitaxial layer, with the bottom of the first trench exposing the drift region of the epitaxial layer, and performing a selective etching process to form rounded corners at corners of the first trench that protrude toward the well region, wherein the selective etching process etches the well region at a greater rate than the drift region.

In some embodiments, when the second trench is formed in the epitaxial layer, the bottom of the second trench exposes the well region.

In some embodiments, when the second trench is formed in the epitaxial layer, the bottom of the second trench is higher than the bottom of the source region.

In some embodiments, the gate structure includes a gate dielectric layer and a gate layer. The width of the gate dielectric layer in the second trench is greater than the width of the gate dielectric layer in the first trench. The gate layer is surrounded by the gate dielectric layer.

Some embodiments of the present disclosure provide a semiconductor device comprising a substrate, an epitaxial layer, a gate structure, a source electrode, and a drain electrode. The epitaxial layer is on the substrate. The gate structure is in the epitaxial layer, wherein the gate structure has, from bottom to top, a first portion, a second portion, and a third portion, the third portion having a width greater than the second portion, and the first portion having a width greater than the second portion. The source electrode is on the epitaxial layer. The drain electrode is below the substrate.

In some embodiments, the epitaxial layer includes a source region and a well region. The source region is adjacent to the third portion of the gate structure, wherein a bottom portion of the third portion of the gate structure is higher than a bottom portion of the source region. The well region is adjacent to the source region and the gate structure.

In some embodiments, the epitaxial layer includes a source region and a well region. The source region is adjacent to a third portion of the gate structure. The well region is adjacent to the source region and the gate structure, wherein the third portion of the gate structure contacts the well region and the source region.

In some embodiments, the gate structure includes a gate dielectric layer and a gate layer. The width of the gate dielectric layer in the third portion of the gate structure is greater than the width of the gate dielectric layer in the first portion of the gate structure. The gate layer is surrounded by the gate dielectric layer.

In some embodiments, the width of the gate dielectric layer of the first portion of the gate structure is greater than the width of the gate dielectric layer of the second portion of the gate structure.

110:Substrate

120: Epitaxial layer

122: Well Area

124: Source Region

126: Drift Zone

128: Sheltered Area

130: Source electrode

140: Drain electrode

150: Gate structure

150A: Part 1

150B: Part 2

150C: Part 3

152: Gate dielectric layer

154: Gate layer

C: Rounded corners

HM1, HM2: Hard mask layers

L: Length

M: Part

T1, T2: Grooves

W1, W2, W3, W4, W5, W6: Width

Figures 1 to 6 illustrate cross-sectional views of semiconductor devices formed in some embodiments of the present disclosure.

FIG7 shows a cross-sectional view of a semiconductor device according to other embodiments of the present disclosure.

Some embodiments of the present disclosure relate to a semiconductor device having a gate structure comprising, from bottom to top, a first portion, a second portion, and a third portion. The width of the third portion is greater than the width of the first portion, and the width of the first portion is greater than the width of the second portion. The first portion of the gate structure can be used to avoid electric field concentration at corners of the gate structure, thereby reducing the on-resistance of the semiconductor device.

Figures 1 through 6 illustrate cross-sectional views of semiconductor devices formed in some embodiments of the present disclosure. Referring to Figure 1, an epitaxial layer 120 is formed on a substrate 110. The substrate 110 and the epitaxial layer 120 can be made of a semiconductor material, such as silicon, silicon carbide, or the like, or a combination thereof. The substrate 110 and the epitaxial layer 120 can have a first conductivity type, with the substrate 110 being a heavily doped region and the epitaxial layer 120 being a lightly doped region. In some embodiments, the substrate 110 can be a heavily N-type doped substrate, and the epitaxial layer 120 can be a lightly N-type doped region. In some embodiments, the first conductivity type doped region can include an N-type dopant, such as nitrogen, arsenic, or phosphorus.

Next, a well region 122 and a source region 124 are formed in the epitaxial layer 120. In some embodiments, a thermal oxidation process may be first performed on the epitaxial layer 120 to form a silicon oxide layer on the surface of the epitaxial layer 120. Then, a first patterned photoresist layer may be formed on the epitaxial layer 120, and an ion implantation process may be performed to implant ions of the second conductive type into the epitaxial layer 120 to form the well region 122. The position of the well region 122 is defined by the first patterned photoresist layer. Then, the first patterned photoresist layer is removed, and a second patterned photoresist layer is formed on the epitaxial layer 120. An ion implantation process may be performed to implant ions of the first conductive type into the epitaxial layer 120 to form the source region 124. The location of the source region 124 is defined by the second patterned photoresist layer. After forming the source region 124 and the well region 122, a wet etching process can be used to remove the second patterned photoresist layer and the silicon oxide layer. In some embodiments, one side of the source region 124 may be substantially aligned with one side of the well region 122, and the source region 124 does not completely cover the well region 122. In other words, a portion of the top of the well region 122 remains exposed. Furthermore, the bottom of the well region 122 is lower than the bottom of the source region 124. The well region 122 may have the second conductivity type, and the source region 124 may have the first conductivity type. The well region 122 may be lightly or moderately doped, while the source region 124 may be heavily doped, i.e., the doping concentration of the source region 124 is greater than that of the well region 122. In some embodiments, the well region 122 may be a lightly or moderately doped P-type region, and the source region 124 may be a heavily doped N-type region. After forming the well region 122 and the source region 124, the remaining portion not occupied by the well region 122 and the source region 124 constitutes the drift region 126. The drift region 126 is a lightly doped region of the first conductivity type, such as a lightly doped N-type region. The doping concentration of the source region 124 is greater than the doping concentration of the drift region 126. In some embodiments, the first conductivity type doping region may include an N-type dopant, such as nitrogen, arsenic, or phosphorus. In some embodiments, the second conductivity type doping region may include a P-type dopant, such as boron, aluminum, or gallium.

Referring to FIG. 2 , a trench T1 is formed in the epitaxial layer 120. Specifically, a hard mask layer HM1 may be formed on the epitaxial layer 120, exposing a portion of the drift region 126 between adjacent source regions 124. In some embodiments, the hard mask layer HM1 may be formed of a dielectric material, such as silicon nitride, silicon oxide, or the like, or a combination thereof. Next, the trench T1 is formed in the epitaxial layer 120 using the hard mask layer HM1 as an etching mask. The trench T1 may be formed by a dry etching process. Trench T1 has vertical sidewalls (e.g., sidewalls substantially perpendicular to the bottom of substrate 110). The bottom of trench T1 exposes the drift region 126 of epitaxial layer 120 and is substantially flush with the well region 122. The sidewalls of trench T1 expose both the well region 122 and the source region 124. Therefore, both the drift region 126 and the well region 122 are exposed near the corners of trench T1. In some embodiments, the width W1 of trench T1 may be between 0.8 microns and 1.1 microns. In some embodiments, the depth of trench T1 may be between 2.2 microns and 2.5 microns.

Referring to Figure 3, a selective etching process is performed to form rounded corners C protruding toward the well region 122 at the corners of the trench T1. Specifically, the drift region 126 and the well region 122 are exposed at the same time near the corners of the trench T1, and the drift region 126 and the well region 122 have dopings of different conductivity types. When the same material is doped with different types of dopants, it is selective for a specific etching process. For example, a selective etching process may have a higher etching rate for a P-type doped region and a lower etching rate for an N-type doped region. Therefore, an appropriate etching process can be selected to form rounded corners C protruding toward the well region 122 at the corners of the trench T1. Specifically, the selective etching process etches the well region 122 (e.g., the P-type doped region) at a greater rate than the drift region 126 (e.g., the N-type doped region), thereby forming a rounded corner C in the well region 122. Consequently, a trench T1 is formed in the epitaxial layer 120. The trench T1 has vertical sidewalls and a rounded corner C protruding toward the well region. The width of the bottom of the trench T1 is greater than the width of the top of the trench T1. In some embodiments, the maximum width W2 of the trench T1 (the width of the portion of the trench T1 having the rounded corner C) may be between 1.2 microns and 1.5 microns. From another perspective, the outer edge of the fillet C extends beyond the sidewall of the trench T1, while the bottom of the fillet C is lower than the bottom surface of the trench T1.

Referring to FIG. 4 , after forming the rounded corners C of trench T1, a shielding region 128 is formed at the bottom of trench T1. Specifically, an ion implantation process can be performed using the hard mask layer HM1 (see FIG. 3 ) as a mask to implant ions of the second conductivity type into the epitaxial layer 120 to form shielding region 128. Shielding region 128 may have the second conductivity type and may be a heavily doped region. In some embodiments, shielding region 128 may be a heavily doped region, with a doping concentration greater than that of the well region 122 and greater than that of the drift region 126. After forming the shielding region 128, the hard mask layer HM1 is removed. In some embodiments, the second conductive type doped region may include a P-type dopant, such as boron, aluminum, or gallium.

Next, a hard mask layer HM2 may be formed on the epitaxial layer 120. The hard mask layer HM2 exposes the trench T1 and a portion of the source region 124. In some embodiments, the hard mask layer HM2 may be formed of a dielectric material, such as silicon nitride, silicon oxide, or the like, or a combination thereof. Then, using the hard mask layer HM2 as an etching mask, a trench T2 is formed in the epitaxial layer 120. The bottom of the trench T2 is higher than the bottom of the trench T1, and the width of the trench T2 is greater than the width of the trench T1. In some embodiments, the width W3 of the trench T2 may be between 1.6 microns and 1.8 microns. In some embodiments, the bottom of trench T2 is higher than the bottom of source region 124, so trench T2 does not expose well region 122. In some embodiments, after trench T2 is formed, the length L of the vertical sidewall of trench T1 is between 1.0 micrometers and 1.2 micrometers.

Referring to FIG. 5 , a wet etching process is used to remove the hard mask layer HM2. Next, a source electrode 130 is formed on the well region 122 and the source region 124, and a drain electrode 140 is formed under the substrate 110. In some embodiments, the source electrode 130 and the drain electrode 140 may be made of a conductive material, such as metal.

Referring to FIG. 6 , a gate structure 150 is formed in trenches T1 and T2. Gate structure 150 includes a gate dielectric layer 152 and a gate layer 154. Gate layer 154 is surrounded by gate dielectric layer 152. The width W4 of gate dielectric layer 152 in trench T2 is greater than the widths W5 and W6 of gate dielectric layer 152 in trench T1. Specifically, trenches T1 and T2 can first be filled with a dielectric material, and a trench can be formed in the dielectric material. Next, a gate material layer can be formed in the trench in the dielectric material. Thus, a gate dielectric layer 152 and a gate layer 154 of the gate structure 150 can be formed in trenches T1 and T2. The sidewalls of the gate layer 154 of the gate structure 150 are substantially perpendicular to the surface of the substrate 110. Therefore, the width W6 of the gate dielectric layer 152 surrounded by the rounded corner C of trench T1 is greater than the width W5 of the gate dielectric layer 152 surrounded by the vertical sidewalls of trench T1. In some embodiments, the gate dielectric layer 152 can be made of silicon oxide, silicon nitride, or the like. The gate layer 154 can be made of a semiconductor material or a conductive material, such as polysilicon or metal.

The resulting semiconductor device is shown in FIG6 . The semiconductor device includes a substrate 110 , an epitaxial layer 120 , a gate structure 150 , a source electrode 130 , and a drain electrode 140 . The epitaxial layer 120 is formed on the substrate 110 . The gate structure 150 is formed in trenches T1 and T2 of the epitaxial layer 120 . Therefore, the gate structure 150 has the same structure as described above for trenches T1 and T2 , and the relevant details will not be repeated. From another perspective, the gate structure 150 comprises, from bottom to top, a first portion 150A, a second portion 150B, and a third portion 150C. The width of the third portion 150C is greater than that of the second portion 150B, and the width of the first portion 150A is greater than that of the second portion 150B. The first portion 150A of the gate structure 150 has an outwardly protruding rounded corner C. In some embodiments, the width of the third portion 150C is also greater than that of the first portion 150A. The source electrode 130 is on the epitaxial layer 120. The drain electrode 140 is below the substrate 110. The epitaxial layer 120 includes a source region 124, a well region 122, a drift region 126, and a shielding region 128. The source region 124 is adjacent to a third portion 150C of the gate structure 150, wherein the bottom of the third portion 150C of the gate structure 150 is higher than the bottom of the source region 124. The first portion 150A of the gate structure 150 contacts the well region 122. The well region 122 is adjacent to the source region 124 and the gate structure 150. The shielding region 128 is at the bottom of the gate structure 150. In some embodiments, the source region 124 and the drift region 126 have a first conductivity type, and the well region 122 and the shielding region 128 have a second conductivity type that is different from the first conductivity type.

In some embodiments of the present disclosure, the gate structure 150 of the semiconductor device includes a gate dielectric layer 152 and a gate layer 154. The gate dielectric layer 154 is surrounded by the gate dielectric layer 152, wherein the width of the gate dielectric layer 152 in the third portion 150C of the gate structure 150 is greater than the width of the gate dielectric layer 152 in the first portion 150A of the gate structure 150, and the width of the gate dielectric layer 152 in the first portion 150A of the gate structure 150 is greater than the width of the gate dielectric layer 152 in the second portion 150B of the gate structure 150. The gate dielectric layer 152 of the first portion 150A of the gate structure 150 can be used to direct the current path away from the corners of the gate layer 154 of the gate structure 150. Therefore, the current path is not affected by the strong electric field in the corners of the gate layer 154 of the gate structure 150. This results in a lower on-resistance of the semiconductor device. The current path can flow from the drain electrode 140 through the drift region 126, the junction between the well region 122 and the gate structure 150, the junction between the well region 122 and the source region 124, and finally to the source electrode 130.

Furthermore, the semiconductor device of the present disclosure can reduce the capacitance between the source region 124 and the gate layer 154. Specifically, the capacitance between the source region 124 and the gate layer 154 can be determined by the gate dielectric layer 152 having vertical sidewalls therebetween (e.g., portion M in FIG. 6 , i.e., the portion of the second portion 150B of the gate structure 150 where the gate dielectric layer 152 overlaps with the source region 124). When the gate structure 150 includes the third portion 150C and the third portion 150C overlaps with the source region 124, the overlap between the second portion 150B of the gate structure 150 and the source region 124 decreases. Consequently, the overlap between the gate dielectric layer 152 of the second portion 150B of the gate structure 150 and the source region 124 also decreases. This reduces the capacitance between the source region 124 and the gate layer 154, thereby reducing the impact of this capacitance on the semiconductor device.

FIG7 illustrates a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. The semiconductor device in FIG7 is similar to the semiconductor device in FIG6 , except that during the formation of the semiconductor device in FIG7 , when trench T2 is formed in the epitaxial layer 120 (as in the step of FIG4 ), the bottom of trench T2 exposes the well region 122. Consequently, the third portion 150C of the gate structure 150 of the semiconductor device contacts the well region 122 and the source region 124. When the third portion 150C of the gate structure 150 contacts the well region 122, the area of the channel region of the semiconductor device (the interface between the well region 122 and the gate structure 150) can be increased. However, since this also causes the resistance of the semiconductor device to increase, the resistance of the semiconductor device can be controlled by controlling the proportion of the third portion 150C of the gate structure 150 that contacts the well region 122.

In summary, some embodiments of the present disclosure relate to a semiconductor device having a gate structure comprising, from bottom to top, a first portion, a second portion, and a third portion. The width of the third portion is greater than the width of the first portion, and the width of the first portion is greater than the width of the second portion. The first portion of the gate structure can be used to avoid electric field concentration at the corners of the gate structure, thereby reducing the on-resistance of the semiconductor device. The third portion of the gate structure can be used to reduce the overlap between the second portion of the gate structure and the source region, thereby reducing the capacitance between the source region and the gate layer, thereby reducing the impact of this capacitance on the semiconductor device.

The above description is only a partial implementation of this disclosure, not all implementations. Any equivalent modifications made to the technical solutions of this disclosure by persons of ordinary skill in the art after reading the specification of this disclosure are covered by the claims of this disclosure.

110: Substrate 120: Epitaxial layer 122: Well region 124: Source region 126: Drift region 128: Shielding region 130: Source electrode 140: Drain electrode 150: Gate structure 150A: First section 150B: Second section 150C: Third section 152: Gate dielectric layer 154: Gate layer C: Fillet M: Section W4, W5, W6: Widths

Claims (8)

A method for manufacturing a semiconductor device comprises: forming an epitaxial layer on a substrate; forming a well region and a source region in the epitaxial layer; forming a first trench in the epitaxial layer, wherein a corner of the first trench has a rounded corner protruding toward the well region; forming a second trench in the epitaxial layer, wherein the bottom of the second trench is higher than the bottom of the first trench and the width of the second trench is greater than the width of the first trench; and forming a gate structure in the first trench and the second trench, wherein the gate structure comprises: a gate dielectric layer, wherein the width of the gate dielectric layer in the second trench is greater than the width of the gate dielectric layer in the first trench; and a gate layer surrounded by the gate dielectric layer. The method of claim 1, wherein forming the first trench in the epitaxial layer comprises: forming a vertical sidewall of the first trench in the epitaxial layer, with the bottom of the first trench exposing a drift region of the epitaxial layer; and performing a selective etching process to form a rounded corner at the corner of the first trench protruding toward the well region, wherein the selective etching process etches the well region at a rate greater than the rate at which the drift region is etched. The method of claim 1, wherein when the second trench is formed in the epitaxial layer, a bottom of the second trench exposes the well region. The method of claim 1, wherein when the second trench is formed in the epitaxial layer, a bottom of the second trench is higher than a bottom of the source region. A semiconductor device comprises: a substrate; an epitaxial layer on the substrate; a gate structure in the epitaxial layer, wherein the gate structure has, from bottom to top, a first portion, a second portion, and a third portion, the third portion having a width greater than the second portion, and the first portion having a width greater than the second portion, wherein the gate structure comprises: a gate dielectric layer, wherein the gate dielectric layer in the third portion of the gate structure has a width greater than the gate dielectric layer in the first portion of the gate structure; and a gate layer surrounded by the gate dielectric layer; A source electrode on the epitaxial layer; and a drain electrode under the substrate. The semiconductor device of claim 5, wherein the epitaxial layer comprises: a source region adjacent to the third portion of the gate structure, wherein a bottom portion of the third portion of the gate structure is higher than a bottom portion of the source region; and a well region adjacent to the source region and the gate structure. The semiconductor device of claim 5, wherein the epitaxial layer comprises: a source region adjacent to the third portion of the gate structure; and a well region adjacent to the source region and the gate structure, wherein the third portion of the gate structure contacts the well region and the source region. The semiconductor device of claim 5, wherein a width of the gate dielectric layer in the first portion of the gate structure is greater than a width of the gate dielectric layer in the second portion of the gate structure.