TWI899724B - Authentication device and method - Google Patents

Abstract

An authentication device is provided in the invention. The authentication device may include a central processing unit (CPU), a volatile memory, a non-volatile memory, a first direct memory access (DMA) circuit and an authentication circuit. When the authentication device is rebooted and reset, the CPU may enter a waiting mode. The non-volatile memory may store a plurality of commands and a non-authentication firmware data. The first DMA circuit may read a first command from the non-volatile memory, and move the non-authentication firmware data from the non-volatile memory to the volatile memory according to the first command. After the authentication circuit receives a trigger signal from the first DMA circuit, the authentication circuit may be configured to authenticate the non-authentication firmware data stored in the volatile memory.

Description

Verification device and method

Embodiments of the present invention generally relate to an authentication technology, and more particularly to an authentication technology for performing firmware data authentication in a volatile memory.

In systems with non-volatile memory, firmware is typically stored in non-volatile memory. According to the concept and implementation of hardware root of trust (RoT) in security, firmware stored in non-volatile memory must be successfully authenticated before it can be executed by the central processing unit (CPU).

However, due to the demand for fast booting, the booting speed will be affected by the limited access speed of non-volatile memory itself and the low efficiency of the central processing unit in executing the verification program and verifying the firmware.

Therefore, how to verify the firmware more efficiently and quickly when the device boots up will be a topic worth studying.

In view of the above-mentioned problems of the prior art, embodiments of the present invention provide a verification device and method.

According to one embodiment of the present invention, a verification device is provided. The verification device includes a central processing unit, a volatile memory, a non-volatile memory, a first direct memory access circuit, and a verification circuit. The central processing unit can enter a standby mode after the verification device is powered on and reset. The non-volatile memory can store multiple instructions and unverified firmware data. The first direct memory access circuit can read a first instruction from the non-volatile memory and, based on the first instruction, move the unverified firmware data from the non-volatile memory to the volatile memory. After receiving a trigger signal from the first direct memory access circuit, the verification circuit can be used to verify the unverified firmware data stored in the volatile memory.

In some embodiments, the first instruction may include a source location, a target location, and a data size corresponding to the unverified firmware data.

In some embodiments, the verification circuit may include a second direct memory access circuit. Furthermore, the second direct memory access circuit may read a second instruction from the non-volatile memory and, based on the second instruction, read the unverified firmware data from the volatile memory.

In some embodiments, the second direct memory access circuit can further obtain a verification key based on the second instruction. In addition, the verification circuit can select a verification method based on the second instruction and verify the unverified firmware data in the volatile memory based on the verification method and the verification key.

In some embodiments, after the verification circuit successfully verifies the unverified firmware data, the verification circuit may send a release signal to the central processing unit. After the central processing unit receives the release signal, the central processing unit may execute the verified unverified firmware data stored in the volatile memory.

In some embodiments, the second instruction may include a target location corresponding to the unverified firmware data, a data size, a key location, and a verification method to be selected.

According to one embodiment of the present invention, a verification method is provided. The verification method can be applied to a verification device. The verification method can include the following steps. After the verification device is powered on and reset, a central processing unit of the verification device enters a standby mode; a first instruction is read from a non-volatile memory of the verification device via a first direct memory access circuit of the verification device; unverified firmware data is moved from the non-volatile memory to a volatile memory of the verification device via the first direct memory access circuit in accordance with the first instruction; and a verification circuit verifies the unverified firmware data stored in the volatile memory after receiving a trigger signal from the first direct memory access circuit.

Regarding other additional features and advantages of the present invention, those skilled in the art may make minor modifications and improvements based on the verification device and method disclosed in the implementation method of this case without departing from the spirit and scope of the present invention.

This section describes the preferred methods for implementing the present invention. Its purpose is to illustrate the spirit of the present invention and is not intended to limit the scope of protection of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

FIG1 is a block diagram illustrating an authentication device 100 according to an embodiment of the present invention. As shown in FIG1 , the authentication device 100 may include a central processing unit (CPU) 110, a first direct memory access (DMA) circuit 120, an authentication circuit 130, a volatile memory 140, a non-volatile memory 150, and a key storage circuit 160. Note that the block diagram shown in FIG1 is merely for the purpose of illustrating the embodiment of the present invention and is not limited to FIG1 . The authentication device 100 may also include other components.

According to an embodiment of the present invention, the verification device 100 can be applied to a microcontroller unit (MCU), a microprocessor unit (MPU), or a device having a similar device architecture to the verification device 100.

According to an embodiment of the present invention, the central processing unit 110 can be used to execute the verified firmware data. In addition, when the verification device 100 is turned on and reset, the central processing unit 110 can first enter a waiting mode.

According to one embodiment of the present invention, the first direct memory access circuit 120 can be used to move unverified firmware data (e.g., firmware code) from the non-volatile memory 150 to the volatile memory 140 based on an instruction (e.g., a first instruction) obtained from the non-volatile memory 150. In addition, the first direct memory access circuit 120 can trigger the verification circuit 130 to perform a verification operation.

According to one embodiment of the present invention, the verification circuit 130 may include a second direct memory access circuit 131. The second direct memory access circuit 131 may read the unverified firmware data stored in the volatile memory 140 based on an instruction (e.g., a second instruction) received from the non-volatile memory 150, and obtain the key stored in the key storage circuit 160. The verification circuit 130 may verify the unverified firmware data based on the instruction received by the second direct memory access circuit 131.

According to one embodiment of the present invention, the volatile memory 140 may be a random access memory (RAM), but the present invention is not limited thereto. The volatile memory 140 may be used to store unverified firmware data from the non-volatile memory 150.

According to one embodiment of the present invention, the non-volatile memory 150 may be a flash memory or a read-only memory (ROM), but the present invention is not limited thereto. The non-volatile memory 150 may be used to store a plurality of instructions and unverified firmware data.

According to one embodiment of the present invention, the key storage circuit 160 can be used to store the key required by the verification circuit 130 to perform verification operations.

According to one embodiment of the present invention, after the authentication device 100 is powered on and reset, the central processing unit 110 enters a standby mode. In other words, in the present invention, the central processing unit 110 does not need to perform operations related to firmware data verification. Once the firmware data is verified, the central processing unit 110 can execute the firmware data.

Furthermore, after the authentication device 100 is powered on and reset, the first direct memory access circuit 120 can retrieve a first instruction from the non-volatile memory 150 and, based on the first instruction, move the unverified firmware data from the non-volatile memory 150 to the volatile memory 140. The first instruction can be pre-stored in a predetermined space in the non-volatile memory 150. In other words, after the authentication device 100 is powered on and reset, the first direct memory access circuit 120 can retrieve the first instruction from this predetermined space. According to one embodiment of the present invention, the first instruction may include a source location corresponding to the unverified firmware data (i.e., the location where the non-volatile memory 150 stores the unverified firmware data), a target location (i.e., the location where the volatile memory 140 stores the unverified firmware data), and a data size (i.e., the size of the unverified firmware data), but the present invention is not limited thereto.

In addition, after the first direct memory access circuit 120 moves the unverified firmware data from the non-volatile memory 150 to the volatile memory 140, the first direct memory access circuit 120 may send a trigger signal to the verification circuit 130 to trigger the verification circuit 130 to start the verification operation.

After verification circuit 130 receives a trigger signal from first direct memory access circuit 120, second direct memory access circuit 131 retrieves a second instruction from non-volatile memory 150 and, based on the second instruction, reads the unverified firmware data stored in volatile memory 140. The second instruction may be pre-stored in a predetermined space in non-volatile memory 150. In other words, when verification circuit 130 receives a trigger signal, second direct memory access circuit 131 retrieves the second instruction from this predetermined space. According to one embodiment of the present invention, the second instruction may include a target location corresponding to the unverified firmware data (i.e., the location where the volatile memory 140 stores the unverified firmware data), a data size (i.e., the size of the unverified firmware data), a key location (i.e., the location where the key is stored in the key storage circuit 160), and a verification method to be selected (i.e., the verification method to be used to verify the unverified firmware data), but the present invention is not limited to this. The second direct memory access circuit 131 may also obtain the key to be used for the verification operation from the key storage circuit 160 based on the second instruction.

After the second direct memory access circuit 131 reads the unverified firmware data and obtains the key, the verification circuit 130 can verify the unverified firmware data stored in the volatile memory 140 according to the verification method indicated by the second instruction (for example, Elliptic Curve Digital Signature Algorithm (ECDSA), but the present invention is not limited to this) and the key.

After the verification circuit 130 successfully verifies the unverified firmware data stored in the volatile memory 140, the verification circuit 130 may send a release signal to the central processing unit 110. After the central processing unit 110 receives the release signal, the central processing unit 110 may leave the standby mode and start executing the verified firmware data stored in the volatile memory 110.

FIG2 is a flow chart of an authentication method according to an embodiment of the present invention. The authentication method may be applied to the authentication device 100. As shown in FIG2, in step S210, after the authentication device 100 is powered on and reset, a central processing unit of the authentication device 100 may enter a waiting mode.

In step S220 , a first direct memory access circuit of the verification device 100 may read a first instruction from a non-volatile memory of the verification device 100 .

In step S230, the first direct memory access circuit of the verification device 100 may move an unverified firmware data from the non-volatile memory of the verification device 100 to a volatile memory of the verification device 100 according to the first instruction.

In step S240, after receiving a trigger signal from the first direct memory access circuit, a verification circuit of the verification device 100 verifies the unverified firmware data stored in the volatile memory.

According to an embodiment of the present invention, in the verification method, the first instruction may include a source location, a target location, and a data size corresponding to the unverified firmware data.

According to one embodiment of the present invention, in a verification method, a second direct memory access circuit of the verification circuit of the verification device 100 may read a second instruction from the non-volatile memory of the verification device 100. Then, the second direct memory access circuit of the verification circuit of the verification device 100 may read unverified firmware data from the volatile memory of the verification device 100 according to the second instruction.

According to one embodiment of the present invention, during the verification method, the second direct memory access circuit of the verification circuit of the verification device 100 can obtain a verification key according to a second instruction. The verification circuit of the verification device 100 can then select a verification method according to the second instruction and verify unverified firmware data stored in the volatile memory of the verification device 100 based on the verification method and the verification key.

According to one embodiment of the present invention, in the verification method, after the verification circuit of the verification device 100 successfully verifies the unverified firmware data, the verification circuit of the verification device 100 transmits a release signal to the central processing unit of the verification device 100. Then, upon receiving the release signal, the central processing unit of the verification device 100 may execute the verified unverified firmware data stored in the volatile memory.

According to an embodiment of the present invention, in the verification method, the second instruction may include a target location corresponding to the unverified firmware data, a data size, a key location, and a verification method to be selected.

According to the verification method proposed in the embodiments of the present invention, when the verification device boots up, unverified firmware data can be verified in the verification device's volatile memory. Furthermore, according to the verification method proposed in the embodiments of the present invention, the verification device no longer needs to rely on a central processing unit to perform firmware data verification operations. Therefore, when the verification device boots up, the verification method proposed in the embodiments of the present invention can perform firmware data verification operations more efficiently and quickly, achieving the requirement of fast boot-up.

Serial numbers in this specification and in the scope of the patent application, such as "first", "second", etc., are for convenience of explanation only and have no sequential relationship with each other.

The methods and algorithm steps disclosed in the specification of the present invention can be directly applied to hardware and software modules or a combination of the two by executing a processor. A software module (including execution instructions and related data) and other data can be stored in a data memory such as random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), register, hard drive, portable hard drive, compact disc read-only memory (CD-ROM), DVD, or any other computer-readable storage medium format known in the art. A storage medium can be coupled to a machine device, for example, such as a computer/processor (for ease of explanation, referred to as a processor in this specification), through which the processor can read information (such as program code) and write information to the storage medium. A storage medium can integrate a processor. An application specific integrated circuit (ASIC) includes a processor and a storage medium. A user device includes an application specific integrated circuit. In other words, the processor and storage medium are included in the user device in a manner that is not directly connected to the user device. In addition, in some embodiments, any product suitable for a computer program includes a readable storage medium, wherein the readable storage medium includes program code related to one or more disclosed embodiments. In some embodiments, a product of a computer program may include packaging materials.

The above paragraphs describe various aspects. Obviously, the teachings herein can be implemented in a variety of ways, and any specific architecture or functionality disclosed in the examples is merely representative. Based on the teachings herein, anyone skilled in the art will understand that each aspect disclosed herein can be implemented independently, or two or more aspects can be combined.

Although the present disclosure has been disclosed above with reference to the embodiments, they are not intended to limit the present disclosure. Anyone skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the invention shall be determined by the scope of the attached patent application.

100: Authentication device 110: Central processing unit 120: First DMA circuit 130: Authentication circuit 131: Second DMA circuit 140: Volatile memory 150: Non-volatile memory 160: Key storage circuit S210-S240: Steps

Figure 1 is a block diagram of an authentication device 100 according to an embodiment of the present invention. Figure 2 is a flow chart of an authentication method according to an embodiment of the present invention.

100: Authentication device 110: Central processing unit 120: First DMA circuit 130: Authentication circuit 131: Second DMA circuit 140: Volatile memory 150: Non-volatile memory 160: Key storage circuit

Claims (10)

A verification device includes: a central processing unit (CPU) that enters a standby mode after the verification device is reset upon power-up; a volatile memory; a non-volatile memory that stores a plurality of instructions and unverified firmware data; a first direct memory access circuit that reads a first instruction from the non-volatile memory and, based on the first instruction, moves the unverified firmware data from the non-volatile memory to the volatile memory; and a verification circuit that, upon receiving a trigger signal from the first direct memory access circuit, verifies the unverified firmware data stored in the volatile memory. The verification device of claim 1, wherein the first instruction includes a source location, a target location, and a data size corresponding to the unverified firmware data. The verification device of claim 1, wherein the verification circuit includes a second direct memory access circuit, and wherein the second direct memory access circuit reads a second instruction from the non-volatile memory, and reads the unverified firmware data from the volatile memory according to the second instruction. The verification device of claim 3, wherein the second direct memory access circuit further obtains a verification key according to the second instruction, and wherein the verification circuit selects a verification method according to the second instruction, and verifies the unverified firmware data according to the verification method and the verification key. The verification device of claim 4, wherein after the verification circuit successfully verifies the unverified firmware data, the verification circuit transmits a release signal to the central processing unit, and after the central processing unit receives the release signal, the central processing unit executes the verified unverified firmware data stored in the volatile memory. The verification device of claim 3, wherein the second instruction includes a target location corresponding to the unverified firmware data, a data size, a key location, and a verification method to be selected. A verification method, applicable to a verification device, comprises: After the verification device is powered on and reset, a central processing unit of the verification device enters a standby mode; Reading a first instruction from a non-volatile memory of the verification device via a first direct memory access circuit of the verification device; Moving unverified firmware data from the non-volatile memory to a volatile memory of the verification device via the first direct memory access circuit in accordance with the first instruction; and Verifying the unverified firmware data stored in the volatile memory via a verification circuit upon receiving a trigger signal from the first direct memory access circuit. The verification method of claim 7 further comprises: Reading a second instruction from the non-volatile memory via a second direct memory access circuit of the verification circuit; and Reading the unverified firmware data from the volatile memory via the second direct memory access circuit in accordance with the second instruction. The verification method of claim 8 further comprises: obtaining a verification key via the second direct memory access circuit in accordance with the second instruction; and selecting a verification method via the verification circuit in accordance with the second instruction, and verifying the unverified firmware data based on the verification method and the verification key. The verification method of claim 9 further comprises: When the verification circuit successfully verifies the unverified firmware data, transmitting a release signal to the central processing unit via the verification circuit; and After the central processing unit receives the release signal, executing the verified unverified firmware data stored in the volatile memory via the central processing unit.