TWI899019B - Method of manufacturing semiconductor structure and fuse structure - Google Patents

Abstract

A method of manufacturing a semiconductor structure includes the following operations. A substrate is provided. The substrate defines the fuse region and the active region. A doping process is performed on the substrate of the fuse region to form a doping area. A stacked layer including a gate oxide layer, a polysilicon layer, a metal layer, and a protective layer is formed on the substrate of the fuse region and the active region. The protective layer of the fuse region and the active region is patterned, in which a width of the protective layer of the fuse region after patterning is the same as a width of the doping area. A source/drain region is formed in the substrate of the active region.

Description

Semiconductor structure manufacturing method and fuse structure

The present disclosure relates to a method for manufacturing a semiconductor structure and a fuse structure.

As semiconductor manufacturing processes become increasingly miniaturized and complex, semiconductor components become more susceptible to various defects and impurities. The failure of a single metal connection, diode, or transistor often constitutes a defect in the entire chip. To address this issue, current technology incorporates fusible links, or fuses, into integrated circuits to ensure their availability.

Generally speaking, fuses are redundant circuits in integrated circuits. Once a part of the circuit is found to be defective, these connecting lines can be used to repair or replace the defective circuits. In addition, current fuse designs can also provide programming elements, so that various customers can program circuits according to different functional designs. In terms of operation, fuses are roughly divided into two types: thermal fuses and electric fuses (eFuse). The so-called thermal fuse is cut by a laser zip step; as for the electric fuse, it uses the principle of electro-migration to open the fuse circuit to achieve the effect of repair or programming function. In addition, the electrical fuse in the semiconductor device may be, for example, a poly efuse, a MOS capacitor anti-fuse, a diffusion fuse, a contact efuse, a contact anti-fuse, etc.

Currently, the demand for low-power drive devices is increasing, leading to an increase in the thickness of the gate oxide used in low-power devices. This results in a decrease in the fuse's breaking rate at the same fuse voltage. Therefore, improving the current fuse structure to produce a fuse that optimizes the fuse's breaking voltage and improves the fuse's breaking rate is a key issue.

According to various embodiments of the present invention, a method for manufacturing a semiconductor structure is provided, comprising the following operations: providing a substrate defining a fuse region and an active region; performing a doping process on the substrate of the fuse region to form a doped region; forming a stack of a gate oxide layer, a polysilicon layer, a metal layer, and a protective layer on the substrate of the fuse region and the active region; patterning the protective layer of the fuse region and the active region, wherein the patterned protective layer of the fuse region has the same width as the doped region; and forming a source/drain region in the substrate of the active region.

According to certain embodiments of the present invention, the doping process includes doping arsenic ions and nitrogen ions, wherein the energy of the doping arsenic ions is 30,000 electron volts, and the energy of the doping nitrogen ions is 30,000 electron volts.

According to certain embodiments of the present invention, the doping concentration of arsenic ions is 1.2×10 ¹⁵ to 1×10 ¹⁶ ions per square centimeter, and the doping concentration of nitrogen ions is 1×10 ¹⁴ to 1×10 ¹⁵ ions per square centimeter.

According to certain embodiments of the present invention, the method for fabricating a semiconductor structure further includes patterning the gate oxide layer, polysilicon layer, and metal layer of the fuse region and the active region using the patterned protective layer as an etching mask.

According to some embodiments of the present invention, the width of the patterned gate oxide layer is substantially the same as the width of the doped region.

According to certain embodiments of the present invention, the thickness of the gate oxide layer in the fuse region is substantially the same as the thickness of the gate oxide layer in the active region.

According to various embodiments of the present invention, a fuse structure is provided, comprising a substrate, a gate oxide layer, a polysilicon layer, a metal layer, and a protective layer. The substrate includes a doped region. The gate oxide layer is disposed on the doped region. The polysilicon layer is disposed on the gate oxide layer. The metal layer is disposed on the polysilicon layer. The protective layer is disposed on the metal layer, wherein the width of the protective layer is substantially the same as the width of the doped region.

According to certain embodiments of the present invention, the doped region comprises arsenic ions and nitrogen ions.

According to certain embodiments of the present invention, the concentration of arsenic ions is 1.2×10 ¹⁵ to 1×10 ¹⁶ ions per square centimeter.

According to certain embodiments of the present invention, a concentration of nitrogen ions is 1×10 ¹⁴ to 1×10 ¹⁵ ions per square centimeter.

This disclosure relates to a method for fabricating a semiconductor structure and a fuse structure. By doping a substrate in the fuse region with arsenic and nitrogen ions, the thickness of a gate oxide layer subsequently formed on the substrate can be controlled, thereby improving the fuse's blow rate.

The following diagrams illustrate several embodiments of the present invention. For the sake of clarity, many practical details are included in the following description. However, it should be understood that these practical details should not be construed as limiting the present invention. In other words, these practical details are not essential to some embodiments of the present invention. Furthermore, for clarity, the size or thickness of components may be exaggerated and not drawn to their original scale. Furthermore, to simplify the diagrams, some commonly used structures and components are depicted in simplified schematic form.

The following disclosure provides many different embodiments or examples to implement different features of each embodiment. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these examples are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the subsequent description may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. In addition, the disclosure may repeat element symbols and/or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "above," and "on" are used herein to facilitate descriptions of the relative relationships of one element or feature to another, as depicted in the figures. The true meaning of these spatially relative terms encompasses alternative orientations. For example, when a figure is rotated 180 degrees, the relationship between one element and another might change from "below" or "beneath" to "above" or "on." Furthermore, spatially relative terms used herein should be interpreted similarly.

FIG1 is a flow chart illustrating a method for fabricating a semiconductor structure according to certain embodiments of the present invention. As shown in FIG1 , method 10 includes operations 102, 104, 106, and 108. The method for fabricating a semiconductor structure will be further described below based on one or more embodiments.

FIG2 is a cross-sectional view of various stages of a process for manufacturing a semiconductor structure according to certain embodiments of the present invention. Please refer to FIG1 and FIG2 simultaneously. In operation 102 of method 10, a substrate 20 is provided. In some embodiments, the substrate 20 may be, for example, a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate. Specifically, the substrate 20 defines a fuse region 210 and an active region 220. The active region 220 can be used to form active elements such as N-type metal oxide semiconductor (NMOS) transistors, P-type metal oxide semiconductor (PMOS) transistors, and/or complementary metal oxide semiconductor (CMOS) transistors. For example, the active region 220 of the present disclosure can simultaneously fabricate an NMOS transistor and a PMOS transistor. The fuse region 210 can be used to form an electrical fuse element. In some embodiments, multiple isolation structures 221 can be fabricated in the substrate 20 of the fuse region 210 and the active region 220 using processes such as shallow trench isolation (STI) or local oxidation (LOCOS) to surround and isolate the active elements of the active region 220. For example, the isolation structure 221 can be a field oxide layer or a shallow trench isolation structure.

FIG3 is a cross-sectional view illustrating various stages of a process for manufacturing a semiconductor structure according to certain embodiments of the present invention. Please refer to FIG1 and FIG3 simultaneously. In operation 104 of method 10, a doping process 240 is performed on the substrate 20 in the fuse region 210. In some embodiments, the doping process 240 includes doping with arsenic ions 241 and nitrogen ions 243. The substrate 20 may be first covered with a mask (not shown) to expose the region of the substrate 20 to be doped in the fuse region 210, and then arsenic and nitrogen may be implanted in the designated region by the doping process 240 such as ion implantation.

It is understood that by doping the substrate 20 in the fuse region 210 with arsenic ions 241, the fuse element can achieve a lower resistance value during melting and reading through electrons on the substrate surface. However, this phenomenon causes the thickness of the subsequently deposited gate oxide layer to increase, resulting in a lower melting rate of the fuse element at the same melting voltage. Therefore, the thickness of the subsequent gate oxide layer is adjusted by adjusting the amount of nitrogen ion doping 243.

In some embodiments, the doping concentration of the arsenic ions 241 is 1.2×10 ¹⁵ to 1×10 ¹⁶ ions per square centimeter, for example, 1.4×10 ¹⁵ ions per square centimeter, 1.6×10 ¹⁵ ions per square centimeter, 1.8×10 ¹⁵ ions per square centimeter, 2.0×10 ¹⁵ ions per square centimeter, 2.5×10 ¹⁵ ions per square centimeter, 3.0×10 15 ions per square centimeter, 3.35×10 ¹⁵ ions per square centimeter, 3.5×10 ¹⁵ ions per square centimeter, 4.0×10 ¹⁵ ions per square centimeter, 4.5×10 ¹⁵ ions per square centimeter, or 5. ions per square centimeter, ^5.0 ×10 ¹⁵ ions per square centimeter, 5.5×10 ¹⁵ ions per square centimeter, 6.0×10 ¹⁵ ions per square centimeter, 6.5×10 ¹⁵ ions per square centimeter, 7.0×10 ¹⁵ ions per square centimeter, 7.5×10 ¹⁵ ions per square centimeter, 8.0×10 ¹⁵ ions per square centimeter, 8.5×10 ¹⁵ ions per square centimeter, 9.0×10 ¹⁵ ions per square centimeter, or 9.5×10 ¹⁵ ions per square centimeter. In some embodiments, the energy of the dopant arsenic ions 241 may be, for example, 30,000 electron volts (eV).

In some embodiments, the doping concentration of nitrogen ions 243 is 1×10 ¹⁴ to 1×10 ¹⁵ ions per square centimeter, for example, 1.5×10 ¹⁵ ions per square centimeter, 2.0×10 ¹⁵ ions per square centimeter, 2.5×10 15 ions per square centimeter, 3.0×10 ¹⁵ ions per square centimeter, 3.5×10 ¹⁵ ions per square centimeter, 4.0×10 ¹⁵ ions per square centimeter, 4.5×10 ¹⁵ ions per square centimeter, 5.0×10 ¹⁵ ions per square centimeter, 5.5×10 15 ions per square centimeter, 6.0×10 ¹⁵ ions per square centimeter, or 7.5×10 ¹⁵ ions per square centimeter. ions per square centimeter, ^6.5 ×10 ¹⁵ ions per square centimeter, 7.0×10 ¹⁵ ions per square centimeter, 7.5×10 ¹⁵ ions per square centimeter, 8.0×10 ¹⁵ ions per square centimeter, 8.5×10 ¹⁵ ions per square centimeter, 9.0×10 ¹⁵ ions per square centimeter, or 9.5×10 ¹⁵ ions per square centimeter. In some embodiments, the energy of the dopant nitrogen ions 243 may be, for example, 3,000 electron volts (eV) or 30,000 eV.

FIG4 is a cross-sectional view illustrating various stages of a semiconductor structure fabrication process according to certain embodiments of the present invention. Please refer to FIG1 and FIG4 in conjunction. In operation 104 of method 10, a stack of gate oxide layer 310, polysilicon layer 320, metal layer 330, and protective layer 340 is formed on substrate 20 in fuse region 210 and active region 220. In some embodiments, the gate oxide layer 310 can be formed on the substrate 20 by, for example, thermal oxidation, chemical oxidation, chemical vapor deposition (CVD), including low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable processes. In some embodiments, the gate oxide layer 310 can include oxide, silicon dioxide, high-k oxide, or the like.

Because a portion of the substrate 20 in the fuse region 210 is doped with arsenic and nitrogen, the gate oxide layer 310 formed on the surface of the substrate 20 has a substantially flat surface. In some embodiments, the thickness of the gate oxide layer 310 in the fuse region 210 is substantially the same as the thickness of the gate oxide layer 310 in the active region 220.

FIG5 is a cross-sectional view of a certain stage of the manufacturing process of a semiconductor structure that has not been nitrogen-doped according to one embodiment of the present invention. As shown in FIG5, when the portion of substrate 20 in fuse region 210 contains only arsenic doping without nitrogen doping, the gate oxide layer 310 formed on the surface of substrate 20 has an uneven surface. More specifically, the thickness of gate oxide layer 310 corresponding to the arsenic-doped region becomes thicker. However, a thicker gate oxide layer 310 can affect the blow rate of the subsequent fuse element after formation.

Returning to FIG. 4 , in some embodiments, the polysilicon layer 320 may be formed on the gate oxide layer 310 by, for example, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, ultra-high vacuum chemical vapor deposition, reduced pressure chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable processes. In some embodiments, the polysilicon layer 320 may be replaced by any suitable conductive layer.

In some embodiments, the metal layer 330 may be formed on the polysilicon layer 320 by, for example, LPCVD. In some embodiments, the metal layer 330 may include tungsten, titanium nitride (TiN), aluminum, copper, tantalum, tantalum nitride (TaN), and/or the like.

In some embodiments, the protective layer 340 may be formed on the metal layer 330 by, for example, spin coating, PVD, CVD, evaporation, sputtering, or other suitable processes. In some embodiments, the protective layer 340 may include a nitride such as silicon nitride and/or the like.

In some embodiments, the substrate 20 in the active region 220 is not subjected to the aforementioned doping process before forming the stack of the gate oxide layer 310, the polysilicon layer 320, the metal layer 330, and the protective layer 340. In other words, the substrate 20 in the active region 220 is not subjected to the arsenic and nitrogen doping process.

FIG6 is a cross-sectional view illustrating a certain stage of a semiconductor structure fabrication process according to certain embodiments of the present invention. Next, the protective layer 340 of the fuse region 210 and the active region 220 may be patterned. The patterning process may include any suitable lithography technique, such as one or more lithography processes, to produce a protective layer 640 with a target pattern, as shown in FIG6 . The protective layer 640 may further serve as an etching mask in the next step. Using the patterned protective layer 640 as a hard mask, the metal layer 330, polysilicon layer 320, and gate oxide layer 310 (shown in FIG. 4 ) not protected by the protective layer 640 are etched, thereby producing a fuse structure (including the gate oxide layer 610, polysilicon layer 620, metal layer 630, and protective layer 640) located in the fuse region 210 and a gate structure (including the gate oxide layer 610, polysilicon layer 620, metal layer 630, and protective layer 640) located in the active region 220, as shown in FIG. In some embodiments, the etching process includes an anisotropic etching process. In some embodiments, the etching process includes performing one or more selective etching processes.

In some embodiments, an offset spacer 650 may be formed on the sidewalls of the fuse structure 60 (including the gate oxide layer 610, the polysilicon layer 620, the metal layer 630, and the protective layer 640) located in the fuse region 210 and the gate structure (including the gate oxide layer 610, the polysilicon layer 620, the metal layer 630, and the protective layer 640) located in the active region 220. The offset spacer 650 may optionally include one or more layers.

Please refer to FIG. 1 and FIG. 6 . In operation 108 of method 10 , source/drain regions 222 are formed in substrate 20 in active region 220 . Specifically, source/drain regions 222 can be formed in substrate 20 in active region 220 by an ion implantation process. Source/drain regions 222 are adjacent to gate oxide layer 610 , thereby forming a transistor structure 70 in the active region. In some embodiments, the material of source/drain regions 222 includes semiconductor materials such as doped silicon or germanium, semiconductor materials such as doped gallium arsenide, indium arsenide, indium phosphide, or silicon carbide compounds, or other suitable materials or materials.

As shown in FIG. 6 , another embodiment of the present disclosure provides a fuse structure 60. Fuse structure 60 includes a substrate 20, a gate oxide layer 610, a polysilicon layer 620, a metal layer 630, and a protective layer 640. Specifically, substrate 20 includes a doped region 24A. In some embodiments, doped region 24A includes arsenic ions 241 and nitrogen ions 243.

In some embodiments, the doping concentration of the arsenic ions 241 is 1.2×10 ¹⁵ to 1×10 ¹⁶ ions per square centimeter, for example, 1.4×10 ¹⁵ ions per square centimeter, 1.6×10 ¹⁵ ions per square centimeter, 1.8×10 ¹⁵ ions per square centimeter, 2.0×10 ¹⁵ ions per square centimeter, 2.5×10 ¹⁵ ions per square centimeter, 3.0×10 15 ions per square centimeter, 3.35×10 ¹⁵ ions per square centimeter, 3.5×10 ¹⁵ ions per square centimeter, 4.0×10 ¹⁵ ions per square centimeter, 4.5×10 ¹⁵ ions per square centimeter, or 5. ions per square centimeter, ^5.0 ×10 ¹⁵ ions per square centimeter, 5.5×10 ¹⁵ ions per square centimeter, 6.0×10 ¹⁵ ions per square centimeter, 6.5×10 ¹⁵ ions per square centimeter, 7.0×10 ¹⁵ ions per square centimeter, 7.5×10 ¹⁵ ions per square centimeter, 8.0×10 ¹⁵ ions per square centimeter, 8.5×10 ¹⁵ ions per square centimeter, 9.0×10 ¹⁵ ions per square centimeter, or 9.5×10 ¹⁵ ions per square centimeter. In some embodiments, the energy of the dopant arsenic ions 241 may be, for example, 30,000 electron volts (eV).

In some embodiments, the doping concentration of nitrogen ions 243 is 1×10 ¹⁴ to 1×10 ¹⁵ ions per square centimeter, for example, 1.5×10 ¹⁵ ions per square centimeter, 2.0×10 ¹⁵ ions per square centimeter, 2.5×10 15 ions per square centimeter, 3.0×10 ¹⁵ ions per square centimeter, 3.5×10 ¹⁵ ions per square centimeter, 4.0×10 ¹⁵ ions per square centimeter, 4.5×10 ¹⁵ ions per square centimeter, 5.0×10 ¹⁵ ions per square centimeter, 5.5×10 15 ions per square centimeter, 6.0×10 ¹⁵ ions per square centimeter, or 7.5×10 ¹⁵ ions per square centimeter. ions per square centimeter, ^6.5 ×10 ¹⁵ ions per square centimeter, 7.0×10 ¹⁵ ions per square centimeter, 7.5×10 ¹⁵ ions per square centimeter, 8.0×10 ¹⁵ ions per square centimeter, 8.5×10 ¹⁵ ions per square centimeter, 9.0×10 ¹⁵ ions per square centimeter, or 9.5×10 ¹⁵ ions per square centimeter. In some embodiments, the energy of the dopant nitrogen ions 243 may be, for example, 3,000 electron volts (eV) or 30,000 eV.

As shown in FIG. 6 , a gate oxide layer 610 is disposed on the doped region 24A. In some embodiments, the width of the gate oxide layer 610 is substantially the same as the width of the doped region 24A. In some embodiments, the vertical projection area of the gate oxide layer 610 on the substrate 20 is substantially the same as the vertical projection area of the doped region 24A on the substrate 20.

As shown in FIG6 , a polysilicon layer 620 is disposed on the gate oxide layer 610. In some embodiments, the width of the polysilicon layer 620 is substantially the same as the width of the gate oxide layer 610. In some embodiments, the vertical projection area of the polysilicon layer 620 on the substrate 20 is substantially the same as the vertical projection area of the gate oxide layer 610 on the substrate 20.

As shown in FIG6 , a metal layer 630 is disposed on the polysilicon layer 620. In some embodiments, the width of the metal layer 630 is substantially the same as the width of the gate oxide layer 610. In some embodiments, the vertical projection area of the metal layer 630 on the substrate 20 is substantially the same as the vertical projection area of the gate oxide layer 610 on the substrate 20.

As shown in FIG6 , a protective layer 640 is disposed on the metal layer 630. In some embodiments, the width of the protective layer 640 is substantially the same as the width of the gate oxide layer 610. In some embodiments, the vertical projection area of the protective layer 640 on the substrate 20 is substantially the same as the vertical projection area of the gate oxide layer 610 on the substrate 20.

In summary, the present disclosure relates to a method for fabricating a semiconductor structure and a fuse structure. By simultaneously doping the substrate in the fuse region with arsenic ions and nitrogen ions, the thickness of the gate oxide layer subsequently formed on the substrate can be controlled, thereby improving the fuse's blow rate.

Although the present invention has been disclosed in the form of embodiments as described above, it is not intended to limit the present invention. Anyone skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Method 102: Operation 104: Operation 106: Operation 108: Operation 20: Substrate 210: Fuse Region 220: Active Region 221: Isolation Structure 222: Source/Drain Region 240: Doping Process 241: Arsenic Ions 243: Nitrogen Ions 24A: Doped Region 310: Gate Oxide Layer 320: Polysilicon Layer 330: Metal Layer 340: Protective Layer 60: Fuse Structure 610: Gate oxide layer 620: Polysilicon layer 630: Metal layer 640: Protective layer 650: Pad layer 70: Transistor structure

Aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 is a flow chart illustrating a method for fabricating a semiconductor structure according to certain embodiments of the present invention. Figures 2, 3, and 4 are cross-sectional views illustrating various stages of a process for fabricating a semiconductor structure according to certain embodiments of the present invention. Figure 5 is a cross-sectional view illustrating a stage of a process for fabricating a non-nitrogen-doped semiconductor structure according to one embodiment of the present invention. Figure 6 is a cross-sectional view of a semiconductor structure at a certain stage of the manufacturing process according to certain embodiments of the present invention.

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20: Substrate 210: Fuse region 220: Active region 221: Isolation structure 222: Source/drain region 241: Arsenic ions 243: Nitrogen ions 24A: Doped region 60: Fuse structure 610: Gate oxide layer 620: Polysilicon layer 630: Metal layer 640: Passivation layer 650: Pad layer 70: Transistor structure

Claims (10)

A method for manufacturing a semiconductor structure includes: providing a substrate defining a fuse region and an active region; performing a doping process on the substrate in the fuse region to form a doped region; forming a stack of a gate oxide layer, a polysilicon layer, a metal layer, and a protective layer on the substrate in the fuse region and the active region; patterning the protective layer in the fuse region and the active region, wherein the patterned protective layer in the fuse region has the same width as the doped region; and forming a source/drain region in the substrate in the active region. The method for manufacturing a semiconductor structure as described in claim 1, wherein the doping process includes doping arsenic ions and nitrogen ions, the arsenic ions are doped with an energy of 30,000 electron volts, and the nitrogen ions are doped with an energy of 30,000 electron volts. A method for manufacturing a semiconductor structure as described in claim 2, wherein a doping concentration of the arsenic ions is 1.2×10 ¹⁵ to 1×10 ¹⁶ ions per square centimeter, and a doping concentration of the nitrogen ions is 1×10 ¹⁴ to 1×10 ¹⁵ ions per square centimeter. The method for manufacturing the semiconductor structure as described in claim 1 further includes using the patterned protective layer as an etching mask to pattern the gate oxide layer, the polysilicon layer and the metal layer of the fuse region and the active region. The method for manufacturing a semiconductor structure as described in claim 4, wherein the width of the gate oxide layer of the fuse region after patterning is substantially the same as the width of the doped region. The method for manufacturing a semiconductor structure as described in claim 1, wherein the thickness of the gate oxide layer in the fuse region is substantially the same as the thickness of the gate oxide layer in the active region. A fuse structure includes: a substrate including a doped region; a gate oxide layer disposed on the doped region; a polysilicon layer disposed on the gate oxide layer; a metal layer disposed on the polysilicon layer; and a protective layer disposed on the metal layer, wherein the width of the protective layer is substantially the same as the width of the doped region. The fuse structure of claim 7, wherein the doped region comprises an arsenic ion and a nitrogen ion. The fuse structure of claim 8, wherein the concentration of the arsenic ions is 1.2×10 ¹⁵ to 1×10 ¹⁶ ions per square centimeter. The fuse structure of claim 8, wherein the nitrogen ion concentration is 1×10 ¹⁴ to 1×10 ¹⁵ ions per square centimeter.