TWI898967B - Method for detecting abnormality in semiconductor structure - Google Patents

Abstract

A method for detecting abnormality in semiconductor structure includes the following steps. A plasma byproduct layer is formed covering a surface of the test wafer. Measure a thickness of the plasma byproduct layer. When the thickness of the plasma byproduct layer is greater than an expected value, a plasma flow rate of the plasma etching is increased. When the thickness of the plasma byproduct layer is less than the expected value, the plasma flow rate of the plasma etching is reduced.

Description

Methods for detecting structural anomalies in semiconductors

The present disclosure relates to the field of semiconductor manufacturing, and more particularly to a method for detecting semiconductor structural anomalies.

Micro-electromechanical (MEM) technology has been advancing at a rapid pace, and device dimensions have been reduced with advancements in technology to provide faster processing and more memory per unit area. As MEMS technology advances, the market demands smaller chips with increasing structures per unit area. One type of device that has seen much progress in miniaturization is memory devices.

Two of the mainstays of the memory sector are non-volatile (NAND) flash and dynamic random access memory (DRAM). DRAM is dynamic, volatile, and very fast, making it well-suited for short-term system memory. Conversely, NAND flash is non-volatile, meaning it has good retention and works well for long-term storage. As demand continues to increase, higher speed, higher density, and lower bit cost have been the primary goals for both of these memory types. DRAM has continued its path of scaling down to smaller cell designs. This scaling has driven the introduction of multiple patterning techniques. Planar NAND also faced scaling limitations and ultimately changed course, moving to a vertical orientation. This vertical integration has relaxed the lithography requirements for 3D NAND devices and, in turn, alleviated most of the complex process challenges associated with deposition and etching. As demand for higher density increases, the typical approach in NAND devices has been to stack more layers. Furthermore, the additional layers result in a thicker stack, which increases etching difficulty due to the increased aspect ratio.

The primary structure is fabricated through alternating film deposition, followed by high-aspect-ratio etching across the entire stack. Each new node in 3D NAND takes the process to even higher vertical stacks. High-aspect-ratio structures present unique process control requirements due to the channel depths of several microns and angstrom-level accuracy requirements. Polymer dumps generated during the plasma etch process typically adhere to the upper and/or lower edges of the trench. This prevents overetching due to excessively large critical dimensions (CDs) at the top edge of the trench, while also increasing/decreasing the etch rate in specific areas, which could otherwise be susceptible to shorting/underetching. These factors result in significant wafer loss and impact product yield, especially in high-aspect-ratio processes, where the impact is difficult to measure. Consequently, etching these high-aspect-ratio structures is becoming increasingly challenging.

To control product yield, detecting anomalies in the plasma etching process is crucial. Therefore, effectively adjusting plasma etching tool parameters to mitigate the risk of over-etching and/or under-etching, thereby reducing wafer scrap and improving product yield, has become a critical technical challenge facing researchers in this field.

According to various embodiments of the present disclosure, a method for detecting semiconductor structural anomalies is provided, comprising the following operations: forming a plasma byproduct layer covering a test wafer; measuring the thickness of the plasma byproduct layer; and increasing the plasma flow rate during plasma etching when the thickness of the plasma byproduct layer is greater than a desired value. When the thickness of the plasma byproduct layer is less than the desired value, decreasing the plasma flow rate during plasma etching.

According to certain embodiments of the present disclosure, during the operation of forming the plasma byproduct layer, the test wafer does not have a mask layer thereon.

According to certain embodiments of the present disclosure, during the operation of forming a plasma byproduct layer, a test wafer is placed on an electrostatic chuck, and the electrostatic chuck has a temperature control device. When the thickness of the plasma byproduct layer is greater than a desired value, the temperature of the temperature control device is reduced. When the thickness of the plasma byproduct layer is less than the desired value, the temperature of the temperature control device is increased. The temperature is preferably between about 10°C and about 30°C.

According to certain embodiments of the present disclosure, the plasma byproduct layer comprises hydrocarbons.

According to certain embodiments of the present disclosure, the desired value is about 3700 Å to about 3900 Å.

According to some embodiments of the present disclosure, the method for detecting semiconductor structural anomalies further includes depositing an oxide layer on the test wafer before forming a plasma byproduct layer covering the test wafer.

According to certain embodiments of the present disclosure, a circle having a center of a test wafer as its center is radially arranged from the center to the circumference, including at least a first region, a second region, and a third region, and multiple measurement points are respectively set in the first region and the third region.

According to some embodiments of the present disclosure, each of the measurement points in the first region is at the same distance from the center of the test wafer.

According to some embodiments of the present disclosure, each of the measurement points in the first region has a different distance from the center of the test wafer.

According to certain embodiments of the present disclosure, the first region has a circular shape and is closest to the center of the circle, while the third region has an annular shape and is closest to the circumference.

The following diagrams illustrate various embodiments of the present disclosure. For the sake of clarity, many practical details are included in the following description. However, it should be understood that these practical details should not be construed as limiting the present disclosure. In other words, these practical details are not essential to some embodiments of the present disclosure. Furthermore, for clarity, the size or thickness of components may be exaggerated and not drawn to their original scale. Furthermore, to simplify the diagrams, some commonly used structures and components are depicted in simplified schematic form.

The following disclosure provides many different embodiments or examples to implement different features of each embodiment. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these examples are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the subsequent description may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. In addition, the disclosure may repeat element symbols and/or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "above," and "on" are used herein to facilitate descriptions of the relative relationships of one element or feature to another, as depicted in the figures. The true meaning of these spatially relative terms encompasses alternative orientations. For example, when a figure is rotated 180 degrees, the relationship between one element and another might change from "below" or "beneath" to "above" or "on." Furthermore, spatially relative terms used herein should be interpreted similarly.

Polymer dump is a byproduct generated in the processing chamber during the plasma etching process. By inspecting and measuring the thickness of the byproduct using a test wafer (or control wafer), it can be used to determine the extent of byproduct generation during the etching process in actual semiconductor structures. Because semiconductor devices have high aspect ratio structures, the plasma will continue to erode the hole during the downward etching process, forming a funnel-shaped structure with a wider top and a narrower bottom. While polymer dump can actually protect the top of the groove from being over-etched, excessive polymer dump may also cause the groove to fail to meet the high aspect ratio specification requirements. Therefore, the thickness of the plasma byproduct generated is highly correlated with over-etching/under-etching of the groove.

FIG1 is a flow chart of a method for detecting a semiconductor structural anomaly according to certain embodiments of the present disclosure. As shown in FIG1 , method 10 includes operation 102, operation 104, and operation 106. The method for detecting a semiconductor structural anomaly will be further described below based on one or more embodiments. It should be understood that for additional embodiments of method 10 for detecting a semiconductor structural anomaly, additional steps may be provided before, during, and after method 10, and some of the steps described below may be replaced or eliminated. In addition, to make the relevant details of each step of this embodiment clearer, the following description will be made in conjunction with a plasma etching device, that is, the plasma etching device can be used to perform the method 10 for detecting a semiconductor structural anomaly of this embodiment.

FIG2 is a schematic diagram illustrating a test wafer placed within a plasma etching chamber according to certain embodiments of the present disclosure. In operation 102, a test wafer 110 is placed within a plasma etching chamber 210 and plasma etching is performed, as shown in FIG2 . In one or more embodiments of the present disclosure, the test wafer 110 is a single-crystal bare silicon wafer. In other embodiments, the test wafer 110 may also be other common semiconductor wafers, such as polycrystalline silicon wafers, germanium wafers, or silicon-germanium alloy wafers, but the present disclosure is not limited thereto.

Embodiments specifically described herein are in the context of using an adjustable direct current (DC) bias during plasma processing. Plasma etching processing can include flowing a gas, igniting the gas to form a plasma, introducing the plasma into a chamber containing a substrate, and using an adjustable DC bias to repel ions from or attract ions to a test wafer 110. Plasma processing can be performed during semiconductor manufacturing. Plasma is an at least partially ionized gas having positive and negative particles, including free radicals, positively and/or negatively charged ions, and electrons (negatively charged). Some examples of plasma processing include plasma etching and plasma ashing. Plasma etching is a form of plasma processing in which plasma is directed to etch a material. The plasma source utilizes an etching species consisting of charged ions, free radicals, and/or neutral atoms. Elements of the material react chemically with reactive species in the plasma to etch the material. Those skilled in the art will appreciate that the complete details of the plasma etching chamber 210 and its associated internal or external structures are not shown in the drawings or described herein.

FIG3 illustrates a schematic diagram of a plasma byproduct layer formed on a test wafer according to certain embodiments of the present disclosure. In operation 104, a plasma byproduct layer 130 is formed overlying _the test wafer 110. In one or more embodiments of the present disclosure, the plasma byproduct layer 130 comprises hydrocarbons ( _CxHyOz ). It should be noted that the plasma byproducts generated during _the plasma reaction help protect the recesses from being over-etched.

In one or more embodiments of the present disclosure, an oxide layer 120 may be deposited on the test wafer 110 before plasma etching to simulate the oxide layer on a semiconductor wafer. Therefore, after the plasma etching, a plasma byproduct layer 130 is formed on and covers the oxide layer 120. In one or more embodiments of the present disclosure, the oxide layer 120 comprises silicon oxide. In one or more embodiments of the present disclosure, the oxide layer 120 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam deposition (MBD), high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Alternatively, other oxide layers 120 formed using any acceptable process may be used.

In one or more embodiments of the present disclosure, the test wafer 110 is placed in the plasma etching chamber 210 without a mask layer (not shown). In other words, since there is no patterned mask layer on the test wafer 110, the plasma does not etch any pattern on the test wafer 110 during the etching process. However, plasma byproducts still accumulate on the surface of the test wafer 110, especially at the edge of the test wafer 110. Because the plasma density is generally lower in this area, under-etching is more likely to occur. On the other hand, because the plasma density is higher in the central area of the test wafer 110, plasma byproducts are less likely to accumulate on the surface of the test wafer 110, resulting in a higher probability of over-etching. Therefore, the thickness of the plasma byproducts can be detected in the subsequent operation 106 to adjust the plasma flow rate.

In operation 106, the thickness 130T of the plasma byproduct layer 130 is measured, as shown in FIG3 . Specifically, when the thickness 130T of the plasma byproduct layer 130 is greater than a desired value, the plasma flow rate of the plasma etching is increased. When the thickness 130T of the plasma byproduct layer 130 is less than the desired value, the plasma flow rate of the plasma etching is decreased. In one or more embodiments of the present disclosure, the thickness 130T of the plasma byproduct layer 130 can be measured using a thickness gauge. In one or more embodiments of the present disclosure, the desired value is between approximately 3700 Å and approximately 3900 Å, for example, 3750 Å, 3800 Å, or 3850 Å.

Figure 4 is a schematic diagram illustrating the distribution of measurement points on a test wafer according to certain embodiments of the present disclosure. In one or more embodiments of the present disclosure, as shown in Figure 4, with the center 110c of the test wafer 110 as the center, a circle extending radially from the center to the circumference includes at least a first zone Z1, a second zone Z2, a third zone Z3, a fourth zone Z4, a fifth zone Z5, and a sixth zone Z6. The first zone Z1 is circular, while the second zone Z2 through the sixth zone Z6 each have an annular shape. Notably, because the plasma density is highest in the center and lowest at the edge, multiple measurement points are provided in the first zone Z1, closest to the center, and the sixth zone Z6, closest to the circumference.

For example, as shown in FIG4 , the test wafer 110 includes 40 measurement points. The first zone Z1 includes four evenly distributed measurement points, all equidistant from the center 110c. Furthermore, the sixth zone Z6 includes 36 evenly distributed measurement points, all equidistant from the center 110c. It should be noted that the zones of the test wafer 110, as well as the location and number of measurement points within each zone, can be flexibly adjusted and divided based on the required plasma etching accuracy, and are not limited to this embodiment.

Please return to Figure 2. The test wafer 110 is placed on an electrostatic chuck (E-Chuck, ESC) 220 in the plasma etching processing chamber 210, and the electrostatic chuck 220 has a temperature control device 230. In the semiconductor manufacturing process, the electrostatic chuck is usually used to fix and support the wafer to prevent the wafer from moving or misaligning during the process. Since the electrostatic chuck uses electrostatic force to hold the wafer, compared to the mechanical chuck or vacuum chuck used previously, it can reduce breakage due to mechanical pressure during use. In addition, the electrostatic chuck increases the area that can be effectively processed and is suitable for operation in a vacuum environment. In semiconductor manufacturing, the center and edge regions of a wafer require different processing conditions, and both regions frequently experience changes in process parameters, such as temperature. Therefore, heat exchange channels are designed in the center and edge regions of the electrostatic chuck. After the coolant flows out, it removes heat from the wafer in each region. A continuous flow of coolant flows into the electrostatic chuck, continuously removing heat.

Figures 5 and 6 are schematic diagrams of plasma byproducts formed in semiconductor structures according to certain embodiments of the present disclosure. The location where the byproducts generated by plasma etching are deposited is actually related to the temperature of the workpiece (e.g., a test wafer 110 or a semiconductor structure with grooves, etc.). Specifically, when the temperature of the workpiece is relatively low (e.g., 10°C), most of the byproducts 520 will accumulate at the bottom of the groove 510, causing the groove 510 to have a structure that is wide at the top and narrow at the bottom, as shown in Figure 5. Conversely, when the temperature of the workpiece is relatively high (e.g., 30°C), most of the byproducts 520 will accumulate at the top of the groove 510, causing the groove 510 to have a structure that is narrow at the top and wide at the bottom, as shown in Figure 6.

Referring back to Figures 2 and 3, it is noted that when the thickness 130T of the plasma byproduct layer 130 is greater than a desired value, the temperature of the temperature control device 230 is decreased, and when the thickness 130T of the plasma byproduct layer 130 is less than the desired value, the temperature of the temperature control device 230 is increased. In one or more embodiments of the present disclosure, the temperature is between approximately 10°C and approximately 30°C.

FIG7 shows the relationship between the thickness of the plasma byproduct layer and the amount of overetching according to certain embodiments of the present disclosure. FIG7 shows that when the plasma byproduct layer is thinner, overetching is more likely to occur, and in this case, the plasma flow rate during plasma etching needs to be reduced. Conversely, when the plasma byproduct layer is thicker, overetching is less likely to occur. In other words, the plasma byproducts can protect the workpiece from continued etching.

FIG8 is a graph showing the relationship between the thickness of the plasma byproduct layer and the amount of under-etching according to certain embodiments of the present disclosure. FIG7 shows that the thicker the plasma byproduct layer, the more likely under-etching will occur. In this case, the plasma flow rate of the plasma etching process needs to be increased. It can also be verified that plasma byproducts can protect the workpiece from continuous etching. Conversely, the thinner the plasma byproduct layer, the less likely under-etching will occur. FIG7 and FIG8 show that the ideal thickness of the plasma byproduct layer is approximately in the range of 3700Å to 3900Å.

In summary, the present disclosure uses test wafers to inspect and measure byproduct thickness, enabling the determination of byproduct generation during the etching process of actual semiconductor structures. This method, through a fixed inspection frequency, allows adjustments to be made to the corresponding semiconductor structure manufacturing batches, reducing the risk of under-etching and over-etching, thereby improving product quality and yield.

Although the present disclosure has been disclosed in the form of embodiments as described above, it is not intended to limit the present disclosure. Anyone skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the attached patent application.

10: Method 102: Operation 104: Operation 106: Operation 110: Test wafer 110c: Center 120: Oxide layer 130: Plasma byproduct layer 130T: Thickness 210: Plasma etching chamber 220: Electrostatic chuck 230: Temperature control device Z1: First zone Z2: Second zone Z3: Third zone Z4: Fourth zone Z5: Fifth zone Z6: Sixth zone 510: Recess 520: Byproducts

Aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 is a flow chart of a method for detecting semiconductor structural anomalies according to certain embodiments of the present disclosure. Figure 2 is a schematic diagram of a test wafer placed in a plasma etching processing chamber according to certain embodiments of the present disclosure. Figure 3 is a schematic diagram of a plasma byproduct layer formed on a test wafer according to certain embodiments of the present disclosure. Figure 4 is a schematic diagram of the distribution of measurement points on a test wafer according to certain embodiments of the present disclosure. Figures 5 and 6 illustrate the formation of plasma byproducts in a semiconductor structure according to certain embodiments of the present disclosure. Figure 7 shows the relationship between the thickness of a plasma byproduct layer and the amount of overetching according to certain embodiments of the present disclosure. Figure 8 shows the relationship between the thickness of a plasma byproduct layer and the amount of underetching according to certain embodiments of the present disclosure.

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10: Methods

102: Operation

104: Operation

106: Operation

Claims (10)

A method for detecting semiconductor structural anomalies includes: forming a plasma byproduct layer covering a test wafer; and measuring a thickness of the plasma byproduct layer. When the thickness of the plasma byproduct layer is greater than a desired value, a plasma flow rate for plasma etching is increased; and when the thickness of the plasma byproduct layer is less than the desired value, the plasma flow rate for plasma etching is decreased. The method for detecting abnormalities in a semiconductor structure as claimed in claim 1, wherein in the operation of forming the plasma byproduct layer, the test wafer does not have a mask layer thereon. A method for detecting semiconductor structural abnormalities as described in claim 2, wherein during the operation of forming the plasma byproduct layer, the test wafer is placed on an electrostatic chuck, and the electrostatic chuck has a temperature control device. When the thickness of the plasma byproduct layer is greater than the expected value, the temperature of the temperature control device is lowered, and when the thickness of the plasma byproduct layer is less than the expected value, the temperature of the temperature control device is increased, and the temperature is between about 10°C and about 30°C. The method for detecting semiconductor structural anomalies as claimed in claim 1, wherein the plasma byproduct layer comprises hydrocarbons. The method for detecting structural anomalies in a semiconductor as claimed in claim 1, wherein the expected value is from about 3700 Å to about 3900 Å. The method for detecting anomalies in a semiconductor structure as claimed in claim 1 further comprises depositing an oxide layer on the test wafer before forming the plasma byproduct layer covering the test wafer. A method for detecting semiconductor structural abnormalities as described in claim 1, wherein a circle having a center of the test wafer as the center and extending from the center to the circumference along a radial direction includes at least a first region, a second region, and a third region, and a plurality of measurement points are respectively set in the first region and the third region. The method for detecting abnormalities in a semiconductor structure as described in claim 7, wherein each of the measurement points in the first area is at the same distance from the center of the test wafer. The method for detecting anomalies in a semiconductor structure as described in claim 7, wherein each of the measurement points in the first area is at a different distance from the center of the test wafer. A method for detecting abnormalities in a semiconductor structure as described in claim 7, wherein the first region has a circular shape and is closest to the center of the circle, and the third region has an annular shape and is closest to the circumference.