TWI898778B - Optical semiconductor element and manufacturing method thereof - Google Patents

Abstract

The present invention aims to improve the characteristics of an optical semiconductor device. The optical semiconductor device comprises a first active layer that receives and emits light at a first wavelength, a tunnel junction layer above the first active layer, and a second active layer above the tunnel junction layer that receives and emits light at a second wavelength. The first and second active layers contain Sb, and the tunnel junction layer comprises a p-type InAs layer and an n-type InAs layer.

Description

Optical semiconductor element and manufacturing method thereof

The present invention relates to an optical semiconductor device and a method for manufacturing the same.

Optical semiconductor devices are known that have two or more vertically stacked active layers with a tunnel junction layer sandwiched between them. These optical semiconductor devices are used as light-emitting devices to increase light output when the wavelengths of the stacked active layers are close, while emitting light of different wavelengths when the wavelengths of the stacked active layers are separated. Similarly, they are also used as light-receiving devices to increase light reception efficiency when the wavelengths of the stacked active layers are close, while providing sensitivity to different wavelength bands when the wavelengths of the stacked active layers are separated.

This type of optical semiconductor device connects multiple active layers in series by vertically overlapping them. When a forward current flows through the light-emitting device, each of the multiple active layers emits light. Generally, the active layers in this case form a pn junction.

The tunnel junction layer is formed by a high-concentration p-type semiconductor layer and an n-type semiconductor layer. When a forward voltage is applied to the active layer, a reverse voltage is applied. Normally, when the layers are connected in the order of p-type, n-type, p-type (or n-type, p-type, n-type), they act as a current gate and prevent current from flowing. However, because the tunnel junction layer sandwiched between the active layers is doped at a high concentration, a tunnel effect occurs within the tunnel junction layer, allowing current to flow.

[Prior Art Literature]

[Patent Literature]

Patent Document 1: Japanese Patent Publication No. 2009-522755

Patent Document 2: Japanese Patent Application No. 2018-201009

Patent Document 1 describes that Al, Ga, In, and P are preferred as the basic constituent materials for the crystal lattice of optical semiconductor devices. However, using only these materials alone does not allow for emission of long-wavelength light exceeding 3000 nm. Furthermore, as described in Patent Document 2, a high n-type dopant concentration of 1.0×10 ¹⁹ atoms/cm ³ or higher is previously preferred for tunnel junction layer formation. However, if an n-type semiconductor layer and a p-type semiconductor layer containing a high concentration of dopant exist between vertically overlapping active layers, the dopant diffuses into the active layer, potentially leading to a decrease in reliability and an increase in leakage current.

This invention was developed in view of the above-mentioned practical situation, and its purpose is to improve the characteristics of optical semiconductor devices.

The present inventors have diligently researched methods to solve the aforementioned problems and have discovered an optical semiconductor device and a method for manufacturing the device, including Sb in the first and second active layers and a tunnel junction layer comprising a p-type InAs layer and an n-type InAs layer, leading to the completion of the present invention. Furthermore, it has been found that the tunnel junction layer of the present invention exhibits a tunneling effect at a dopant concentration lower than previously believed necessary. The gist of the present invention is as follows.

(1) An optical semiconductor element comprising a first active layer that receives/emit light at a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer that receives/emit light at a second wavelength, wherein the first active layer and the second active layer contain Sb, and the tunnel junction layer comprises a p-type InAs layer and an n-type InAs layer.

(2) The optical semiconductor device according to (1), wherein the dopant concentration in the tunnel junction layer is greater than or equal to 1.0×10 ¹⁸ atoms/cm ³ and less than 1.0×10 ¹⁹ atoms/cm ³ .

The optical semiconductor element described in (1) or (2), wherein the first active layer and the second active layer have a quantum well structure, and the first wavelength and the second wavelength are greater than 3000 nm.

(4) The optical semiconductor device according to any one of (1) to (3), wherein the first wavelength and the second wavelength are the same.

(5) The optical semiconductor device according to any one of (1) to (4), wherein the p-type InAs layer is provided on the first active layer side of the tunnel junction layer, a p-type electron blocking layer is provided between the first active layer and the tunnel junction layer, and the film thickness between the first active layer and the tunnel junction layer is 100 nm or less.

(6) The optical semiconductor device according to any one of (1) to (5), wherein the n-type InAs layer is provided on the second active layer side of the tunnel junction layer, a spacer layer is provided between the tunnel junction layer and the second active layer, and the film thickness between the tunnel junction layer and the second active layer is 100 nm or less.

(7) A method for manufacturing an optical semiconductor element, comprising the following steps: forming a first active layer having a light receiving/emitting wavelength of a first wavelength on a substrate; forming a tunnel junction layer on the first active layer; and forming a second active layer having a light receiving/emitting wavelength of a second wavelength on the tunnel junction layer, wherein the first active layer and the second active layer contain Sb, and the step of forming the tunnel junction layer comprises the step of forming an n-type InAs layer and the step of forming a p-type InAs layer on the n-type InAs layer.

(8) The method for manufacturing an optical semiconductor device according to (7), wherein the dopant concentration in the tunnel junction layer is greater than or equal to 1.0×10 ¹⁸ atoms/cm ³ and less than 1.0×10 ¹⁹ atoms/cm ³ .

Provided are optical semiconductor devices with improved characteristics and methods for manufacturing the same. For example, in the case of a light-emitting device, the device can have high luminous output power and forward voltage, and a center wavelength of 3000 nm or greater, and a method for manufacturing the same. Furthermore, since leakage current is reduced in the case of a light-emitting device, the device can also have low dark current and high shunt resistance in the case of a light-receiving device, and a method for manufacturing the same.

100: Optical semiconductor components/semiconductor light-emitting components

105: Growth substrate

140: Semiconductor integrated circuits

141: n-type contact layer

142: n-type window layer

143: First spacer layer

144: First active layer

144b: Barrier layer of the first active layer

144w: Well layer of the first active layer

145: First p-type electron blocking layer

146: First p-type window layer

147: Tunnel Layer

1471: p-type tunnel junction layer

1472: n-type tunnel junction layer

148: Second spacer layer

149: Second active layer

149b: Barrier layer of the second active layer

149w: Well layer of the second active layer

150: Second p-type electron blocking layer

151: Second p-type window layer

152: p-type contact layer

191: Upper electrode

195:Lower electrode

200: Optical semiconductor components

205: Growth substrate

240: Semiconductor integrated circuits

241: n-type contact layer

242: n-type window layer

243: First compartment layer

244: First active layer

245: First p-type electron blocking layer

246: First p-type window layer

247: Tunnel Layer

248: Second spacer layer

249: Second active layer

250: Second p-type electron blocking layer

251: Second p-type window layer

252: p-type contact layer

260:Power Distribution Department

261: Transparent insulating layer

265: Ohm electrode section

271: Metal reflective layer

279: Metal bonding layer

280: Supporting substrate

291: Upper electrode

295: Back electrode

300: Optical semiconductor components

352: Second tunnel junction layer

3521: p-type InAs layer of the second tunnel junction layer

3522: n-type InAs layer of the second tunnel junction layer

354: Third active layer

357: Third Tunnel Layer

3571: p-type InAs layer of the third tunnel junction layer

3572: n-type InAs layer of the third tunnel junction layer

359: Fourth active layer

FIG1 is a schematic cross-sectional view illustrating a first embodiment of an optical semiconductor device according to the present invention.

Figure 2 is a schematic cross-sectional view illustrating a second embodiment of the optical semiconductor device according to the present invention.

FIG3 is a schematic cross-sectional view illustrating an example of a method for manufacturing the second embodiment of the optical semiconductor device according to the present invention.

FIG4 is a schematic cross-sectional view illustrating an example of a manufacturing method following FIG3 .

FIG5 is a schematic cross-sectional view illustrating an example of a manufacturing method following FIG4.

FIG6 is a schematic cross-sectional view illustrating a third embodiment of the optical semiconductor device according to the present invention.

Figure 7 is a graph showing the results of measuring the diffusion state of Te ions in Example 1 using secondary ion mass spectroscopy (SIMS).

Figure 8 is a graph showing the results of measuring the diffusion state of Zn ions in Example 1 using secondary ion mass spectrometry (SIMS).

Before describing the embodiments of the present invention, the following aspects will be described in advance.

In this embodiment, the active layer containing Sb refers to a compound also expressed as InAs _x Sb _1-x (0<x<1). Furthermore, in the case of an InAs layer, AlInAs layer, or InAsP layer, Sb is not included in the composition ratio. However, as long as no Sb source gas is used during the growth of the layer, Sb may be included as an unavoidable dopant element, either from residual Sb in the chamber or from diffusion from adjacent Sb-containing layers. In this specification, when the composition ratio is not explicitly stated and "AlInAsSb" is simply described, it refers to any compound in which the chemical composition ratio of Group III elements (the sum of Al and In) and Group V elements (the sum of As and Sb) is 1:1, and the ratios of Al and In as Group III elements and As and Sb as Group V elements are undefined. This includes cases where neither Al nor In is included in the Group III elements, and also includes cases where neither As nor Sb is included in the Group V elements. The composition ratios of the individual III-V elements in AlInAsSbP can be measured by photoluminescence measurement, X-ray diffraction measurement, and other methods.

In this specification, layers without intentional addition of specific dopants such as Zn, Te, and Si are referred to as "undoped." Undoped layers may contain unavoidable incorporation of dopants during the manufacturing process. The concentrations of dopants such as Zn, Te, and Si are determined by secondary ion mass spectroscopy (SIMS) analysis.

The III-V compound semiconductor in this embodiment contains at least one of Al, Ga, and In as a Group III element, and at least P, As, and Sb as a Group V element.

The thickness of each layer formed by epitaxial growth can be calculated by observing the cross-section of the grown layer using a scanning electron microscope (SEM) or a transmission electron microscope (TEM). SEM is preferred for film thicknesses of 10 nm or greater, while TEM is preferred for film thicknesses less than 10 nm.

In this specification, the following situation is described: for different active layers, the center wavelengths of the emission wavelengths are compared with each other, and the emission wavelengths are the same, but the present invention is not limited to this. The center wavelengths of the emission wavelengths can be separated or similar. When the center wavelengths are separated, different effects can be given to each center wavelength. In this specification, the center wavelengths of the emission wavelengths are similar to each other, which means that the center wavelengths exist in a relationship in which the range of the half-value full width in the emission spectrum overlaps. For example, it means that the wavelength difference is included in the value of the half-value full width (for example, within 100nm). If the center wavelengths are the same or similar, the synthesis of the emission spectrum is effective in improving the emission intensity. The above description is based on the case of a light-emitting element, but the same applies to the case of a light-receiving element.

The optical semiconductor device according to the present invention comprises a first active layer that receives and emits light at a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer that receives and emits light at a second wavelength. The first and second active layers contain Sb, and the tunnel junction layer comprises a p-type InAs layer and an n-type InAs layer.

The following describes embodiments of the present invention with reference to the drawings. For ease of explanation, the vertical and horizontal ratios of the substrate and various layers are exaggerated relative to actual ratios in each figure. Furthermore, Group III-V compound semiconductors containing three or more elements may sometimes be described without the composition ratios of the individual elements (e.g., "InAsSb").

(First implementation form)

An example of an optical semiconductor device 100 according to a first embodiment of the present invention will be described with reference to FIG1 and a manufacturing method. Optical semiconductor device 100 includes a growth substrate 105 and a semiconductor multilayer structure 140 comprising multiple semiconductor layers stacked on growth substrate 105 and emitting light when current is applied. As will be described in detail later, semiconductor multilayer structure 140 functions as a so-called double-stack light-emitting diode, comprising multiple active layers including pn junctions. These active layers sandwich a tunnel junction layer, which allows current to flow in opposite directions (from n-type layer to p-type layer) via the tunnel effect.

The first embodiment is an embodiment of a semiconductor light-emitting device 100 in which an n-type contact layer 141, an n-type window layer 142, a first spacer layer 143, a first active layer 144, a p-type intermediate layer (a first p-type electron blocking layer 145 and a first p-type window layer 146), a tunnel junction layer 147 (a p-type tunnel junction layer 1471 and an n-type tunnel junction layer 1472), an n-type intermediate layer (a second spacer layer 148), a second active layer 149, a second p-type electron blocking layer 150, a second p-type window layer 151, and a p-type contact layer 152 are sequentially formed and stacked on a growth substrate 105, with the growth substrate 105 being used directly as a substrate.

<Substrate>

The following describes a substrate that can be used in the optical semiconductor device 100. The substrate used in the present invention can be any substrate having a thickness sufficient to mechanically maintain the shape of the semiconductor multilayer body 140 comprising the first active layer 144, the tunnel junction layer 147, and the second active layer 149. It can also be the growth substrate 105 used for epitaxial growth of the semiconductor multilayer body 140 when forming the optical semiconductor device 100.

<<Growth Substrate>>

As the growth substrate 105, a compound substrate such as GaAs, InP, InAs, GaSb, or InSb can be used. In order to form an active layer containing Sb, it is ideal to use a substrate of InAs, GaSb, or InSb. However, since these substrates are expensive, a GaAs substrate is preferred in terms of cost. The GaAs substrate is preferably doped with Si to form an n-type substrate, and the semiconductor multilayer body 140 is preferably laminated on the (100) surface of the GaAs substrate. Furthermore, the film thickness of the GaAs substrate is preferably not less than 200 μm and not more than 900 μm.

Furthermore, when using a GaAs or InP substrate, a buffer layer is preferably provided between the growth substrate 105 and the n-type contact layer 141 to mitigate lattice mismatch. This buffer layer may include an InAs buffer layer grown at a low temperature. Alternatively, the buffer layer may employ a composition gradient or a superlattice structure in which the compositional values α and β of the _{InαGa1 -αAsβSb1 - β} layer vary within a range of 0 to 1.

<<n-type contact layer>>

An n-type contact layer 141 comprising a III-V compound semiconductor layer may also be provided on the growth substrate 105. The n-type contact layer 141 has high conductivity and is advantageous in electrode formation. The film thickness is preferably 20 nm to 500 nm. Examples of dopants that can be used here include Si, Te, S, Ge, Sn, and Se. The dopant concentration is preferably higher than that of the n-type window layer 142, described below, and is more preferably 8.0 × 10 ¹⁸ /cm ³ to 3.0 × 10 ¹⁹ /cm ³ .

<<n-type window layer>>

An n-type window layer 142 comprising a III-V compound semiconductor layer may also be provided on the n-type contact layer 141. The thickness is preferably between 500 nm and 6000 nm. Examples of dopants that can be used in this case include Si, Te, S, Ge, Sn, and Se. If the lattice constants of the growth substrate 105 and the first active layer 144 differ, a thickness of less than 500 nm for the n-type window layer 142 can cause defects to propagate into the first active layer 144. Furthermore, a thickness less than 500 nm prevents sufficient carriers from being supplied to the first active layer 144, resulting in reduced light output and a poorer performance. On the other hand, even if the n-type window layer 142 is thicker than 6000nm, significant performance improvements are not expected. Furthermore, the growth time is prolonged, and the raw material costs increase, leading to productivity issues and thus a suboptimal performance.

In addition, the dopant concentration of the n-type window layer 142 is preferably lower than that of the n-type contact layer 141 , and is preferably greater than or equal to 1.0×10 ¹⁸ /cm ³ and less than or equal to 8.0×10 ¹⁸ /cm ³ .

Furthermore, the composition of the n-type window layer 142 is preferably lattice-matched to that of the first active layer 144. The composition of the n-type window layer 142 is preferably AlInAs, which has a lower Al composition ratio (i.e., a smaller band gap) than the first p-type electron blocking layer 145 described later, and more preferably InAs.

<First partition layer>

An undoped first spacer layer 143 comprising a III-V compound semiconductor layer may be disposed on the n-type window layer 142. The thickness is preferably set to 1 nm to 100 nm. The first spacer layer 143 is preferably the same as the barrier layer or the n-type window layer 142 that constitutes the first active layer 144 and is not doped with an n-type dopant. The first spacer layer 143 reduces the amount of n-type dopant that diffuses from the n-type window layer 142 into the first active layer 144.

<First active layer>

A first active layer 144 containing Sb is disposed on the first spacer layer 143. The first active layer 144 comprises an InAs _x1 Sb _1-x1 layer (0<x1<1) serving as a light-emitting layer. Figure 1 illustratively illustrates a quantum well structure in which the first active layer 144 further comprises an InAs _y1 P _1-y1 layer (0<y1<1), a well layer 144w comprising the InAs _x1 Sb _1-x1 layer as the first active layer, and a barrier layer 144b comprising the InAs _y1 P _1-y1 layer as the first active layer. However, the first active layer 144 may also comprise a single InAs _x1 Sb _1-x1 layer. Furthermore, the composition other than Sb is not limited to In and As; other III-V compound semiconductors may also be used. Furthermore, it is also preferred to adjust the compositional difference between the well layer 144w of the first active layer and the barrier layer 144b of the first active layer and to apply strain to the well layer. To improve light output by suppressing crystal defects, the first active layer 144 preferably has a multiple quantum well (MQW) structure as shown in FIG1 . The multiple quantum well structure can be formed by alternating and repeating the well layers and barrier layers. When using a multiple quantum well structure, the number of well layer and barrier layer combinations is preferably 3 or more and 40 or less. That is, including the initial barrier layer, the number is preferably 3.5 or more and 40.5 or less. Furthermore, the thickness of each well layer is preferably between 5 nm and 40 nm, and the thickness of each barrier layer is preferably between 10 nm and 50 nm. Furthermore, the first active layer 144 is preferably undoped. The first active layer 144 has a wavelength region with a central emission wavelength of 3000 nm or greater. Barrier layers can be made of materials other than InAsP, such as AlInAs.

<P-type intermediate layer between the first active layer and the tunnel junction layer>

A p-type intermediate layer is formed between the first active layer 144 and the tunnel junction layer 147 (described later). The thickness between the first active layer 144 and the tunnel junction layer 147 is preferably 100 nm or less. Furthermore, the p-type intermediate layer preferably includes a p-type electron blocking layer.

<First p-type electron blocking layer>

A first p-type electron blocking layer 145 comprising a III-V compound semiconductor layer may be provided on the first active layer 144. The film thickness is preferably 5 nm to 60 nm. Examples of dopants that can be used in this layer include Mg, Zn, C, and Be. The p-type dopant concentration is preferably 1.0 × 10 ¹⁸ /cm ³ to 5.0 × 10 ¹⁸ /cm ^3. The first p-type electron blocking layer 145 injects and confines carriers into the first active layer 144. In addition, the first p-type electron blocking layer 145 also has the effect of reducing the diffusion of p-type dopants from the tunnel junction layer 147 to be described later to the first active layer 144 .

The composition of the first p-type electron blocking layer 145 is preferably Al _z1 In _1-z1 As (0.05 ≤ z1 ≤ 0.40), more preferably Al _z1 In _1-z1 As (0.10 ≤ z1 ≤ 0.35). This is because by setting the Al composition z1 to 0.05 or greater, the luminescence efficiency of the first p-type electron blocking layer 145 can be improved, while by setting the Al composition z1 to 0.40 or less, the decrease in luminescence efficiency caused by an increase in forward voltage can be suppressed. Furthermore, the p-type dopant concentration in the first p-type electron blocking layer 145 is preferably lower than the p-type dopant concentration in the p-type tunnel junction layer 1471, described later.

A first p-type window layer 146 may be further formed on the first p-type electron blocking layer 145. The composition of the first p-type window layer 146 preferably has a lower Al content than the composition z1 of the first p-type electron blocking layer 145, such as InAs. The p-type dopant concentration is preferably greater than 1.0×10 ¹⁸ /cm ³ and less than 5.0×10 ¹⁸ /cm ³ .

The p-type intermediate layer between the first active layer 144 and the tunnel junction layer 147 may include layers other than the first p-type electron blocking layer 145 or the first p-type window layer 146. In this case, the present invention can also suppress the dopant concentration in the tunnel junction layer 147 to a low level. Therefore, even if diffusion of the p-type dopant from the p-type tunnel junction layer 1471 occurs, the p-type dopant concentration in the p-type intermediate layer can be kept to, for example, 5.0×10 ¹⁸ /cm ³ or less, and the total film thickness between the first active layer 144 and the tunnel junction layer 147 can be suppressed to 100 nm or less. By suppressing the diffusion of dopants and reducing the thickness in this way, it is expected that the forward voltage of the entire device can be reduced.

<Tunnel Layer>

A tunnel junction layer 147 comprising a p-type tunnel junction layer 1471 made of InAs and an n-type tunnel junction layer 1472 is provided on the first p-type window layer 146. The thickness of the tunnel junction layer 147 is preferably not less than 10 nm and not more than 200 nm. Examples of dopants that can be used in the p-type tunnel junction layer 1471 include Mg, Zn, C, and Be, while examples of dopants that can be used in the n-type tunnel junction layer 1472 include Si, Te, S, Ge, Sn, and Se. The p-type tunnel junction layer 1471 faces the first active layer 144, while the n-type tunnel junction layer 1472 faces the second active layer 149. The film thickness and dopant concentration of the p-type tunnel junction layer 1471 and the n-type tunnel junction layer 1472 can be the same or different. Furthermore, the dopant concentration of the p-type tunnel junction layer 1471 and the n-type tunnel junction layer 1472 does not need to be uniform within the layer and can have a concentration gradient.

Typically, to form a tunnel junction, the semiconductor doping ratio must be significantly increased, thinning the depletion layer formed at the interface between the n-type and p-type semiconductor layers to a level that allows quantum tunneling. Therefore, in compound semiconductors, a dopant concentration of at least 1.0×10 ¹⁹ /cm ³ (preferably 1.0×10 ²⁰ /cm ³ ) is required. However, in the present invention, a tunnel junction can be achieved even with a dopant concentration of 1.0×10 ¹⁸ /cm ³ or higher and less than 1.0×10 ¹⁹ /cm ^3. The dopant concentration in tunnel junction layer 147 is more preferably 5.0×10 ¹⁸ /cm ³ or higher and 9.0×10 ¹⁸ /cm ³ or lower. Since less diffusion of the dopant into the first active layer 144 and the second active layer 149 helps improve characteristics such as reliability, if quantum tunneling can be generated, it is preferable that the dopant concentration relative to the tunnel junction layer 147 is low.

<<p-type tunnel junction layer>>

The p-type dopant concentration in the p-type tunnel junction layer 1471 is preferably 1.0×10 ¹⁸ atoms/cm ³ or more and less than 1.0×10 ¹⁹ atoms/cm ³ , and more preferably 9.0×10 ¹⁸ atoms/cm ³ or less. The film thickness is preferably 5 nm or more and 100 nm or less.

<<n-type tunnel junction layer>>

The n-type dopant concentration in the n-type tunnel junction layer 1472 is preferably greater than or equal to 1.0×10 ¹⁸ atoms/cm ³ and less than or equal to 1.0×10 ¹⁹ atoms/cm ³ , and more preferably less than or equal to 9.0×10 ¹⁸ atoms/cm ³ . The film thickness is preferably greater than or equal to 5 nm and less than or equal to 100 nm.

<N-type intermediate layer between the tunnel junction layer and the second active layer>

An n-type interlayer is located between the tunnel junction layer 147 and the second active layer 149 (described later). The n-type interlayer can be undoped. The thickness between the tunnel junction layer 147 and the second active layer 149 is preferably 100 nm or less. Furthermore, the n-type interlayer preferably includes a spacer layer.

<Second partition layer>

A second spacer layer 148 may be provided on the tunnel junction layer 147, preferably with a thickness of 1 nm to 100 nm. The second spacer layer 148 may have the same composition as the n-type tunnel junction layer 1472 of the tunnel junction layer 147 or the barrier layer of the second active layer 149, or may have a composition that increases the band gap compared to the barrier layer. It is preferably an undoped layer (an undoped layer) that is not intentionally doped by flowing a raw material gas of an n-type dopant during growth. The second spacer layer 148 reduces diffusion of the n-type dopant from the n-type tunnel junction layer 1472 of the tunnel junction layer 147 into the second active layer 149.

A layer other than the second spacer layer 148 may be included between the second active layer 149 and the tunnel junction layer 147. In this case, the present invention can also suppress the dopant concentration in the tunnel junction layer 147 to a low level. Therefore, even if n-type dopant diffusion occurs from the n-type tunnel junction layer 1472, the n-type dopant concentration in the n-type intermediate layer can be kept below 5.0×10 ¹⁸ /cm ³ , for example. The total film thickness between the second active layer 149 and the tunnel junction layer 147 can also be suppressed to below 100 nm. By suppressing the amount of dopant diffusion and thus reducing the thickness of the layer, it is expected that the forward voltage of the entire device will be reduced.

<Second active layer>

A second active layer 149 containing Sb is disposed on the second spacer layer 148. The second active layer 149 preferably has the same structure as the first active layer 144. For example, FIG1 illustrates a quantum well structure in which the second active layer 149 includes a well layer comprising an InAs _x2 Sb _1-x2 layer (0<x2<1) serving as a light-emitting layer and a barrier layer comprising an InAs _y2 P _1-y2 layer (0<y2<1). The well layer 149w of the second active layer preferably has the same structure as the well layer 144w of the first active layer, and the barrier layer 149b of the second active layer preferably has the same structure as the barrier layer 144b of the first active layer. In addition, the first active layer 144 and the second active layer 149 have the same emission wavelength and have a wavelength region where the emission center wavelength is greater than or equal to 3000 nm.

<Second p-type electron blocking layer>

A second p-type electron blocking layer 150 comprising a III-V compound semiconductor layer may also be provided on the second active layer 149. The film thickness is preferably 5 nm to 60 nm. Examples of dopants that can be used here include Mg, Zn, C, and Be. The dopant concentration is preferably 1.0 × 10 ¹⁸ /cm ³ to 5.0 × 10 ¹⁸ /cm ^3. The second p-type electron blocking layer 150 injects and confines carriers into the second active layer 149. Furthermore, the second p-type electron blocking layer 150 also reduces diffusion of dopants from the second p-type window layer 151 into the second active layer 149.

The composition of the second p-type electron blocking layer 150 is preferably Al _z2 In _1-z2 As (0.05 ≤ z2 ≤ 0.4), more preferably Al _z2 In _1-z2 As (0.10 ≤ z2 ≤ 0.35). This is because by setting the Al composition z2 to 0.05 or greater, the luminescence efficiency of the second p-type electron blocking layer 150 can be improved, while by setting the Ak composition z2 to 0.40 or less, the decrease in luminescence efficiency caused by an increase in forward voltage can be suppressed. Furthermore, the p-type dopant concentration in the second p-type electron blocking layer 150 is preferably lower than the p-type dopant concentration in the p-type tunnel junction layer 1471.

<Second p-type window layer>

A second p-type window layer 151 comprising a III-V compound semiconductor layer can also be provided on the second p-type electron blocking layer 150, preferably with a thickness of at least 500 nm and no more than 2000 nm. If the second p-type window layer 151 is thicker, the current spreads to the ends of the light-emitting diode (LED) chip, increasing surface recombination. Furthermore, the ohmic resistance of the device increases, thereby reducing luminous efficiency, which is undesirable. On the other hand, if the second p-type window layer 151 is thinner, light emission occurs directly below the electrode, hindering light extraction, which is undesirable. Examples of dopants that can be used in this regard include Mg, Zn, C, and Be. The dopant concentration of the second p-type window layer 151 is preferably greater than or equal to 1.0×10 ¹⁸ atoms/cm ³ and less than or equal to 5.0×10 ¹⁸ atoms/cm ³ .

<p-type contact layer>

A p-type contact layer 152 comprising a III-V compound semiconductor layer may be provided on the second p-type window layer 151. The thickness is preferably between 20 nm and 300 nm. The dopant concentration of the p-type contact layer 152 is preferably higher than that of the second p-type window layer 151, and is between 8.0 × 10 ¹⁸ atoms/cm ³ and 3.0 × 10 ¹⁹ atoms/cm ³ .

The following describes an example embodiment of the method for manufacturing the optical semiconductor device 100 described so far. When the growth substrate 105 is n-type or undoped, the optical semiconductor device 100 is fabricated by sequentially epitaxially growing a first active layer 144, a tunnel junction layer 147 comprising InAs, and a second active layer 149. Here, the first active layer 144 and the second active layer 149 contain Sb, and the tunnel junction layer 147 comprises a p-type tunnel junction layer 1471 formed of a p-type InAs layer and an n-type tunnel junction layer 1472 formed of an n-type InAs layer, stacked vertically. The first active layer 144 faces the p-type tunnel junction layer 1471, and the n-type tunnel junction layer 1472 faces the second active layer 149. In addition, the dopant concentration of the tunnel junction layer 147 is greater than or equal to 1.0×10 ¹⁸ atoms/cm ³ and less than or equal to 1.0×10 ¹⁹ atoms/cm ³ .

A first p-type electron blocking layer 145 or a first p-type window layer 146 with a total thickness of 100 nm or less may be formed between the first active layer 144 and the tunnel junction layer 147. Furthermore, an undoped second spacer layer 148 with a thickness of 100 nm or less may be formed between the tunnel junction layer 147 and the second active layer 149.

Furthermore, one or more layers of the n-type contact layer 141, n-type window layer 142, and first spacer layer 143 may be formed between the growth substrate 105 and the first active layer 144. One or more layers of the second p-type electron blocking layer 150, first p-type window layer 151, and p-type contact layer 152 may also be formed on the second active layer.

On the other hand, if the growth substrate 105 used for epitaxially growing the semiconductor layers of the semiconductor integrated circuit 140 is p-type, the second active layer 149, tunnel junction layer 147, and first active layer 144 are sequentially formed on the growth substrate 105. At this point, the second active layer 149 faces the n-type tunnel junction layer 1472, and the p-type tunnel junction layer 1471 faces the first active layer 144.

Each semiconductor layer can be formed by epitaxial growth, for example, by a well-known thin film growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). For example, by using trimethylindium (TMIn) as an In source, trimethylgallium (TMGa) or triethylgallium (TEGa) as a Ga source, trimethylaluminum (TMAl) as an Al source, hydrogen arsenide ( _AsH3 ) or tertiary butylarsenic (TBAs) as an As source, trimethylantimony (TMSb), triethylantimony (TESb), or tris-dimethylaminoantimony (TDMASb) as a Sb source, and phosphine ( _PH3 ) or tertiary butylphosphine (TBP) as a P source in a predetermined mixing ratio, and using a carrier gas to perform vapor phase growth of these raw material gases, a desired thickness can be formed by adjusting the growth time. To dope each layer to p-type or n-type, the desired dopant source gas can be used. For example, when doping with Zn, DEZn (diethylzinc) gas can be used. Furthermore, InAs is also n-type when undoped.

In Figure 1, a lower electrode 195 is provided on the back surface of the growth substrate 105. Furthermore, an upper electrode 191 is provided on a portion of the p-type contact layer 152. Upper electrode 191 may also include an ohmic electrode wiring portion and a pad portion. Although not shown, the pad portion may also include a metal layer or solder for bonding. The metal materials and formation methods used for upper electrode 191 and lower electrode 195 can be known. Examples of usable metal materials include Ti, Pt, Au, Ag, Al, Zn, and Ni.

When a forward voltage is applied from upper electrode 191 to lower electrode 195, a forward voltage is applied to first active layer 144 and second active layer 149, causing both to emit light. At this time, a reverse voltage is applied to the tunnel junction (pn junction) in tunnel junction layer 147. This causes current to flow through tunnel junction layer 147 due to the tunnel effect.

(Second implementation form)

Referring to FIG. 2 , an optical semiconductor device 200 according to a second embodiment of the present invention will be described. Optical semiconductor device 200 is a junction-type optical semiconductor device obtained by bonding a support substrate and then removing the growth substrate. Components identical to those of optical semiconductor device 100 are generally assigned the same reference numerals in the last two digits of the three-digit number, and repeated descriptions will be omitted. The optical semiconductor device 200 includes at least a supporting substrate 280, a metal bonding layer 279 and a metal reflective layer 271 disposed on the surface of the supporting substrate 280, a power distribution unit 260 having a transparent insulating layer 261 with a through hole and an ohmic electrode portion 265 disposed in the through hole on the metal reflective layer 271, and a semiconductor integrated circuit 240 disposed on the power distribution unit 260.

The semiconductor multilayer 240 in the optical semiconductor device 200 in Figure 2 includes, starting from the side opposite the supporting substrate 280, an n-type contact layer 241, an n-type window layer 242, a first spacer layer 243, a first active layer 244, a first p-type electron blocking layer 245, a first p-type window layer 246, a tunnel junction layer 247, a second spacer layer 248, a second active layer 249, a second p-type electron blocking layer 250, a second p-type window layer 251, and a p-type contact layer 252.

Support substrate 280, separate from the growth substrate, is preferably inexpensive and has higher thermal conductivity than the growth substrate. For example, compound substrates such as Si, Ge, and GaAs can be used. Alternatively, a metal substrate using a metal with a low thermal expansion coefficient, such as copper alloy, molybdenum, tungsten, or Kovar nickel cobalt, or a submount substrate with a metal attached to a ceramic substrate, such as AlN, can be used. In terms of processability and cost, a Si substrate is also preferred for support substrate 280.

An example embodiment of the optical semiconductor device 200 and its manufacturing method will be described in more detail below with reference to Figures 3 to 5. First, a growth substrate 205 is prepared. Then, referring to Figure 3 , a semiconductor multilayer body 240 is formed. At this time, an etch stop layer (not shown) may be formed on the growth substrate 205. Semiconductor multilayer body 240 is similar to semiconductor multilayer body 140 described above.

<Formation of the Power Distribution Department>

A power distribution section 260 is formed on the p-type contact layer 252. This section includes a transparent insulating layer 261 having a through-hole and an ohmic electrode section 265 disposed in the through-hole. The specific method for forming the power distribution section 260 is arbitrary. An example of a specific embodiment of forming the power distribution section 260 is described below with reference to Figures 4 and 5.

First, a transparent insulating layer 261 is formed on the semiconductor integrated circuit 240. This layer formation can be accomplished using known methods such as plasma chemical vapor deposition (CVD) or sputtering. A resist pattern for the power distribution section is then formed on the transparent insulating layer 261 using a photomask. The resist pattern is then used to etch away a portion of the transparent insulating layer 261 to form a through-hole. This through-hole exposes a portion of the outermost surface of the semiconductor integrated circuit 240. Afterwards, the ohmic electrode portion 265 is formed, and then stripped using a resist pattern to form the power distribution portion 260. A transparent insulating layer 261 and the ohmic electrode portion 265 are arranged side by side on the power distribution portion 260. Furthermore, while the ohmic electrode portion 265 is shown filling the through-hole for simplicity in the diagram, this is not limiting; a gap may also be created between the transparent insulating layer 261 and the ohmic electrode portion 265.

The ohmic electrode portion 265 can be formed by dispersing the electrodes in a predetermined pattern in an island-like pattern. Materials such as Au, AuZn, AuBe, and AuTi can be used for the ohmic electrode portion 265, and a laminated structure of these materials is preferred. For example, Ti/Au can be used for the ohmic electrode portion 265. The film thickness (or total film thickness) of the ohmic electrode portion 265 is not limited and can be, for example, 300 nm to 1300 nm, more preferably 350 nm to 800 nm.

<Formation of Metal Reflective Layer>

As shown in FIG4 , a metal reflective layer 271 is preferably formed on the power distribution unit 260. The metal reflective layer 271 may include multiple metal layers. Besides Au, the metal constituting the metal reflective layer 271 may also include Al, Pt, Ti, Ag, and the like. For example, the metal reflective layer 271 may be a single layer containing only Au, or may include two or more Au metal layers. The metal reflective layer 271 preferably contains at least 50% by mass of Au. In order to reliably bond with the metal bonding layer 279 in subsequent steps, it is preferable to set the outermost layer of the metal reflective layer 271 (the surface opposite to the semiconductor integrated circuit body 240) as an Au metal layer.

For example, metal reflective layer 271 can be formed by depositing metals in the order of Al, Au, Pt, and Au on power distribution unit 260 (including the gap if provided). The thickness of the Au1 layer in metal reflective layer 271 can be set, for example, to 400 nm to 2000 nm, and the thickness of metal layers containing metals other than Au can be set, for example, to 5 nm to 200 nm. Metal reflective layer 271 can be formed using a common method such as evaporation.

<Bonding with the supporting substrate>

Referring to Figure 4 , the bonding to the support substrate 280 will be described. At least the semiconductor integrated circuit 240 and the power distribution unit 260 are bonded to the support substrate 280 via the metal bonding layer 279. The metal reflective layer 271 can be provided to bond the metal reflective layer 271 to the metal bonding layer 279. The metal bonding layer 279 and the metal reflective layer 271 are positioned facing each other, bonded together, and then heat-compression-bonded at a temperature of approximately 250°C to 500°C.

<Metal bonding layer>

Metal bonding layer 279 can be formed using metals such as Ti, Pt, Au, or metals that form a eutectic alloy with Au (such as Sn), or solder. Preferably, these layers are stacked to form metal bonding layer 279. For example, starting from the surface of support substrate 280, Ti can be stacked to a thickness of 400nm to 800nm, Pt to a thickness of 5nm to 20nm, and Au to a thickness of 700nm to 1200nm. For example, when bonding metal reflective layer 271 and metal bonding layer 279, the outermost layer of metal bonding layer 279 can be made of Au, and the outermost layer of metal reflective layer 271 can also be made of Au, thereby achieving bonding between the Au layers based on Au-Au diffusion.

<Supporting substrate>

The support substrate 280 can be any type of substrate, as long as it is different from the growth substrate 205. Submount substrates based on the previously described semiconductor substrates, metal substrates, or ceramic substrates can be used. Because of the bonding method described above, the support substrate 280 can be lattice-mismatched with the semiconductor layers formed in this embodiment. Furthermore, while the support substrate 280 can be insulating depending on the application, a conductive substrate is preferred. For processability and cost, a Si substrate is preferred for the support substrate 280. Using a Si substrate significantly reduces the thickness of the support substrate 280 compared to conventional substrates, making it suitable for mounting in combination with various semiconductor devices. Si substrates also offer advantages in heat dissipation compared to InAs substrates.

<Removal of Growth Substrate>

The removal of the growth substrate is described with reference to Figure 5 . After bonding the support substrate 280, the growth substrate 205 is removed. If the growth substrate 205 is a GaAs substrate, for example, wet etching can be performed on the growth substrate 205 using an ammonia-hydrogen peroxide mixture. If an etch stop layer is used, it can be removed sequentially after the growth substrate 205 is removed. Alternatively, by leaving a portion of the etch stop layer, it can be used as an n-type contact layer to reduce the contact resistance to the upper electrode 291.

Furthermore, as shown in FIG2 , an upper electrode 291 can be formed on the semiconductor multilayer 240, and a back electrode 295 can be formed on the back surface of the support substrate 280. The upper electrode 291 can also include a wiring portion and a pad portion. The upper electrode 291 and the back electrode 295 can be formed using known methods, such as sputtering, electron beam evaporation (also referred to as evaporation), or resistance heating. In addition to methods using metal masks, there are also methods that combine photolithography, lift-off, and metal etching to form the electrode patterns.

The above manufacturing method can produce the optical semiconductor device 200 shown in Figure 2. These embodiments are examples and are not limiting. Gradients can be provided on the device's side surfaces during mesa etching, and the electrode shape can be a top-surface double electrode or a flip-chip configuration, which can be modified as appropriate.

(Third implementation form)

Next, referring to Figure 6 , an optical semiconductor device 300 according to a third embodiment of the present invention will be described. The third embodiment further forms a tunnel junction layer and an active layer on the second p-type window layer of the first embodiment. Specifically, the semiconductor light-emitting device of Figure 6 includes a second tunnel junction layer 352, a third active layer 354, a third tunnel junction layer 357, and a fourth active layer 359, in that order, on the second p-type window layer. Details of each structure are described below.

Similar to the tunnel junction layer 147 of the first embodiment, the second tunnel junction layer 352 includes a p-type InAs layer 3521 and an n-type InAs layer 3522. Furthermore, the p-type InAs layer 3521 faces the second active layer, while the n-type InAs layer 3522 faces the third active layer 354. The second tunnel junction layer 352 may have the same composition and thickness as the first tunnel junction layer, or may have different thicknesses.

Like the first active layer, the third active layer 354 includes an InAs _x3 Sb _1-x3 layer (0<x3<1) as a light-emitting layer and has the same emission wavelength as the first active layer. Furthermore, the third active layer 354 may have the same composition and thickness as the first active layer, or may have different compositions and thicknesses.

Similar to the tunnel junction layer 147 of the first embodiment, the third tunnel junction layer 357 includes a p-type InAs layer 3571 and an n-type InAs layer 3572. Furthermore, the p-type InAs layer 3571 faces the third active layer 354, while the n-type InAs layer 3572 faces the fourth active layer 359. The third tunnel junction layer 357 may have the same composition and thickness as the first tunnel junction layer, or may have different compositions and thicknesses.

Like the first active layer, the fourth active layer 359 includes an InAs _x4 Sb _1-x4 layer (0<x4<1) as a light-emitting layer and has the same emission wavelength as the first active layer. Furthermore, the fourth active layer 359 may have the same composition and thickness as the first active layer, or may have different compositions and thicknesses.

The layer above the fourth active layer 359 has the same structure as the layer above the second active layer 149 in the first embodiment.

In the third embodiment, the following embodiment is described: a second tunnel junction layer 352, a third active layer 354, a third tunnel junction layer 357, and a fourth active layer 359 are formed on the second electron blocking layer, forming a total of three tunnel junction layers and a total of four active layers. In this embodiment, instead of the embodiment shown in FIG6 , a total of N tunnel junction layers (N is an integer greater than or equal to 3) can be formed, and a total of (N+1) active layers can be formed. For example, a total of two tunnel junction layers can be formed, and a total of three active layers can be formed, or a total of four tunnel junction layers can be formed, and a total of five active layers can be formed. The embodiment shown in FIG6 is a specific example where N is 3. In this case, the dopant concentration of each tunnel junction layer is also 1×10 ¹⁸ atoms/cm ³ or more and 1×10 ¹⁹ atoms/cm ³ or less, the center wavelength of each active layer is 3000 nm or more, and the wavelengths of each active layer are the same.

(Fourth embodiment: light receiving element)

The fourth embodiment of the optical semiconductor light receiving element according to the present invention will be described. For example, by replacing the first active layer 144 and the second active layer 149 in the first embodiment with an InAsSb first light absorption layer and an InAsSb second light absorption layer, the optical semiconductor element of the present invention can be used as an optical semiconductor light receiving element. Furthermore, because the semiconductor light receiving element according to the present invention has two absorption layers separated by a tunnel junction layer, it can achieve a semiconductor light receiving element with reduced dark current, higher shunt resistance, and better characteristics compared to a single absorption layer.

[Example]

[Experimental Example 1]

(Example 1)

Using MOCVD, a high-dopant (Te concentration 1.0×10 ¹⁹ /cm ³ ) n-type InAs contact layer (thickness: 0.3 μm), a Te-doped n-type InAs window layer (thickness: 4.9 μm, Te concentration 3.0×10 ¹⁸ /cm ³ ), and an undoped InAs spacer layer (thickness: 75 nm) were first formed on the (100) surface of a Si-doped n-type GaAs growth substrate (substrate thickness: 350 μm). Next, a first active layer (total thickness: 430 nm) with a quantum well structure emitting at a central wavelength of 4300 nm was formed. The active layer of the quantum well structure is composed of 10 layers of undoped InAs _0.90 P _0.10 barrier layers (thickness: 30nm) and InAs _0.87 Sb _0.13 well layers (thickness: 10nm) alternately stacked in sequence. Then, the InAs _0.90 P _0.10 barrier layer is grown, with the final barrier layer included in the total number of 10.5 layers. A Zn-doped p-type Al _0.32 In _0.68 As electron blocking layer (thickness: 15 nm, Zn concentration 2.5 × 10 ¹⁸ /cm ³ ) and a Zn-doped p-type InAs window layer (thickness: 50 nm, Zn concentration 2.5 × 10 ¹⁸ /cm ³ ) were formed on the first active layer, and a tunnel junction layer was formed thereon.

The tunnel junction layer is formed by forming a Te-doped InAs layer (50 nm thickness, 8 × 10 ¹⁸ /cm ³ Te concentration during growth) on a Zn-doped InAs layer (50 nm thickness, 8 × 10 ¹⁸ /cm ³ Zn concentration during growth). This enables tunneling effects at these interfaces. Growth of the tunnel junction layer is performed at a pressure of 50 Torr using a raw material gas with a ratio of Group V to Group III elements (V/III ratio) of 50.

Next, an undoped InAs spacer layer (75nm thick) was formed on the tunnel junction layer, and a second active layer (430nm thick) identical to the first active layer was formed thereon. A Zn-doped p-type Al _0.32 In _0.68 As electron blocking layer (15nm thick, Zn concentration 2.5×10 ¹⁸ /cm ³ ) was formed on the second active layer. Furthermore, a Zn-doped p-type InAs window layer (thickness: 900 nm, Zn concentration 2.5×10 ¹⁸ /cm ³ ) was formed, and a p-type InAs contact layer (thickness: 100 nm) with a high dopant concentration (Zn concentration 1.0×10 ¹⁹ /cm ³ ) was formed thereon.

Table 1 below lists the composition and thickness of each layer, the type of dopant, the (designed) dopant concentration during growth, and the dopant concentration obtained by SIMS analysis, including dopant diffusion after all epitaxial growth was completed and removed from the MOCVD apparatus. The raw material gases used to form each layer were trimethylindium (TMIn) as an In source, trimethylgallium (TMGa) as a Ga source, trimethylaluminum (TMAl) as an Al source, hydrogen arsenide ( _AsH3 ) as an As source, triethylantimony (TESb) as a Sb source, and phosphine ( _PH3 ) as a P source. In addition, DEZn (diethylzinc) and DETe (diethyltellurium) were used as dopant gases.

The composition of each layer was determined using a BRUKER JV-QC3 X-ray diffractometer (XRD). The composition of each layer was calculated by fitting using analytical software (Jordan Valley RADS). The thickness of each layer was calculated based on cross-sectional observation of the grown layer using a SEM (scanning electron microscope) or a TEM (transmission electron microscope).

[Table 1]

Next, a transparent insulating layer composed of _SiO2 (550nm thick) was formed entirely on the p-type InAs contact layer using plasma CVD. A power distribution pattern was formed on top using an etchant, and the _SiO2 in the areas not covered by the etchant was removed by etching, exposing the Zn-doped p-type InAs contact layer. Next, Ti (thickness: 10nm) and Au (thickness: 530nm) were deposited by evaporation to form the ohmic metal portion. The resist in the power distribution pattern was removed along with the metal deposited thereon, leaving only the ohmic metal portion formed on the exposed Zn-doped p-type InAs contact layer. This resulted in a power distribution portion with the ohmic metal portion and the transparent insulating film arranged in parallel. Next, a metal reflective layer (Al (thickness: 10nm)/Au (thickness: 650nm)/Pt (thickness: 100nm)/Au (thickness: 900nm)) was deposited by evaporation in the shape of the power distribution portion.

Next, a metal bonding layer (Ti (thickness: 650nm)/Pt (thickness: 20nm)/Au (thickness: 900nm)) was formed on the support substrate (Si substrate) by evaporation. The metal reflective layer and the metal bonding layer were then placed facing each other and bonded by heat and compression at 300°C. The growth substrate was then wet-etched using an ammonia-hydrogen peroxide mixture to remove the n-type contact layer. Next, Ti (thickness: 150nm)/Au (thickness: 1250nm) was deposited on the n-type contact layer by evaporation, forming an n-type ohmic electrode. Next, a pad electrode (Ti (thickness: 150nm)/Pt (thickness: 100nm)/Au (thickness: 2500nm)) was formed on the n-type ohmic electrode using evaporation. The n-type ohmic electrode and pad electrode were then combined to form the upper electrode. Furthermore, a lift-off method using an etchant was used to pattern the electrode.

Next, the semiconductor laminate between each element (width: 60μm) is removed by mesa etching to form a cutting line. Then, a back electrode (Ti (film thickness: 10nm)/Pt (film thickness: 50nm)/Au (film thickness: 200nm)) is formed on the back side of the supporting substrate by evaporation and heat treated at 300°C for 1 minute to perform alloying. Next, the entire wafer is immersed in a nitric acid solution maintained at 8°C±1°C for 5 seconds to roughen the surface of the semiconductor laminate outside the area where the upper electrode is formed. Thereafter, it is immersed in ammonia water for 1 minute and then cleaned with pure water for 1 minute. Finally, the wafer is singulated by dicing to produce the optical semiconductor element of Example 1. Furthermore, the chip size is 500μm×500μm.

Figure 7 is a graph showing the results of secondary ion mass spectroscopy (SIMS) measurements of the Te ion diffusion state in the optical semiconductor device fabricated in Example 1. In Figure 7 , the horizontal axis represents depth (μm), the vertical axis on the left represents the concentration (atoms/cm ³ ) of the n-type dopant (here, Te, Si, C, H, and O), and the vertical axis on the right represents the secondary ion intensity of Sb (counts/sec). In Example 1, the maximum concentration of Te, the n-type dopant doped in the semiconductor laminate 140, was 8.0×10 ¹⁸ atoms/cm ³ . The maximum value is observed at the location corresponding to the n-type tunnel junction layer, where Te is observed to diffuse from the n-type tunnel junction layer toward the undoped spacer layer and the initial barrier layer. However, even though the Te concentration in the spacer layer and the initial barrier layer increases due to diffusion, it remains below 4.0×10 ¹⁸ atoms/cm ³ , which is within the optimal Te concentration range.

Figure 8 is a graph showing the results of SIMS measurements of the Zn ion diffusion state in the optical semiconductor device fabricated in Example 1. In Figure 8 , the horizontal axis represents depth (μm), the vertical axis on the left represents the concentration of the p-type dopant (in this case, Zn) (atoms/cm ³ ), and the vertical axis on the right represents the secondary ion intensity (counts/sec). In Example 1, the maximum concentration of Zn, the p-type dopant doped in the semiconductor laminate 140, was 6.0×10 ¹⁸ atoms/cm ³ . The maximum value is located at the p-type tunnel junction layer, where Zn diffusion is observed from the p-type tunnel junction layer toward the p-type window layer and electron barrier layer. However, even though the Zn concentration in the p-type window layer and electron barrier layer increases due to diffusion, it remains below 5.0×10 ¹⁸ atoms/cm ³ , which is within the optimal Zn concentration range.

(Example 2)

The various semiconductor layers were epitaxially grown in the same manner as in Example 1 up to the second active layer. Next, a second tunnel junction layer, a third active layer, a third tunnel junction layer, and a fourth active layer were sequentially formed on the second active layer. Similarly to the second active layer in Example 1, an electron blocking layer, a p-type window layer, and a p-type contact layer were sequentially formed on the fourth active layer. The third and fourth active layers had the same film thickness and composition as the first active layer, and the second and third tunnel junction layers had the same film thickness and composition as the first tunnel junction layer. Here, electron blocking layers with the same film thickness and composition as the electron blocking layer located between the first active layer and the first tunnel junction layer are formed between the second active layer and the second tunnel junction layer, and between the third active layer and the third tunnel junction layer. Furthermore, spacer layers with the same film thickness and composition as the spacer layer located between the first tunnel junction layer and the second active layer are formed between the second tunnel junction layer and the third active layer, and between the third tunnel junction layer and the fourth active layer. Table 2 below reports the composition and thickness of each layer, as well as the type of dopant and dopant concentration during growth, and dopant concentrations obtained by SIMS analysis, including dopant diffusion. The dopant concentration can be limited to a preferred range of diffusion amount by causing the same diffusion as in Example 1.

[Table 2]

(Comparative example 1)

An optical semiconductor device of Comparative Example 1 was obtained in the same manner as in Example 1, except that the thickness of the second active layer was changed from 430 nm to 0 nm, the thickness of the spacer layer above the tunnel junction layer was changed from 75 nm to 0 nm, the thickness of the Te-doped InAs layer in the tunnel junction layer was changed from 50 nm to 0 nm, the thickness of the Zn-doped InAs layer in the tunnel junction layer was changed from 50 nm to 0 nm, the thickness of the electron blocking layer below the tunnel junction layer was changed from 15 nm to 0 nm, and the number of well layers and barrier layers in the quantum well structure of the first active layer was set to 20.5 pairs (total thickness: 860 nm).

<Evaluation: Luminous output power evaluation>

A constant current voltage source was used to flow a current of 100 mA through the photoconductor devices obtained in the Examples and Comparative Examples. The forward voltage Vf (V) and the luminous output power Po (W) from the integrating sphere were measured. Furthermore, the leakage current (A) was measured when a reverse voltage of -0.1 V was applied. The results are shown in Table 3.

Based on the above results, it is confirmed that by increasing the number of PN junctions (active layers) and tunnel junctions, the luminous output power and forward voltage increase, thereby reducing the leakage current.

The present invention provides an optical semiconductor device comprising two or more active layers containing Sb, sandwiched between a tunnel junction layer containing InAs, and a method for manufacturing the same.

100: Optical semiconductor components

105: Growth substrate

140: Semiconductor integrated circuits

141: n-type contact layer

142: n-type window layer

143: First spacer layer

144: First active layer

144b: Barrier layer of the first active layer

144w: Well layer of the first active layer

145: First p-type electron blocking layer

146: First p-type window layer

147: Tunnel Layer

148: Second spacer layer

149: Second active layer

149b: Barrier layer of the second active layer

149w: Well layer of the second active layer

150: Second p-type electron blocking layer

151: Second p-type window layer

152: p-type contact layer

191: Upper electrode

195:Lower electrode

Claims (7)

A photo-semiconductor element comprises a first active layer that receives/emit light at a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer that receives/emit light at a second wavelength. In the photo-semiconductor element, the first active layer and the second active layer contain Sb, the tunnel junction layer comprises a p-type InAs layer and an n-type InAs layer, the p-type InAs layer is provided on the first active layer side of the tunnel junction layer, a p-type electron blocking layer is provided between the first active layer and the tunnel junction layer, and the film thickness between the first active layer and the tunnel junction layer is less than 100 nm. The optical semiconductor device according to claim 1, wherein the dopant concentration in the tunnel junction layer is greater than or equal to 1.0×10 ¹⁸ atoms/cm ³ and less than 1.0×10 ¹⁹ atoms/cm ³ . The optical semiconductor device according to claim 1 or 2, wherein the first active layer and the second active layer have a quantum well structure, and the first wavelength and the second wavelength are greater than or equal to 3000 nm. An optical semiconductor element as described in claim 1 or 2, wherein the first wavelength and the second wavelength are the same as each other. The optical semiconductor element according to claim 1 or 2, wherein the n-type InAs layer is provided on the second active layer side of the tunnel junction layer, a spacer layer is provided between the tunnel junction layer and the second active layer, and the film thickness between the tunnel junction layer and the second active layer is 100 nm or less. A method for manufacturing an optical semiconductor element includes the following steps: forming a first active layer on a substrate that receives/emit light at a first wavelength; forming a tunnel junction layer on the first active layer; and forming a second active layer on the tunnel junction layer that receives/emit light at a second wavelength, wherein the first active layer and the second active layer contain Sb. The step of forming the tunnel junction layer includes forming an n-type InAs layer, forming a p-type InAs layer on the n-type InAs layer and on a side of the first active layer, and forming a p-type electron blocking layer with a film thickness of less than 100 nm between the first active layer and the tunnel junction layer. The method for manufacturing an optical semiconductor device according to claim 6, wherein the dopant concentration in the tunnel junction layer is greater than or equal to 1.0×10 ¹⁸ atoms/cm ³ and less than 1.0×10 ¹⁹ atoms/cm ³ .