TWI898621B - Circuit test system and method thereof - Google Patents

Abstract

The present invention provides a circuit test system and its method thereof, which utilizes a conversion unit to convert an input signal into a communication format signal, decodes the communication format signal and generates a control command signal through a control unit according to the pattern of the communication format signal, and controls the circuit to be tested to perform an in-built test to test whether there is a defect in the circuit to be tested by the control command signal, utilizing the system and its method of the present invention. By using the system and method of the present invention, it is not necessary to change the communication format of the input signals according to the type of the circuits to be tested, so as to minimize the difficulty of data input, and at the same time, reduce the difficulty of error debugging.

Description

Circuit testing system and method thereof

The present invention relates to a circuit testing system and method thereof, and in particular to a circuit testing system and method thereof that does not require input signal conversion according to the type of circuit to be tested.

Traditionally, testers have to write their own firmware control, which results in a significant amount of time spent writing and debugging each subsequent model test. Testers also need extensive training in firmware control writing and the fundamentals of related communication formats. The lack of standardized writing standards creates difficulties during debugging, creating inconvenience for testers. Different interfaces require different transmission formats, necessitating constant firmware modifications based on these interfaces.

Early self-test technologies were limited by additional design costs and insufficient test error coverage, making them virtually unusable. Furthermore, traditional integrated circuit built-in self-test technology was limited to testing digital logic circuits. However, with increasing design complexity, a system-on-a-chip (SoC) no longer consists solely of digital logic circuits, but also incorporates a significant number of analog or mixed-signal circuits. This not only requires innovation in manufacturing technology, but also presents numerous design challenges, such as noise speed and power consumption. Consequently, the difficulty and complexity of testing have also increased. Because single-chip systems have many registers, testing time is also extended. Even using the latest full scan technology, it still requires a long test application time, making the testing cost high.

Conventional test equipment (ATE) cannot provide the fast test signals and storage memory for the large number of test patterns required by current single-chip systems. Even if they did, high-speed and high-capacity test equipment would be very expensive and limited by the available pins on integrated circuits. Therefore, it is impossible to find all errors in an integrated circuit.

At-speed testing is also a difficult aspect of single-chip system testing. Therefore, built-in self-test technology for digital logic circuits and analog/mixed-signal circuits has become a hot topic of discussion.

Traditional digital integrated circuits (DICs) feature built-in self-test circuitry, which can be tested using boundary scanning or vector generation from an automatic test vector generation circuit. This type of testing essentially connects all DUTs together, generating one or more scan chains. Typically, a state machine is deployed within the DUT to generate and analyze the required test vectors. When operating in test mode, the tester serially scans in the test vector data, adds one or more functional clock cycles, and then scans out the captured response data.

Engineers store test patterns generated by automatic test pattern generation (ATPG) in memory. By scanning the input and output data of these memory elements, engineers provide sufficient control and observability. However, the disadvantage is that fault assessment (fault grade) of the circuit under test usually cannot be performed until the circuit under test is nearly complete, which reduces verification performance. Furthermore, the size of the memory in the built-in self-test circuit directly affects the controllability and observability of the boundary scan test circuit.

The key advantage of built-in self-test (BIST) technology is that test pattern generation and test result verification are largely performed within the chip, significantly reducing the cost of test equipment. Furthermore, internal testing allows for simultaneous verification of signals or design parameters within both analog and mixed-signal digital circuits, without being limited by the number of output and input pins. Therefore, test time does not necessarily increase linearly with the number of bits. This increases the verifiability and testability of module circuits, significantly reducing verification and testing costs and effectively resolving the challenges of testing analog, mixed-signal, and module circuits within single-chip systems. For the increasingly complex single-chip systems of the future, BIST circuitry is a valuable measurement tool.

However, since the built-in self-test circuits (BISTs) of various types of circuits under test (CUTs) currently utilize different communication formats, performing built-in tests using BISTs requires the tester to be familiar with and able to write firmware controls for each communication format. Furthermore, debugging is significantly more difficult because each CUT utilizes a different communication format.

Therefore, providing a circuit testing system and method with a unified communication format is a problem that technicians in this field want to solve.

One purpose of the present invention is to provide a circuit testing system comprising a conversion unit, a control unit, and a circuit under test. The system utilizes the conversion unit to convert input signals to accommodate various circuit communication formats. This allows testers to control integrated circuits through the control unit to perform built-in tests without having to learn various communication formats. This also reduces debugging effort and eliminates the need for repeated modification of the control firmware for different interfaces.

In view of the above-mentioned purpose, the present invention provides a circuit testing system, which is applied to control a circuit under test to execute a built-in test software, comprising: a conversion unit, which receives an input signal, the input signal corresponding to the circuit under test and a test item of the circuit under test, the conversion unit converts the input signal into a communication format signal through a conversion method, the communication format signal including a mode; and a control unit, which is connected to the conversion unit and the circuit under test. The control unit determines the mode of the communication format signal and executes a decoding method corresponding to the mode to decode the communication format signal and generate a corresponding control command signal. The control command signal is used to control the circuit under test to perform the built-in test. This allows testers to control the integrated circuit to perform built-in tests through the control unit without having to learn various communication formats. This also reduces the difficulty of debugging and eliminates the need for repeated modification of the control firmware according to different interfaces.

The present invention provides an embodiment, wherein the conversion method converts the input signal into the communication format signal through a mask corresponding to the circuit under test.

The present invention provides an embodiment, wherein the communication format signal is transmitted to the control unit in the form of a packet.

The present invention provides an embodiment, wherein the control unit receives the communication format signal via a USB, a universal asynchronous receiver/transmitter (UASRT) or a wireless communication.

The present invention provides an embodiment, wherein the built-in test is a test in which the circuit under test performs a self-test.

The present invention provides an embodiment, wherein the control unit further includes: a storage unit, which is used to store the communication format signal.

Another object of the present invention is to provide a circuit testing method that converts input signals into different communication formats through a conversion unit and transmits them to a control unit. The control unit then decodes the signals and controls the circuit under test to perform built-in tests. This eliminates the need to write commands in different communication formats for different circuits under test and also makes subsequent debugging easier.

In view of the above-mentioned purpose, the present invention provides a circuit testing method, the steps of which include: providing an input signal to a conversion unit, the input signal corresponding to a circuit to be tested and a test item of the circuit to be tested; the conversion unit converts the input signal through a conversion method and generates a communication format signal, the communication format signal includes a pattern; the conversion unit transmits the communication format signal to a control unit, the control unit The control unit determines the mode of the communication format signal and executes a decoding method corresponding to the mode to decode the communication format signal and generate a corresponding control command signal; and the control unit transmits the control command signal to a circuit under test, and the circuit under test executes a built-in test based on the control command signal. This eliminates the need to write different communication format instructions for different circuits under test and also makes subsequent debugging easier.

The present invention provides an embodiment, wherein the conversion method converts the input signal into the communication format signal through a mask corresponding to the circuit under test.

The present invention provides an embodiment, wherein the communication format signal is transmitted to the control unit in the form of a packet.

The present invention provides an embodiment, wherein the control unit receives the communication format signal via a USB, a universal asynchronous receiver/transmitter (UASRT) or a wireless communication.

The present invention provides an embodiment, wherein the built-in test is a test in which the circuit under test performs a self-test.

Therefore, a circuit testing system and method are provided to solve the problem that technicians in this field want to solve.

To help you gain a deeper understanding of the features and effects of this invention, we would like to provide you with a preferred embodiment and detailed explanations as follows:

In the past, integrated circuit testers had to write their own firmware control, which required a significant amount of time to write and debug each subsequent model test. This also required a significant amount of time to train testers in the ability to write firmware control and the fundamentals of the relevant communication formats. The lack of a unified writing standard made debugging firmware control difficult, creating inconvenience for testers. Furthermore, because different interfaces required different transmission formats, the control firmware had to be constantly modified to suit each interface.

The present invention converts an input signal into a communication format signal through a conversion unit, transmits the communication format signal to a control unit, decodes the communication format signal and generates a control command signal, and uses the control command signal to control the circuit under test to perform built-in tests. Using the conversion unit to convert the input signal eliminates the need for testers to learn various communication formats, reduces debugging difficulty, and eliminates the need for repeated modification of the control firmware based on different interfaces.

Hereinafter, the present invention will be described in detail by illustrating various embodiments of the present invention with reference to the drawings. However, the concept of the present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein.

First, please refer to FIG. 1 , which is a circuit test system architecture diagram of the present invention. As shown in the figure, the present invention provides a circuit test system 1, which includes: a conversion unit 10; and a control unit 20 connected to the conversion unit 10 and a circuit to be tested 30.

Continuing with the above, please refer to FIG. 2, which is a schematic diagram of the signal transmission of the circuit test system of the present invention. As shown in the figure, the conversion unit 10 receives an input signal 12, and the conversion unit 10 generates a communication format signal 14 through a conversion method. The communication format signal 14 includes a mode 142; the control unit 20 determines the mode 142 of the communication format signal 14, and executes a decoding method corresponding to the mode 142 to decode the communication format signal 14 and generate a corresponding control command signal 22; and the control command signal 2 2 is transmitted to the circuit under test 30. The control command signal 22 is used to control the circuit under test 30 to perform a built-in test 32. The input signal 12 corresponds to the circuit under test 30 and a test item of the circuit under test 30. This enables the conversion unit 10 to rewrite the input signal 12 into the communication format signal 14 according to the communication format of the circuit under test 30. In this way, the control unit 20 can use the control command signal 22 generated by decoding the communication format signal 14 to control the circuit under test 30 to perform the built-in test 32.

Continuing from the above, the input signal 12 corresponds to different circuits under test 30. The input signal 12 also corresponds to different test items of the circuits under test 30. That is, when the circuits under test 30 are different or when the circuits under test 30 are the same but different test items are being executed, the conversion unit 10 will receive different input signals 12 depending on the test items.

Continuing from the above, the communication format signal 14 is transmitted to the control unit 20 in the form of a packet.

Continuing from the above, the control unit 20 receives the communication format signal 14 via a USB, a universal asynchronous receiver/transmitter (UASRT) or a wireless communication.

Continuing from the above, the built-in test 32 is a test for the circuit under test 30 to perform a self-test, and is used to detect the signals or design parameters in the circuit under test 30, analog or hybrid circuit.

Continuing with the above, another embodiment is provided. Please refer to FIG. 3 , which is a system architecture diagram of another embodiment of the present invention. As shown in the figure, the control unit 20 further includes a storage unit 24. The storage unit 24 is used to store the communication format signal 14. When the circuit under test 30 is of a model or type that has been executed before, the communication format signal 14 can be directly extracted from the storage unit 24 without re-providing the input signal 12. The control command signal 22 can be generated and the circuit under test 30 can be controlled to execute the built-in test 32.

Continuing with the above, another embodiment is provided. Please refer to FIG. 4 , which is a schematic diagram of the conversion method of the present invention. The conversion method converts the input signal 12 into the communication format signal 14 through a mask 18 corresponding to the circuit under test 30. The mask 18 is used to apply Inti, CMD, DATA, and DCX to DATA, respectively, so that DATA changes as shown in FIG. 4 .

Next, a practical example is provided. Please refer to FIG. 5 , which is a schematic diagram of an embodiment of the present invention. As shown in the figure, the circuit test system 1 of the present invention is inputted into an compiler (the conversion unit 10) by inputting the input signal 12. The input signal 12 further includes a combination 122 (e.g., CMD, DATA) and an encoding method 124 (e.g., WriteFormatDefine). The compiler will execute the output signal according to the encoding method 124 (e.g., WriteFormatDefine). The combination 122 (e.g., CMD, DATA) is converted into the form of the communication format signal 14, and the communication format signal 14 is transmitted to the control unit 20. The control unit 20 decodes the communication format signal 14 according to the mode 142 of the communication format signal 14 and generates the control command signal 22. The control command signal 22 is used to control the circuit under test 30 to perform the built-in test 32.

In the embodiment described above, the present invention provides a circuit testing system. The conversion unit 10 utilizes the conversion method to convert the input signal 12 and generate the communication format signal 14. The control unit 20 receives the communication format signal 14 and decodes it according to the mode 142 to generate the control command signal 22. The control unit 20 controls the circuit under test 30 to perform the built-in test 32 based on the control command signal 22. This eliminates the need to modify the input signal 12 based on the different communication formats of the circuit under test 30. This makes subsequent debugging easier and significantly reduces the time required to train testers in firmware control programming. Testers only need to understand basic datasheet reading skills to control the circuit under test 30 to perform the built-in test 32 using the input signal 12.

Next, please refer to FIG. 6, which is a flow chart of the circuit testing method of the present invention. As shown in the figure, the present invention provides a circuit testing method as follows:

Step S10: providing an input signal to the conversion unit, wherein the input signal corresponds to the circuit to be tested and the test item of the circuit to be tested;

Step S20: The conversion unit converts the input signal through the conversion method and generates a communication format signal, wherein the communication format signal includes a mode;

Step S30: The conversion unit transmits the communication format signal to the control unit. The control unit determines the mode of the communication format signal and executes a decoding method corresponding to the mode to decode the communication format signal and generate a corresponding control command signal.

Step S40: The control unit transmits a control command signal to the circuit under test, and the circuit under test performs a built-in test according to the control command signal.

Continuing with the above, referring again to FIG. 2 and FIG. 5 , steps S10-S40 are described in detail as follows:

In step S10, the input signal 12 is provided to the conversion unit 10. The input signal 12 corresponds to the circuit under test 30 and a test item of the circuit under test 30. The input signal 12 corresponds to different circuits under test 30 and also corresponds to different test items of the circuit under test 30. In other words, when the circuits under test 30 are different or when the circuits under test 30 are the same but different test items are being executed, the conversion unit 10 will receive different input signals 12 depending on the test item.

In step S20, the conversion unit 10 converts the input signal 12 through the conversion method and generates the communication format signal 14. The communication format signal 14 includes the pattern 142. Referring again to FIG. 4 , the conversion method converts the input signal 12 into the communication format signal 14 through a mask 18 corresponding to the circuit under test 30. The mask 18 is used to apply Inti, CMD, DATA, and DCX to DATA, respectively, so that DATA changes as shown in FIG. 4 .

In step S30, the conversion unit 10 transmits the communication format signal 14 to the control unit 20. The control unit 20 determines the mode 142 of the communication format signal 14 and executes a decoding method corresponding to the mode 142 to decode the communication format signal 14 and generate the corresponding control command signal 22. The communication format signal 14 is transmitted to the control unit 20 in the form of a packet. The control unit 20 receives the communication format signal 14 through a universal serial bus, a universal asynchronous receiver and transmitter, or a wireless communication, but is not limited thereto.

Continuing from the above, as shown in FIG. 2 and FIG. 7, FIG. 7 is a schematic diagram of the decoding of the present invention. As shown in the figure, the control unit 20 executes step S31: After receiving the packet, it executes step S32: starts to determine the mode. After determining the mode 142, it executes step S33: executes the decoding method corresponding to the mode 142 according to the different modes, then executes step S34: generates the control command signal 22 to control the circuit under test 30 to execute the built-in test 32, and then executes step S35: determines whether there is a new packet. If so, repeats the above steps S31-step S35; if not, executes step S36: determines whether to shut down, if not, repeats step S35; if so, executes step S37: shuts down.

In step S40, the control unit 20 transmits the control command signal 22 to the circuit under test 30. The circuit under test 30 executes the built-in test 32 according to the control command signal 22. The built-in test 32 is a self-test of the circuit under test 30, which is used to detect signals or design parameters in the analog or hybrid circuit of the circuit under test 30.

Continuing with the above, another embodiment is provided. Please refer to FIG. 3 . As shown in the figure, the control unit 20 further includes a storage unit 24. The storage unit 24 is used to store the communication format signal 14. When the circuit under test 30 is of a model or type that has been executed before, the communication format signal 14 can be directly extracted from the storage unit 24 without re-providing the input signal 12. The control command signal 22 can be generated to control the circuit under test 30 to execute the built-in test 32.

Next, a practical example is provided. Please refer to FIG. 4, FIG. 6 and FIG. 8. FIG. 8 is a schematic diagram of data organization of the present invention. As shown in the figure, the circuit test system 1 of the present invention is inputted into an encoder (the conversion unit 10) by inputting the input signal 12. The input signal 12 further includes a combination 122 (such as CMD, DATA) and an encoding method (such as WriteFormatDefine). Then, the combination 122 (such as CMD, DATA) is organized into data, as shown in FIG. As shown, the data is converted into digital data and arranged to generate a conversion combination 1222. The compilation method (e.g., WriteFormatDefine) is used as a mask 18 to process the conversion combination 1222. Then, the communication format signal 14 is generated. The control unit 20 decodes the communication format signal 14 according to the mode 142 of the communication format signal 14 and generates the control command signal 22. The control command signal 22 is used to control the circuit under test 30 to execute the built-in test 32.

In the embodiment described above, the present invention provides a circuit testing system. The conversion unit 10 utilizes the conversion method to convert the input signal 12 and generate the communication format signal 14. The control unit 20 receives the communication format signal 14 and decodes it according to the mode 142 to generate the control command signal 22. The control unit 20 controls the circuit under test 30 to perform the built-in test 32 based on the control command signal 22. This eliminates the need to modify the input signal 12 based on the different communication formats of the circuit under test 30. This makes subsequent debugging easier and significantly reduces the time required to train testers in firmware control programming. Testers only need to understand basic datasheet reading skills to control the circuit under test 30 to perform the built-in test 32 using the input signal 12.

Therefore, this invention is novel, progressive, and industrially applicable, and should undoubtedly meet the patent application requirements under Taiwan's Patent Law. Therefore, we have filed an invention patent application in accordance with the law and pray that the Bureau will approve the patent as soon as possible. I am deeply grateful for your prayers.

However, the above description is only a preferred embodiment of the present invention and is not intended to limit the scope of implementation of the present invention. All equivalent changes and modifications based on the shape, structure, characteristics and spirit described in the patent application scope of the present invention should be included in the patent application scope of the present invention.

Steps S10-S40 Steps S31-S37 1: Circuit Test System 10: Conversion Unit 12: Input Signal 122: Combination 1222: Conversion Combination 124: Compilation Method 14: Communication Format Signal 142: Mode 18: Mask 20: Control Unit 22: Control Command Signal 24: Storage Unit 30: Circuit Under Test 32: Built-in Test

Figure 1: A circuit test system architecture diagram of the present invention; Figure 2: A schematic diagram illustrating signal transmission within the circuit test system of the present invention; Figure 3: A system architecture diagram of another embodiment of the present invention; Figure 4: A schematic diagram illustrating the conversion method of the present invention; Figure 5: A schematic diagram illustrating an embodiment of the present invention; Figure 6: A flow chart illustrating the circuit test method of the present invention; Figure 7: A schematic diagram illustrating the decoding of the present invention; and Figure 8: A schematic diagram illustrating the data organization of the present invention.

1: Circuit test system

10:Conversion unit

12: Input signal

14: Communication format signal

142: Mode

20: Control unit

22: Control command signal

30: Circuit under test

32: Built-in Tests

Claims (9)

A circuit testing system, used to control a circuit under test to execute built-in test software, includes: a conversion unit that receives an input signal corresponding to the circuit under test and a test item of the circuit under test, and converts the input signal into a communication format signal through a conversion method, wherein the communication format signal includes a pattern; and a control unit connected to the conversion unit and the circuit under test, the control unit determines the pattern of the communication format signal and executes a decoding method corresponding to the pattern to decode the communication format signal and generate a corresponding control command signal, wherein the control command signal is used to control the circuit under test to execute the built-in test; wherein the conversion method converts the input signal into the communication format signal through a mask corresponding to the circuit under test. The circuit testing system as described in claim 1, wherein the communication format signal is transmitted to the control unit in the form of a packet. The circuit testing system as claimed in claim 1, wherein the control unit receives the communication format signal via a universal serial bus (USB), a universal asynchronous receiver/transmitter (A/R/TSM), or a wireless communication. The circuit testing system as claimed in claim 1, wherein the built-in test is a self-test of the circuit under test. The circuit testing system as described in claim 1, wherein the control unit further includes: a storage unit, which is used to store the communication format signal. A circuit testing method includes the following steps: providing an input signal to a conversion unit, the input signal corresponding to a circuit to be tested and a test item of the circuit to be tested; the conversion unit converting the input signal through a conversion method and generating a communication format signal, the communication format signal including a pattern; the conversion unit transmitting the communication format signal to a control unit, the control unit determining the pattern of the communication format signal and executing a decoding method corresponding to the pattern to decode the communication format signal and generate a corresponding control command signal; and the control unit transmitting the control command signal to the circuit to be tested, the circuit to be tested performing a built-in test according to the control command signal; wherein the conversion method converts the input signal to the communication format signal through a mask corresponding to the circuit to be tested. The circuit testing method as described in claim 6, wherein the communication format signal is transmitted to the control unit in the form of a packet. The circuit testing method as described in claim 6, wherein the control unit receives the communication format signal through a universal serial bus, a universal asynchronous receiver and transmitter, or a wireless communication. The circuit testing method as described in claim 6, wherein the built-in test is a test for performing a self-test on the circuit to be tested.