TWI898215B - Advanced lithography and self-assembled devices - Google Patents

Abstract

Advanced lithography techniques including sub-10nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Description

Advanced lithography and self-polymerization equipment

Embodiments of the present invention are in the field of semiconductor devices and processing, and in particular, relate to sub-10 nm pitch patterning and self-polymerizing devices.

For the past several decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features has enabled an increased density of functional units on the limited surface area of a semiconductor chip. For example, shrinking transistor size allows an increasing number of memory or logic devices to be combined on a chip, leading to the manufacture of products with increased throughput. However, the desire for more and more capacity is not without its problems. The need to optimize the performance of each device has become increasingly important.

Variability in conventional and currently known manufacturing processes may limit their potential to extend further into the sub-10nm range. Therefore, the fabrication of functional components required for future technology nodes may require the introduction of new methodologies or the integration of new technologies into or replacement of current manufacturing processes.

and

Advanced pitch patterning and self-polymerizing devices are described, particularly advanced pitch patterning techniques and self-polymerizing device fabrication methods for producing sub-10 nanometer (nm) devices and structures. In the following description, a number of specific details, such as specific integration and material states, are set forth to provide a thorough understanding of embodiments of the present invention. It will be apparent to those skilled in the art that embodiments of the present invention can be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail to avoid unnecessarily obscuring embodiments of the present invention. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the claimed subject matter or the application and uses of such embodiments. As used herein, the word "exemplary" means "serving as a range, example, or illustration." Any embodiment described herein as exemplary is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the prior art, background, brief summary, or the following detailed description.

This specification includes references to "one embodiment" or "an embodiment." The appearance of the phrase "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present invention.

Terminology. The following paragraphs provide definitions and/or background for terms found in this specification (including the accompanying claims):

The term "comprising" is open-ended. As used in the appended claims, this term does not exclude additional structures or steps.

"Configured to." Each unit or component may be described or claimed as "configured to" perform a task or tasks. In this context, "configured to" is used to imply structure, by indicating that the unit/component includes structure to perform those tasks during operation. Thus, a unit/component may be said to be configured to perform the tasks even when the specified unit/component is not currently operating (e.g., not turned on/active). Reciting a unit/circuit/component as "configured to" perform one or more tasks expressly disclaims the implication that 35 U.S.C. §112 (sixth paragraph) applies to the unit/component.

"First," "second," etc. As used herein, these terms are used as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, reference to a "first" solar cell does not necessarily imply that the solar cell is the first solar cell in a sequence; instead, the term "first" is used to distinguish the solar cell from other solar cells (e.g., a "second" solar cell).

"Coupled" - The following description refers to elements, nodes, or features being "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element/node/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically.

Additionally, certain terms may be used in the following description for reference purposes only and are not intended to be limiting. For example, terms such as "higher," "lower," "above," and "below" refer to directions in the figures to which the reference is applied. Terms such as "front," "back," "rear," "side," "outward," and "inward" describe the orientation and/or position of a portion of a component within a fixed (but arbitrary) frame of reference, as made apparent by reference to the text and associated figures describing the component in question. This terminology may include the words expressly mentioned above, their derivatives, and words of similar import.

"Inhibit" - As used herein, inhibit is used to describe the reduction or minimization of an effect. When a component or feature is described as inhibiting an action, behavior, or condition, it may completely prevent the result, consequence, or future condition. Furthermore, "inhibit" may also refer to the reduction or mitigation of consequences, properties, and/or effects that might otherwise occur. Thus, when a component, element, or feature is referred to as inhibiting a result or condition, it need not completely prevent or eliminate that result or condition.

The embodiments described herein may be directed to front-end-of-the-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned into a semiconductor substrate or layer. FEOL typically encompasses all steps up to (but not including) the deposition of metal interconnect layers. Following the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any traces).

The embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected to wiring (e.g., a metallization layer or layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal steps, and joints for chip-to-package connections. In the BEOL stage of fabrication, contacts (pads), interconnect wiring, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers may be added to the BEOL. The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although example processing schemes may be described using a FEOL processing context, these approaches may also be applied to BEOL processing. Similarly, although example processing schemes may be described using a BEOL processing context, these approaches may also be applied to FEOL processing.

Pitch segmentation processing and patterning schemes may be implemented to enable or may be included as part of the embodiments described herein. Pitch segmentation patterning generally refers to pitch halving, pitch quartering, etc. Pitch segmentation schemes may be applied to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. In accordance with one or more embodiments described herein, photolithography is first implemented to print unidirectional lines (e.g., strictly unidirectional or predominantly unidirectional) at a predetermined pitch. Pitch segmentation processing is then implemented as a technique to increase line density.

In one embodiment, the term "grating structure" is used herein to refer to a tight-pitch grating structure with respect to metal lines, ILD lines, or hard mask lines. In such an embodiment, the tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask, as is known in the art. Furthermore, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern described herein can have metal lines, ILD lines, or hard mask lines separated by a substantially constant pitch and having a substantially constant width. For example, in some embodiments, the pitch can vary within 10 percent and the width can vary within 10 percent, and in some embodiments, the pitch can vary within 5 percent and the width can vary within 5 percent. Patterns can be created by halving the pitch or by quartering the pitch (or other pitch divisions). In one embodiment, the grating does not necessarily have to be a single pitch.

In a first example, pitch halving can be implemented to double the line density of the resulting grating structure. FIG. 1A illustrates a cross-sectional view of the starting structure following deposition of a hard mask material layer formed on an interlayer dielectric (ILD) layer (but before patterning). FIG. 1B illustrates a cross-sectional view of the structure of FIG. 1A following patterning of the hard mask layer with pitch halving.

1A , a starting structure 100 has a hard mask material layer 104 formed on an interlayer dielectric (ILD) layer 102. A patterned mask 106 is disposed over the hard mask material layer 104. The patterned mask 106 has spacers 108 formed along the sidewalls of its features (lines) on the hard mask material layer 104.

1B , the hard mask material layer 104 is patterned in a pitch-halving manner. Specifically, the patterned mask 106 is removed first. The resulting pattern of the spacers 108 has twice the density of the mask 106, or half the pitch or features thereof. The pattern of the spacers 108 is transferred to the hard mask material layer 104, for example, by an etching process to form a patterned hard mask 110, as shown in FIG1B . In one such embodiment, the patterned hard mask 110 is formed to have a grating pattern of unidirectional lines. The grating pattern of the patterned hard mask 110 can be a close-pitch grating structure. For example, a close pitch may not be directly achievable using conventional lithography techniques. Even though not shown, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern of the patterned hard mask 110 of FIG. 1B can have hard mask lines separated by a constant pitch and having a constant width relative to each other. The resulting dimensions can be much smaller than the critical dimensions of the utilized lithography technology.

Therefore, for front-end-of-line (FEOL) or back-end-of-line (BEOL) (or both) integration schemes, the capping film can be patterned using lithography and etching processes (which can involve, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning (SBQP) or pitch quartering). It should be understood that other pitch division methods can also be implemented.

For example, Figure 2 illustrates a cross-sectional view of a spacer-based sixfold patterning (SBSP) process involving a pitch division by a factor of six. Referring to Figure 2, in operation (a), the sacrificial pattern X is shown after lithography, thinning, and etching. In operation (b), spacers A and B are shown after deposition and etching. In operation (c), the pattern from operation (b) is shown after spacer A is removed. In operation (d), the pattern from operation (c) is shown after spacer C is deposited. In operation (e), the pattern from operation (d) is shown after spacer C is etched. In operation (f), the pitch /6 pattern is obtained after sacrificial pattern X is removed and spacer B is removed.

In another example, Figure 3 illustrates a cross-sectional view of a spacer-based ninefold patterning (SBNP) process involving a pitch division by a factor of nine. Referring to Figure 3 , in operation (a), a sacrificial pattern X is shown after lithography, thinning, and etching. In operation (b), spacers A and B are shown after deposition and etching. In operation (c), the pattern from operation (b) is shown after spacer A is removed. In operation (d), the pattern from operation (c) is shown after spacers C and D are deposited and etched. In operation (e), a pitch /9 pattern is obtained after spacer C is removed.

In any case, in one embodiment, the grid layout can be fabricated using conventional or state-of-the-art lithography, such as 193nm immersion lithography (193i). Pitch segmentation can be implemented to increase the density of lines in the grid layout by a factor of n. A grid layout formed using 193i lithography coupled with pitch segmentation by a factor of n can be designated as 193i+P/n pitch segmentation. In such an embodiment, 193nm immersion scaling can be extended for many generations using cost-effective pitch segmentation.

In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become increasingly common as device dimensions continue to shrink. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-volume bulk silicon infrastructure.

However, the scaling of multi-gate transistors is not without consequences. As the dimensions of these fundamental building blocks of microelectronic circuits decrease and as the total number of building blocks fabricated in a given area increases, the limitations of the semiconductor processes used to fabricate these building blocks become increasingly problematic.

In one embodiment, directed self-polymerization (DSA) is implemented to provide hard mask differentiation (e.g., to form hard masks with different etching properties). In some embodiments, differentiated hard masks may also be referred to as "colored" hard masks, where hard masks of the same color have the same or similar etch selectivity and where hard masks of different colors have different etch selectivities. It should be noted that in actual implementations, the term "color" does not refer to the actual color of the hard mask material. Hard mask differentiation (or coloring) can be used to pattern or selectively remove semiconductor fins within a plurality of gridded semiconductor fins. One or more embodiments described herein relate to processes and structures for edge placement error (EPE) correction based on (and resulting from) aligned pitch quartering (or other) patterning approaches. One or more embodiments may be described as a differentiated or "colored" alternating hard mask approach for semiconductor fin patterning. Embodiments may include one or more of DSA, semiconductor material patterning, pitch segmentation (e.g., pitch quartering), differentiated hard mask selectivity, and self-alignment for fin patterning. One or more embodiments are particularly well-suited for non-planar semiconductor device fabrication.

According to embodiments of the present invention, ultra-fine fin patterning is achieved by doubling the allowable edge placement error and doubling the cut size for small features on a tight pitch. In one embodiment, all features (e.g., fin lines) are transferred into the semiconductor substrate as a single group with varying critical dimensions (CD). This approach contrasts with current state-of-the-art approaches, which typically rely on spacers with three discrete groups of line widths (e.g., backbone or mandrel, complementary, and spacer dimensions) reduced to a quarter of the pitch.

To provide background, it may be desirable to use bulk silicon for fin or tri-gate based semiconductor devices. In one embodiment, directed self polymerization (DSA) is implemented to achieve pitch separation of every other feature and "coloring" the desired pattern. In one such embodiment, the patterning method is particularly applicable to patterning silicon fins in a tri-gate transition patterning flow. In one embodiment, the advantages of the embodiments described herein may include one or more of the following: (1) enabling a single population of feature widths, (2) doubling the edge layout error requirements for feature cutting, (3) doubling the size of the hole or opening required to cut a single feature (e.g., relaxing the restrictions on the size of the opening), or (4) reducing the cost of the patterning process. Structural artifacts resulting from the process include (in one embodiment) a single population of critical dimensions on a guard ring surrounding the die of the wafer during transitions from one pitch to another and/or from one grid to another. Embodiments enable the sawing of tight pitch lines without expanding edge placement error requirements.

In an example processing scheme, Figures 4A-4N illustrate cross-sectional views of various operations in a method of fabricating a non-planar semiconductor device, in accordance with an embodiment of the present invention.

FIG4A illustrates a bulk semiconductor substrate 402 having a first patterned hard mask 404 formed thereon. In one embodiment, the bulk semiconductor substrate 402 is a bulk single-crystalline silicon substrate having fins 402 etched therein. In one embodiment, the bulk semiconductor substrate 402 is undoped or lightly doped at this stage. For example, in a specific embodiment, the bulk semiconductor substrate 402 has a boron dopant concentration of less than approximately 1E17 atoms/ ^cm³ .

In one embodiment, the first patterned hard mask 404 includes features having a pitch 406. In one such embodiment, the first patterned hard mask 404 represents half of the possible number of fins that will ultimately be formed in the substrate 402. That is, the pitch 406 is effectively widened to double the pitch of the final pattern of fins formed. In one embodiment, the first hard mask 404 is patterned directly using a lithography process. However, in other embodiments, pitch division is applied (e.g., the pitch is halved) and used to provide a patterned hard mask 404 having the pitch 406. It should be understood that in one embodiment, the first guide pattern can be formed using conventional patterning (lithography/etching), lithography alone, spacer-based double patterning, or other pitch division methods. In one embodiment, the guide pattern is separated from the DSA pattern through the use of two or more hard masks so that its CD is formed from a single population (e.g., one etch).

FIG4B illustrates the structure of FIG4A , following the formation of a second hard mask layer 408 between the first patterned hard mask 404. In one embodiment, the second hard mask layer 408 is formed by forming a blanket hard mask layer over the substrate 402 and the first patterned hard mask 404 and then planarizing the blanket hard mask layer to form the second hard mask layer 408, for example, by chemical mechanical planarization (CMP). In another embodiment, ALD or CVD techniques will follow the contours of the wafer surface; since fin dicing is used as an example, the wafer is substantially flat at this point in the process.

In one embodiment, the second hard mask layer 408 has different etching characteristics than the first patterned hard mask 404. In one embodiment, one or both of the second hard mask layer 408 and the first patterned hard mask 404 is a layer of a silicon nitride (e.g., silicon nitride) or a layer of a silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials, such as silicon carbide. In another embodiment, the hard mask material comprises a metal. For example, the hard mask or other overlying material may include a layer of titanium or other metal nitride (e.g., titanium nitride). Potentially smaller amounts of other materials, such as oxygen, may be included in one or more of these layers. The hard mask layer may be formed by CVD, PVD, or by other deposition methods.

FIG4C illustrates the structure of FIG4B , following the application of a selective brush material layer 410 . The selective brush material 410 is a selective material that can be applied by a brush (in some embodiments). It should be noted that the term “brush material” is often used as a technical term in the DSA process and does not imply that the selective material 410 is used as a brush. In one embodiment, the selective brush material layer 410 is only adhered to the first patterned hard mask 404 , as shown in FIG4C . However, in another embodiment, the selective brush material is applied to the second hard mask layer 408 instead. In yet another embodiment, the selective brush material layer 410 is adhered only to the first patterned hard mask 404, and a second, different selective brush material is formed on the second hard mask layer 408.

In one embodiment, the selective brush material layer 410 includes a molecular species comprising polystyrene having a head group selected from the group consisting of -SH, -PO ₃ H ₂ , -CO ₂ H, -NRH, -NRR', and -Si(OR) _3. In another embodiment, the selective brush material layer 410 includes a molecular species comprising polymethyl methacrylate having a head group selected from the group consisting of -SH, -PO ₃ H ₂ , -CO ₂ H, -NRH, -NRR', and -Si(OR) _3. In one embodiment, the selective brush material layer 410 is attracted to a component of a DSA block copolymer (e.g., polystyrene or polymethyl methacrylate). The selective material layer 410 may include other suitable materials in other embodiments.

Figure 4D illustrates the structure of Figure 4C, subsequent to the application of direct self-polymerizing (DSA) block copolymer 414/416 (A/B) and the polymer polymerization process. In one embodiment, the DSA block copolymer is applied to the surface and annealed to separate the polymer into a first polymer block 414 and a second polymer block 416 (identified as 416A and 416B in Figure 4D). In one embodiment, polymer block 416 preferentially adheres to the selective brush material layer 410 during the annealing process. Polymer block 414 adheres to the second hard mask layer 408. However, in certain embodiments, the pitch of the polymerization is half the pitch of the first patterned hard mask 404. In this case, portion 416A of polymer block 416 adheres to the selective brush material layer 410 on the first hard mask 404 , while portion 416B of polymer block 416 is formed on the second hard mask layer 408 between polymer blocks 414 .

In one embodiment, block copolymer molecule 414/416 (A/B) is a polymer molecule formed by chains of covalently bonded monomers. In a two-block copolymer, there are two different types of monomers, and these different types of monomers are primarily contained in two different blocks or adjacent sequences of monomers. The block copolymer molecule shown includes a block of polymer 414 and a block of polymer 416 (A/B). In one embodiment, the block of polymer 414 predominantly includes chains of covalently bonded monomer A (e.g., A-A-A-A-A...), while the block of polymer 416 (A/B) predominantly includes chains of covalently bonded monomer B (e.g., B-B-B-B-B...). Monomers A and B can represent any of the different types of monomers used in block copolymers known in the art. For example, monomer A can represent a monomer used to form polystyrene, while monomer B can represent a monomer used to form polymethyl methacrylate (PMMA), or vice versa, although the scope of the invention is not so limited. In other embodiments, there can be more than two blocks. Furthermore, in other embodiments, each of the blocks can include a different type of monomer (e.g., each block can itself be a copolymer). In one embodiment, blocks of polymer 414 and blocks of polymer 416 (A/B) are covalently bonded together. Blocks of polymer 414 and blocks of polymer 416 (A/B) can be of approximately equal length, or one block can be significantly longer than the other.

Typically, the blocks of a block copolymer (e.g., block 414 and block 416 (A/B)) can each have different chemical properties. For example, one of the blocks can be relatively hydrophobic (e.g., repelling water) while the other can be relatively hydrophilic (attracting water). At least conceptually, one of the blocks can be relatively oil-like while the other can be relatively water-like. These differences in chemical properties between different block polymers (whether hydrophilic-hydrophobic or otherwise) can cause the block copolymer molecules to self-polymerize. For example, self-polymerization can be based on microphase separation of the polymer blocks. Conceptually, this can be analogous to the phase separation of oil and water, which are normally immiscible. Similarly, differences in hydrophilicity between polymer blocks (e.g., one block is relatively hydrophobic and another is relatively hydrophilic) can cause similar microphase separation, where different polymer blocks try to "separate" from each other because they chemically dislike each other.

However, in one embodiment, because the polymer blocks are covalently bonded to one another, they cannot be completely separated on a macroscopic scale. Instead, polymer blocks of a given type tend to separate or aggregate with polymer blocks of other molecules of the same type in extremely small (e.g., nanosized) domains or phases. The specific size and shape of the domains or microphases typically depends at least in part on the relative lengths of the polymer blocks. In one embodiment, for example, in a two-block copolymer, if the blocks are approximately the same length, a grid-like pattern of alternating polymer 414 lines and polymer 416 (A/B) lines is produced.

In one embodiment, the polymer 414/polymer 416 (A/B) grating is first applied as an unpolymerized block copolymer layer portion, which includes (for example) block copolymer material applied by a brush or other coating process. The unpolymerized form refers to the state in which (at the time of deposition) the block copolymer has not yet substantially phase-separated and/or self-polymerized to form nanostructures. In this unpolymerized form, the block polymer molecules are highly random, with different polymer blocks oriented and positioned in a highly random manner. The unpolymerized block copolymer layer portion can be applied in a variety of different ways. For example, the block copolymer can be dissolved in a solvent and then spun onto the surface. Alternatively, the unpolymerized block copolymer can be sprayed, dipped, dip-coated, or otherwise applied or coated onto the surface. Other methods of applying block copolymers, as well as other methods known in the art for applying similar organic coatings, can potentially be used. The unpolymerized layer can then form a polymerized block copolymer layer portion, for example, by microphase separation and/or autopolymerization of the unpolymerized block copolymer layer portion. Microphase separation and/or autopolymerization occurs through rearrangement and/or reorientation of the block copolymer molecules, and in particular, the rearrangement and/or reorientation of the different polymer blocks of the block copolymer molecules.

In this embodiment, an annealing treatment may be applied to the unpolymerized block copolymer to initiate, accelerate, increase, or enhance the quality of microphase separation and/or autopolymerization. In certain embodiments, the annealing treatment may include a treatment operable to increase the temperature of the block copolymer. An example of such a treatment is baking the layer, heating the layer in an oven or over a heat lamp, applying infrared radiation to the layer, or applying heat to the layer or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate microphase separation and/or autopolymerization of the block copolymer without damaging the block copolymer or any other important materials or structures of the integrated circuit substrate. Typically, the heating range may be from about 50°C to about 300°C, or from 75°C to about 250°C, but not exceeding the thermal degradation limits of the block copolymer or integrated circuit substrate. Heating or annealing can help provide energy to the block copolymer molecules, making them more mobile/elastic to increase the rate of microphase separation and/or improve the quality of microphase separation. This microphase separation or rearrangement/reorientation of the block copolymer molecules can lead to self-polymerization to form extremely small (e.g., nanoscale) structures. Self-polymerization can occur under the influence of surface energy, molecular affinity, and other surface-related and chemical-related forces.

In any case, in certain embodiments, self-polymerization of block copolymers (whether based on hydrophobicity or hydrophilicity) can be used to form extremely small periodic structures (e.g., precisely spaced nanoscale structures or wires). In certain embodiments, this can be used to form nanoscale wires or other nanoscale structures that can ultimately be used to form semiconductor fin wires.

FIG4E illustrates the structure of FIG4D , following the removal of one of the blocks of the dual-block copolymer. In one embodiment, polymer portion 414 is selectively removed by a wet or dry etch process to leave portion 416 (A/B). The pitch of remaining portion 416 (A/B) is approximately half the pitch of the first patterned hard mask 404.

FIG4F illustrates the structure of FIG4E , following the transfer of the pattern of the remaining polymer portion into the underlying fully crystalline semiconductor substrate. In one embodiment, the pattern of the remaining polymer portion 416(A/B) (i.e., the pattern of the first patterned hard mask 404 when the pitch is halved) is etched into the bulk semiconductor substrate 402. The patterning operation patterns the second hard mask layer 408 to form a second patterned hard mask layer 424 corresponding to the polymer portion 416B. The first patterned hard mask 404 corresponds to the polymer portion 416A. In one embodiment, the plurality of fins 418 are formed directly on the bulk substrate 402 (which becomes the patterned substrate 420 ) and are thus formed to be connected to the bulk substrate 402 / 420 , on a generally planar surface 422 .

FIG4G illustrates the structure of FIG4F after the remaining polymer layers and any brush layers have been removed. In one embodiment, the remaining polymer layers 416 (A/B) and the brush layer 410 are removed to leave a plurality of alternating fins 418 having alternating "colored" first patterned hard masks 404 and second patterned hard masks 424 thereon. In one embodiment, the remaining polymer layers 416 (A/B) and the brush layer 410 are removed using an ashing and cleaning process. The resulting pitch 426 of the fins is half the pitch 406 of the original first patterned hard mask 404.

FIG4H illustrates the structure of FIG4G after formation of an interlayer dielectric (ILD) layer 428 between the plurality of fins 418. In one embodiment, the ILD layer 428 is composed of silicon dioxide, such as is used in shallow trench isolation processes. However, other dielectrics may be used instead, such as carbides or nitrides. The ILD layer 428 may be deposited by chemical vapor deposition (CVD) or other deposition processes (e.g., ALD, PECVD, PVD, HDP, assisted CVD, low-temperature CVD) and may be planarized by chemical mechanical polishing (CMP) techniques to expose the top surfaces of the hard mask layers 404 and 428.

FIG4I illustrates the structure of FIG4H , following the formation and patterning of a photoresist material for forming a patterned mask 430. In one embodiment, the patterned mask 430 has an opening 432 formed therein. The opening 432 exposes a target one of the plurality of fins 418 having the first patterned hard mask 404 thereon for eventual fin removal. The opening 432 has a cutout dimension 436. In one embodiment, the restriction on the cutout dimension 436 is relaxed, and even portions of adjacent fins having the second patterned hard mask 424 thereon may be exposed. In one embodiment, the patterning operation uses "coloring" or hard mask material differentiation to prepare the unwanted features for cutting out to allow the cut size to be twice the pitch 426 of the feature 418 (i.e., to result in the original pitch 406). In one embodiment, the hard mask material allows for selective differentiation by plasma or wet etching between two hard mask materials. Furthermore, the edge placement error (EPE) 434 is half pitch. In comparison, in a standard patterning process (no coloring), the cut size is 1X pitch and the edge placement error (EPE) is 1/4 pitch. Therefore, in one embodiment, the process described herein doubles the edge placement error budget and doubles the size of the hole or opening required to cut a single feature.

In one embodiment, the patterned mask 430 is comprised of a photoresist layer, as is known in the art, and can be patterned by conventional lithography and development processes. In a particular embodiment, the portion of the photoresist layer exposed to the light source is removed when the photoresist layer is developed. Thus, the patterned photoresist layer is comprised of a positive photoresist material. In a particular embodiment, the photoresist layer is comprised of a positive photoresist material, such as, but not limited to, a 248 nm resist, a 193 nm resist, a 157 nm resist, an extreme ultraviolet (EUV) resist, an e-beam resist, an imprint layer, or a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another specific embodiment, the portion of the photoresist layer exposed to the light source is retained when developing the photoresist layer. Therefore, the photoresist layer is composed of a negative photoresist material. In a specific embodiment, the photoresist layer is composed of a negative photoresist material, such as (but not limited to) poly-cis-isoprene or poly-vinyl-cinnamate. In one embodiment, the lithography operation is performed using 193nm immersion lithography (193i), EUV and/or electron beam direct write (EBDW) lithography, etc. Positive tone or negative tone resist can be used. In one embodiment, patterned mask 430 is a three-layer mask consisting of a topographical shielding portion, an antireflective coating (ARC), and a photoresist layer. In a specific embodiment, the topographical shielding portion is a carbon hard mask (CHM) layer and the ARC is a silicon-containing ARC layer. In one such embodiment, a spin-on glass material with additional chromophores is used to help suppress reflectivity. Chemically, it is a (siloxane)-containing silicon carbon polymer. When annealed, it forms a mixture of silicon dioxide and carbon polymer.

FIG4J illustrates the structure of FIG4I following etching of a selected one of the plurality of fins 418 and subsequent removal of the patterned mask 430. In one embodiment, this process is referred to as the "fin cutting" or "feature selection" operation of the process. In one embodiment, one of the plurality of fins 418 is removed at location 438 to form a patterned plurality of fins 418' having a first interrupted pattern. In one such embodiment, the exposed first patterned hard mask 404 is first removed using an etching process that is selective to any exposed second patterned hard mask 424 and selective to the ILD layer 428. In another embodiment, a "fin retention" approach is used, where the features are selected using the opposite tone of the photoresist and protected during the etch process, while the background or unprotected fins are removed. This is the opposite polarity of the lithography process (e.g., negative versus positive tone imaging). It should be understood that either process can be used for this operation. The exposed fins are then removed at location 438 using an etch process that is selective to the exposed second patterned hard mask 424 and selective to the ILD layer 428. In the first embodiment, the fins are removed at location 438 to level 440, leaving a protruding portion 446 above the planar surface 422. In the second embodiment, the fin is removed at location 438 to a level 442 that is approximately coplanar with the flat surface 422. In the third embodiment, the fin is removed at location 438 to a level 444, leaving a recess 448 below the flat surface 422.

FIG4K illustrates the structure of FIG4J following formation and patterning of a photoresist material for forming a patterned mask 450. In one embodiment, the patterned mask 450 has an opening 452 formed therein. The opening 452 exposes a second of the plurality of fins 418′ having a second patterned hard mask 424 thereon for final fin removal. In one embodiment, the patterning operation prepares the unwanted features for cutting out using “coloring” or differentiation of the hard mask material to allow the cut size to be twice the pitch 426 of the features 418′. As described in relation to FIG4I , the process described herein doubles the edge placement error budget and doubles the size of the hole or opening required to cut a single feature. In one embodiment, patterned mask 450 is comprised of materials such as those described in connection with FIG. 4I .

FIG4L illustrates the structure of FIG4K subsequent to etching of the selected second of the plurality of fins 418′. In one embodiment, the second of the plurality of fins 418′ is removed at location 454 to form a patterned plurality of fins 418′ having a second interrupted pattern. In one such embodiment, the exposed second patterned hard mask 424 is first removed using an etching process that is selective to any exposed first patterned hard mask 104 and selective to the ILD layer 428. The exposed fins are then removed at location 454 using an etching process that is selective to the exposed first patterned hard mask 404 and selective to the ILD layer 428. In the first embodiment, The fin is removed at location 454 to level 456, leaving a protrusion above planar surface 422 at a height above surface 440 of protrusion 446. In a second embodiment, the fin is removed at location 454 to level 458, leaving a protrusion 464 above planar surface 422 and at approximately the same height as surface 440 of protrusion 446. In a third embodiment, the fin is removed at location 454 to level 460, approximately coplanar with planar surface 422. In a fourth embodiment, the fin is removed at location 454 to level 462, leaving a recess 466 below planar surface 422.

FIG. 4M illustrates the structure of FIG. 4L following removal of the patterned mask 450 and formation of an interlayer dielectric (ILD) layer 468 over the plurality of fins 418″ and in locations 438 and 454 where the fins were removed. In one embodiment, the ILD layer 468 is composed of silicon dioxide, such as is used in shallow trench isolation processes. However, other dielectrics may be substituted. Carbides such as nitrides are used. ILD layer 468 can be deposited by chemical vapor deposition (CVD) or other deposition processes (e.g., ALD, PECVD, PVD, HDP-assisted CVD, low-temperature CVD). Spin-on materials are another common option for these films. Many low-k dielectric materials can be spun onto wafers and cured. These are commonly used in industry.

FIG4N illustrates the structure of FIG4M following planarization of the ILD layer 468 and removal of the first and second patterned hard masks 404 and 424. In one embodiment, chemical mechanical polishing (CMP) techniques are used to remove the first patterned hard mask 404 and the second hard mask 424 to recess the ILD layers 428 and 468 to form planarized ILD layers 428′ and 468′, respectively, and to expose the surfaces of the plurality of fins 418″. In one embodiment, the planarized ILD layer 428′ is formed from a substantially similar surface to the planarized ILD layer 468′. In one embodiment, planarized ILD layer 428′ is composed of a different material than planarized ILD layer 468′. In either case, in one embodiment, a seam is formed between ILD layer 468′ and ILD layer 428′, for example, at location 438 or 454. It should be understood that, in one embodiment, the exposed surfaces of the plurality of fins 418″ can be used to form a planar semiconductor device.

According to another embodiment, FIG. 5 illustrates the structure of FIG. 4N after exposing the upper portion of the plurality of fins 418″. Referring to FIG. 5 , the ILD layer 468′ and the ILD layer 428′ are recessed to expose the protruding portion 472 of the fin 418′ and provide the recessed ILD layer 468″ and the recessed ILD layer 428″ to a recess height 476. The recess height 476 is Reference numeral 76 defines the location between the upper fin portion 472 and the lower fin portion 474. Recessing of the ILD layer 468' and the ILD layer 428' can be performed by plasma, vapor, or wet etching processes. In one embodiment, a dry etching process selective to the silicon fin 418" is used. The dry etching process is based on plasma generated from a gas such as, but not limited to, _NF3 , _CHF3 , _C4F8 , HBr, and _O2 , at a pressure typically in the range of 30-100 _mTorr and a plasma bias of 50-1000 Watts.

In an exemplary embodiment, referring again to Figures 4J, 4L and 5, a semiconductor structure includes a plurality of semiconductor fins 418" protruding from a substantially planar surface 422 of a semiconductor substrate 420. The plurality of semiconductor fins 418" have a grating pattern interrupted by a first location 438, wherein the first location 438 has a first fin portion 446, and the first fin portion 446 has a first height. The grating pattern of the semiconductor fin is further interrupted by a second location 454, which has a second fin portion 464, and the second fin portion 464 has a second height. In one embodiment, the second height of the second fin portion 454 is different from the first height of the first fin portion 446. In another embodiment, the second height of the second fin portion 454 is the same as the first height of the first fin portion 446. In one embodiment, the grating pattern has a constant pitch 126 when viewed without the discontinuities.

In an exemplary embodiment, referring again to Figures 4J, 4L and 5, a semiconductor structure includes a plurality of semiconductor fins 418" protruding from a substantially planar surface 422 of a semiconductor substrate 420. The plurality of semiconductor fins 418" have a grating pattern interrupted by a first location 438 having a first recess. In one embodiment, the grating pattern of the semiconductor fins is further interrupted by a second location 454 having a second recess, or one of the fin portions. In one embodiment, the grating pattern has a constant pitch 426 when viewed without the interruptions. In one embodiment, a trench isolation layer 468" is disposed in and above the recesses.

It should be understood that the above methods can be applied to fabricate semiconductor geometries other than semiconductor fins. For example, in one embodiment, the above methods are implemented to fabricate semiconductor nanowires or semiconductor nanoribbons. In one embodiment, the term "semiconductor body" or "plurality of semiconductor bodies" generally refers to geometries such as fins, nanowires, and nanoribbons.

It should be understood that the structures resulting from the above-described example processing schemes (e.g., the structures from Figures 4N and 5) can be used in the same or similar forms of subsequent processing operations to complete device fabrication (e.g., PMOS and NMOS device fabrication). As examples of completed devices, Figures 6A and 6B illustrate, respectively, a cross-sectional view and a plan view (taken along the a-a' axis of the cross-sectional view) of a non-planar semiconductor device, according to an embodiment of the present invention.

6A , a semiconductor structure or device 600 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 604 and a sub-fin region 605) formed from a substrate 602 (and within an isolation region 606). A gate line 608 is disposed over the protruding portion 604 of the non-planar active region and over a portion of the isolation region 606. As shown, the gate line 608 includes a gate electrode 650 and a gate dielectric layer 652. In one embodiment, the gate line 608 may also include a dielectric capping layer 654. Gate contact 614 and upper gate contact via 616 are also shown in this perspective view, along with upper metal interconnect 660, which are all disposed in an interlayer dielectric stack or layer 670. Also shown in the perspective view of FIG6A is that gate contact 614 (in one embodiment) is disposed above isolation region 606, but not above the non-planar active region.

As also shown in FIG6A , in one embodiment, an artifact of the fin selection recess remains in the final structure. For example, in the embodiment shown, a residual protrusion 699 remains. In other embodiments, the recess may remain, as described above.

As also shown in FIG6A , in one embodiment, an interface 680 exists between the protruding fin portion 604 and the sub-fin region 605. Interface 680 can be a transition region between the doped sub-fin region 605 and the slightly or undoped upper fin portion 604. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin doping is provided from an adjacent solid doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

Referring to FIG6B , gate line 608 is shown disposed above protruding fin portion 604. Source and drain regions 604A and 604B of protruding fin portion 604 can be seen in this perspective view. In one embodiment, source and drain regions 604A and 604B are doped portions of the original material of protruding fin portion 604. In another embodiment, the material of protruding fin portion 604 is removed and replaced with another semiconductor material, for example, by epitaxial deposition. In either case, source and drain regions 604A and 604B can extend below the height of dielectric layer 606, i.e., into sub-fin region 605. According to an embodiment of the present invention, the more heavily doped sub-fin region (i.e., the doped portion of the fin beneath the interface 680) prevents source-to-drain leakage through this portion of the bulk semiconductor fin.

In one embodiment, the semiconductor structure or device 600 is a non-planar device, such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is comprised of or formed as a three-dimensional body. In such an embodiment, the gate electrode stack of the gate line 608 surrounds at least the top surface and a pair of sidewalls of the three-dimensional body.

Substrate 602 can be composed of a semiconductor material that can withstand the manufacturing process and in which charge migration is possible. In one embodiment, substrate 602 is a bulk substrate composed of crystalline silicon, silicon/germanium, or a germanium layer doped with charge carriers (such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof) to form active region 604. In one embodiment, the concentration of silicon in bulk substrate 602 is greater than 97%. In another embodiment, bulk substrate 602 is composed of an epitaxial layer grown on top of a separate crystalline substrate, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The bulk substrate 602 may alternatively be composed of a group III-V material. In one embodiment, the bulk substrate 602 is composed of a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate 602 is composed of a Group III-V material, and the charge carrier dopant atoms are, for example, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

The isolation region 606 can be formed of a material suitable for ultimately electrically isolating (or facilitating isolation of) a portion of the permanent gate structure from the underlying bulk substrate or from an active region formed within the underlying bulk substrate, such as an isolation fin active region. For example, in one embodiment, the isolation region 606 is formed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

The gate line 608 may be formed of a gate electrode stack including a gate dielectric layer 652 and a gate electrode layer 650. In one embodiment, the gate electrode of the gate electrode stack is formed of a metal gate, and the gate dielectric layer is formed of a high-K material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, bismuth oxide, bismuth oxynitride, bismuth silicate, tantalum oxide, zirconia, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of the gate dielectric layer may include a layer of native oxide formed from the top layers of substrate 602. In one embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of einsteinium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some embodiments, the gate dielectric portion is a "U"-shaped structure, including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

In one embodiment, the gate electrode is formed from a metal layer such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, einsteinium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a specific embodiment, the gate electrode is formed from a non-work function setting fill material formed on a metal work function setting layer. The gate electrode layer can be formed from a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS or NMOS transistor. In some embodiments, the gate electrode layer may include a stack of two or more metal layers, one or more of which are work function metal layers and at least one of which is a conductive fill layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides such as ruthenium oxide. The P-type metal layer enables the formation of a PMOS gate electrode with a work function between approximately 4.9 eV and approximately 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, einsteinium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as einsteinium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer enables the formation of an NMOS gate electrode with a work function between approximately 3.9 eV and approximately 4.2 eV. In some embodiments, the gate electrode may include a "U"-shaped structure having a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may be a solely planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In further embodiments of the present invention, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

The spacers associated with the gate electrode stack may be composed of a material suitable for ultimately electrically isolating (or facilitating isolation of) the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

The gate contact 614 and the upper gate contact via 616 can be formed of a conductive material. In one embodiment, one or more contacts or vias are formed of a metal species. The metal species can be a pure metal such as tungsten, nickel, or cobalt, or an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material).

In one embodiment (although not shown), providing structure 600 involves forming a contact pattern that is perfectly aligned with an existing gate pattern while eliminating the need for a lithography operation with an extremely stringent registration budget. In one such embodiment, this approach enables the use of an inherently highly selective wet etch (e.g., relative to conventionally performed dry or plasma etch) to create the contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, this approach eliminates the need for other critical lithography operations (as conventionally used) to create the contact pattern. In one embodiment, the trench contact grid is not separately patterned, but is formed between the poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed subsequent to patterning the gate grating but before cutting the gate grating.

Furthermore, the gate stack structure 608 can be fabricated using a replacement gate process. In this technique, virtual gate materials, such as polysilicon or silicon nitride pillar materials, are removed and replaced with permanent gate electrode materials. In one such embodiment, a permanent gate dielectric layer is also formed during this process, as opposed to being formed from an earlier process. In one embodiment, the virtual gate is removed using a dry or wet etch process. In one embodiment, the virtual gate is composed of polysilicon or amorphous silicon and is removed using a dry etch process that includes the use of _SF6 . In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etch process including aqueous NH ₄ OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etch process including aqueous phosphoric acid.

In one embodiment, one or more of the methods described herein generally contemplate a dummy and replacement gate process, in conjunction with a dummy and replacement contact process, to obtain structure 600. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for a high temperature anneal of at least a portion of the permanent gate stack. For example, in certain such embodiments, an anneal of at least a portion of the permanent gate structure (e.g., after the gate dielectric layer is formed) is performed at a temperature greater than about 600 degrees Celsius. The anneal is performed prior to the formation of the permanent contact.

Referring again to FIG. 6A , the semiconductor structure or device 600 is configured to place the gate contact above the isolation region. Such a configuration may be viewed as an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of a gate electrode formed above an active region. Typically, one or more embodiments of the present invention include first using a gate-aligned trench contact process before (e.g., in addition to) forming a gate contact structure (e.g., a via) above the active portion of the gate and in the same layer as the trench contact via. Such a process may be implemented to form a trench contact structure for semiconductor structure fabrication, for example, for integrated circuit fabrication. In one embodiment, the trench contact pattern is formed aligned with the existing gate pattern. Conventional approaches, in contrast, typically involve an additional lithography process with a lithographic contact pattern closely aligned to the existing gate pattern, combined with a selective contact etch. For example, conventional processes may include patterning of a separate patterned poly (gate) grid with contact features.

It should be understood that not all forms of the above-described process need be implemented to fall within the spirit and scope of the embodiments of the present invention. For example, in one embodiment, the virtual gate need not be formed before the gate contact is formed on the active portion of the gate stack. The above-described gate stack may actually be a permanent gate stack, as formed initially. At the same time, the process described herein can be used to manufacture one or more semiconductor devices. The semiconductor device can be a transistor or the like. For example, in one embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor used in logic or memory, or a bipolar transistor. Also, in one embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independent access bi-gate device, or a fin-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-10 nanometer (10 nm) technology nodes.

It should be understood that in the example FEOL embodiments described above, in one embodiment, sub-10nm processing is implemented directly into the fabrication scheme and resulting structures. In other embodiments, FEOL considerations may be driven by BEOL sub-10nm processing requirements. For example, the material selectivity and layout for FEOL layers and devices may need to accommodate BEOL sub-10nm processing. In one such embodiment, the material selectivity and gate stack architecture are selected to accommodate high-density metallization in the BEOL layers, for example, to reduce edge capacitance in transistor structures formed in the FEOL layers but coupled together by the high-density metallization in the BEOL layers. Thus, FEOL structures and processes can be directly impacted by sub-10nm processing or can be indirectly impacted by sub-10nm processing of BEOL layers.

Back-end-of-line (BEOL) layers of integrated circuits typically include conductive microelectronic structures, known in the art as vias, for electrically connecting metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are typically formed by lithographic processes. Typically, a photoresist layer can be spun onto a dielectric layer, the photoresist layer can be exposed to patterned actinic radiation through a patterned mask, and the exposed layer can then be developed to form an opening in the photoresist layer. Next, an opening for the via can be etched into the dielectric layer using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form a via.

The size and spacing of vias have decreased significantly in the past, and are expected to continue to decrease significantly in the future for at least certain types of integrated circuits (e.g., advanced microprocessors, chipset assemblies, graphics chips, etc.). Patterning extremely small vias with very small pitches using these lithography processes presents several inherent challenges. One such challenge is that the overlap between the via and the overlying interconnect, as well as the overlap between the via and the underlying interconnect, must be controlled to a high tolerance, typically on the order of one-quarter of the via pitch. As the via pitch scales down, the overlap tolerance tends to shrink at a greater rate than the lithography equipment can keep up.

Another challenge is that the critical dimensions of the via opening tend to shrink faster than the resolving power of the lithography scanner. Scaling technologies exist to shrink the critical dimensions of the via opening. However, the amount of scaling tends to be limited by the minimum via pitch and the ability of the scaling process to be sufficiently optical proximity correction (OPC) neutral without significantly compromising line width roughness (LWR) and/or critical dimension uniformity (CDU). Yet another challenge is that the LWR and/or CDU properties of the photoresist typically need to be improved as the critical dimensions of the via opening decrease to maintain the same overall fraction of the critical dimension budget. However, the LWR and/or CDU properties of most current photoresists have not improved as rapidly as the critical dimensions of the via openings have decreased.

Furthering these challenges, extremely small via pitches typically tend to be below the resolution capabilities of even extreme ultraviolet (EUV) lithography scanners. Consequently, several different lithography masks are typically used, which tends to increase costs. At some point, if pitches continue to decrease, it may become impossible (even with multiple masks) to print these extremely small pitch via openings using EUV scanners.

These factors also pertain to the layout and scaling of non-conductive spaces or discontinuities (referred to as "plugs," "dielectric plugs," or "wire terminations") between metal lines in back-end-of-the-line (BEOL) metal interconnect structures. These factors also pertain to conductive tabs, which (by definition) are conductive links between two conductive metal lines (e.g., between two parallel conductive lines). These tabs are typically located in the same layer as the metal lines. Consequently, there is a need for improvements in the back-end-of-the-line metallization fabrication techniques used to fabricate metal lines, metal vias, conductive tabs, and dielectric plugs.

In some embodiments described below, patterning and alignment of via features (or other BEOL features) is achieved using multiple reticles and a key alignment strategy. In other embodiments, in contrast, the methods described herein enable the fabrication of self-aligned plugs and/or vias. In the latter embodiment, only one key overlay step (Mx+1 grating) may need to be performed.

It should be understood that the layers and materials described below in connection with back-end-of-the-line (BEOL) structures and processing are typically formed on or above an underlying semiconductor substrate or structure (such as the underlying device layer of an integrated circuit). In one embodiment, the underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include (but are not limited to) single crystal silicon, polycrystalline silicon and silicon-on-insulator (SOI), as well as similar substrates formed from other semiconductor materials (such as substrates including germanium, carbon, or Group III-V materials). The semiconductor substrate (depending on the stage of manufacture) often includes transistors, integrated circuits, etc. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the depicted structures may be fabricated on underlying lower-level interconnect layers.

Although the method of fabricating the metallization layer (or portion of the metallization layer) of the BEOL metallization layer is described in detail with respect to selected operations, it should be understood that additional or intermediate operations thereof may include standard microelectronics fabrication processes, such as lithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, and/or any other actions associated with microelectronic component fabrication. Also, it should be understood that the process operations described with respect to the following process flow may be performed in an alternative order, not every operation need be performed, and/or additional process operations may be performed.

In some cases, the resulting structure enables the fabrication of a via directly focused on the underlying metal line. The via may be wider, narrower, or the same thickness as the underlying metal line, for example, due to a non-perfectly selective etch process. However, in one embodiment, the center of the via is aligned (matched) with the center of the metal line. Thus, in one embodiment, deviations due to conventional lithography/damascene patterning (which must otherwise be accommodated) are not a factor in the resulting structure of one or more of the following process options.

It should be understood that certain interconnect fabrication schemes described below can be implemented to save significant alignment/exposure, can be implemented to improve electrical contact (e.g., by reducing via resistance), or can be implemented to reduce overall process operations and processing time compared to those required to pattern these features using conventional methods. It should also be understood that in subsequent or additional fabrication operations beyond those shown, in some instances, dielectric layers can be removed from the metal line layers to provide air gaps between the metal lines.

According to an embodiment of the present invention, a backbone method is described. The backbone method may involve multiple stages of atomic layer deposition (ALD). In one embodiment, dense pitch formation is achieved by stacking spacer formation, for example, using an ALD process.

To provide context, lithographic patterning of features used in semiconductor manufacturing is limited to the resolution of the imaging tool, whether optical (e.g., 193nm), electron beam, or EUV. Process methods such as multi-pass patterning, pattern reduction, and spacer-based pitch segmentation can be used to extend the resolution by factors of 2 to 4, or even potentially 8. However, these methods are limited in that process variations in the original lithographic steps remain with similar values in the final pattern. For example, a lithographic operation may have a variation of +/- 3nm. If this were utilized to produce a final pitch of 8nm (4nm feature size) using a pitch segmentation process method, the resulting final pattern would vary by 4nm +/- 3nm.

One or more embodiments described herein involve using stacked spacers or thin film deposition to define all or substantially all of the final critical small features for a layer, such as a BEOL layer. These features can have variations of better than +/- 1 nm, which is consistent with ALD technology. Multiple materials can be utilized to enable "coloring" of patterns to address alternative features (e.g., vias, cuts, plugs, etc.) with increased tolerance to edge placement errors.

7A and 7B illustrate cross-sectional views of a target base structure for enabling very fine pitch final patterning of semiconductor layers, according to an embodiment of the present invention.

7A , target base layer 700 includes patterned layer 702, on top of hard mask layer 704, on top of transfer layer 706, and on top of substrate 708. Patterned layer 702 includes backbone features 710. Backbone features 710 are relatively wide features (e.g., 6-12 nm) with an intermediate group 712 of relatively smaller features (e.g., 6-100s of smaller features between adjacent backbone features 710, where the smaller features are, for example, 4-6 nm wide).

In one embodiment, each of the intermediate group 712 of relatively small features includes a small feature 716 of a first material type, a small feature 714 of a second material type different from the first material type, and a small feature 718 of a third material type different from both the first and second material types. The differences in material types can provide different etching properties or selectivity between these material types. In one embodiment, the material of the backbone feature 710 is the same as the material of the third material type of the small feature 718, as depicted in FIG7A . In another embodiment, the material of the backbone feature 710 is different from the material of the third material type of the small feature 718, but has similar etching properties or selectivity as the third material type of the small feature 718.

7B , target base layer 750 includes patterned layer 752, on top of hard mask layer 754, on top of transfer layer 756, and on top of substrate 758. Patterned layer 752 includes backbone features 760. Backbone features 760 are relatively wide features (e.g., 6-12 nm) with an intermediate group 762 of relatively smaller features (e.g., 6-100s of smaller features between adjacent backbone features 760, where the smaller features are, for example, 4-6 nm wide).

In one embodiment, each of the intermediate group 762 of relatively small features includes a small feature 764 of a first material type, a small feature 766 of a second material type different from the first material type, and a small feature 768 of a third material type different from both the first and second material types. The differences in material types can provide different etching properties or selectivity between the material types. In one embodiment, the material of the backbone feature 760 is the same as the material of the second material type of the small feature 766, as depicted in FIG7B . In another embodiment, the material of the backbone feature 760 is different from the material of the second material type of the small feature 766, but has similar etching properties or selectivity as the third material type of the small feature 766.

Referring to both Figures 7A and 7B , in one embodiment, structure 700 or 750 comprises several stacked vertical layers of alternating materials that will ultimately define the final location of features in a semiconductor pattern (e.g., metal, transistors, etc.). Occasionally, larger features may appear because they represent lithographically defined structures that (in one embodiment) are larger (wider) due to their greater size variation. In one embodiment, between six and hundreds of narrow features are present.

Figures 8A-8H illustrate cross-sectional views of various operations in a method for fabricating a target base structure for enabling a very fine pitch final patterning of a semiconductor layer, according to an embodiment of the present invention. Generally, in one embodiment, stacked film generation operations are utilized. For example, conformal film deposition is performed, followed by anisotropic etching (e.g., spacer formation), selective growth, or directed self-polymerization (DSA). Patterning processes such as those described below can be implemented to provide a patterning process suitable for producing a very fine pitch final patterning of a semiconductor layer. In one embodiment, advantages of implementing such a process flow include improved dimensional control of tight pitch features, utilizing a built-in method for coloring alternating features to allow self-aligned via, plug, and saw formation.

Figure 8A illustrates a process operation involved in high-backbone formation. A plurality of backbone features 808 are formed on a hard mask layer 806, which is formed on a transfer layer 804, which is formed on a substrate 802. In one embodiment, the formation of the plurality of backbone features 808 involves using standard lithography operations (e.g., 193nm or EUV), followed by etching transfer into a hard mask (e.g., SiN, _SiO2 , SiC) and then removing any remaining resist and/or antireflective layer (e.g., by ashing or wet cleaning).

FIG8B illustrates a process operation involving the formation of a first spacer (Spacer 1). A first set of small features 810 composed of a first material is formed along the sidewalls of each of the plurality of bone features 808. In one embodiment, the first set of small features 810 is formed using deposition (e.g., ALD) and etching. In another embodiment, the first set of small features 810 is formed using a selective growth method.

FIG8C illustrates a process operation involving the formation of a second spacer (Spacer 2), a third spacer (Spacer 3), and a fourth spacer (Spacer 4), utilizing specific layers as shown in one possible example embodiment. A second set of small features 812 composed of a second material are formed along the exposed sidewalls of each of the first set of small features 810. A third set of small features 814 composed of a third material are formed along the exposed sidewalls of each of the two sets of small features 812. A fourth set of small features 816 composed of a second material are formed along the exposed sidewalls of each of the third set of small features 814. In one embodiment, the second set of small features 812 are first formed using a deposition (e.g., ALD) and etching method or a selective growth method. A third set of small features 814 is then formed using another deposition (e.g., ALD) and etch process or a selective growth process. A fourth set of small features 816 is then formed using another deposition (e.g., ALD) and etch process or a selective growth process.

FIG8D illustrates a process operation involving successive layer generation. An additional spacer layer 818 is sequentially formed, utilizing a selective ordering of material types. The additional spacer layer 818 can be fabricated using a deposition and etching process, a selective growth process, or a combination thereof. It should be understood that more layers than shown may be added. For example, in one embodiment, an additional 20-200 sets of spacers are formed at this stage. Spacer deposition may be completed before adjacent sidewall growth merges, for example, spacer formation is stopped when openings 820 remain. It should be understood that although deposition and etching or selective growth methods are described as options with respect to Figures 8A-8D, directed self-polymerization (DSA) can be used in place of or in addition to the spacer formation described herein. In one such example, a three-block-based DSA is used. An example of a three-block-based DSA is described below in connection with Figures 12A-12K.

In one embodiment, referring collectively to Figures 8A-8D, a stacked production of thin layers of alternating materials is performed on the sides of the original lithographically defined template features. One potential method for achieving this structure is through thin film deposition followed by anisotropic etching. In one embodiment, a single process tool is used to perform both deposition and etching, significantly improving the efficiency of this approach. Other methods for producing thin layers of well-controlled thickness include selective growth or DSA.

FIG8E illustrates a process operation involving bone removal. Bone feature 808 is removed to leave opening 822. In one embodiment, opening 822 has a width approximately the same as the width of opening 820, as depicted in FIG8E. In one embodiment, each of openings 820 and 822 has spacers 824 as sidewalls, spacers 824 being composed of a first material. As shown, some of spacers 824 are reassigned from previously designated spacers 810. In one embodiment, bone feature 808 is removed to provide more space for further small features to be created.

FIG8F illustrates a process operation involving continuous layer generation. Openings 820 and 822 are ultimately completely filled using continuous spacer formation. In an exemplary embodiment, spacer 826 is formed along the exposed sidewalls of spacer 824. In one such embodiment, spacer 826 is composed of a second material. In one embodiment, a final wide feature 828 is ultimately formed at the center of each of openings 820 and 822 at a stage when further spacer formation is undesirable or achievable. In one embodiment, the formation of final wide feature 828 involves the merging of material growth formed along adjacent sidewalls of spacer 826. In one such embodiment, the combined growth of materials provides final width features 828, each having a seam approximately centered within final width feature 828. In one embodiment, final width feature 828 is of a third material composition.

FIG8G illustrates a process operation involving planarization of the structure of FIG8F. In one embodiment, planarization is performed using a chemical mechanical polishing (CMP) operation. In one embodiment, the planarization process provides a flat structure prior to plug/cut and via process operations. Locations 828 centered directly beneath the original lithographic feature (which results in opening 822) and isolated midway therebetween (which results in opening 820) can be targeted to be larger to accommodate the larger size variations associated with the lithographic operation, as compared to a single film (etch) operation. In one embodiment, as shown, the structure of FIG8G is similar to or identical to that described in connection with FIG7A.

FIG8H illustrates a process operation involving the selective removal of all features composed of a first material, such as spacers 810/824 (corresponding to small features 716 of the first material type from the structure of FIG7A , as shown in FIG8G ). In one embodiment, small features 716 of the first material type are removed using a selective etching process that does not remove (or only minimally removes) the remaining spacer material. In the example embodiment shown in FIG8H , after removing small features 716 of the first material type, metal line patterned features 830 are formed within the openings created by the removal of all small features 716 of the first material type. Portions of metal line patterned features 830 are associated with underlying via patterned features 832. Although not depicted, selected ones of the small features 716 of the first material type may be retained (e.g., by a photolithographic blocking process that blocks the removal of selected ones of the small features 716 of the first material type) to form plug patterned features. In one embodiment, the metal line patterned features 830, the via patterned features 832, and any plug patterned features are ultimately patterned into the hard mask layer 806 and the transfer layer 804 for final patterning of the underlying layers. In another embodiment, as shown, the metal line patterned features 830, the via patterned features 832, and any plug patterned features actually represent metal lines, vias, and plugs formed in layer 834, as shown. Both the metal line patterned features 830 and the actual metal lines may have an overlying hard mask capping layer 836 to protect the features during subsequent processing of layer 834, as shown in Figure 8H. Referring again to Figure 8H, in one embodiment, by shifting only one spacer type, additional tolerance is provided for process variations in plug, via, and/or saw patterning operations.

8H' and 8H" illustrate cross-sectional views of an example structure following via and plug patterning, according to an embodiment of the present invention.

FIG8H′ illustrates a process operation involving the selective removal of all material from the backbone feature 710 of FIG8H and all small features 718 of the third material type. In one embodiment, the backbone feature 710 and the small features 718 of the third material type are removed using a selective etching process that does not remove (or only removes a small amount of) remaining spacer material or replaced spacer material. In the example embodiment shown in FIG8H′, after the backbone feature 710 and the small features 718 of the third material type are removed, second wire patterned features 838 are formed in most or all of the openings created when the backbone feature 710 and the small features 718 of the third material type were removed. In one embodiment, any remaining openings created when removing the backbone features 710 and the small features of the third material type 718 are filled with plug material 850 (e.g., to provide end features composed of a non-conductive material such as SiN or _SiO2 ), or are otherwise retained as plug regions. Portions of the second metal line patterned features 838 are associated with the underlying second via patterned features 840. In one embodiment, the second metal line patterned features 838, the second via patterned features 840, and any plug patterned features 850 are ultimately patterned into a hard mask layer 806 and a transfer layer 804 for final patterning of the underlying layers. In another embodiment, as shown, the second metal line patterned feature 838, the second via patterned feature 840, and any plug patterned feature 850 actually represent a metal line, a via, and a plug, respectively.

Each of the metal line second patterned feature 838 and the actual metal line, and each of the patterned plug feature 850 and the actual plug feature 850, may have an overlying hard mask capping layer 842 to protect the features during subsequent processing operations, as shown in FIG8H '. In one embodiment, the overlying hard mask capping layer 842 has a different composition than the overlying hard mask capping layer 836. Thus, in one embodiment, alternating features have different hard mask materials. This configuration can better facilitate subsequent connection of vias from subsequently formed layers above, with increased edge placement tolerance to prevent vias from reaching the wrong metal features.

It should be understood that because metal line 830 (or patterned feature) and second metal line 838 (or patterned feature) are formed in different processing operations, the composition of metal line 830 and second metal line 838 may be different. In an exemplary embodiment, Figure 8H" illustrates an example in which metal line 830' has a different composition than metal line 838. Therefore, the alternating features can be composed of different conductive materials.

It will be appreciated that certain older forms of spacer-based pitch segmentation techniques may be used for high volume manufacturing. The above-described embodiments surrounding a backbone approach may be implemented with spacer-based pitch segmentation extending one or two passes to achieve an extremely high number of stacked spacer formation operations. One or more embodiments provide a method for density scaling of semiconductor chips with high manufacturing yields. One or more embodiments provide a method for fabricating dense interconnects, or even transistors if applied to FEOL processing, with consistently well-formed feature sizes. It will be appreciated that reverse engineering of products fabricated using a backbone approach may reveal remarkably dense pitch features (e.g., sub-10 nm pitch features) with occasional wide one-dimensional (1D) features. Cross-sectional scanning electron microscopy (XSEM) can reveal "colored" (i.e., different in properties such as etch selectivity) hard masks on alternating features.

According to embodiments of the present invention, pitch segmentation is applied to provide a method for fabricating alternating metal lines in a BEOL fabrication scheme. One or more embodiments described herein relate to a pitch segmentation patterning process flow that increases the overlap tolerance for vias, cuts, and plugs. Embodiments can enable continuous scaling of the pitch of metal layers beyond the resolution capabilities of state-of-the-art lithography equipment. In one embodiment, the spacing between metal lines is constant and can be controlled to angstrom level accuracy using ALD. In one embodiment, the process flow is designed such that an "alternative ILD" flow is possible. That is, the ILD can be deposited after patterning and metallization are completed. The patterning process typically damages the ILD through the etch/clean steps; however, in this process, the ILD can be deposited last, thus avoiding damage during patterning.

To provide background, edge placement errors in via, saw, and plug patterning are problematic as feature sizes and pitches scale. State-of-the-art solutions to these problems involve attempts to tighten edge placement errors by improving scanner overlap and critical dimension (CD) control, or by using super-self-aligned integration. In contrast, the embodiments described herein relate to a process implementation that achieves similar improvements in edge placement error range without the need for lithography tools or super-self-alignment enhancements.

According to an embodiment of the present invention, metal lines are fabricated in two separate sequences of operations to double the amount of overlap tolerance for cut/plug and via patterning. In the first part of the exemplary process flow, a pitch-slicing method is used to pattern the metal lines, plugs, and then vias into the interlayer dielectric material. In the second part of the exemplary process flow, the trench/via openings are filled with metal (e.g., dual damascene metallization) and then polished. The sacrificial hard mask layer is then removed between the metal lines. The metal lines are then coated with a sacrificial dielectric material using, for example, atomic layer deposition (ALD). In the third part of the exemplary process flow, an isotropic spacer etch is performed to expose the bottom of the trench. Using a plug patterning flow, dielectric material is added to the locations where the metal line ends should occur, and via etching is performed on the complementary metal lines. The metal from the first metal line acts as an etch stop to prevent etching in these locations. In the fourth part of the exemplary process flow, the trenches are filled with metal and polished to expose the metal. After polishing, the sacrificial hard mask material is removed and, optionally, replaced with dielectric material and then polished again to complete the metallization process. By tuning the deposition of the dielectric material, air gaps can also be inserted. In addition, embodiments may involve the use of a sacrificial hard mask material (instead of metal). The sacrificial hard mask can be removed and replaced with metal during the "second" metallization operation.

In an example processing scheme, Figures 9A-9L illustrate oblique cross-sectional views of a portion of an integrated circuit layer representing various operations in a method involving pitch-splitting patterning for increased overlay tolerance for back-end-of-line (BEOL) interconnect fabrication, according to an embodiment of the present invention.

Referring to FIG. 9A , a starting point structure 900 is provided as a starting point for fabricating a new metallization layer. Starting point structure 900 includes a hard mask layer 902 disposed on a sacrificial layer 904, which in turn is disposed on an interlayer dielectric (ILD) layer 906. The ILD layer can be disposed above a substrate and, in one embodiment, above an underlying metallization layer. In one embodiment, hard mask layer 902 is a silicon nitride (SiN) or titanium nitride hard mask layer. In one embodiment, the sacrificial layer is a silicon layer, such as a polysilicon layer or an amorphous silicon layer.

Referring to FIG. 9B , the hard mask layer 902 and the sacrificial layer 904 of the structure of FIG. 9B are patterned. The hard mask layer 902 and the sacrificial layer 904 are patterned to form a patterned hard mask layer 908 and a patterned sacrificial layer 910, respectively. The patterned hard mask layer 908 and the patterned sacrificial layer 910 include patterns of first line openings 912 and line end regions 914. In one embodiment, the silicon sacrificial layer is suitable for patterning into fine features using an anisotropic plasma etching process. In one embodiment, a lithographic resist mask exposure and etching process is used to form a patterned hard mask layer 908 and a patterned sacrificial layer 910, with subsequent removal of the resist layer or stack. In one embodiment, the first line opening 912 has a grating type pattern, as depicted in FIG9B . In one embodiment, a pitch-slicing patterning scheme is used to form the pattern of the first line opening 912. Examples of suitable pitch-slicing schemes are described in more detail below. A subsequent line "cutting" or plug-retention lithographic process can then be used to define the line end region 914.

FIG9C illustrates the structure of FIG9B after patterning of the underlying via locations. Via openings 916 can be formed at selected locations in ILD layer 906 to form patterned ILD layer 918. In one embodiment, the vias are patterned using a self-aligned via process. The selected locations are formed within the areas of ILD layer 906 exposed by the first line of openings 912. In one embodiment, separate lithography and etching processes are used to form via openings 916, following the lithography patterning process used to form the first line of openings 912.

FIG9D illustrates the structure of FIG9C following the first metallization process. In one embodiment, a dual damascene metallization process is used, in which the vias and metal lines are filled simultaneously. Interconnects 920 and conductive vias 920 are formed in the first line and via openings 916. In one embodiment, a metal fill process is performed to provide the interconnects 920 and conductive vias 920. In one embodiment, the metal fill process is performed using metal deposition and a subsequent planarization treatment scheme, such as a chemical mechanical planarization (CMP) process. In the case where the patterned sacrificial hard mask layer 910 is substantially composed of silicon, a liner material may be deposited before forming the conductive fill layer to prevent silicidation of the patterned sacrificial hard mask layer 910.

FIG9E illustrates the structure of FIG9D following exposure of interconnect 920. Patterned hard mask layer 908 and patterned sacrificial layer 910 are removed to leave interconnect 920 exposed, with underlying conductive vias in patterned ILD layer 918. Line end openings 924 are revealed. Line end openings 924 provide breaks in the grating pattern of interconnect 920. In one embodiment, patterned hard mask layer 908 and patterned sacrificial layer 910 are removed using a selective wet etch process.

FIG9F illustrates the structure of FIG9E following formation of the conformal patterning layer. A spacer material layer 926 is formed over and conformally with the grating pattern of interconnect 920. In one embodiment, atomic layer deposition (ALD) is used due to its high conformal and extremely precise (e.g., controlled to angstrom levels). It should be understood that line end openings 924 are (in one embodiment) too short to effectively disrupt the normal grating pattern of interconnect 920 for the formation of conformal spacer material layer 926. In one such embodiment, line end openings 924 are filled with spacer material layer 926 without disrupting the normal grating pattern of interconnect 920. In one embodiment, spacer material layer 926 is deposited using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. In one embodiment, spacer material layer 926 is a silicon layer, such as a polysilicon layer or an amorphous silicon layer. In certain such embodiments, a liner material is deposited over interconnect 920 prior to forming the silicon spacer material layer to prevent silicidation of spacer material layer 926. In one embodiment, the line end cut (plug) is less than or equal to twice the spacer thickness so that it is completely filled with conformal dielectric material. If it is greater than 2 times the thickness, seams may form and the metal may short the wires together during subsequent processing.

FIG9G illustrates the structure of FIG9F after forming spacer lines from a spacer material layer. In one embodiment, spacers 928 are formed along the sidewalls of interconnect line 920 using an anisotropic plasma etching process. In one embodiment, a spacer material layer 926 remains in the line end opening 924 to form a line end placeholder 930 for interconnect line 920.

FIG9H illustrates the structure of FIG9G after the formation of a plug-filling layer. Plug-filling layer 932 is formed between spacers 928 adjacent to interconnect 920. Plug-filling layer 932 is initially formed in the location where the second set of interconnects will eventually be formed. In one embodiment, plug-filling layer 932 is formed using a deposition and planarization process that confines plug-filling layer 932 between spacers 928.

FIG9I illustrates the structure of FIG9H after patterning the plug-receiving layer. Plug-receiving layer 932 is patterned to leave plug-receiving layers 934 in selected locations where the line ends are ultimately formed. In one embodiment, a lithography resist mask exposure and etch process is used to form plug-receiving layers 934, with subsequent removal of the resist layer or stack.

FIG9J illustrates the structure of FIG9I following the second metallization process. Interconnect lines 936 are formed in openings (second line openings) formed during the patterning of plug-receiving layer 932 to form plug-receiving layers 934. Additionally, although the patterning omits a separate processing operation, via openings (and ultimately conductive vias 938) can be formed in selected locations beneath conductive lines 936. This process results in a double-patterned (two different via patterning operations) ILD layer 940, as depicted in FIG9J .

In one embodiment, a metal fill process is performed to provide interconnects 936 and conductive vias 938. In one embodiment, the metal fill process is performed using metal deposition and a subsequent planarization process, such as a chemical mechanical planarization (CMP) process. In the case where the spacers 928 are substantially composed of silicon, a liner material may be deposited before forming the conductive fill layer to prevent silicidation of the spacers 928.

It should be understood that, in one embodiment, because interconnect 936 (and corresponding conductive via 938) is formed in a later process than the process used to fabricate interconnect 920 (and corresponding conductive via 922), interconnect 936 can be fabricated using a different material than that used to fabricate conductive line 920. In such an embodiment, the metallization layer ultimately includes alternating conductive interconnects of different first and second compositions.

FIG9K illustrates the structure of FIG9J after the exposure of two sets of interconnects 920 and 936. Spacers 928, line terminal placeholders 930, and plug placeholders 934 are removed to leave exposed interconnects 920 and 936, respectively, with underlying conductive vias 922 and 938 in patterned ILD layer 940. Line terminal openings 942 are revealed. Line terminal openings 942 provide breaks in the grating pattern of interconnect 920 and in the grating pattern of interconnect 936. In one embodiment, spacers 928, line terminal placeholders 930, and plug placeholders 934 are removed using a selective wet etch process.

In one embodiment, the structure of FIG. 9K represents the final metallization structure with an air-gap architecture. That is, because interconnects 920 and 936 are finally exposed to the process described herein, the air-gap architecture is enabled. In another embodiment, because interconnects 920 and 936 are exposed at this stage in the process, there is an opportunity to remove the sidewalls of the interconnect's diffusion barrier layer. For example, in one embodiment, the removal of this diffusion barrier layer physically thins the conductive features of interconnects 920 and 936. In another embodiment, the resistance of interconnects 920 and 936 is reduced upon removal of this diffusion barrier layer. 9K , characteristic sidewall portions 960 of interconnects 920 and 936 are exposed, while portions 962 beneath these lines are not. Thus, in one embodiment, the diffusion barrier layer of interconnects 920 and 936 is removed from the sidewalls 960 of interconnects 920 and 936 but not from regions 962 of interconnects 920 and 936. In a particular embodiment, the removal of this portion of the diffusion barrier layer involves the removal of Ta and/or TaN layers.

Thus, referring to operations 9A-9K, in one embodiment, a method for fabricating a back-end-of-line (BEOL) metallization layer includes forming a plurality of conductive lines 920/936 in a sacrificial material 928 formed above a substrate. Each of the plurality of conductive lines 920/936 includes a barrier layer formed along the bottom and sidewalls of the conductive fill layer. The sacrificial material 928 is then removed. The barrier layer is removed from the sidewalls of the conductive fill layer (e.g., at location 960). In one embodiment, removing the barrier layer from the sidewalls of the conductive fill layer includes removing tantalum nitride or a tantalum layer from the sidewalls of the conductive fill layer comprising a material selected from the group consisting of Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au, and alloys thereof.

FIG9L illustrates the structure of FIG9K after the permanent ILD layer is formed. Interlayer dielectric (ILD) layers 946/948 are formed between interconnects 920 and 936. ILD layers 946/948 include a portion 946 between interconnects 920 and 936. ILD layers 946/948 also include a line termination (or dielectric plug) portion 948 between interconnects 920 and 936 at the locations of the line breaks.

Referring again to FIG. 9L , in one embodiment, semiconductor structure 999 includes a substrate (with ILD layer 940 shown thereunder). A plurality of alternating first 920 and second 936 conductive line types are arranged along the same direction of back-end-of-line (BEOL) metallization layers disposed above the substrate. In one embodiment, as described in connection with FIG. 9K , the overall composition of first conductive line type 920 is different from the overall composition of second conductive line type 936. In certain such embodiments, the overall composition of first conductive line type 920 consists essentially of copper, while the overall composition of second conductive line type 936 consists essentially of a material selected from the group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au, and alloys thereof, or vice versa. However, in another embodiment, the overall composition of the first conductive line type 920 is the same as the overall composition of the second conductive line type 936.

In one embodiment, the lines of the first conductive line type 920 are separated by a pitch, while the lines of the second conductive line type 936 are separated by the same pitch. In one embodiment, a plurality of alternating first and second conductive line types are arranged in an interlayer dielectric (ILD) layer 946/948. However, in another embodiment, the plurality of alternating first and second conductive line types 920/936 are separated by an air gap, as described in connection with FIG. 9K .

In one embodiment, each of the plurality of alternating first and second conductive line types 920/936 includes a barrier layer disposed along the bottom and sidewalls of the line. However, in another embodiment, each of the plurality of alternating first and second conductive line types 920/936 includes a barrier layer disposed along the bottom 962 of the line, but not along the sidewalls 960 of the line, as illustrated in the embodiment of FIG. 9K . In one embodiment, one or more of the plurality of alternating first and second conductive line types 920/936 are connected to underlying vias 922/938, which are connected to the underlying metallization layer of the semiconductor structure. In one embodiment, one or more of the plurality of alternating first and second conductive line types 920/936 are interrupted by dielectric plugs 948.

The resulting structure 999 (or the air gap structure of FIG. 9K ) as described in connection with FIG. 9L can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, structure 999 of FIG. 9L (or the structure of FIG. 9K ) can represent the final metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations can be performed in an alternative order, that not every operation needs to be performed, and/or that additional process operations can be performed. It should also be understood that the above examples have focused on metal line and plug or terminal formation. However, in other embodiments, a similar approach can be used to form via openings in an ILD layer.

According to one or more embodiments of the present invention, a self-aligned DSA dual block or selective growth bottom-up approach is described. One or more embodiments described herein relate to self-aligned via and plug patterning. The self-aligned form of the process described herein may be based on a directed self-polymerization (DSA) mechanism, as described in more detail below. However, it should be understood that its selective growth mechanism can be utilized in place of (or in conjunction with) a DSA-based approach. In one embodiment, the process described herein is to enable the implementation of self-aligned metallization for back-end process feature fabrication. More specifically, one or more embodiments relate to an approach that utilizes an underlying metal as a template to create conductive vias and non-conductive spaces or interruptions (referred to as "plugs") between the metals.

Figures 10A-10M illustrate portions of an integrated circuit layer representing various operations in a method for self-aligned via and metal patterning, according to an embodiment of the present invention. In each illustration of each of the operations, a plan view is shown on the left, and a corresponding cross-sectional view is shown on the right. These views will be referred to herein as corresponding cross-sectional and plan views.

FIG10A illustrates a plan view and corresponding cross-sectional views of a front metallization structure according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (a), a starting structure 1000 includes a pattern of metal lines 1002 and interlayer dielectric lines (ILD) 1004. Starting structure 1000 can be patterned as a grating pattern, with metal lines spaced at a constant pitch and having a constant width (e.g., for DSA embodiments, but not necessarily for directional selective growth embodiments), as depicted in FIG10A. The pattern can be fabricated, for example, by halving or quartering the pitch. Some lines may be associated with underlying vias, such as line 1002' shown in one example in the cross-sectional view.

Referring again to FIG. 10A , alternative options (b)-(f) discuss situations in which an additional film is formed (e.g., deposited, grown, or left as an artifact from a previous patterning process) on the surface of one (or both) of metal line 1002 and interlayer dielectric line 1004. In example (b), additional film 1006 is disposed on interlayer dielectric line 1004. In example (c), additional film 1008 is disposed on metal line 1002. In example (d), additional film 1006 is disposed on interlayer dielectric line 1004, while additional film 1008 is disposed on metal line 1002. Furthermore, although the metal line 1002 and the interlayer dielectric line 1004 are depicted as coplanar in (a), in other embodiments, they may be non-coplanar. For example, in (e), the metal line 1002 protrudes above the interlayer dielectric line 1004. In example (f), the metal line 1002 is recessed below the interlayer dielectric line 1004.

Referring again to examples (b)-(d), additional layers (e.g., layers 1006 or 1008) can be used as hard masks (HMs) or protective layers or to enable selective growth and/or autopolymerization as described below in connection with subsequent processing operations. Such additional layers can also be used to protect the ILD from further processing. In addition, selectively depositing another material over the metal lines may be advantageous for similar reasons. Referring again to examples (e) and (f), the ILD lines or metal lines can also be recessed using any combination of protective/HM materials on either or both surfaces. In summary, at this stage, there are several options for preparing the final lower surface for selective or directional autopolymerization processes.

FIG10B illustrates a plan view and corresponding cross-sectional views of the structure of FIG10A after formation of interlayer dielectric (ILD) lines 1010, subsequent to the formation of the structure of FIG10A, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (c) taken along axes a-a' and c-c', respectively, ILD lines 1010 are formed in the grating structure in a direction perpendicular to underlying lines 1004. In one embodiment, the blanket film of material for lines 1010 is deposited by chemical vapor deposition or a similar technique. In one embodiment, the capping film is then patterned using lithography and etching processes (which may involve, for example, spacer-based quadruple patterning (SBQP) or pitch quartering). It should be understood that the grating pattern of line 1010 can be fabricated by a number of methods, including EUV and/or EBDW lithography, directed autopolymerization, and the like. As will be described in more detail below, subsequent metal layers will therefore be patterned in an orthogonal direction relative to the previous metal layer, since the grating of line 1010 is orthogonal to the direction of the underlying structure. In one embodiment, a single 193nm lithographic mask is used to align/register to the previous metal layer 1002 (e.g., the grating of line 1010 is aligned in X to the previous layer "plug" pattern and in Y to the previous metal grating). Referring to cross-sectional structures (b) and (d), a hard mask 1012 can be formed over the dielectric line 1010 or left in place after the dielectric line 1010 is patterned. The hard mask 1012 can be used to protect the line 1010 during subsequent patterning steps. As described in more detail below, the formation of line 1010 in a raster pattern exposes areas of the previous metal line 1002 and the previous ILD line 1004 (or the corresponding hard mask layer above 1002/1004). These exposed areas correspond to all possible future via locations where metal is exposed. In one embodiment, the previous metal layer (e.g., line 1002) is protected, marked, brushed, etc. at this point in the process flow.

FIG10C illustrates a plan view and corresponding cross-sectional views of the structure of FIG10B after selectively distinguishing all potential via locations from all plug locations, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', b-b', c-c', and d-d', respectively, following the formation of ILD line 1010, a surface modification layer 1014 is formed on the exposed areas of underlying ILD line 1004. In one embodiment, surface modification layer 1014 is a dielectric layer. In one embodiment, surface modification layer 1014 is formed by a selective bottom-up growth process. In one such embodiment, the bottom-up growth approach involves a directed self-polymerization (DSA) brush coating having a polymer component that preferentially aggregates on the underlying ILD lines 1004 or (alternatively) on the metal lines 1002 (or on a sacrificial layer that is disposed on or grown on the underlying metal or ILD material).

FIG10D illustrates a plan view and corresponding cross-sectional views of the structure of FIG10C following the addition of differential polymers to the exposed portions of the underlying metal and ILD lines of FIG10C, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', b-b', c-c', and d-d', respectively, directed self-polymerization (DSA) or selective growth on the exposed portions of the underlying metal/ILD 1002/1004 grating is used to form intermediate lines 1016 having alternating polymers or alternating polymer compositions between the ILD lines 1010. For example, as shown, polymer 1016A (or polymer component 1016A) is formed on or over the exposed portion of interlayer dielectric (ILD) line 1004 in FIG 10C , while polymer 1016B (or polymer component 1016B) is formed on or over the exposed portion of metal line 1002 in FIG 10C . Although polymer 1016A is formed on or over surface modification layer 1014 described in connection with FIG 10C (see cross-sectional views (b) and (d) of FIG 10D ), it should be understood that in other embodiments, surface modification layer 1014 may be omitted or alternating polymers or alternating polymer components may instead be formed directly in the structure described in connection with FIG 10B .

10D , in one embodiment, once the surface of the underlying structure (e.g., structure 1000 of FIG. 10A ) has been prepared (e.g., as in the structures of FIG. 10B or FIG. 10C ) or is directly used, a 50-50 diblock copolymer, such as polystyrene-polymethyl methacrylate (PS-PMMA), is coated on the substrate and annealed to drive self-polymerization, resulting in the polymer 1016A/polymer 1016B layer 1016 of FIG. 10D . In this embodiment, the diblock copolymer separates upon exposure to the underlying material between the ILD lines 1010 using appropriate surface energy conditions. For example, in one particular embodiment, polystyrene is selectively aligned to the exposed portion of the underlying metal line 1002 (or a corresponding metal line cap or hard mask material), while polymethylmethacrylate is selectively aligned to the exposed portion of the ILD line 1004 (or a corresponding metal line cap or hard mask material).

Therefore, in one embodiment, the underlying metal and ILD grid (e.g., exposed between ILD lines 1010) are regenerated in a block copolymer (BCP, i.e., polymer 1016A/polymer 1016B). This is particularly true if the BCP pitch is comparable to the underlying grating pitch. The polymer grid (polymer 1016A/polymer 1016B), in one embodiment, is robust to some small deviation from a properly aligned grid. For example, if the small plugs effectively set a material such as oxide (where a properly aligned grid would have metal), a properly aligned polymer 1016A/polymer 1016B grid can still be achieved. However, because the ILD line grating (in one embodiment) is an idealized grating structure with no metal fractures in the ILD backbone, it may be desirable to make the ILD surface neutral because two types of polymer (1016A and 1016B) will (in this example) be exposed to the ILD-type material and only one type will be exposed to the metal.

In one embodiment, the thickness of the applied polymer (polymer 1016A/polymer 1016B) is approximately the same as (or slightly thicker than) the final thickness of the ILD layer ultimately formed in its place. In one embodiment, as described in more detail below, the polymer grating is not formed as an etch resist, but rather as a scaffold around which a permanent ILD layer is ultimately grown. As such, the thickness of polymer 1016 (polymer 1016A/polymer 1016B) can be important because it can be used to define the final thickness of the subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown in FIG. 10D is ultimately replaced with an ILD grating of approximately the same thickness.

In one embodiment, as described above, the polymer 1016A/polymer 1016B grid of Figure 10D is a block copolymer. In this embodiment, a block copolymer molecule is a polymer molecule formed by chains of covalently bonded monomers. In a block copolymer, there are at least two different types of monomers, and these different types of monomers are primarily included in different blocks or adjacent sequences of monomers. The block copolymer molecule shown includes blocks of polymer 1016A and blocks of polymer 1016B. In one embodiment, the blocks of polymer 1016A primarily include chains of covalently bonded monomer A (e.g., A-A-A-A-A...), while the blocks of polymer 1016B primarily include chains of covalently bonded monomer B (e.g., B-B-B-B-B...). Monomers A and B can represent any of the different types of monomers used in block copolymers known in the art. For example, monomer A can represent a monomer used to form polystyrene, while monomer B can represent a monomer used to form polymethyl methacrylate (PMMA), although the scope of the invention is not so limited. In other embodiments, there can be more than two blocks. Furthermore, in other embodiments, each of the blocks can include a different type of monomer (e.g., each block can itself be a copolymer). In one embodiment, the blocks of polymer 1016A and the blocks of polymer 1016B are covalently bonded together. The blocks of polymer 1016A and the blocks of polymer 1016B can be approximately the same length, or one block can be significantly longer than the other.

Typically, the blocks of a block copolymer (e.g., block of polymer 1016A and block of polymer 1016B) can each have different chemical properties. For example, one of the blocks can be relatively hydrophobic (e.g., repels water) while the other can be relatively hydrophilic (attracts water). At least conceptually, one of the blocks can be relatively oil-like while the other can be relatively water-like. These differences in chemical properties between different block polymers (whether hydrophilic-hydrophobic or otherwise) can cause the block copolymer molecules to self-polymerize. For example, self-polymerization can be based on microphase separation of the polymer blocks. Conceptually, this can be analogous to the phase separation of oil and water, which are normally immiscible. Similarly, differences in hydrophilicity between polymer blocks (e.g., one block is relatively hydrophobic and another is relatively hydrophilic) can result in a roughly analogous microphase separation, where different polymer blocks attempt to "separate" from each other because they chemically dislike each other.

However, in one embodiment, because the polymer blocks are covalently bonded to one another, they cannot completely separate on a macroscopic scale. Instead, polymer blocks of a given type tend to separate or aggregate with polymer blocks of other molecules of the same type in extremely small (e.g., nanoscale) regions or phases. The specific size and shape of the regions or microphases typically depends, at least in part, on the relative lengths of the polymer blocks. In one embodiment, by way of example (as shown in FIG. 10D ), in a two-block copolymer, if the blocks are of approximately the same length, a grid-like pattern of alternating polymer 1016A lines and polymer 1016B lines is produced. In another embodiment (not shown), in a two-block copolymer, if one of the blocks is longer than the other, but not significantly longer than the other, a columnar structure can be formed. In a columnar structure, the block copolymer molecules can align with its shorter polymer blocks within the microphase separated into columns, and with its longer polymer blocks extending away from and surrounding the columns. For example, if the blocks of polymer 1016A are longer than the blocks of polymer 1016B (but not significantly longer), a columnar structure can be formed in which many block copolymer molecules align with its shorter blocks of polymer 1016B, forming a columnar structure surrounded by the phase having the longer blocks of polymer 1016A. When this occurs over an area of sufficient size, a two-dimensional array of generally hexagonally packed columnar structures can be formed.

In one embodiment, the polymer 1016A/polymer 1016B grating is first applied as an unpolymerized block copolymer layer portion, which includes (for example) block copolymer material applied by a brush or other coating process. The unpolymerized form refers to the state in which (at the time of deposition) the block copolymer has not yet substantially phase-separated and/or self-polymerized to form nanostructures. In this unpolymerized form, the block polymer molecules are quite random, with different polymer blocks oriented and arranged relatively randomly, as opposed to the polymerized block copolymer layer portion discussed with respect to the resulting structure of FIG10D. The unpolymerized block copolymer layer portion can be applied in a variety of different ways. For example, the block copolymer can be dissolved in a solvent and then spin-coated onto a surface. Alternatively, the unpolymerized block copolymer can be sprayed, dip-coated, dip-coated, or otherwise applied or coated onto a surface. Other methods of applying block copolymers, as well as other methods known in the art for applying similar organic coatings, can potentially be used. The unpolymerized layer can then form a polymerized block copolymer layer portion, for example, by microphase separation and/or self-polymerization of the unpolymerized block copolymer layer portion. Microphase separation and/or self-polymerization occurs through rearrangement and/or reorientation of the block copolymer molecules, and in particular, the rearrangement and/or reorientation of different polymer blocks of the block copolymer molecules.

In this embodiment, an annealing treatment may be applied to the unpolymerized block copolymer to initiate, accelerate, increase, or enhance the quality of microphase separation and/or autopolymerization. In certain embodiments, the annealing treatment may include a treatment operable to increase the temperature of the block copolymer. An example of such a treatment is baking the layer, heating the layer in an oven or over a heat lamp, applying infrared radiation to the layer, or applying heat to the layer or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate microphase separation and/or autopolymerization of the block copolymer without damaging the block copolymer or any other important materials or structures of the integrated circuit substrate. Typically, the heating range may be from about 50°C to about 300°C, or from 75°C to about 250°C, but not exceeding the thermal degradation limits of the block copolymer or integrated circuit substrate. Heating or annealing can help provide energy to the block copolymer molecules, making them more mobile/elastic to increase the rate of microphase separation and/or improve the quality of microphase separation. This microphase separation or rearrangement/reorientation of the block copolymer molecules can lead to self-polymerization to form extremely small (e.g., nanoscale) structures. Self-polymerization can occur under the influence of surface energy, molecular affinity, and other surface-related and chemical-related forces.

In any case, in certain embodiments, self-polymerization of block copolymers (whether or not based on hydrophobic-hydrophilic differentiation) can be used to form extremely small periodic structures (e.g., precisely spaced nanoscale structures or wires). In certain embodiments, it can be used to form nanoscale wires or other nanoscale structures that can ultimately be used to form vias and openings. In certain embodiments, directed self-polymerization of block copolymers can be used to form self-aligned vias and interconnects, as described in more detail below.

Referring again to FIG. 10D , in one embodiment, for a DSA process, the growth process can be influenced by the sidewalls of the ILD line 1010 material, in addition to the direction from the underlying ILD/metal 1004/1002 surface. Thus, in one embodiment, DSA is controlled by both epitaxy (from the sidewalls of the line 1010) and chemoepitaxy (from the exposed surface features below). Physically and chemically confining the DSA process can significantly assist the process from a defectivity perspective. The resulting polymer 1016A/1016B has fewer degrees of freedom and is completely trapped in all directions, both chemically (e.g., by brushing the underlying ILD or metal line, or surface modification thereof) and physically (e.g., from trenches formed between the ILD lines 1010).

In an alternative embodiment, a selective growth process is used in place of the DSA approach. FIG10E illustrates a cross-sectional view of the structure of FIG10B subsequent to selecting exposed portions of the underlying metal and ILD lines, in accordance with another embodiment of the present invention. Referring to FIG10E , a first material type 1090 is grown over the exposed portions of the underlying ILD lines 1004. A second (different) material type 1092 is grown over the exposed portions of the underlying metal lines 1002. In one embodiment, the selective growth is achieved by a dep-etch-dep-etch approach for each of the first and second materials, resulting in multiple layers of each of those materials, as depicted in FIG10E . This approach can be desirable compared to conventional selective growth techniques, which can form films with a "mushroom-top" shape. The tendency for mushroom-top film growth can be reduced through an alternating deposition/etch/deposition (dep-etch-dep-etch) approach. In another embodiment, a film is selectively deposited over the metal, followed by a different film selectively deposited over the ILD (or vice versa), and this is repeated multiple times to create a sandwich-like stack. In another embodiment, both materials are grown simultaneously in a chamber (e.g., by a CVD-style process), selectively growing on exposed areas of the underlying substrate.

FIG10F illustrates a plan view and corresponding cross-sectional views of the structure of FIG10D following polymer removal, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', b-b', c-c', and d-d', respectively, polymer or polymer portion 1016A is removed to re-expose ILD line 1004 (or a hard mask or capping layer formed over ILD line 1004), while polymer or polymer portion 1016B remains over metal line 1002. In one embodiment, a deep ultraviolet (DUV) bulk exposure followed by a wet etch or selective dry etch is used to selectively remove polymer 1016A. It should be understood that instead of first removing the polymer from the ILD lines 1004 (as shown), removal from the metal lines 1002 may alternatively be performed first. Alternatively, a dielectric film is selectively grown over this region and a hybrid support is not used.

FIG10G illustrates a plan view and corresponding cross-sectional views of the structure of FIG10F following the formation of an ILD material in the locations opened by the removal of a polymer, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', b-b', c-c', and d-d', respectively, the exposed areas of the underlying ILD lines 1004 are filled with a permanent interlayer dielectric (ILD) layer 1018. As a result, the open spaces between all possible via locations are filled with the ILD layer 1018, including a hard mask layer 1020 disposed thereon, as depicted in the plan view and cross-sectional views (b) and (d) of FIG10G. It should be understood that the material of the ILD layer 1018 does not need to be the same material as the ILD lines 1010. In one embodiment, the ILD layer 1018 is formed by a deposition and polishing process. In the case where the ILD layer 1018 is formed with an accompanying hard mask layer 1020, a special ILD fill material may be used (e.g., polymer-encapsulated nanoparticles in the ILD that fill the holes/trench). In this case, a polishing operation may not be required.

Referring again to FIG. 10G , in one embodiment, the resulting structure comprises a uniform ILD structure (ILD lines 1010 + ILD layer 1018), with all potential plug locations covered with hard mask 1020 and all potential vias located within regions of polymer 1016B. In this embodiment, ILD lines 1010 and ILD layer 1018 are composed of the same material. In another such embodiment, ILD lines 1010 and ILD layer 1018 are composed of different ILD materials. In either case, in a particular embodiment, distinctions such as seams between the materials of ILD lines 1010 and ILD layer 1018 can be observed in the final structure. An example seam 1099 is shown in FIG. 10G for illustration purposes.

FIG10H illustrates a plan view and corresponding cross-sectional views of the structure of FIG10G following via patterning, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', b-b', c-c', and d-d', respectively, via locations 1022A, 1022B, and 1022C are opened by removing polymer 1016B in selected locations. In one embodiment, selective via location formation is accomplished using lithography techniques. In one such embodiment, polymer 1016B is entirely removed with ash and refilled with photoresist. Photoresists can be highly sensitive and exhibit significant acid diffusion and aggressive deprotection or crosslinking (depending on the resist tint) because the latent image is confined in two directions by the ILD (e.g., by ILD lines 1010 and ILD layer 1018). The resist acts as a digital switch, turning "on" or "off," depending on whether a via is desired in a particular location. Ideally, the photoresist can be applied to fill only the via without overflowing. In one embodiment, via locations 1022A, 1022B, and 1022C are fully confined to the process, such that line edge or width roughness (LWR), as well as line breakup and/or reflections, are mitigated (if not eliminated). In one embodiment, low dose is used with EUV/EBDW and the run rate is significantly increased. In one embodiment, an additional advantage of utilizing EBDW is that there is only a single type/size of shot that can increase the run rate by significantly reducing the number of apertures required and reducing the dose that needs to be delivered. In the case where 193nm immersion lithography is used, in one embodiment, the process flow limits the via locations to two directions so that the size of the vias actually patterned is twice the size of the actual vias on the wafer (e.g., assuming a 1:1 line/space pattern). Alternatively, the via locations can be selected in reverse tone, where the vias that need to be retained are protected with photoresist while the remaining locations are removed and later filled with ILD. This approach allows for a single metal fill/polish process at the end of the patterning flow rather than two separate metal deposition steps.

FIG10I illustrates a plan view and corresponding cross-sectional views of the structure of FIG10H subsequent to via formation, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', b-b', c-c', and d-d', respectively, via locations 1022A, 1022B, and 1022C are filled with metal to form vias 1024A, 1024B, and 1024C, respectively. In one embodiment, via locations 1022A, 1022B, and 1022C are filled with excess metal, and a subsequent polishing operation is performed. However, in another embodiment, via locations 1022A, 1022B, and 1022C are filled without metal overfill and the polishing operation is omitted. It should be understood that the via filling shown in FIG. 10I can be skipped in the inverse tone via selection method.

FIG10J illustrates a plan view and corresponding cross-sectional views of the structure of FIG10I following removal of the second polymer and replacement with an ILD material, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', b-b', c-c', and d-d', respectively, the remaining polymer or polymer portion 1016B (e.g., where the via location has not yet been selected) is removed to re-expose the metal line 1002. Subsequently, an ILD layer 1026 is formed in the location where the remaining polymer or polymer portion 1016B was removed, as depicted in FIG10J.

Referring again to FIG. 10J , in one embodiment, the resulting structure comprises a uniform ILD structure (ILD line 1010 + ILD layer 1018 + ILD layer 1026), with all potential plug locations covered with a hard mask 1020. In this embodiment, the ILD line 1010, ILD layer 1018, and ILD layer 1026 are composed of the same material. In another embodiment, two of the ILD line 1010, ILD layer 1018, and ILD layer 1026 are composed of the same material, and the third is composed of a different ILD material. In yet another embodiment, the ILD line 1010, ILD layer 1018, and ILD layer 1026 are each composed of a different ILD material. In either case, in a particular embodiment, distinctions such as seams between the material of ILD line 1010 and ILD layer 1026 can be observed in the final structure. Example seams 1097 are shown in FIG. 10J for illustration. Similarly, distinctions such as seams between the material of ILD layer 1018 and ILD layer 1026 can be observed in the final structure. Example seams 1098 are shown in FIG. 10J for illustration.

FIG10K illustrates a plan view and corresponding cross-sectional views of the structure of FIG10J following patterning of the resist or mask at selected plug locations, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b), taken along axes a-a' and b-b', respectively, plug locations 1028A, 1028B, and 1028C are retained by forming a mask or resist layer over those locations. This retained patterning can be referred to as metal-end-to-end lithographic patterning, where the plug locations are determined to be where breaks in the subsequently formed metal lines are desired. It should be understood that because the plug locations can only be in those locations where the ILD layer 1018/hard mask 1020 is placed, the plug can occur above the previous layer ILD line 1004. In one embodiment, patterning is achieved using a lithography operation (e.g., EUV, EBDW, or immersion 193nm). In one embodiment, the process shown in Figure 10K illustrates the use of a positive tone patterning process, in which the space between the metals is retained where desired. It should be understood that in another embodiment, it is also possible to open the holes and reverse the tone of the process.

FIG10L illustrates a plan view and corresponding cross-sectional views of the structure of FIG10K , subsequent to hard mask removal and ILD layer recessing, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a' and b-b', respectively, hard mask 1020 is removed and ILD layer 1018 and ILD layer 1026 are recessed to form recessed ILD layer 1018' and recessed ILD layer 1026', respectively, by etching these layers below their original topmost surfaces. It should be understood that recessing ILD layer 1018 and ILD layer 1026 is performed without etching or recessing ILD line 1010. Selectivity can be achieved by using a hard mask layer 1012 over the ILD lines (as depicted in cross-sectional views (a) and (b)). Alternatively, in the case where ILD lines 1010 are composed of an ILD material different from the material of ILD layers 1018 and 1026, selective etching can still be used even in the absence of hard mask 1012. Recessing of ILD layers 1018 and 1026 is used to provide locations for second-level metal lines, such as those isolated by ILD lines 1010, as described below. The extent or depth of the recess (in one embodiment) is selected based on the desired final thickness of the metal lines formed thereon. It should be understood that the ILD layer 1018 in the plug locations 1028A, 1028B, and 1028C is not recessed.

FIG10M illustrates a plan view and corresponding cross-sectional views of the structure of FIG10L subsequent to metal line formation, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a), (b), and (c), taken along axes a-a', b-b', and b-b', respectively, metal for forming metal interconnects is conformally formed over the structure of FIG10L. The metal is then planarized (e.g., by CMP) to provide metal lines 1030, which are confined to locations above recessed ILD layer 1018' and recessed ILD layer 1026'. Metal line 1030 is coupled to underlying metal line 1002 through predetermined via locations 1024A, 1024B, and 1024C (1024B is shown in cross-sectional view (c); note: for illustrative purposes, another via 1032 is depicted directly adjacent to plug 1028B in cross-sectional view (b), even though this is inconsistent with previous diagrams). Metal lines 1030 are isolated from each other by ILD lines 1010 and interrupted or separated by remaining plugs 1028A, 1028B, and 1028C. Any hard mask remaining on the plug locations and/or ILD line 1010 can be removed during this portion of the process flow, as depicted in FIG10M. The metal (e.g., copper and associated barrier and seed layers) deposition and planarization processes used to form the metal lines 1030 may be those typically used in standard back-end-of-line (BEOL) single or double damascene processes. In one embodiment, the ILD lines 1010 may be removed in subsequent manufacturing operations to provide air gaps between the resulting metal lines 1030.

The structure of Figure 10M can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 10M can represent the last metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations can be performed in an alternative order, not every operation needs to be performed and/or additional process operations can be performed. Furthermore, although the above-described process flow focuses on the application of directed self-polymerization (DSA), selective growth processes can also be used alternatively at one or more locations in the process flow. In any case, the resulting structure enables it to be focused directly on the fabrication of vias on the underlying metal lines. That is, the vias can have a wider, narrower, or the same thickness as the underlying metal lines, for example, due to a non-perfectly selective etch process. However, in one embodiment, the center of the via is directly aligned (matched) with the center of the metal line. As such, in one embodiment, deviations due to conventional lithography/damascene patterning (which would otherwise need to be accommodated) are not a factor in the resulting structure described herein.

One or more embodiments described herein relate to front-end self-aligned via and plug patterning. The self-aligned aspect of the process described herein can be based on a directed self-polymerization (DSA) mechanism, as described in more detail below. However, it should be understood that selective growth mechanisms can be utilized in place of (or in combination with) DSA-based approaches. In one embodiment, the process described herein enables the implementation of self-aligned metallization for back-end-of-line feature fabrication.

Figures 11A-11M illustrate portions of an integrated circuit layer representing various operations in a method for self-aligned via and metal patterning, according to an embodiment of the present invention. In each illustration of each of the operations, a plan view is shown on the left, and a corresponding cross-sectional view is shown on the right. These views will be referred to herein as corresponding cross-sectional views and plan views.

FIG11A illustrates a plan view and corresponding cross-sectional views of an alternative front metallization structure, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view alternative (a), a starting structure 1100 includes a pattern of metal lines 1102 and interlayer dielectric lines (ILD) 1104. The starting structure 1100 can be patterned as a grating pattern with metal lines spaced at a constant pitch and having a constant width, as depicted in FIG11A, if self-polymerizing materials are to be used. If a directional selective growth technique is used, the underlying pattern does not need to be of a single pitch or width. The pattern can, for example, be fabricated with a pitch halved or a pitch quartered. Some lines may be associated with underlying vias, such as line 1102' shown in one example in the cross-sectional view.

Referring again to FIG. 11A , alternative options (b)-(f) discuss situations in which an additional film is formed (e.g., deposited, grown, or left as an artifact from a previous patterning process) on the surface of one (or both) of the metal line 1102 and the interlayer dielectric line 1104. In example (b), the additional film 1106 is disposed on the interlayer dielectric line 1104. In example (c), the additional film 1108 is disposed on the metal line 1102. In example (d), the additional film 1106 is disposed on the interlayer dielectric line 1104, while the additional film 1108 is disposed on the metal line 1102. Furthermore, although the metal line 1102 and the interlayer dielectric line 1104 are depicted as coplanar in (a), in other embodiments, they may be non-coplanar. For example, in (e), the metal line 1102 protrudes above the interlayer dielectric line 1104. In example (f), the metal line 1102 is recessed below the interlayer dielectric line 1104.

Referring again to examples (b)-(d), additional layers (e.g., layers 1106 or 1108) can be used as hard masks (HMs) or protective layers or to enable selective growth and/or autopolymerization as described below in connection with subsequent processing operations. Such additional layers can also be used to protect the ILD from further processing. In addition, selectively depositing another material over the metal lines may be advantageous for similar reasons. Referring again to examples (e) and (f), the ILD lines or metal lines can also be recessed using any combination of protective/HM materials on either or both surfaces. In summary, at this stage, there are several options for preparing the final lower surface for selective or directional autopolymerization processes.

FIG11B illustrates a plan view and corresponding cross-sectional views of an alternative for directed self-polymerization (DSA) growth on an underlying metal/ILD grating (e.g., on the structure shown in FIG11A ), according to an embodiment of the present invention. Referring to the plan view, structure 1110 includes a layer having alternating polymers or alternating polymer components. For example, as shown, polymer A (or polymer component A) is formed on or over interlayer dielectric (ILD) line 1104 of FIG11A , and polymer B (or polymer component B) is formed on or over metal line 1102 of FIG11A . Referring to the cross-sectional views, in (a), polymer A (or polymer component A) is formed on ILD line 1104, and polymer B (or polymer component B) is formed on metal line 1102. In (b), polymer A (or polymer component A) is formed on an additional film 1106 formed on the ILD line 1104, and polymer B (or polymer component B) is formed on the metal line 1102. In (c), polymer A (or polymer component A) is formed on the ILD line 1104, and polymer B (or polymer component B) is formed on an additional film 1108 formed on the metal line 1102. In (d), polymer A (or polymer component A) is formed on the additional film 1106 formed on the ILD line 1104, and polymer B (or polymer component B) is formed on the additional film 1108 formed on the metal line 1102.

Referring again to FIG. 11B , in one embodiment, once the surface of the underlying structure (e.g., structure 1100 of FIG. 11A ) has been prepared, a 50-50 biblock copolymer, such as polystyrene-polymethyl methacrylate (PS-PMMA), is coated on the substrate and annealed to drive self-polymerization, resulting in the polymer A/polymer B layers of structure 1110 of FIG. 11B . In this embodiment, utilizing appropriate surface energy conditions, the block copolymer segregates based on the underlying material of structure 1100. For example, in one particular embodiment, the polystyrene selectively aligns to the underlying metal line 1102 (or a corresponding metal line capping or hard mask material). Simultaneously, PMMA is selectively aligned to the ILD lines 1104 (or corresponding metal line capping or hard mask material).

Therefore, in one embodiment, the underlying metal and ILD grids are regenerated from block copolymers (BCPs, i.e., Polymer A/Polymer B). This is particularly true if the BCP pitch matches the underlying grating pitch. The polymer grid (Polymer A/Polymer B), in one embodiment, is robust to some small deviation from a perfectly aligned grid. For example, if the small plugs effectively set a material such as oxide (where a perfectly aligned grid would have metal), a perfectly aligned Polymer A/Polymer B grid can still be achieved. However, because the ILD line grating (in one embodiment) is an idealized grating structure with no metal fractures in the ILD backbone, it may be desirable to neutralize the ILD surface since both types of polymer (A and B) will (in this example) be exposed to the ILD material and only one type will be exposed to the metal.

In one embodiment, the thickness of the applied polymer (A/B) is approximately the same as (or slightly thicker than) the final thickness of the ILD layer ultimately formed in its place. In one embodiment, as described in more detail below, the polymer grating is not formed as an etch resist, but rather as a scaffold around which a permanent ILD layer is ultimately grown. As such, the thickness of the polymer (A/B) can be important because it can be used to define the final thickness of the subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown in FIG. 11B is ultimately replaced with an ILD grating of approximately the same thickness.

In one embodiment, as described above, the polymer A/polymer B grid of FIG. 2 is a block copolymer. In one such embodiment, the block copolymer molecule is one such as described above in connection with FIG. 10D . In one embodiment, via a first example (as shown in FIG. 11B ), if the blocks in two block copolymers are approximately the same length, a grid-like pattern of alternating polymer A and polymer B lines is produced. In another embodiment, via a second example (not shown), if one of the blocks in two block copolymers is longer than the other, but not significantly longer, a vertical columnar structure can be formed. In a columnar structure, block copolymer molecules can align with their shorter polymer blocks within the microphase segregated into columns, as well as their longer polymer blocks extending away from and surrounding the columns. For example, if the blocks of polymer A are longer (but not too long) than the blocks of polymer B, a columnar structure can form in which many block copolymer molecules align with the shorter blocks of polymer B, forming a columnar structure surrounded by the phase with the longer blocks of polymer A. When this occurs in an area of sufficient size, a two-dimensional array of columnar structures, typically packed hexagonally, can form.

In one embodiment, the Polymer A/Polymer B grating is first applied as part of an unpolymerized bulk copolymer layer, comprising, for example, a bulk copolymer material applied by a brush or other coating process, as described above in connection with FIG 10D . In this embodiment, an annealing treatment may be applied to the unpolymerized bulk copolymer to initiate, accelerate, improve its quality, or enhance microphase separation and/or autopolymerization, as described above in connection with FIG 10D .

FIG11C illustrates a plan view and corresponding cross-sectional view of the structure of FIG11B following removal of a polymer, according to an embodiment of the present invention. Referring to FIG11C , polymer B is removed to re-expose metal line 1102 (or a hard mask or capping layer formed on metal line 1102), while polymer A remains in ILD line 1104, forming structure 1112. In one embodiment, a deep ultraviolet (DUV) bulk exposure followed by a wet etch or selective dry etch is used to selectively remove polymer B. It should be understood that, instead of first removing the polymer from metal line 1102 (as shown), removal from the ILD line can alternatively be performed first.

FIG11D illustrates a plan view and corresponding cross-sectional view of the structure of FIG11C after formation of a sacrificial material layer over metal line 1102, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (b), structure 1114 includes a sacrificial layer B formed on or above metal line 1102 and between polymer A over or above ILD line 1104. In one embodiment, referring to cross-sectional view (a), the trenches between the polymer A lines are filled by low-temperature deposition, for example, with an oxide (e.g., TiO _x ) or other sacrificial material as a conformal layer 1116. The conformal layer 1116 is then confined to the region above the metal line 1102 by dry etching or a chemical mechanical planarization (CMP) process. The resulting layer is referred to herein as sacrificial B because, in some embodiments, its material is ultimately replaced with a permanent ILD material. However, in other embodiments, it should be understood that the permanent ILD material may be formed at this stage instead. Where a sacrificial material is used, in one embodiment, the sacrificial material possesses the necessary deposition properties, thermal stability, and etch selectivity relative to the other materials used in the process.

FIG11E illustrates a plan view and corresponding cross-sectional view of the structure of FIG11D , following replacement of polymer A with a permanent interlayer dielectric (ILD) material, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (c), structure 1118 includes permanent interlayer dielectric (ILD) lines 1120 above or on ILD lines 1104 and between sacrificial B material lines. In one embodiment, as depicted in cross-sectional view (a), the polymer A lines are removed. Next, referring to cross-sectional view (b), an ILD material layer 1119 is conformally formed over the resulting structure. The conformal layer 1119 is then confined to the area above the ILD lines 1104 by dry etching or chemical mechanical planarization (CMP) processes. In one embodiment, structure 1118 effectively replaces the polymer (A/B) grating of FIG. 11B with a grating of very thick material (e.g., permanent ILD 1120 and sacrificial B) that is symmetrical and aligned with the underlying metal grating. Two different materials can be used to ultimately define the possible locations of plugs and vias, as described in more detail below.

FIG11F illustrates a plan view and corresponding cross-sectional view of the structure of FIG11E following selective hard mask formation on the permanent ILD lines, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (c), structure 1122 includes a hard mask layer 1124 formed on permanent interlayer dielectric (ILD) lines 1120. In one embodiment, referring to cross-sectional view (c), a selective growth process is used to form hard mask layer 1124 confined to the surface of permanent ILD lines 1120. In another embodiment, a conformal material layer 1123 is first formed (cross-sectional view (a)) on a structure having recessed permanent ILD lines 1120. Conformal layer 1123 then undergoes a timed etch and/or CMP process to form hard mask layer 1124 (cross-sectional view (b)). In the latter case, ILD lines 1120 are recessed relative to the sacrificial B material, and a non-conformal (planarized) hard mask 1123 is then deposited over the resulting grating. Material 1123 is thinner on the sacrificial B lines than on the recessed ILD lines 1120, so that the timed etch or polishing operation of the hard mask selectively removes material 1123 from the sacrificial B material.

FIG11G illustrates a plan view and corresponding cross-sectional view of the structure of FIG11F after the sacrificial B lines have been removed and replaced with permanent ILD lines 1128, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (c), structure 1126 includes permanent ILD lines 1128 replacing the sacrificial B lines of FIG11F , i.e., above and aligned with metal lines 1102. In one embodiment, the sacrificial B material is removed (cross-sectional view (a)) and replaced with permanent ILD lines 1128 (cross-sectional view (c)), for example, by deposition of a conformal layer and subsequent timed etch or CMP processing (cross-sectional view (b)). In one embodiment, the resulting structure 1126 comprises uniform ILD material (permanent ILD lines 1120 + permanent ILD lines 1128), wherein all potential plug locations are covered with hard mask 1124 and all potential vias are located in the areas of the exposed permanent ILD lines 1128. In this embodiment, permanent ILD lines 1120 and 1128 are composed of the same material. In another embodiment, permanent ILD lines 1120 and permanent ILD lines 1128 are composed of different ILD materials. In either case, in a particular embodiment, a difference, such as a seam between the materials of permanent ILD lines 1120 and 1128, can be observed in the final structure 1126. An example seam 1199 is shown in FIG. 11F for illustration.

FIG11H illustrates a plan view and corresponding cross-sectional views of the structure of FIG11G following trench formation (e.g., grating definition), according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', b-b', c-c', and d-d', respectively, a grating is defined within structure 1130 by forming trench 1132 in the structure of FIG11G (perpendicular to the grating of FIG11G ), ultimately defining a region between the patterned metal lines. In one embodiment, trench 1132 is formed by patterning and etching the grating pattern into a sacrificial grating of an earlier structure. In one embodiment, a grid is formed that effectively defines all spaces between the ultimately formed metal lines, along with the locations of all plugs and vias. In one embodiment, trenches 1132 reveal the locations of the underlying ILD lines 1104 and metal lines 1102.

FIG11I illustrates a plan view and corresponding cross-sectional views of the structure of FIG11H following formation of a sacrificial material grating in the trench of FIG11H , according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a′, b-b′, c-c′, and d-d′, respectively, a material layer 1134 (which is an interlayer dielectric layer or sacrificial layer) is formed in trench 1132 of the structure of FIG11H . In one embodiment, material layer 1134 is formed by conformal deposition of either a permanent ILD material or a sacrificial layer, followed by a timed etch or CMP (which can later be removed, for example, if air gaps are to be created). In the former case, material layer 1134 ultimately becomes the ILD material, lying between parallel metal lines subsequently formed on the same metal layer. In the latter case, the material can be referred to as a sacrificial C material, as shown. In one embodiment, material layer 1134 exhibits high etch selectivity with respect to other ILD materials and to hard mask layer 1128.

FIG11J illustrates a plan view and corresponding cross-sectional views of the structure of FIG11I following formation and patterning of the mask and subsequent etching of the via locations, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b), taken along axes a-a' and b-b', respectively, a mask 1136 is formed on the structure of FIG11I. The mask is patterned, for example, by a lithographic process, to have openings 1137 formed therein. In one embodiment, the openings are determined according to the desired via patterning. That is, at this stage, all possible vias and plugs (e.g., as placeholders) have been patterned and self-aligned to the final metal layers above and below. Here, a subset of via and plug locations are selected to be retained, such as locations where metal lines are to be etched. In one embodiment, ArF, EUV, or electron beam etchant is used to cut or select the vias to be etched, i.e., at the locations of the exposed portions of metal lines 1102. It should be understood that hard mask 1124 and material layer 1134 serve as the actual etch masks that determine the shape and location of the vias. Mask 1136 simply blocks the remaining vias from being etched. In this way, the tolerance for the size of the opening 1137 is relaxed because the surrounding materials (e.g., hard mask 1124 and material layer 1134) of the selected via location (i.e., the portion of the opening 1137 directly above the exposed portion of the metal line 1102) are resistant to the etching process used to remove the ILD line 1128 above the selected portion of the metal line 1102 for final via fabrication. In one embodiment, the mask 1136 is composed of a topographical shielding portion 1136C, an anti-reflective coating (ARC) layer 1136B, and a photoresist layer 1136A. In a particular such embodiment, the topographical shielding portion 136C is a carbon hard mask (CHM) layer and the anti-reflective coating 136B is a silicon ARC layer.

FIG11K illustrates a plan view and corresponding cross-sectional views of the structure of FIG11J following mask and hard mask removal and subsequent plug patterning and etching, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b), taken along axes a-a' and b-b', respectively, the mask 1136 shown in FIG11J is removed after patterning the via locations. Thereafter, a second mask 1138 is formed and patterned to cover the selected plug locations. Specifically, in one embodiment, and as depicted in FIG11K , portions of the hard mask 1124 are retained in the locations where the plugs will ultimately be formed. That is, at this stage, all possible plugs exist in the form of hard mask plugs. 11K is operative to remove all portions of hard mask 1124 except those selected to remain for the plugs. The patterning effectively exposes substantially portions of ILD lines 1120 and 1128, e.g., as a unified dielectric layer.

FIG11L illustrates a plan view and corresponding cross-sectional view of the structure of FIG11K following mask removal and metal line trench etching, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (a) and (b), taken along axes a-a' and b-b', respectively, mask 1138 shown in FIG11K is removed after patterning the via locations. Thereafter, a partial etch of the exposed portions of ILD lines 1120 and 1128 is performed to provide recessed ILD lines 1120' and 1128'. The extent of the recess can be determined based on the timing of the etching process, such as the depth of the desired metal line thickness. The portion of ILD line 1120 protected by the portion of hard mask 1124 that remains is not recessed by etching, as shown in FIG11L . Furthermore, material layer 1134 (which may be a sacrificial material or a permanent ILD material) is not etched or recessed. It should be understood that the process shown in FIG11L does not require lithography because the via locations (on the exposed portions of metal line 1102) have already been etched, as well as the plugs (at the locations where hard mask 1124 remains).

FIG11M illustrates a plan view and corresponding cross-sectional views of the structure of FIG11L following metal line deposition and polishing, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b), taken along axes a-a' and b-b', respectively, metal for forming metal interconnects is conformally formed over the structure of FIG11L. The metal is then planarized (e.g., by CMP) to provide metal lines 1140. The metal lines are coupled to underlying metal lines via predetermined via locations and isolated by retained plugs 1142 and 1144. The metal (e.g., copper and associated barrier and seed layers) deposition and planarization processes can be standard BEOL dual damascene processes. It should be understood that in subsequent manufacturing operations, the material layer lines 1134 can be removed to provide air gaps between the resulting metal lines 1140.

The structure of Figure 11M can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 11M can represent the last metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations can be performed in an alternative order, not every operation needs to be performed and/or additional process operations can be performed. Furthermore, although the above-described process flow focuses on the application of directed self-polymerization (DSA), selective growth processes can also be used alternatively at one or more locations in the process flow. In any case, the resulting structure enables it to be focused directly on the fabrication of vias on the underlying metal lines. That is, the vias can have a wider, narrower, or the same thickness as the underlying metal lines, for example, due to a non-perfectly selective etching process. However, in one embodiment, the center of the via is directly aligned (matched) with the center of the metal line. As such, in one embodiment, deviations due to conventional lithography/damascene patterning (which would otherwise need to be accommodated) are not a factor in the resulting structure described herein.

According to one embodiment of the present invention, a self-aligned DSA triblock bottom-up approach is described. One or more embodiments described herein relate to triblock copolymers for self-aligning vias or contacts. By using more advanced block copolymers and directed self-polymerization strategies, alignment to underlying dense metal layers can be achieved. The embodiments described herein can be implemented to improve cost, scalability, pattern placement error, and variability.

Generally, one or more embodiments described herein relate to the use of three phases of a triblock copolymer material to achieve phase separation as a "self-aligned photobucket." For example, the use of a self-aligned triblock copolymer to produce an aligned photobucket is described. Additional embodiments for the fabrication and use of photobuckets are described in more detail below, in embodiments beyond the present embodiment of Figures 12A-12K. However, it should also be understood that the embodiments are not limited to the concept of photobuckets, but have broad application to structures having preformed features fabricated using bottom-up and/or directed self-polymerization (DSA) methods.

12A-12C illustrate oblique-angle cross-sectional views representing various operations in a method for forming self-aligned vias or contacts for back-end-of-line (BEOL) interconnects using a triblock copolymer, according to an embodiment of the present invention.

Referring to FIG. 12A , a semiconductor structure layer 1200 has a grating pattern of alternating metal lines 1202 and interlayer dielectric (ILD) lines 1204. Structure 1200 can be treated to perform a first molecular brush operation (i) with a first molecular species 1206. Structure 1200 can also be treated to perform a second molecular brush operation (ii) with a second molecular species 1208. It should be understood that the order of operations (i) and (ii) can be reversed, or even performed at substantially the same time.

12B , a molecular brush operation can be performed to modify or provide a derivatized surface to alternating metal lines 1202 and ILD lines 1204. For example, the surface of the metal line 1202 can be treated to have an A/B surface 1210 on the metal line 1202. The surface of the ILD line 1204 can be treated to have a C surface 1212 on the ILD line 1204.

12C , the structure of FIG 12B can be processed using a processing operation (iii) involving the application of a triblock copolymer (triblock BCP) 1214, and possibly a subsequent separation process, to form a separation structure 1220. Separation structure 1220 includes a first region 1222 of a separation triblock BCP over ILD line 1204. Alternating second and third regions 1224 and 1226 of the separation triblock BCP are located over metal line 1202. The final configuration of the three blocks of triblock copolymer 1214 is based on chemoepitaxial growth, as only a bottom pattern (rather than a coplanar pattern, as used in epitaxy) is used to direct the polymerization of triblock copolymer 1214 to form separation structure 1220.

12A-12C , in one embodiment, a structure 1220 for directed self-polymerization of a back-end-of-the-line (BEOL) semiconductor structure metallization layer includes a substrate (not shown, but described below and understood to be below the ILD lines 1204 and metal lines 1202). The lower metallization layer includes alternating metal lines 1202 and dielectric lines 1204 disposed above the substrate. A triblock copolymer layer 1214 is disposed above the lower metallization layer. The triblock copolymer layer includes a first separated block component 1222 disposed above the dielectric lines 1204 of the lower metallization layer. The tri-block copolymer layer includes alternating second 1224 and third 1226 separate block components disposed over dielectric lines 1202 of the underlying metallization layer.

In one embodiment, the third separated block 1226 component of the triblock copolymer layer 1214 is photosensitive. In one embodiment, the triblock copolymer layer 1214 is formed to a thickness in the range of approximately 5-100 nanometers. In one embodiment, the triblock copolymer layer 1214 includes a triblock copolymer type selected from the group consisting of any three of: polystyrene and other polyvinylaromatics, polyisoprene and other polyolefins, polymethacrylates and other polyesters, polydimethylsiloxane (PDMS) and related silane-based polymers, polyferrocenesilanes, polyethylene oxide (PEO) and related polyethers, and polyvinylpyridine. In one embodiment, the alternating second 1224 and third 1226 separated block components have a ratio of approximately 1:1, as depicted in FIG21C (and as described below in connection with FIG12H ). In another embodiment, the alternating second 1224 and third 1226 separated block components have a ratio of X:1, with the second separated block component 1224 relative to the third separated block component 1226, where X is greater than 1, and where the third separated block component 1226 has a columnar structure surrounded by the second separated block component, as described below in connection with FIG12I . In another embodiment, the triblock copolymer layer 1214 is a mixture of homopolymers of A, B, and/or C or a biblock BCP of A-B, B-C, or A-C components to achieve the desired morphology.

In one embodiment, structure 1220 further includes a first molecular brush layer 1212 disposed on dielectric lines 1204 of the underlying metallization layer. In this embodiment, first isolated block components 1222 are disposed on the first molecular brush layer. In one embodiment, structure 1220 also includes a second (different) molecular brush layer 1210 disposed on metal lines 102 of the underlying metallization layer. Alternating second 1224 and third 1226 isolated block components are disposed on the second molecular brush layer 1210. In one embodiment, the first molecular brush layer 1212 includes molecular species 1208, which includes polystyrene having a head group selected from the group consisting _of -SH, _-PO3H2 , _-CO2H , -NRH, -NRR', and -Si(OR) ₃ ; and the second molecular brush layer 1210 includes molecular species 1206, which includes polymethyl methacrylate having a head group selected from the group consisting of _-SH , _-PO3H2 , _-CO2H , -NRH, -NRR', and -Si(OR) ₃ .

In one embodiment, the alternating metal lines 1202 and dielectric lines 1204 of the lower metallization layer have a grating pattern with a constant pitch. In one embodiment, the third separated block component 1226 of the tri-block copolymer layer 1214 defines all possible via locations in the metallization layer above the lower metallization layer. In one embodiment, the third separated block component 1226 of the tri-block copolymer layer 1214 is photosensitive to an extreme ultraviolet (EUV) source or an electron beam source.

12D illustrates an oblique angled cross-sectional view representing operations in a method for forming self-aligned vias or contacts for back-end of line (BEOL) interconnects using a triblock copolymer, in accordance with an embodiment of the present invention.

Referring to FIG12D , all portions of the third isolated block component 1226 of the structure 1220 of FIG12C are removed. In one such embodiment, the removal of all portions of the third isolated block component 1226 opens up all possible via locations that can be formed on the underlying metallization layer. These openings can be filled with a photoresist layer to ultimately allow selection of only those via locations required for a particular design. It should be understood that in the case of FIG12D, the third isolated block component 1226 of the structure 1220 can be (but need not be) light-sensitive because the third isolated block component 1226 of the structure 1220 of FIG12C can be performed solely by selective etching (e.g., selective to the first isolated block component 1222 and selective to the second isolated block component 1224). In such an embodiment, the selective etching can be performed using selective dry etching or selective wet etching (or both).

12E illustrates an oblique angled cross-sectional view showing operations in another method of forming self-aligned vias or contacts for back-end of line (BEOL) interconnects using a triblock copolymer, according to another embodiment of the present invention.

12E , only a selected portion of the third isolated block component 1226 of the structure 1220 of FIG. 12C is removed. In one such embodiment, the removal of only the selected portion of the third isolated block component 1226 opens only those via locations above the underlying metallization layer that are required for a particular design. It should be understood that in the case of FIG. 2E , the third isolated block component 1226 of the structure 1220 is light sensitive, and the location selection is performed using a localized, but highly resistant lithographic exposure. The exposure can be described as resistant because the adjacent materials 1222 and 1224 adjacent locations 1226 (in one embodiment) are not light sensitive to the lithography used to partially select the locations for removal of component 1226.

FIG. 12F illustrates a triblock copolymer for forming self-aligned vias or contacts for back-end-of-line (BEOL) interconnects, according to an embodiment of the present invention.

Referring to FIG. 12F , a three-block BCP 1250 can be partitioned along axis 1252 into portions 1222 , 1224 , and 1226 . It should be understood that other partitioning configurations are possible, such as asymmetric configurations. In one embodiment, there is an etch selectivity between components 1222 , 1224 , and 1226 , which can be as great as 10:1 for one component relative to the other two. In one embodiment, the use of a three-block BCP 1250 can improve pattern fidelity and reduce critical dimension (CD) variation. In one embodiment, the split three-block BCP 1250 can be implemented to enable a self-alignment strategy that complements 193 nm immersion lithography (193i) or extreme ultraviolet lithography (EUVL) processes.

It should be understood that, in general, the blocks of a triblock copolymer can each have different chemical properties. For example, one of the blocks can be relatively hydrophobic (e.g., repelling water) while the other two blocks can be relatively hydrophilic (attracting water), or vice versa. At least conceptually, one of the blocks can be relatively oil-like while the other two blocks can be relatively water-like, or vice versa. Such differences in chemical properties between different block polymers (whether hydrophilic-hydrophobic or otherwise) can cause the block copolymer molecules to self-polymerize. For example, self-polymerization can be based on microphase separation of the polymer blocks. Conceptually, this can be analogous to the phase separation of oil and water, which are normally immiscible.

Similarly, differences in hydrophilicity between polymer blocks can result in a somewhat similar microphase separation, in which different polymer blocks attempt to "separate" from each other because they chemically dislike each other. However, in one embodiment, because the polymer blocks are covalently bonded to each other, they cannot completely separate on a macroscopic scale. Instead, polymer blocks of a given type may tend to separate or aggregate with polymer blocks of other molecules of the same type in extremely small (e.g., nanometer-sized) regions or phases. The specific size and shape of the regions or microphases typically depends at least in part on the relative lengths of the polymer blocks. In one embodiment, for example, Figures 12C, 12H, and 12I depict possible polymerization schemes for a triblock copolymer.

It will be appreciated that the patterns used to open the pre-formed vias or plug locations can be formed to be quite small, enabling an increase in the overlap tolerance of the lithography process. Pattern features can be made of uniform size, which can reduce the scanning time of direct electron beam writing and/or the complexity of optical proximity correction (OPC) using optical lithography. Pattern features can also be formed to be shallow, which can improve patterning resolution. The subsequent etching process can be an isotropic chemical selective etching. This etching process reduces other related profiles and critical dimensions, and reduces the anisotropy problems typically associated with dry etching methods. This etching process is also relatively much cheaper (from an equipment and throughput perspective) compared to other selective removal methods.

The following describes portions of an integrated circuit layer illustrating various operations in a method for self-aligned vias and metal patterning. In particular, Figures 12G and 12H illustrate plan views and corresponding cross-sectional views of various operations in a method for forming self-aligned vias or contacts for back-end-of-the-line (BEOL) interconnects using a triblock copolymer, according to an embodiment of the present invention.

FIG12G illustrates a plan view and corresponding cross-sectional view taken along the a-a' axis for a selected front metallization structure, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view selection (a), a starting structure 1260 includes a pattern of metal lines 1262 and interlayer dielectric lines (ILD) 1264. Starting structure 1260 can be patterned into a grating pattern, with metal lines spaced at a constant pitch and having a constant width, as depicted in FIG12G , when a self-polymerizing material is ultimately formed. In the cross-sectional view (a), metal lines 1262 and inter-layer dielectric (ILD) lines 1264 are coplanar with each other. Some lines may be associated with underlying vias, such as line 1262' shown in one example in the cross-sectional view.

Referring again to FIG. 12G , alternative options (b)-(f) discuss situations in which an additional film is formed (e.g., deposited, grown, or left as an artifact from a previous patterning process) on the surface of one (or both) of metal line 1262 and interlayer dielectric line 1264. In example (b), additional film 1266 is disposed on interlayer dielectric line 1264. In example (c), additional film 1268 is disposed on metal line 1262. In example (d), additional film 1266 is disposed on interlayer dielectric line 1264, while additional film 1268 is disposed on metal line 1262. Furthermore, although the metal line 1262 and the interlayer dielectric line 1264 are depicted as coplanar in (a), in other embodiments, they may be non-coplanar. For example, in (e), the metal line 1262 protrudes above the interlayer dielectric line 1264. In example (f), the metal line 1262 is recessed below the interlayer dielectric line 1264.

Referring again to examples (b)-(d), additional layers (e.g., layers 1266 or 1268) can be used as hard masks (HMs) or protective layers or to enable autopolymerization as described below in connection with subsequent processing operations. Such additional layers can also be used to protect the ILD from further processing. In addition, selectively depositing another material over the metal lines may be advantageous for similar reasons. Referring again to examples (e) and (f), the ILD lines or metal lines can also be recessed using any combination of protective/HM materials on either or both surfaces. In summary, at this stage, there are several options for preparing the final lower surface for the directed autopolymerization process.

12H , a triblock copolymer layer 1270 is formed on the structure of FIG 12G (e.g., a plan view of the cross-sectional structure (a)). The triblock copolymer layer 1270 is separated to have a region 1272 formed over the ILD line 1264 and alternating second regions 1274 and third regions 1276 formed over the metal line 1262.

Referring to the cross-sectional view taken along axis b-b' of FIG. 12H , third region 1276 is shown above metal line 1262, while first region 1272 is shown above ILD line 1264. Also shown, according to one embodiment, is layer 1280 between first region 1272 and ILD line 1264, which may be a remnant of a molecular brush layer. However, it should be understood that layer 1280 may not be present. According to one embodiment, third region 1276 is shown as being formed directly on metal line 1262. However, it should be understood that remnants of a molecular brush layer may be between third region 1276 and metal line 1262.

Referring to the cross-sectional view taken along the c-c' axis of FIG. 12H , second region 1274 is shown above metal line 1262, while first region 1272 is shown above ILD line 1264. Also shown, according to one embodiment, is layer 1280 between first region 1272 and ILD line 1264, which may be a remnant of a molecular brush layer. However, it should be understood that layer 1280 may not be present. Also shown, according to one embodiment, is layer 1282 between second region 1274 and metal line 1262, which may be a remnant of a molecular brush layer. However, it should be understood that layer 1282 may not be present. It should also be understood that region 1276 may be formed to be photosensitive or may be replaced with a photosensitive material.

Therefore, in one embodiment, the underlying metal and ILD grids are regenerated in a block copolymer (BCP). This is particularly true if the BCP pitch matches the underlying grating pitch. The polymer grid, in one embodiment, is robust to some small deviations from a perfectly aligned grid. For example, if the small plugs effectively set a material such as oxide (where a perfectly aligned grid would have metal), a substantially perfectly aligned block copolymer grid can still be achieved.

In one embodiment, referring again to FIG. 12H , the applied triblock copolymer layer 1270 is approximately the same thickness as (or slightly thicker than) the final thickness of the ILD that will eventually be formed in its place. In one embodiment, as described in more detail below, the polymer grating is not formed as an etch resist, but rather as a scaffold around which a permanent ILD layer will eventually be grown. As such, the thickness of the triblock copolymer layer 1270 can be important because it can be used to define the final thickness of the subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown in FIG. 12H is ultimately replaced with an ILD/metal line grating of approximately the same thickness.

In one embodiment, triblock copolymer layer 1270 molecules are polymer molecules formed from chains of covalently bonded monomers. In a triblock copolymer, there are three different types of monomers, and these different types of monomers are primarily included in two different blocks or adjacent sequences of monomers. In one embodiment, triblock copolymer layer 1270 is first applied as an unpolymerized block copolymer layer portion, which includes (for example) block copolymer material applied by a brush or other coating process. The unpolymerized state refers to the state in which (at the time of deposition) the block copolymer has not yet substantially phase separated and/or self-polymerized to form nanostructures. In this unpolymerized form, the block polymer molecules are quite random, with the different polymer blocks being relatively randomly oriented and arranged, in contrast to the polymerized triblock copolymer layer 1270 discussed in conjunction with the resulting structure of FIG12H. The unpolymerized block copolymer layer portion can be applied in a variety of different ways. For example, the block copolymer can be dissolved in a solvent and then spin-coated onto the surface. Alternatively, the unpolymerized block copolymer can be sprayed, dip-coated, dip-coated, or otherwise applied or coated onto the surface. Other methods of applying block copolymers, as well as other methods known in the art for applying similar organic coatings, can potentially be used. The unpolymerized layer can then form a polymerized block copolymer layer portion, for example, by microphase separation and/or self-polymerization of the unpolymerized block copolymer layer portion. Microphase separation and/or self-polymerization occurs through rearrangement and/or reorientation of the block copolymer molecules, and in particular, rearrangement and/or reorientation of the different polymer blocks of the block copolymer molecules to form a triblock copolymer layer 1270.

In this embodiment, an annealing treatment may be applied to the unpolymerized block copolymer to initiate, accelerate, increase, or enhance the quality of microphase separation and/or self-polymerization to form the triblock copolymer layer 1270. In certain embodiments, the annealing treatment may include a treatment operable to increase the temperature of the block copolymer. An example of such a treatment is baking the layer, heating the layer in an oven or over a heat lamp, applying infrared radiation to the layer, or applying heat to the layer or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate microphase separation and/or self-polymerization of the block polymer without damaging the block copolymer or any other important materials or structures of the integrated circuit substrate. Typically, the heating range may be from about 50°C to about 300°C, or from 75°C to about 250°C, but not exceeding the thermal degradation limits of the block copolymer or integrated circuit substrate. Heating or annealing can help provide energy to the block copolymer molecules, making them more mobile/elastic to increase the rate of microphase separation and/or improve the quality of microphase separation. This microphase separation or rearrangement/reorientation of the block copolymer molecules can lead to self-polymerization to form extremely small (e.g., nanoscale) structures. Self-polymerization can occur under the influence of forces such as surface tension, molecular likes and dislikes, and other surface-related and chemical-related forces.

In any case, in certain embodiments, self-polymerization of block copolymers (whether based on hydrophobic-hydrophilic differentiation) can be used to form extremely small periodic structures (e.g., precisely spaced nanoscale structures or wires) in the form of triblock copolymer layer 12720. In certain embodiments, this can be used to form nanoscale wires or other nanoscale structures that can ultimately be used to form via openings. In certain embodiments, directed self-polymerization of block copolymers can be used to form self-aligned vias and interconnects, as described in more detail below.

It should be understood that the two components of the triblock copolymer structure formed over the metal line need not have a 1:1 ratio (a 1:1 ratio is shown in Figures 12C and 12H). For example, the third discrete block component may be present in a smaller amount than the second component and may have a pillar-like structure surrounded by the second discrete block component. Figures 12I-12L illustrate plan views and corresponding cross-sectional views of various operations in a method for forming self-aligned vias or contacts for back-end-of-the-line (BEOL) interconnects using a triblock copolymer, according to an embodiment of the present invention.

12I , the plan view and the corresponding cross-sectional view taken along the d-d′ axis show that the third component 1276 is smaller than the second component 1274. The third separated block component 1276 has a columnar structure surrounded by the second separated block component 1274.

12J , a plan view shows that lithography 1290 of some 1292 of the third separated block components 1276 is selectively performed to ultimately provide via locations for the upper metallization structure.

It should be understood that FIG12I effectively illustrates an unexposed photosensitive DSA structure, while FIG12J illustrates an exposed photosensitive DSA structure. In contrast to FIG12H, FIG12I and FIG12J show examples of columnar structures that can be formed when many block copolymer molecules align with shorter blocks of one polymer forming a columnar structure, which is surrounded by phases having longer blocks of another polymer. According to embodiments of the present invention, the photoactivatable nature of the DSA structure provides the ability to effectively "insert" or "cut" a type of DSA polymer region using, for example, electron beam or EUV exposure.

12K , a plan view shows an exposed/chemically enlarged region 1294 within the exposed zone. The only modification effective with respect to selectivity is the material of the exposed portion of the third isolated block component 1276. It should be understood that although shown as cleared in FIG. 12K , the selected region may not have been cleared.

12L , a plan view and a corresponding cross-sectional view taken along the e-e′ axis are shown following lithographic development to provide cleared regions 1294. Cleared regions 1294 may ultimately be used for via formation.

The resulting patterned DSA structure of FIG. 12L (or FIG. 12C , 12D , 12E , or 12H ) described above may ultimately be used as a scaffold from which the permanent layer is ultimately formed. That is, it is possible that no DSA material is present in the final structure, but is used to guide the fabrication of the final interconnect structure. In one such embodiment, the permanent ILD replaces one or more regions of DSA material, and subsequent processing (such as metal wire fabrication) is completed. That is, it is possible that all DSA components are ultimately removed to allow for the final self-aligned via and plug formation. In other embodiments, at least some DSA material may remain in the final structure.

Referring again to Figures 12A-12C, 12G, 12H, and 12I-12L, in one embodiment, a method for fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer having alternating metal lines and dielectric lines on a substrate. A triblock copolymer layer is formed on the lower metallization layer. The triblock copolymer layer is separated to form a first separated block assembly above the dielectric lines of the lower metallization layer, and to form alternating second and third separated block assemblies disposed above the metal lines of the lower metallization layer. The third separated block assembly is photosensitive. The method also includes irradiating and developing selected locations of the third separated block assembly to provide via openings above the metal lines of the lower metallization layer.

In one embodiment, the alternating second and third isolated block assemblies have a ratio of approximately 1:1, as described in connection with Figures 12C and 12H. In another embodiment, the alternating second and third isolated block assemblies have a ratio of approximately X:1, with the second isolated block assembly relative to the third isolated block assembly, where X is greater than 1. In this embodiment, the third isolated block assembly has a columnar structure surrounded by the second isolated block assembly, as described in connection with Figure 12I.

In one embodiment, the method further includes: after irradiating and developing selected locations of the third separated block components to provide via openings, using the resulting patterned triblock copolymer layer as a scaffold to form a second order of alternating metal and dielectric lines above, coupled with, and orthogonal to the first order of alternating metal and dielectric lines. In one embodiment, one or more components of the triblock copolymer layer are retained in the final structure. However, in other embodiments, all components of the triblock copolymer layer are ultimately sacrificial, as none of the material is retained in the final product. Example embodiments of the latter embodiment are described below in conjunction with FIG. 13 .

In one embodiment, the method further includes forming a first molecular brush layer on the dielectric lines of the underlying metallization layer (before forming the triblock copolymer layer), and forming a second (different) molecular brush layer on the metal lines of the underlying metallization layer, example embodiments of which are described above in conjunction with Figures 12A-12C. In one embodiment, irradiating and developing selected locations of the third isolated block component includes exposing the selected locations of the third isolated block component to an extreme ultraviolet (EUV) source or an electron beam source.

Providing only an example of the final structure that can ultimately be obtained, FIG13 illustrates a plan view and corresponding cross-sectional views of a self-aligned via structure, subsequent to metal line, via, and plug formation, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b), taken along axes f-f' and g-g', respectively, an upper-level metal line 1302 is provided with a dielectric frame (e.g., on a dielectric layer 1304 and adjacent to a dielectric line 1314). Metal line 1302 is coupled to underlying metal line 1262 (an example of which 1306 is shown in cross-sectional view (a)) through predetermined via locations and is isolated by plugs (examples of which include plugs 1308 and 1310). Underlying lines 1262 and 1264 may be described above in connection with FIG. 12G , such as being formed orthogonally to metal line 1302. It should be understood that dielectric line 1314 may be removed in subsequent fabrication operations to provide air gaps between the resulting metal lines 1302.

The resulting structure (such as that described in connection with FIG. 13 ) can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 13 may represent the final metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in an alternative order, that not every operation needs to be performed, and/or that additional process operations may be performed. In any case, the resulting structure enables the fabrication of a via that is directly focused on the underlying metal line. That is, the via may be wider, narrower, or the same thickness as the underlying metal line, for example, due to an imperfectly selective etch process. However, in one embodiment, the center of the via is directly aligned (matched) with the center of the metal line. Thus, in one embodiment, variations due to conventional lithography/damascene patterning (which must be accommodated) are not a factor in the resulting structure described herein. It should be understood that the above examples have focused on via/contact formation. However, in other embodiments, similar approaches can be used to retain or form areas for line terminations (plugs) within metal line layers.

It will be understood that the processes described herein may be described as being primarily DSA based (such as several of the process schemes described above), while others may be primarily etch based. In accordance with embodiments of the present invention, a deep subtractive approach is implemented for BEOL processing. One or more of the embodiments described herein relate to subtractive approaches for self-aligned via and plug patterning, and the resulting structures. In one embodiment, the procedures described herein enable the implementation of self-aligned metallization for back-end feature fabrication. Overlap issues anticipated for next generation via and plug patterning may be addressed by one or more of the approaches described herein. Typically, one or more of the embodiments described herein involve the use of a subtractive method to pre-form each via and plug using etched trenches. An additional operation is then used to select which vias and plugs to retain.

14A-14N illustrate portions of an integrated circuit layer representing various operations in a method for subtractive self-aligned via and plug patterning, according to an embodiment of the present invention. In each figure depicting each operation, an oblique angled three-dimensional cross-sectional view is provided.

FIG14A illustrates a starting point structure 1400 for a subtractive via and plug formation process following deep metal line fabrication, according to an embodiment of the present invention. Referring to FIG14A , structure 1400 includes a metal line 1402 with an intermediate interlayer dielectric (ILD) line 1404. The ILD line 1404 includes a plug capping layer 1406. In one embodiment, as described in more detail below in conjunction with FIG14E , the plug capping layer 1406 is later patterned to ultimately define all possible locations for subsequent plug formation.

In one embodiment, the grating structure formed by the metal lines 1402 is a close-pitch grating structure. In this embodiment, the close pitch cannot be directly obtained by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Even the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Therefore, the grating pattern of Figure 14A can have metal lines separated by a constant pitch and having a constant width. The pattern can be manufactured by halving the pitch or reducing the pitch to one-quarter. It should also be understood that some of the lines 1402 can be associated with underlying vias for coupling to a previous interconnect layer.

In one embodiment, metal line 1402 is formed by patterning a trench into an ILD material (e.g., the ILD material of line 1404) with a plug capping layer 1406 formed thereon. The trench is then filled with metal and, if necessary, planarized to the plug capping layer 1406. In one embodiment, the metal trench and fill process involves high aspect ratio features. For example, in one embodiment, the aspect ratio of metal line height (h) to metal line width (w) is approximately in the range of 5-10.

FIG14B illustrates the structure of FIG14A following recessing of the metal lines, according to an embodiment of the present invention. Referring to FIG14B , metal line 1402 is selectively recessed to provide first-level metal line 1408. The recessing is performed selectively to ILD line 1404 and plug cap layer 1406. The recessing can be performed by etching using dry etching, wet etching, or a combination thereof. The degree of recessing can be determined by the target thickness (th) of first-level metal line 1408 for use as a suitable conductive interconnect within a back-end-of-line (BEOL) interconnect structure.

FIG14C illustrates the structure of FIG14B following hard mask filling in the recessed region of the recessed metal line, according to an embodiment of the present invention. Referring to FIG14C , a hard mask layer 1410 is formed in the region formed during the recessing to form the first-level metal line 1408. Hard mask layer 1410 can be formed to the level of plug cap layer 1406 by material deposition and chemical mechanical planarization (CMP) processes, or by a controlled bottom-up growth process. In one specific embodiment, hard mask layer 1410 is composed of a carbon-rich material.

FIG14D illustrates the structure of FIG14C subsequent to deposition and patterning of a hard mask layer, according to an embodiment of the present invention. Referring to FIG14D , a second hard mask layer 1412 is formed on or above the hard mask layer 1410 and the plug cap layer 1406. In this embodiment, the second hard mask layer 1412 is formed with a grating pattern that is orthogonal to the grating pattern of the first-order metal lines 1408/ILD lines 1404, as shown in FIG14D . In a specific embodiment, the second hard mask layer 1412 is composed of a silicon-based anti-reflective coating material. In one embodiment, the grating structure formed by the second metal lines 1412 is a fine-pitch grating structure. In this embodiment, a tight pitch cannot be achieved directly through conventional lithography. For example, a pattern based on conventional lithography can be formed first, but the pitch can be halved by patterning using spacer masks, as is known in the art. Furthermore, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern of the second hard mask layer 1412 of FIG. 14D can have hard mask lines separated by a constant pitch and having a constant width.

FIG14E illustrates the structure of FIG14D after trenches defined by the pattern of the hard mask of FIG14D are formed, according to an embodiment of the present invention. Referring to FIG14E , exposed areas of the hard mask layer 1410 and the plug cap layer 1406 (i.e., those not protected by 1412) are etched to form trenches 1414. The etch stops on (and thus exposes) the top surfaces of the first-level metal lines 1408 and the ILD lines 1404.

FIG14F illustrates the structure of FIG14E following ILD formation in the trenches of FIG14E and removal of the second hard mask, according to an embodiment of the present invention. Referring to FIG14F , second ILD lines 1416 are formed in trenches 1414 of FIG14E . In one embodiment, a flowable ILD material is used to fill trenches 1414. In one embodiment, trenches 1414 are filled and the fill material is then planarized. Planarization can further be used to remove second hard mask layer 1412, exposing hard mask layer 1410 and plug capping layer 1406, as shown in FIG14F .

Referring again to FIG. 14F , in one embodiment, the resulting structure comprises a uniform ILD structure (ILD line 1404 + ILD line 1416). All possible plug locations are occupied by the remaining portion of plug cap layer 1406, while all possible via locations are occupied by the remaining portion of hard mask layer 1410. In this embodiment, ILD line 1404 and ILD line 1416 are composed of the same material. In another such embodiment, ILD line 1404 and ILD line 1416 are composed of different ILD materials. In either case, in a particular embodiment, differences such as seams between the materials of ILD line 1404 and ILD line 1416 can be observed in the final structure. Furthermore, in one embodiment, there is no distinct etch stop layer where the ILD line 1404 and the ILD line 1416 meet, unlike conventional single or double damascene patterning.

FIG14G illustrates the structure of FIG14F after the remaining portions of the hard mask layer covering all possible via locations have been removed, according to an embodiment of the present invention. Referring to FIG14G , the remaining portions of the hard mask layer 1410 are selectively removed to form openings 1418 for all possible via locations. In this embodiment, the hard mask layer 1410 is composed essentially of carbon and is selectively removed using an ash process.

Typically, one or more of the embodiments described herein involve using a subtractive method to pre-form each via and plug using an etched trench. An additional operation is then used to select which vias and plugs to retain. These operations may be illustrated using a "photobucket," although a more traditional resist exposure and ILD backfill approach may also be used to perform the selection process. It should also be understood that the embodiments are not limited to the concept of a photobucket, but have broad application to structures having pre-formed features fabricated using bottom-up and/or directed self-polymerization (DSA) approaches. Additional embodiments for the fabrication and use of photobuckets are described in more detail below, in embodiments beyond the present embodiments of Figures 14A-14N and 15A-15D.

Figure 14H illustrates the structure of Figure 14G following the formation of photobuckets in all possible via locations, according to an embodiment of the present invention. Referring to Figure 14H, photobuckets 1420 are formed in all possible via locations above the exposed portion of the first-level metal line 1408. In one embodiment, the opening 1418 of Figure 14G is filled with an ultra-fast photoresist or an electron beam resist or other photosensitive material. In this embodiment, thermal backfill of the polymer into the opening 1418 is used following the spin-on application. In one embodiment, the fast photoresist is manufactured by removing the inhibitor from the existing photoresist material. In another embodiment, the photobucket 1420 is formed by an etch-back process and/or a lithography/reduction/etching process. It should be understood that the photobucket does not need to be filled with actual photoresist, as long as the material acts as a photosensitive switch.

Figure 14I illustrates the structure of Figure 14H following selection of a via location, according to an embodiment of the present invention. Referring to Figure 14I, the photobucket 1420 from Figure 14H is removed when a via location is selected. In locations where a via is not selected to be formed, the photobucket 1420 is retained, converted to permanent ILD material, or replaced with permanent ILD material. For example, Figure 14I illustrates via location 1422 with the corresponding photobucket 1420 removed to expose a portion of one of the first-level metal lines 1408. The other location previously occupied by the photobucket 1420 is now shown as area 1424 in Figure 14I. Location 1424 is not selected for via formation and instead forms part of the final ILD structure. In one embodiment, the material of the photobucket 1420 is left in position 1424 to become the final ILD material. In another embodiment, the material of the photobucket 1420 is modified (e.g., by cross-linking) in position 1424 to form the final ILD material. In yet another embodiment, the material of the photobucket 1420 in position 1424 is replaced with the final ILD material.

Referring again to Figure 14I, to form the via locations 1422, lithography is used to expose the corresponding photobuckets 1420. However, the lithography constraints can be relaxed and the misalignment tolerance can be high because the photobuckets 1420 are surrounded by non-photodegradable material. Furthermore, in one embodiment, instead of exposing to (for example) 30mJ/ ^cm2 , such a photobucket can be exposed to (for example) 3mJ/ ^cm2 . Normally this would result in very poor CD control and roughness. But in this case, the CD and roughness control will be defined by the photobuckets 1420, which can be extremely well controlled and defined. Therefore, the photobucket approach can be used to prevent the imaging/dose trade-off that limits the yield of next generation lithography processes.

Referring again to FIG. 14I , in one embodiment, the resulting structure includes a uniform ILD structure (ILD 1424 + ILD lines 1404 + ILD lines 1416). In this embodiment, both or all of ILD 1424, ILD lines 1404, and ILD lines 1416 are composed of the same material. In another such embodiment, ILD 1424, ILD lines 1404, and ILD lines 1416 are composed of different ILD materials. In either case, in a particular embodiment, differences such as a seam between the material of ILD 1424 and ILD line 1404 (e.g., seam 1497) and/or a seam between the material of ILD 1424 and ILD line 1416 (e.g., seam 1498) are observed in the final structure.

FIG14J illustrates the structure of FIG14I after hard mask filling in the opening of FIG14I, according to an embodiment of the present invention. Referring to FIG14J, a hard mask layer 1426 is formed in the via location 1422 and over the ILD location 1424. The hard mask layer 1426 can be formed by deposition and subsequent chemical mechanical planarization.

Figure 14K illustrates the structure of Figure 14J subsequent to the removal of the plug capping layer and the formation of a second plurality of photobuckets, according to an embodiment of the present invention. Referring to Figure 14K, the plug capping layer 1406 is removed, for example, by a selective etching process. Photobuckets 1428 are then formed in all possible plug locations above the exposed portions of the ILD lines 1404. In one embodiment, the openings formed upon removal of the plug capping layer 1406 are filled with an ultra-high-speed photoresist or an electron beam resist or other photosensitive material. In this embodiment, thermal backfill of the polymer into the openings is used subsequent to the spin-on application. In one embodiment, a fast photoresist is fabricated by removing an inhibitor from an existing photoresist material. In another embodiment, the photobucket 1428 is formed by an etch-back process and/or a lithography/reduction/etching process. It should be understood that the photobucket does not need to be filled with actual photoresist, as long as the material functions as a photosensitive switch.

Figure 14L illustrates the structure of Figure 14K following selection of a plug position, according to an embodiment of the present invention. Referring to Figure 14L, the photobuckets 1428 from Figure 14K that are not in the selected plug position are removed. In positions where plugs are selected to be formed, the photobuckets 1428 are retained, converted to permanent ILD material, or replaced with permanent ILD material. For example, Figure 14L illustrates a non-plug position 1430 with the corresponding photobuckets 1428 removed to expose a portion of the ILD line 1404. The other position previously occupied by the photobuckets 1428 is now shown as region 1432 in Figure 14L. Region 1432 is selected for plug formation and forms part of the final ILD structure. In one embodiment, the material of the corresponding photobucket 1428 is retained in region 1432 to form the final ILD material. In another embodiment, the material of the photobucket 1428 is modified (e.g., by cross-linking) in region 1432 to form the final ILD material. In yet another embodiment, the material of the photobucket 1428 in region 1432 is replaced with the final ILD material. In any case, region 1432 may also be referred to as plug 1432.

Referring again to Figure 14L, to form the opening 1430, lithography is used to expose the corresponding photobucket 1428. However, the lithography constraints can be relaxed and the misalignment tolerance can be high because the photobucket 1428 is surrounded by non-photodegradable material. Furthermore, in one embodiment, instead of exposing to (for example) 30 mJ/ ^cm2 , such a photobucket can be exposed to (for example) 3mJ/ ^cm2 . Normally this would result in very poor CD control and roughness. But in this case, the CD and roughness control will be defined by the photobucket 1428, which can be extremely well controlled and defined. Therefore, the photobucket approach can be used to prevent the imaging/dose trade-off that limits the yield of next generation lithography processes.

Referring again to FIG. 14L , in one embodiment, the resulting structure includes a uniform ILD structure (plug 1432 + ILD 1424 + ILD line 1404 + ILD line 1416). In this embodiment, two or more of plug 1432, ILD 1424, ILD line 1404, and ILD line 1416 are composed of the same material. In another such embodiment, plug 1432, ILD 1424, ILD line 1404, and ILD line 1416 are composed of different ILD materials. In either case, in a particular embodiment, differences such as a seam between the plug 1432 and the material of the ILD line 1404 (e.g., seam 1499) and/or a seam between the plug 1432 and the material of the ILD line 1416 (e.g., seam 1496) are observed in the final structure.

FIG14M illustrates the structure of FIG14L after removal of the hard mask of FIG14L, according to an embodiment of the present invention. Referring to FIG14M, the hard mask layer 1426 is selectively removed to form metal line and via openings 1434. In this embodiment, the hard mask layer 1426 is composed essentially of carbon and is selectively removed using an ash process.

FIG14N illustrates the structure of FIG14M after metal line and via formation, according to an embodiment of the present invention. Referring to FIG14N , metal line 1434 and vias (one of which is shown as 1438) are formed over the metal fill of opening 1434 of FIG14M . Metal line 1436 is coupled to underlying metal line 1408 by via 1438 and interrupted by plug 1432. In one embodiment, opening 1434 is filled with a metal damascene method, where metal is used to overfill the opening and then planarized back to provide the structure shown in FIG14N . Therefore, the metal (e.g., copper and associated barrier and seed layers) deposition and planarization processes used to form metal lines and vias in the manner described above may be those typically used in standard back-end-of-line (BEOL) single or double damascene processes. In one embodiment, the ILD lines 1416 may be removed in subsequent manufacturing operations to provide air gaps between the resulting metal lines 1436.

The structure of Figure 14N can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 14N can represent the last metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations can be performed in an alternative order, not every operation needs to be performed and/or additional process operations can be performed. In any case, the resulting structure enables the fabrication of a via that is directly focused on the underlying metal line. That is, the via can have a wider, narrower, or the same thickness as the underlying metal line, for example, due to an imperfectly selective etch process. However, in one embodiment, the center of the via is directly aligned (matched) with the center of the metal line. Furthermore, the ILD used to select which plugs and vias will likely be significantly different from the main ILD and will be highly self-aligned in both directions. Thus, in one embodiment, variations due to conventional lithography/dual damascene patterning (which must be accommodated separately) will not be a factor in the resulting structure described herein. Referring again to FIG. 14N , self-aligned fabrication via a subtractive approach can then be completed at this stage. Fabricating the next layer in a similar manner can involve repeating the above process again. Alternatively, other approaches can be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

The process flow described above involves the use of deep trench etching. In another form, a more superficial approach involves plug-only self-aligned subtractive processing techniques. For example, Figures 15A-15D illustrate portions of an integrated circuit layer representing various operations in a method for subtractive self-aligned plug patterning, according to another embodiment of the present invention. In each illustration of each of the operations, a plan view is shown at the top, while a corresponding cross-sectional view is shown at the bottom. These views will be referred to herein as the corresponding cross-sectional view and plan view.

FIG15A illustrates a plan view and corresponding cross-sectional views of a start plug grid according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a' and b-b', respectively, the start plug grid structure 1500 includes an ILD layer 1502 having a first hard mask layer 1504 disposed thereon. A second hard mask layer 1508 is disposed on the first hard mask layer 1504 and patterned to have a grating structure. A third hard mask layer 1506 is disposed on the second hard mask layer 1508 and on the first hard mask layer 1504. In addition, the opening 1510 remains between the grating structures of the second hard mask layer 1508 and the third hard mask layer 1506 .

FIG15B illustrates a plan view and corresponding cross-sectional views of the structure of FIG15A following photobucket filling, exposure, and development, according to an embodiment of the present invention. Referring to the plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and b-b', respectively, photobuckets 1512 are formed in openings 1510 of FIG15A. Thereafter, selected photobuckets are exposed and removed to provide selected plug locations 1514, as shown in FIG15B.

FIG15C illustrates a plan view and corresponding cross-sectional views of the structure of FIG15B subsequent to plug formation, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a' and b-b', respectively, plug 1516 is formed within opening 1514 of FIG15B. In one embodiment, plug 1516 is formed by spin-on coating and/or deposition and etch-back.

FIG15D illustrates a plan view and corresponding cross-sectional views of the structure of FIG15C following removal of the hard mask layer and the remaining photobuckets, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a' and b-b', respectively, the third hard mask layer 1506 is removed, leaving behind the second hard mask layer 1508 and plugs 1516. The resulting pattern (second hard mask layer 1508 and plugs 1516) can then be used to pattern the hard mask layer 1504 for final patterning of the ILD layer 1502. In one embodiment, the third hard mask layer 1506 consists essentially of carbon and is removed by performing a gray process.

Thus, the structure of FIG. 15D can then be used as a basis for forming ILD line and plug patterns. It should be understood that the process operations described above may be performed in alternate orders, that not every operation needs to be performed, and/or that additional process operations may be performed. In any case, the resulting structure enables the fabrication of self-aligned plugs. Thus, in one embodiment, variations due to conventional lithography/damascene patterning (which would otherwise need to be accommodated) are not a factor in the resulting structure described herein.

According to embodiments of the present invention, dielectric helmet-based approaches and/or hard mask selectively-based approaches (and resulting structures) for back-end-of-line (BEOL) processing are described. One or more embodiments described herein relate to methods for fabricating self-aligned interconnects using a dielectric helmet in directed self-polymerization (DSA) or selective growth. Embodiments may explore or implement one or more of the use of a dielectric helmet, directed self-polymerization, selective deposition, self-alignment, or tight-pitch patterned interconnects. Embodiments may be implemented to provide improved via short tolerance by utilizing self-alignment through "coloring" of selective deposition, followed by directed self-polymerization (e.g., for sub-10nm technology nodes).

To provide context, current solutions for improving short tolerance can include: (1) using metal recesses to fill alternating metal trenches with different hard masks, (2) using different "color" metal caps to act as templates for directed self-polymerization (DSA) or selective growth, or (3) recessing the metal or ILD to "steer" the via toward the associated line. Overall, typical process flows for improving via short tolerance require metal recessing. However, recessing the metal with acceptable uniformity has proven to be a challenge in many of these process schemes.

According to embodiments of the present invention, one or more of the aforementioned issues are addressed by implementing a method for depositing a non-conformal dielectric cap over half of the interconnect population. The non-conformal dielectric cap is used as a template for selective growth or directed self-polymerization. In one such embodiment, this approach can be applied to any interconnect metal layer and (possibly) to the gate contact. In certain embodiments, the need for metal recessing, as seen in state-of-the-art approaches, is effectively eliminated from the processing scheme described herein.

As a general overview of the concepts discussed herein, Figures 16A-16D illustrate cross-sectional views of a portion of an integrated circuit layer representing various operations in a method involving the formation of a dielectric shield for back-end-of-line (BEOL) interconnect fabrication, in accordance with an embodiment of the present invention.

16A , a starting point structure 1600 is provided as a starting point for fabricating a new metallization layer. Starting point structure 1600 includes a hard mask layer 1602 disposed on an interlayer dielectric (ILD) layer 1604. As described below, the ILD layer can be disposed above a substrate and, in one embodiment, above an underlying metallization layer. Openings are formed in hard mask layer 1604 (corresponding to trenches formed in ILD layer 1602). Spaces between these trenches are filled with a conductive layer to provide first metal lines 1606 (and, in some cases, corresponding conductive vias 1607). The remaining trenches are left unfilled, providing open trenches 1608. In one embodiment, structure 1600 is fabricated by patterning a hard mask and an ILD layer and then metallizing half of the metal trenches (e.g., every other one of the trenches), leaving the other half open. In one embodiment, the trenches in the ILD are patterned using a pitch-slicing patterning process flow. It should be understood that the following process operations described below may or may not initially involve pitch-slicing. In either case, but particularly when pitch-slicing is also used, embodiments can enable continued scaling of the metal layer pitch beyond the resolution capabilities of state-of-the-art lithography equipment.

FIG16B illustrates the structure of FIG16A after a non-conformal dielectric capping layer 1610 has been deposited over structure 1600. Non-conformal dielectric capping layer 1610 includes a first portion 1600A that covers the exposed surfaces of hard mask layer 1604 and metal line 1606. Non-conformal dielectric capping layer 1610 includes a second portion 1610B connected to first portion 1610A. Second portion 1610B of non-conformal dielectric capping layer 1610 is formed within open trench 1608, along sidewalls 1608A and bottom 1608B of open trench 1608. In one embodiment, second portion 1610B of non-conformal dielectric cap layer 1610 is substantially thinner than first portion 1610A, as depicted in FIG16B . In other embodiments, portion 1610B is absent or discontinuous. In this manner, the deposition of non-conformal dielectric cap layer 1610 is considered non-conformal because the thickness of non-conformal dielectric cap layer 1610 is not the same at all locations. The resulting geometry can be referred to as a helmet shape for non-conformal dielectric cap layer 1610 because the uppermost portion of ILD layer 1602 has the thickest portion of non-conformal dielectric cap layer 1610 thereon and is therefore protected to a greater extent than other areas. In one embodiment, the non-conformal dielectric capping layer 1610 is a dielectric material such as, but not limited to, silicon nitride or silicon oxynitride. In one embodiment, the non-conformal dielectric capping layer 1610 is formed using a plasma enhanced chemical vapor deposition (PECVD) process or, in another embodiment, physical vapor deposition (PVD).

FIG16C illustrates the structure of FIG16B following via patterning, metallization, and planarization of the second half of the metal lines. In one embodiment, a metal fill process is performed to provide a second metal line 1612. However, in one embodiment, the via locations are first selected and opened prior to the metal fill. Then, during the metal fill, vias 1613 are formed associated with certain of the second metal lines 1612. In one such embodiment, the via opening is formed by extending one of the opened trenches 1608 by etching through a non-conformal dielectric cap layer 1610 on the bottom of the selected trench 1608 and then extending the trench through the dielectric layer 1602. The result is a break in the continuity of the non-conformal dielectric cap layer 1610 at the location of the via of the second metal line 1612, as depicted in FIG16C.

In one embodiment, the metal fill process used to form the second metal line 1612 and the conductive via 1613 is performed using a metal deposition and subsequent planarization process, such as a chemical mechanical planarization (CMP) process. The planarization process exposes (but does not remove) the non-conformal dielectric capping layer 1610, as depicted in FIG16C. It should be understood that, in one embodiment, because the second metal line 1612 (and corresponding conductive via 1613) are formed in a later process than the process used to fabricate the first metal line 1606 (and corresponding conductive via 1607), the second metal line 1612 can be fabricated using a different material than the material used to fabricate the first metal line 1606. In one such embodiment, the metallization layer ultimately includes alternating conductive interconnects of different first and second compositions. However, in another embodiment, metal lines 1612 and 1606 are made from substantially the same material.

In one embodiment, the first metal line 1606 is isolated at a pitch, and the second metal line 1612 is isolated at the same pitch. In other embodiments, the lines are not necessarily isolated at a pitch. However, by including the non-conformal dielectric cap layer 1610 (or dielectric helmet), only the surface of the second metal line 1612 is exposed. Therefore, the pitch between the adjacent first and second metal lines that would otherwise be exposed is relaxed to only the pitch of the second metal line. Thus, the alternating exposed dielectric surfaces of the non-conformal dielectric cap layer 1610 and the exposed surfaces of the second metal line 1612 provide a distinct surface on the pitch of the second metal line 1612.

FIG16D illustrates the structure of FIG16C after continuing with a directed autopolymerization or selective deposition method to ultimately form two different (alternating) first and second hard mask layers 1614 and 1616, respectively. In one embodiment, the materials of the hard mask layers 1614 and 1616 exhibit different etch selectivities with respect to each other. The first hard mask layer 1614 is aligned with the exposed areas of the non-conformal dielectric cap layer 1610. The second hard mask layer 1616 is aligned with the exposed areas of the second metal line 1612. As described in more detail below, directed autopolymerization or selective growth can be used to selectively align the first and second hard mask layers 1614 and 1616, respectively, to the dielectric and metal surfaces.

In a first general embodiment, to ultimately form first and second hard mask layers 1614 and 1616, a directed self-polymerizing (DSA) block copolymer deposition and polymer polymerization process is performed. In one embodiment, the DSA block copolymer is coated on a surface and annealed to separate the polymer into a first block and a second block. In one embodiment, the first polymer block preferentially adheres to the non-conformal dielectric capping layer 1610. The second polymer block adheres to the second metal line 1612. In one embodiment, the block copolymer molecules are polymer molecules formed by chains of covalently bonded monomers, examples of which are described above.

Referring again to FIG. 16D , in the case of a DSA process, in a first embodiment, the first and second hard mask layers 1614 and 1616 are first and second bulk polymers, respectively. However, in a second embodiment, the first and second bulk polymers are sequentially replaced with the materials of the first and second hard mask layers 1614 and 1616, respectively. In one such embodiment, a selective etching and deposition process is used to replace the first and second bulk polymers with the materials of the first and second hard mask layers 1614 and 1616, respectively.

In a second general embodiment, a selective growth process is used in place of a DSA process to ultimately form the first and second hard mask layers 1614 and 1616. In one such embodiment, the material of the first hard mask layer 1614 is grown over the exposed portions of the underlying non-conformal dielectric cap layer 1610. The second (different) material of the second hard mask layer 1616 is grown over the exposed portions of the underlying second metal line 1612. In one embodiment, the selective growth is achieved by a dep-etch-dep-etch process for each of the first and second materials, resulting in multiple layers of each of these materials. This process may be desirable compared to conventional selective growth techniques that can form "mushroom-top" films. The tendency of mushroom-top film growth can be reduced by using an alternating deposition/etch/deposition (dep-etch-dep-etch) approach. In another embodiment, a film is selectively deposited on the metal, followed by a different film selectively deposited on the ILD (or vice versa), and this is repeated multiple times to create a sandwich stack. In another embodiment, both materials are grown simultaneously in a chamber (e.g., by a CVD-like process), selectively growing on exposed areas of the underlying substrate.

As described in more detail below, in one embodiment, the resulting structure of FIG. 16D enables improved via short tolerance when a later via layer is fabricated on the structure of FIG. 16D . In one embodiment, improved short tolerance is achieved because fabricating the structure with alternating "color" hard masks reduces the risk of via shorts to erroneous metal lines. In one embodiment, self-alignment is achieved because the alternating color hard masks are self-aligned to the underlying metal trenches. In one embodiment, the need for metal recesses is removed from the process scheme, which reduces process variation.

In a first more detailed example process flow, Figures 16E-16P illustrate cross-sectional views of a portion of an integrated circuit layer representing various operations in another method involving dielectric shield formation for back-end-of-line (BEOL) interconnect fabrication, according to an embodiment of the present invention.

Referring to FIG. 16E , a starting point structure 1630 is provided (following the first metallization process) as a starting point for fabricating a new metallization layer. Starting point structure 1630 includes a hard mask layer 1634 (e.g., silicon nitride) disposed on an interlayer dielectric (ILD) layer 1632. As described below, the ILD layer can be disposed above a substrate and (in one embodiment) above an underlying metallization layer. A first metal line 1636 (and, in some cases, a corresponding conductive via 1637) is formed in ILD layer 1632. A protruding portion 1636A of metal line 1636 has adjacent dielectric spacers 1638. A sacrificial hard mask layer 1640 (e.g., amorphous silicon) is included between adjacent dielectric spacers 1638. Although not depicted, in one embodiment, metal lines 1636 are formed by first removing the second sacrificial hard mask material between the dielectric spacers 1638 and then etching the hard mask layer 1634 and the ILD layer 1632 to form trenches that will be filled during the metallization process.

16F illustrates the structure of FIG 16E after a second pass of metal processing including trench etching. Referring to FIG 16F , the sacrificial hard mask layer 1640 is removed to expose the hard mask layer 1634. The exposed portion of the hard mask layer 1634 is removed and trenches 1642 are formed in the ILD layer 1632.

Figure 16G illustrates the structure of Figure 16F after the sacrificial material fill. Sacrificial material 1644 is formed in trench 1642 and over spacers 1638 and metal lines 1636. In one embodiment, sacrificial material 1644 is formed in a spin-on process, leaving a substantially flat layer, as depicted in Figure 16G.

FIG16H illustrates the structure of FIG16G following a planarization process for re-exposing the hard mask layer 1634, removing the dielectric spacers 1638, and removing the protruding portion 1636A of the metal line 1636. Furthermore, the planarization process confines the sacrificial material 1644 to the trenches 1642 formed in the dielectric layer 1632. In one embodiment, the planarization process is performed using a chemical mechanical polishing (CMP) process.

Figure 16I illustrates the structure of Figure 16H after the sacrificial material is removed. In one embodiment, the sacrificial material 1644 is removed from the trench 1642 using a wet etch or dry etch process.

FIG16J illustrates the structure of FIG16I following the deposition of a non-conformal dielectric capping layer 1646 (which may be referred to as a dielectric helmet). In one embodiment, non-conformal dielectric capping layer 1646 is formed using a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process, such as a plasma-enhanced CVD (PECVD) process. Non-conformal dielectric capping layer 1646 may be as described above in connection with non-conformal dielectric capping layer 1610.

FIG16K illustrates the structure of FIG16J following deposition of a sacrificial capping layer. Sacrificial capping layer 1648 is formed on the upper surface of non-conformal dielectric capping layer 1646 and may be implemented to protect non-conformal dielectric capping layer 1646 during subsequent etching or CMP processes. In one embodiment, sacrificial capping layer 1648 is a titanium nitride (TiN) layer formed by, for example, a PVD or CVD process.

Figure 16L illustrates the structure of Figure 16K following via lithography and etching. Selected trenches 1638 are exposed and subjected to an etch process that breaks the non-conformal dielectric cap layer 1646 at location 1650 and extends the trench to provide a via site 1652, as described above.

FIG16M illustrates the structure of FIG16L after the second metal line is fabricated. In one embodiment, the second metal line 1654 (and, in some cases, the associated conductive via 1656) is formed by performing a metal fill and polishing process. The polishing process may be a CMP process, which further removes the sacrificial capping layer 1648.

FIG. 16N illustrates the structure of FIG. 16M following directed self-polymerization (DSA) or selective growth, for example, to provide first and second alternating placeholder materials 1658 and 1660 (which may be permanent materials, as described in conjunction with FIG. 16D ).

Figure 16O illustrates the structure of Figure 16N subsequent to replacing the first and second alternating placeholder materials 1658 and 1660 with permanent first and second hard mask layers 1662 and 1664, respectively. The processing of Figures 16N and 16O may be described in conjunction with Figure 16D.

FIG16P illustrates the structure of FIG16O after patterning the next level of vias. An upper ILD layer 1666 is formed over the first and second hard mask layers 1662 and 1664. An opening 1668 is formed in the upper ILD layer 1666. In one embodiment, the opening 1668 is formed wider than the via feature size. Selected locations of the exposed first and second hard mask layers 1662 and 1664 are selected for selective removal, for example, by a selective etching process. In this case, areas of the first hard mask 1662 are removed selectively to the exposed portions of the second hard mask layer 1664. Conductive via 1670 is then formed in opening 1668 and in the area where the first hard mask 1662 area has been removed. Conductive via 1670 contacts one of the first metal lines 1636. In one embodiment, conductive via 1670 contacts one of the first metal lines 1636 without shorting to one of the adjacent second metal lines 1654. In a specific embodiment, portion 1672 of conductive via 1670 is disposed over a portion of second hard mask layer 1664 without contacting the underlying second metal line 1654, as depicted in FIG16P. Consequently, in one embodiment, improved short circuit tolerance is achieved.

In one embodiment, as described in the embodiments above, regions of the first hard mask 1662 are removed to facilitate the fabrication of the via 1670. In this case, the openings formed upon removal of selected regions of the first hard mask 1662 further require etching through the uppermost portion of the non-conformal dielectric capping layer 1646. However, in another embodiment, regions of the second hard mask 1664 are removed to facilitate the fabrication of the via 1670. In this case, the openings formed upon removal of such selected regions of the second hard mask 1664 directly expose the metal line 1654 to which the via 1670 is connected.

In a second, more detailed example process flow involving a first approach to via etching, Figures 17A-17J illustrate cross-sectional views of a portion of an integrated circuit layer, representing various operations in another method involving dielectric shield formation for back-end-of-line (BEOL) interconnect fabrication, according to an embodiment of the present invention.

Referring to FIG. 17A , a starting point structure 1700 is provided (following the first metallization process) as a starting point for fabricating a new metallization layer. Starting point structure 1700 includes a hard mask layer 1704 (e.g., silicon nitride) disposed on an interlayer dielectric (ILD) layer 1702. As described below, the ILD layer can be disposed above a substrate and (in one embodiment) above an underlying metallization layer. A first metal line 1706 (and, in some cases, a corresponding conductive via 1707) is formed in ILD layer 1702. A protruding portion 1706A of metal line 1706 has adjacent dielectric spacers 1708. A sacrificial hard mask layer 1710 (e.g., amorphous silicon) is included between adjacent dielectric spacers 1708. Although not depicted, in one embodiment, metal lines 1706 are formed by first removing the second sacrificial hard mask material between the dielectric spacers 1708 and then etching the hard mask layer 1704 and the ILD layer 1702 to form trenches that will be filled during the metallization process.

FIG17B illustrates the structure of FIG17A after a second pass metallization process is performed to include trench and via locations. Referring to FIG17B , sacrificial hard mask layer 1710 is removed to expose hard mask layer 1704. The exposed portion of hard mask layer 1704 is removed and trenches 1712 are formed in ILD layer 1702. Additionally, in one embodiment, via locations 1722 are formed in selected locations using a via lithography and etching process, as depicted in FIG17B .

FIG17C illustrates the structure of FIG17B after the sacrificial material fill. Sacrificial material 1714 is formed in trench 1712 and over spacers 1708 and metal lines 1706. In one embodiment, sacrificial material 1714 is formed in a spin-on process, leaving a substantially flat layer, as depicted in FIG17C.

FIG17D illustrates the structure of FIG17C following a planarization process for re-exposing the hard mask layer 1704, removing the dielectric spacers 1708, and removing the protruding portion 1706A of the metal line 1706. Furthermore, the planarization process confines the sacrificial material 1714 to the trenches 1712 formed in the dielectric layer 1702. In one embodiment, the planarization process is performed using a chemical mechanical polishing (CMP) process.

FIG17E illustrates the structure of FIG17D after partial removal of sacrificial material 1714 to provide recessed sacrificial material 1715. In one embodiment, sacrificial material 1714 is recessed within trench 1712 using a wet or dry etch process. Recessed sacrificial material 1715 may be retained at this point to protect the metal layer below via location 1722.

FIG17F illustrates the structure of FIG17E following the deposition of a non-conformal dielectric capping layer 1716 (which may be referred to as a dielectric helmet). In one embodiment, non-conformal dielectric capping layer 1716 is formed using physical vapor deposition (PVD), a selective growth process, or a chemical vapor deposition (CVD) process, such as a plasma-enhanced CVD (PECVD) process. Non-conformal dielectric capping layer 1716 may be as described above in connection with non-conformal dielectric capping layer 1710. Alternatively, the non-conformal dielectric cap layer 1716 may include only an upper portion 1716A, with substantially no portion of the non-conformal dielectric cap layer 1716 formed in the trench 1712, as depicted in FIG. 17F.

FIG17G illustrates the structure of FIG17F after the second metal line is fabricated. In one embodiment, the second metal line 1724 (and, in some cases, the associated conductive via 1726) is formed by performing a metal fill and polishing process (following the removal of the recessed sacrificial material 1715). The polishing process can be a CMP process.

FIG. 17H illustrates the structure of FIG. 17G following directed self-polymerization (DSA) or selective growth, for example, to provide first and second alternating placeholder materials 1728 and 1730 (which may alternatively be permanent materials, as described in conjunction with FIG. 16D ).

Figure 17I illustrates the structure of Figure 17H subsequent to replacing the first and second alternating placeholder materials 1728 and 1730 with permanent first and second hard mask layers 1732 and 1734, respectively. The processing of Figures 17H and 3I may be described in conjunction with Figure 16D.

FIG17J illustrates the structure of FIG17I after patterning the next level of vias. An upper ILD layer 1736 is formed over the first and second hard mask layers 1732 and 1734. An opening 1738 is formed in the upper ILD layer 1736. In one embodiment, the opening 1738 is formed wider than the via feature size. Selected locations of the exposed first and second hard mask layers 1732 and 1734 are selected for selective removal, for example, by a selective etching process. In this case, areas of the first hard mask 1732 are removed that are selective to the exposed portions of the second hard mask layer 1734. Conductive via 1740 is then formed in opening 1738 and in the area where the first hard mask 1732 area has been removed. Conductive via 1740 contacts one of the first metal lines 1706. In one embodiment, conductive via 1740 contacts one of the first metal lines 1706 without shorting to one of the adjacent second metal lines 1724. In a specific embodiment, portion 1742 of conductive via 1740 is disposed over a portion of second hard mask layer 1734 without contacting the underlying second metal line 1724, as depicted in FIG17J. Consequently, in one embodiment, improved short circuit tolerance is achieved.

In one embodiment, as described in the embodiments above, regions of the first hard mask 1732 are removed to allow for the fabrication of the via 1740. In this case, the openings formed upon removal of selected regions of the first hard mask 1732 further require etching through the uppermost portion of the non-conformal dielectric cap layer 1716. However, in another embodiment, regions of the second hard mask 1734 are removed to allow for the fabrication of the via 1740. In this case, the openings formed upon removal of such selected regions of the second hard mask 1734 directly expose the metal line 1724 to which the via 1740 is connected.

Referring again to Figures 16P and 17J, the dielectric helmet can be viewed over half of the total metal count by cross-sectional analysis. Additionally, hard masks of different materials are self-aligned to the dielectric helmet. Such structures may include one or more conductive vias having improved short circuit tolerance, alternating hard mask materials, and the presence of a dielectric helmet. The resulting structure (such as that described in connection with Figures 16P or 17J) may then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figures 16P or 17J may represent the last metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in an alternative order, not every operation needs to be performed, and/or additional process operations may be performed.

According to embodiments of the present invention, patterned build-up layers for vias and plugs are described. One or more embodiments described herein relate to process schemes for via critical dimension (CD) control. Embodiments may include improvements in via CD control, via CD uniformity, edge placement error (EPE), and via self-alignment. Embodiments may improve edge placement error (EPE) in semiconductor patterning of vias and may enable self-alignment of multiple via lithography passes. In one embodiment, all via edges are defined with a grating in place of a standard resist edge. The sacrificial grating is generated beneath the via resist in the same direction as the metal via is located. The vias are patterned using a standard photoresist. However, during the subsequent etching of the gratings (e.g., two crossed gratings) through the sacrificial grating and the self-aligned via (SAV) metal grating, all via edges are defined by these gratings. In one embodiment, no variability from the via resist edges is transferred into the substrate, and the resulting process capability enables better control of the via CD and improves yield and process capability.

To provide background for the following embodiments, currently known solutions involve using a resist edge to define the via edge, which determines the shorting tolerance to the underlying metal. However, standard via resist patterning is known to have much higher edge placement errors than photograting patterning. In contrast, according to the embodiments described herein, using a sacrificial photograting to define the via edge provides improved control over the via edge, and the risk of shorting to the wrong metal is significantly improved.

According to the embodiments described herein, a pattern buildup process is described for a multi-via pattern with a sacrificial grating in the stack to define the via edge and then etch. The "screen" stack is created by applying a hard mask over the patterned upper metal (M1) layer interlayer dielectric (where the plugs already exist). The hard mask flattens the wafer for subsequent processing. The next layer formed can be used as an etch stop, continuing with the buildup layer formation. At this stage, the grating can be generated at twice the pitch of the underlying lower metal (M0) layer and in the same orientation as the M0 grating. This grating effectively blocks every other M0 line underneath and ultimately defines the critical dimension (CD) of the via post etch. In one embodiment, because the grating is twice the pitch of the underlying M0, a substantial amount of hard mask (+/- 20nm) between the vias is included to allow for edge placement error (EPE) of the overlying etch resist features.

Next, the majority of the via mask pattern is deposited in the buildup layer through a photo grating. After deposition, the photo grating is inverted without requiring additional lithography to expose the remaining lower metal (M0) lines and protect the resulting vias. A liner is inserted between the photo gratings to ensure that vias on adjacent M0 lines do not merge. The spacing between vias can be adjusted by varying the thickness of the liner.

Finally, the via pattern from one or more via masks can be accumulated through the inverted grating to complete the patterning in the accumulation of all delineated vias. The grating is then removed and the accumulated via pattern in the accumulation layer is etched down through the upper metal (M1) hard mask grating into the interlayer dielectric below the M1 line and to the underlying M0. The stack and overlying hard mask layer above the M1 grating are removed. The trenches and vias are then metallized and then polished. The result is extremely good CD control of the formed vias in both directions, as well as self-alignment of all vias with respect to each other.

Next, in one aspect, one or more embodiments described herein relate to a method for utilizing an underlying metal grating structure (or a portion of such a structure orthogonal thereto) as a template for creating overlying conductive vias. In an exemplary process scheme, Figures 18A-18W illustrate plan views (upper portion of the figures) and corresponding oblique angle (middle portion of the figures) and cross-sectional views (lower portion of the figures) illustrating various operations in a metal via processing scheme for back-end-of-line (BEOL) interconnects, according to embodiments of the present invention.

Referring to FIG18A , a starting point structure 1800 is provided as a starting point for fabricating a new metallization layer. Starting point structure 1800 includes an array of alternating metal lines 1802 and dielectric lines 1804. Metal lines 1802 have upper surfaces that are approximately coplanar with the upper surfaces of dielectric lines 1804. An etch stop layer 1806 is then formed on starting structure 1800, as depicted in FIG18B .

Referring to FIG18C , an interlayer dielectric layer 1808 is formed on the structure of FIG18B . A patterned hard mask 1810 is then formed on the structure of FIG18C , and the pattern of patterned hard mask 1810 is partially transferred into interlayer dielectric layer 1808 to form patterned interlayer dielectric layer 1812 (having metal line regions 1814 formed therein), as depicted in FIG18D . In one embodiment, patterned hard mask 1810 has a grating-type pattern, as depicted in the figure. In a specific embodiment, patterned hard mask 1810 is composed of titanium nitride (TiN).

Referring to FIG18E , a hard mask layer 1816 is formed over the structure of FIG18D . In one embodiment, the bottom surface of hard mask layer 1816 conforms to the topography of the structure of FIG18D , while the top surface of hard mask layer 1816 is planarized. In a specific embodiment, hard mask layer 1816 is a carbon hard mask (CHM) layer. An etch stop layer 1818 is then formed over the structure of FIG18E , as depicted in FIG18F . In a specific embodiment, etch stop layer 1818 is composed of silicon oxide (SiO x or SiO ₂ ).

Referring to FIG. 18G , a pattern buildup layer 1820 is then formed over the structure of FIG. 18F . In one embodiment, pattern buildup layer 1820 is a layer where multiple patterns will ultimately be accumulated, for example, for final via patterning. In a specific embodiment, pattern buildup mask 1820 is comprised of amorphous silicon (a-Si). A patterned hard mask 1822 is then formed over the structure of FIG. 18G , as depicted in FIG. 18H . In one embodiment, patterned hard mask 1822 has a grating-type pattern, as depicted. In one such embodiment, the grating-type pattern is orthogonal to the grating of patterned hard mask 1810 and parallel to the grating of metal line 1802. However, in one embodiment, from a top-down view, patterned hard mask 1822 exposes only every other metal line 1802 (e.g., metal line 1802(A)) and blocks alternate metal lines 1802 (e.g., metal line 1802(B)), as depicted in FIG18H. In a particular embodiment, patterned hard mask 1822 is comprised of silicon nitride (SiN).

Referring to FIG. 18I , a hard mask 1824 is then formed over the structure of FIG. 18H . In a specific embodiment, hard mask 1824 is a carbon hard mask (CHM). Hard mask 1824 is then patterned (e.g., by a lithography process using a single or multi-layer resist structure) and the pattern is transferred into the portion of pattern accumulation layer 1820 exposed by patterned hard mask 1822 to form a primary patterned memory layer 1826, as depicted in FIG. 18J . In one embodiment, the pattern is transferred into the portion of pattern accumulation layer 1820 by an etch process that terminates with etch stop layer 1818 . In one embodiment, after forming the patterned memory layer 1826 once, the hard mask 1824 is removed, as also depicted in Figure 18J. It should be understood that the process can be repeated for several different masking operations.

Referring to FIG. 18K , barrier lines 1828 are then formed by filling the openings in patterned hard mask 1822 of the structure of FIG. 18J with a layer of barrier material. In certain embodiments, the barrier material layer is a flowable silicon oxide material. In other embodiments, the barrier material layer is any of several other suitable materials. Patterned hard mask 1822 is then removed from the structure of FIG. 18K , leaving barrier lines 1828, as depicted in FIG. 18L .

Referring to FIG. 18M , an insulating spacer-forming material layer 1830 is then formed on the structure of FIG. 18L , conforming to the barrier line 1828. In one embodiment, the insulating spacer-forming material layer 1830 is composed of a dielectric material. In one embodiment, the spacer-forming material layer 1830 is composed of silicon oxide (SiOx or _SiO2 ). The spacer-forming material layer 1830 is then patterned to form spacers 1832 adjacent to the sidewalls of the barrier line 1828, as depicted in FIG. 18N . In one embodiment, the spacer-forming material layer 1830 is patterned using an anisotropic dry etching process to form the spacers 1832.

18O , the collective pattern of barrier lines 1828, spacers 1832, and the protective areas of the patterned mask formed after forming spacers 1832 is then transferred into the primary patterned memory layer 1826 to form the secondary patterned memory layer 1834. In one embodiment, the pattern is transferred into the primary patterned memory layer 1826 by an etch process that terminates with an etch stop layer 1818. The barrier lines 1828, spacers 1832, and any additional masking material of the structure of FIG. 18O are then removed to expose the secondary patterned memory layer 1834, as depicted in FIG. 18P .

18Q , the pattern of the secondary patterned memory layer 1834 of the structure of FIG18P is then transferred to the etch stop layer 1818 to form the patterned etch stop layer 1836 and expose a portion of the hard mask layer 1816. In one embodiment, the pattern of the secondary patterned memory layer 1834 is transferred to the etch stop layer 1818 using a dry etching process. The secondary patterned memory layer 1834 of the structure of FIG18Q is then removed, as depicted in FIG18R .

18S , the pattern of patterned etch stop layer 1836 of the structure of FIG 18R is then transferred into hard mask layer 1816 to form patterned hard mask layer 1838. Patterned hard mask layer 1838 exposes portions of line region 1814 of patterned interlayer dielectric layer 1812 and portions of patterned hard mask 1810. That is, while patterned hard mask layer 1838 exposes a wider area than line region 1814 of patterned interlayer dielectric layer 1812, patterned hard mask 1810 protects the “exposed” areas of patterned interlayer dielectric layer 1812 outside line region 1814. The pattern of the patterned hard mask layer 1838 of the structure of FIG18S is then transferred to the inter-patterned layer dielectric layer 1812 to form a secondary inter-patterned layer dielectric layer 1840 and expose the etch stop layer 1806, as depicted in FIG18T. However, in one embodiment, the patterned hard mask 1810 inhibits the overall transfer of the pattern, as also depicted in FIG18T. In one embodiment, the pattern of the patterned hard mask layer 1838 is transferred to the inter-patterned layer dielectric layer 1812 by an etching process that uses the etch stop layer 1806 as a termination point.

18U , the exposed portion of etch stop layer 1806 of the structure of FIG18T is removed to form patterned etch stop layer 1842 and expose via location 1844 of metal line 1802. Patterned etch stop layer 1836, patterned hard mask layer 1838, and patterned hard mask 1810 of the structure of FIG18U are then removed, as depicted in FIG18V . This removal exposes secondary patterned interlayer dielectric layer 1840 and via location 1844 of metal line 1802, as well as upper metal line location 1846. In one embodiment, the patterned etch stop layer 1836, the patterned hard mask layer 1838, and the patterned hard mask 1810 are removed using a selective wet etching process.

Referring to FIG. 18W , an upper metallization layer is formed on the structure of FIG. 18V . In particular, a metal fill process is performed to provide metal vias 1848 and metal lines 1850 . In one embodiment, the metal fill process is performed using a metal deposition and subsequent planarization treatment scheme, such as a chemical mechanical planarization (CMP) process. In one embodiment, the surface of the formed structure of FIG. 18W is substantially the same as (although orthogonal to) the surface of the starting structure 1800 of FIG. 18A . Thus, in one embodiment, the process described in conjunction with FIG. 18B - 18W may be repeated on the structure of FIG. 18W to form the next metallization layer, and so on.

The resulting structure (such as that described in connection with FIG. 18W ) can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 18W may represent the final metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in an alternative order, that not every operation need be performed, and/or that additional process operations may be performed. It should also be understood that the above examples have focused on via/contact formation. However, in other embodiments, similar approaches may be used to retain or form areas for line terminations (plugs) within metal line layers.

According to embodiments of the present invention, grid-based via and plug patterning methods are described. One or more embodiments described herein relate to grid self-aligned and super self-aligned metal via processing schemes. The embodiments described herein can be implemented to provide self-aligned methods for metal/via layers. Almost all plug and via geometries are possible by implementing the methods described herein. In addition, the final via critical dimension (CD) can be independent of the lithography performed for patterning. Furthermore, the methods described herein can provide a "loop-through process" in that the end of the process flow has the same or substantially the same layer stack and layout as the beginning of the process flow. Therefore, once each operation in the process flow is completed, the process flow can be repeated as many times as needed to add as many metal/via layers as needed. In one or more embodiments, the overlap between vertical grids is used to define the layout of vias and metal lines. The size of the via can be determined by the overlap area between two grids.

To provide background for the embodiments described below, the methods described herein can provide for nearly any plug and via layout that can be used, as compared to currently known methods for self-aligning vias. The methods described herein can require less selective etching. The methods described herein can provide final plug and via CDs that are independent of the lithography utilized. Next, in one form, one or more of the embodiments described herein relate to a method that utilizes an underlying metal grating structure as a template for creating an overlying conductive via. It should be understood that similar methods can be implemented to create non-conductive spaces or discontinuities between metal (plugs).

In an exemplary process scheme, Figures 19A-19L illustrate plan views (upper portion of the figures) and corresponding oblique cross-sectional views (lower portion of the figures) illustrating various operations in a grid-aligned metal via process scheme for back-end-of-the-line (BEOL) interconnects, according to an embodiment of the present invention. It should be understood that different metallization layers are shown as separate (upper and lower) in the oblique cross-sectional views for clarity, although this is not the case in practice.

19A , a starting point structure 1900 is provided as a starting point for fabricating a new metallization layer. Starting point structure 1900 includes an array of alternating metal lines 1902 and dielectric lines 1904. Metal lines 1902 are recessed beneath dielectric lines 1904. Hard mask layers 1906 are disposed over metal lines 1902 and alternate with dielectric lines 1904. In one embodiment, dielectric lines 1904 are comprised of silicon nitride (SiN) and hard mask layers 1906 are comprised of silicon carbide (SiC) or silicon oxide (SiO ₂ ). The next patterned layer 1908 is then fabricated over starting point structure 1900, as depicted in FIG19B . In one embodiment, the next patterned layer 1908 includes an etch stop layer 1910, a dielectric layer 1912, and a photograting structure 1914. In one embodiment, the etch stop layer 1910 is composed of silicon oxide (SiO), the dielectric layer 1912 is composed of silicon nitride (SiN), and the photograting structure 1914 is composed of silicon oxide (SiO). In one embodiment, the photograting structure 1914 is formed using a pitch-halving or pitch-quartering scheme (e.g., by spacer patterning).

Referring to FIG19C , the pattern of the grating structure 1914 is transferred to the dielectric layer 1912 to form a patterned dielectric layer 1916. In one embodiment, the pattern of the grating structure 1914 is transferred to the dielectric layer 1912 using an etching process that uses an etch stop layer 1910 as the end point of the etching process. A through etch is then performed to remove the exposed portions of the etch stop layer 1910 to form a patterned etch stop layer 1918, as depicted in FIG19D . In one embodiment, the through etch reveals all possible via locations 1920 that can potentially be formed into the structure 1900.

19E , plug patterning is then performed by forming a patterned hard mask 1922 on the structure of FIG 19D (in the position where the plug will be retained). The combined pattern of the patterned hard mask 1922 and the grating structure 1914 is then transferred into the structure 1900 to form structure 1900′, which has regions 1924 for metal line formation within the structure 1900, as depicted in FIG 19F . In one embodiment, the combined pattern of the patterned hard mask 1922 and the grating structure 1914 is transferred into the structure 1900 using an etching process. This etching process may etch both layers 1904 and 1906 at substantially the same rate (or may be performed as several etching operations) and may be followed by a clean process to remove the patterned hard mask 1922, as also depicted in FIG. 19F.

19G , via patterning is then performed by forming a patterned lithographic mask 1926 over the structure of FIG. 19F , which exposes the locations where vias are to be formed (eg, a via selection process). The combined pattern of patterned lithographic mask 1926 and photograting structure 1914 is then transferred into structure 1900′ to form structure 1900″ having region 1928 for metal via formation within structure 1900′, as depicted in FIG19H . In one embodiment, the combined pattern of patterned lithographic mask 1926 and photograting structure 1914 is transferred into structure 1900′ using an etching process. This etching process may etch layer 1906 selectively to layer 1904 and may be followed by a clean process for removing patterned lithographic mask 1926, as also depicted in FIG19H .

19I , a metal fill process is performed on the structure of FIG. 19I to provide an underlying structure 1930. The metal fill process forms metal vias 1932 and metal lines 1934 in the structure 1930. The metal fill process may also fill the region between the photograting structure 1914 and the metal lines 1936, as depicted in FIG. 19I . In one embodiment, the metal fill process is performed using a metal deposition and subsequent planarization treatment scheme. The structure of FIG. 19I may then be reduced in thickness to remove the photograting structure 1914 to expose the patterned dielectric 1916 and provide a metal line 1938 on top that is reduced in thickness from the metal line 1936, as depicted in FIG. 19J . In one embodiment, the structure of FIG. 19I may then be reduced in thickness using a planarization process, such as a chemical mechanical planarization (CMP) process.

19K , metal lines 1938 are removed from the structure of FIG19J to leave behind patterned dielectric layer 1916 and patterned etch stop layer 1918. Metal lines 1938 can be removed by a selective etching process that removes metal lines 1938 while ensuring that no metal remains above the height of material layers 1904 and 1906 (i.e., such that no metal remains above the plug region of structure 1930). A hard mask layer 1940 is then formed over the structure of FIG19K , between the lines of patterned dielectric layer 1916, as depicted in FIG19L . In one embodiment, hard mask layer 1940 is composed of silicon carbide (SiC) or silicon oxide (SiO ₂ ) and is formed using a deposition and planarization process. In one embodiment, hard mask layer 1940 is composed of the same material as hard mask layer 1906. In one embodiment, the surface of the structure formed from patterned dielectric layer 1916 and hard mask layer 1940 is substantially the same as (although orthogonal to) the surface of starting structure 1900 of FIG. 19A . Therefore, in one embodiment, the process described in conjunction with FIG. 19B-19L can be repeated on the structure of FIG. 19L to form the next metallization layer, and so on.

It should be understood that the process described in conjunction with Figures 19B-19L (e.g., repeated on the structure of Figure 19L to form the next metallization layer) can be referred to as a cyclic flow, as the end of the process flow has the same or substantially the same layer stack and layout as the beginning of the process flow. In one embodiment, forming additional metallization layers includes using this cyclic flow. However, it should also be understood that the cyclic or repeated process can be implemented only for selected metallization layers. Other metallization layers in the resulting stack (e.g., layers above, below, or between layers fabricated using the processing scheme of Figures 19B-19L) can be fabricated using conventional dual damascene or other methods.

The resulting structure (such as 1931 described in connection with FIG. 19L ) can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, structure 1931 of FIG. 19L may represent the final metal interconnect layer in an integrated circuit. It should also be understood that in subsequent manufacturing operations, the dielectric lines may be removed to provide air gaps between the resulting metal lines. It should be understood that the above examples have focused on via/contact formation. However, in other embodiments, similar approaches may be used to retain or form areas for line terminations (plugs) within the metal line layer.

According to embodiments of the present invention, grating-based via and plug patterning is described. One or more embodiments described herein relate to grating-based plug and cut for feature termination formation. Embodiments may involve one or more of lithographic patterning, associated line end CD generation, and spacer-based patterning. Embodiments utilize methods to produce plugs and cuts with layout control and uniformity of one-dimensional (1D) features. It should be understood that there is a tradeoff between better control over line end (plug) or via layout, implying that vias and line ends are placed in more restricted locations.

To provide background for the embodiments described herein, to enable patterning of tighter pitch features in semiconductor manufacturing, grating and plug or grating and cut approaches are being applied to more layers. As feature sizes continue to shrink, the ability to robustly pattern cuts and plugs can limit scaling and throughput. Cut and plug features are typically defined directly by a lithographic operation with primarily two-dimensional (2D) features. These 2D features have much higher variation and non-uniformity than one-dimensional (1D) features.

Referring to Figures 20A-20G described below, an overview of a simplified patterning process for producing grating-defined plugs is provided in one embodiment. A sacrificial 1D pattern is generated orthogonal to the principal direction of the layer being patterned. A selection mask is then used to cut or preserve portions of the 1D pattern that will ultimately be used to cut or preserve portions of the primary grating. The final edge of the cut/save on the primary pattern is thus defined by the edge of the 1D sacrificial grating, with much better control and uniformity. 20A-20G illustrate plan views (top) and corresponding cross-sectional views (middle and bottom) illustrating operations in a method of fabricating grating-based plugs and cutting for back-end-of-line (BEOL) interconnect feature formation, according to an embodiment of the present invention.

Referring to FIG. 20A , a starting point structure 2000 is provided as a starting point for fabricating a new metallization layer. Starting point structure 2000 includes an interlayer dielectric (ILD) material layer 2002 having a first hard mask layer 2004 formed thereon. A second hard mask layer 2006 is formed on first hard mask layer 2004. Second hard mask layer 2006 has a grating pattern, which can be considered primarily a one-dimensional (1D) grating pattern. In one embodiment, the grating pattern of second hard mask 2006 is ultimately used to define the 1D locations of the final layer to be patterned, but not yet having features patterned therein. The first hard mask layer 2004 and/or the second hard mask layer 2006 can be made of a material such as, but not limited to, silicon nitride (SiN), silicon oxide (SiO ₂ ), titanium nitride (TiN), or silicon (Si). In one embodiment, the first hard mask layer 2004 and the second hard mask layer 2006 are made of different materials.

Referring to FIG. 20B , a third hard mask layer 2008 is formed on the structure of FIG. 20A . In one embodiment, the third hard mask layer 2008 has a grating pattern, which can be considered primarily a one-dimensional (1D) grating pattern, orthogonal to the 1D grating pattern of the second hard mask layer 2006 . The third hard mask layer 2008 can be fabricated from a material such as, but not limited to, silicon nitride (SiN), silicon oxide (SiO ₂ ), titanium nitride (TiN), or silicon (Si). In one embodiment, the third hard mask layer 2008 is fabricated from a material different from that of the first hard mask layer 2004 and the second hard mask layer 2006 . It should be understood that any of the above-mentioned hard mask layers may actually include multiple sub-layers, for example, to provide enhanced etch selectivity.

In one embodiment, the grating pattern of the third hard mask layer 2008 and the grating pattern of the second hard mask layer 2006 together define all allowable line end locations for the metal wire metallization layer. In one such embodiment, the grating pattern of the third hard mask layer 2008 and the grating pattern of the second hard mask layer 2006 together define line end locations at locations where lines of the grating patterns overlap. In another such embodiment, the grating pattern of the third hard mask layer 2008 and the grating pattern of the second hard mask layer 2006 together define line end locations at locations where spaces are exposed between the lines of the grating patterns.

Referring to FIG. 20C , a region of a lithographically patterned mask 2010 is formed over the structure of FIG. 20B . The region of the lithographically patterned mask 2010 can be formed from a photoresist layer, multiple layers, or similar lithographically patterned masks. In one embodiment, the region of the lithographically patterned mask 2010 provides the pattern of the cut/save region on the sacrificial grating formed from the second hard mask layer 2006 and the third hard mask layer 2008. Next, in one embodiment, a lithographic process is used to select the portion of the sacrificial grating (cut or save) that will ultimately define the end location of the main pattern of the metal lines. In one such embodiment, 193nm or EUV lithography is used, along with etching of the resist pattern into the underlying layer before etching the sacrificial grating pattern. In one embodiment, the lithography process involves multiple exposures of the resist layer or a deposition/etch/deposition repeat process. It should be understood that the masked areas can be referred to as cuts or storage locations, where the orthogonal grating overlap areas or spaces between the gratings are used to define the plug (or possibly via) locations.

Referring to FIG. 20D , using the regions of the lithographically patterned mask 2010 of the structure of FIG. 20C as a mask, the third hard mask layer 2008 is selectively etched to form a patterned hard mask layer 2012. That is, a portion of the sacrificial grating is etched to occupy portions of the pattern of the regions of the lithographically patterned mask 2010, which protects portions of the third hard mask layer 2008 from the etching process. In one embodiment, the portions of the third hard mask layer 2008 removed during the etching process are not part of the final target design. In one embodiment, these regions of the lithographically patterned mask 2010 are removed after forming the patterned hard mask layer 2012, as depicted in FIG. 20D .

20E , the combined pattern formed by the second hard mask layer 2006 and the patterned hard mask layer 2012 of the structure of FIG 20D is transferred into the first hard mask layer 2004 and into the ILD material layer 2002 , for example, by a selective etching process. The patterning forms a patterned ILD layer 2014 and a patterned hard mask layer 2016 .

Referring to FIG. 20F , the patterned hard mask layer 2012 and the second hard mask layer 2006 (i.e., the sacrificial grating) of the structure of FIG. 20E are then removed. The patterned hard mask layer 2016 may be retained at this stage, as depicted in FIG. 20F , or may be removed. Selective wet or dry processing techniques may be utilized for the removal of the patterned hard mask layer 2012 and the second hard mask layer 2006 (and, potentially, the patterned hard mask layer 2016). It should be understood that the resulting structure of FIG. 20F may subsequently be used as a starting point for metal fill, with the option of first removing the remaining patterned hard mask layer 2016. The location of where the metal feature ends (line ends) is defined by the edge of the 1D sacrificial grating which is transferred into the ILD material layer 2002 and is therefore well controlled.

Referring to FIG. 20G , a metal fill process is performed on the structure of FIG. 20F to form metal lines 2018 in the openings of the patterned ILD layer 2014. The metal lines have line ends formed by interruptions in the continuity formed in the patterned ILD layer 2014. In one embodiment, the metal fill process is performed by depositing and then planarizing one or more metal layers over the patterned ILD layer 2014. The patterned hard mask layer 2016 may remain during the metal deposition process and then be removed during the planarization process, as depicted in FIG. 20F and 20G . However, in other embodiments, the patterned hard mask layer 2016 is removed prior to the metal fill process. In yet other embodiments, the patterned hard mask layer 2016 is retained in the final structure. Referring again to FIG. 20G , it will be understood that metal lines 2018 may be formed over underlying features (such as conductive vias 2020 shown as an example).

The resulting structure (such as that described in connection with FIG. 20G ) can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 20G may represent the final metal interconnect layer in an integrated circuit. It will be understood that the above-described process operations may be performed in an alternative order, not every operation need be performed and/or additional process operations may be performed. In one embodiment, deviations due to conventional lithography/damascene patterning (which need to be accommodated separately) are not a factor in the resulting structure described herein. It will be understood that the above examples have focused on line end/plug/cut formation or retention. However, in other embodiments, a similar approach may be used to form vias/contacts above or below metal line layers. It should also be understood that in subsequent fabrication operations, the dielectric lines may be removed to provide air gaps between the resulting metal lines.

Referring again to Figures 20A-20G, in one embodiment, a patterning process for producing photogate-defined plugs is described. Advantages of this embodiment may include better dimensional control of end-to-end features, which reduces the probability of end-to-end shorts (production failures) that are otherwise observed under worst-case process variation conditions. The improved dimensional control of the end-to-end features provides more area under worst-case process variation (for via placement and coverage). Therefore, in one embodiment, improved electrical connectivity can be achieved from layer to layer, with increased yield and product performance. The improved dimensional control of the end-to-end features can enable smaller end-to-end widths, and therefore, better product density (cost per function) can be achieved.

In one embodiment, an advantage of the present invention is that all line end positions are defined by a single lithography operation. For example, when plug/cut pitches become extremely small, a common solution is to use multi-pass lithography with additional processing to produce composite plug/cut patterns. In contrast, in the embodiments described herein, feature end positions are a function of multiple lithography operations and, therefore, have greater variability than when a single lithography operation is used to define feature ends (as is the case with the embodiments described herein).

According to embodiments of the present invention, methods for wire end cutting are described. One or more embodiments described herein relate to techniques for patterning metal wire ends. The embodiments may include one or more of contact fabrication, damascene processing, dual damascene processing, interconnect fabrication, and metal trench patterning.

To provide background, in advanced nodes of semiconductor manufacturing, low-level interconnects are produced using separate patterning processes for line gratings, line terminations, and vias. The fidelity of the composite pattern tends to degrade as vias encroach on line terminations, and vice versa. The embodiments described herein provide a line termination process, also known as a plug process, that eliminates the associated approximation rules. These embodiments allow vias to be placed on line terminations and large vias to wrap around the line terminations.

To provide further context, FIG21A illustrates a plan view of a metallization layer of a conventional semiconductor device and a corresponding cross-sectional view taken along the a-a' axis of the plan view. FIG21B illustrates a cross-sectional view of a terminal or plug fabricated using a currently known process scheme. FIG21C illustrates another cross-sectional view of a terminal or plug fabricated using a currently known process scheme.

Referring to FIG. 21A , metallization layer 2100 includes metal line 2102 formed in dielectric layer 2104. Metal line 2102 can be coupled to underlying via 2103. Dielectric layer 2104 can include a line termination or plug region 2105. Referring to FIG. 21B , a conventional line termination or plug region 2105 of dielectric layer 2104 can be fabricated by patterning a hard mask layer 2110 on dielectric layer 2104 and then etching exposed portions of dielectric layer 2104. The exposed portions of dielectric layer 2104 can be etched to a depth suitable for forming line trench 2106 or further etched to a depth suitable for forming via trench 2108. 21C , two vias adjacent opposite sidewalls of the terminal or plug 2105 may be fabricated in a single large exposure 2116 to ultimately form a line trench 2112 and a via trench 2114 .

However, referring again to Figures 21A-21C, fidelity issues and/or hard mask erosion issues can result in imperfect patterning. Instead, one or more embodiments described herein include implementations of a process flow involving the construction of a line-end dielectric (plug) following trench and via patterning. In one exemplary process, Figures 21D-21J illustrate cross-sectional views of various operations in a process for patterning metal line ends for back-end-of-the-line (BEOL) interconnects, according to embodiments of the present invention.

21D , a method for fabricating a metallization layer for interconnecting semiconductor dies includes forming a wire trench 2128 in an upper portion (above a lower portion 2130) of an interlayer dielectric (ILD) material layer 2126 formed above a lower metallization layer 2120. The lower metallization layer 2120 includes a metal wire 2122 disposed in a dielectric layer 2124.

21E , via trenches 2132A and 2132B are formed in the lower portion 2130 of the ILD material layer 2126 to form a patterned lower portion 2130′ of the ILD material layer 2126. As an exemplary embodiment, via trench 2132A exposes two metal lines 2122 of the underlying metallization layer 2120, while via trench 2132B exposes one metal line 2122 of the underlying metallization layer 2120.

21F , a sacrificial material 2134 (e.g., a matrix material) is formed over the ILD material layer (portion 2130′ shown in FIG. 21F ) and in line trenches 2128 and via trenches 2132A and 2132B. In one embodiment, a patterned hard mask layer 2136 is formed over the sacrificial material 2134, as depicted in FIG. 21F .

21G , the sacrificial material 2134 is patterned to form an opening (the left-hand opening in FIG. 21G ) that exposes a portion of the lower metallization layer 2120 between two metal lines 2122 of the lower metallization layer 2120 associated with the via trench 2132A in FIG. 21E . In the illustrated exemplary embodiment, the sacrificial material 2134 is further patterned to form an opening (the right-hand opening in FIG. 21G ) that exposes a portion of the patterned lower portion 2130′ of the ILD material layer adjacent to the via trench 2132B in FIG. 2E . In one embodiment, the sacrificial material 2134 is patterned by transferring the pattern of the patterned hard mask 2136 to the sacrificial material 2134 (by an etching process).

21H , the openings in the sacrificial material 2134 (now shown as patterned and filled with the sacrificial material 2134′) are filled with a dielectric material 2138. In one embodiment, the openings in the sacrificial material 2134 are filled with the dielectric material 2138 using a deposition process selected from the group consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD). In one embodiment, the openings in the sacrificial material 2134 are filled with the dielectric material 2138 comprising a first dielectric material. In one such embodiment, the ILD material layer 2126 includes a second dielectric material comprised of a different material than the first dielectric material. However, in another such embodiment, the ILD material layer 2126 is composed of a first dielectric material.

21I , the filled sacrificial material 2134′ is removed to provide dielectric plugs 2140A and 2140B. In the illustrated exemplary embodiment, dielectric plug 2140A is disposed on a portion of lower metallization layer 2120 between two metal lines 2122 of lower metallization layer 2120. Dielectric plug 2140A is adjacent to via trench 2132A and line trench 2128′, and (in the case shown in FIG. 21I ) is located between substantially symmetrical via trench 2132A and line trench 2128′. Dielectric plug 2140B is disposed on a portion of patterned lower portion 2130′ of ILD material layer 2126. Dielectric plug 2140 is adjacent to via trench 2142B and the corresponding line trench (to the right of dielectric plug 2140B). In one embodiment, the structure of FIG21H undergoes a planarization process to remove excess areas of dielectric material 2138 (areas above and above the surface on either side of the trench), to remove patterned hard mask 2136, and to reduce the height of sacrificial material 2134′ and the portion of dielectric material 2138 therein. Sacrificial material 2134′ is then removed using a selective wet or dry process etching technique.

Referring to FIG. 21J , line trench 2128′ and via trenches 2132A and 2132B are filled with a conductive material. In one embodiment, filling line trench 2128′ and via trenches 2132A and 2132B with the conductive material forms metal lines 2142 and conductive vias 2144 in patterned dielectric layer 2130′. In the exemplary embodiment, referring to plug 2140A, first metal line 2142 and first conductive via 2144 are directly adjacent to the left-hand sidewall of dielectric plug 2140A. Second metal line 2142 and second conductive via 2144 are directly adjacent to the right-hand sidewall of dielectric plug 2140A. Referring to plug 2140B, a first metal line 2142 is directly adjacent to the right-hand sidewall of dielectric plug 2140B, while a lower portion of patterned lower portion 2130' of the ILD layer is directly adjacent to a first conductive via 2144. However, on the left-hand side of dielectric plug 2140B, only metal line 2142 (and not an associated conductive via) is associated with dielectric plug 2140B. In one embodiment, the metal fill process is performed by depositing and then planarizing one or more metal layers over the structure of FIG. 2I .

Referring again to FIG. 21J , several different embodiments can be illustrated using diagrams. For example, in one embodiment, the structure of FIG. 21J represents the final metallization layer structure. In another embodiment, dielectric plugs 2140A and 2140B are removed to provide an air gap structure. In another embodiment, dielectric plugs 2140A and 2140B are replaced with another dielectric material. In yet another embodiment, dielectric plugs 2140A and 2140B may be sacrificial patterns that are ultimately transferred to another underlying interlayer dielectric material layer.

In an exemplary embodiment, referring again to FIG. 21J (and previous processing operations), the metallization layer for interconnecting the semiconductor die includes a metal line 2142 disposed in a trench 2128′ of an interlayer dielectric (ILD) material layer 2126. The ILD material layer 2126 is composed of a first dielectric material. A conductive via 2144 is disposed in the ILD 2126 material layer, below the metal line 2142 and electrically connected to the metal line 2142. A dielectric plug 2140A (or 2140B) is directly adjacent to the metal line 2142 and the conductive via 2144. A second metal line 2142 and the conductive via 2144 may also be directly adjacent to the dielectric plug (e.g., dielectric plug 2140A). In one embodiment, the dielectric plug 2140A (or 2140B) is composed of a second dielectric material different from the first dielectric material.

It should be understood that filling the openings of the sacrificial material 2134 with dielectric material may result in the formation of a seam in the dielectric material approximately at the center of the resulting dielectric plug. For example, FIG. 21K illustrates a cross-sectional view of a metallization layer of an interconnect structure for a semiconductor die including a dielectric terminal or plug having a seam therein, according to an embodiment of the present invention.

21K , the metallization layer of the semiconductor die interconnect structure includes a metal line 2140 disposed in a trench (shown as lower portion 2130′) of an interlayer dielectric (ILD) material layer. Conductive vias 2144 are disposed in the ILD material layer 2130′, below and electrically connected to metal line 2142. Dielectric plugs 2152A and 2152B are directly adjacent to metal line 2142 and conductive vias 2144. Dielectric plugs 2152A and 2152B each include a seam 2150 approximately centered within the dielectric plug, which may facilitate deposition of the dielectric plug by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

It should be understood that a termination or plug may be associated with a metal line that does not have an underlying via immediately adjacent to the dielectric plug. For example, FIG. 21L illustrates a cross-sectional view of a metallization layer of an interconnect structure for a semiconductor die that includes a dielectric termination or plug that does not immediately adjacent to a conductive via, according to an embodiment of the present invention. Referring to FIG. 21L , dielectric plug 2152 is associated with a metal line 2142 that does not have an underlying via (e.g., via 2144) immediately adjacent to dielectric plug 2152 (and above an associated patterned dielectric layer 2154′).

The resulting structure (such as that described in connection with FIG. 21J , FIG. 21K , or FIG. 21L ) can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 21J , FIG. 21K , or FIG. 21L can represent the final metal interconnect layer in an integrated circuit. In one embodiment, variations due to conventional lithography/damascene patterning (which must otherwise be accommodated) are mitigated for the resulting structure described herein. It should also be understood that the dielectric layer can be removed in subsequent manufacturing operations to provide air gaps between the resulting metal lines.

According to embodiments of the present invention, self-aligned etching of preformed vias and plugs is described. One or more embodiments described herein relate to self-aligned via and plug patterning. The self-aligned aspect of the process described herein may be based on a directed self-polymerization (DSA) mechanism, as described in more detail below. However, it should be understood that selective growth mechanisms may be utilized in place of (or in combination with) DSA-based approaches. In one embodiment, the process described herein enables the implementation of self-aligned metallization for back-end feature fabrication.

Embodiments described herein may involve a self-aligned isotropic etch process for preforming vias or plugs (or both). For example, the process scheme may involve preforming every possible via and plug in a metallization layer (such as a back-end metallization layer of a semiconductor structure). Photolithography is then used to select specific via and/or plug locations to be opened/closed (e.g., saved/removed). Implementations of the embodiments described herein may involve using this etch scheme to form all vias/plugs in a photobucket configuration for each corresponding via/metal layer in a metallization stack. As will be understood, the vias may be formed in a different layer than the plugs are formed (eg, the latter being formed in a metal line layer that is vertically between the via layers), or the plugs and vias may be formed in the same layer.

One or more embodiments described herein provide a more efficient approach to patterning by maximizing the overlap process window, minimizing the size and shape of the required pattern, and increasing the efficiency of the lithography process used to pattern the holes or plugs. In more specific embodiments, the patterns used to open the pre-formed vias or plug locations can be formed to be quite small, enabling an increase in the overlap tolerance of the lithography process. Pattern features can be made of uniform size, which can reduce the scan time of direct write electron beams and/or the optical proximity correction (OPC) complexity of optical lithography. Pattern features can also be formed to be shallow, which can improve patterning resolution. The subsequent etch process can be an isotropic chemical selective etch. This etch process reduces the profile and critical dimensions associated with dry etching and alleviates the anisotropy issues typically associated with dry etching. This etch process is also much less expensive (from an equipment and throughput perspective) compared to other selective removal methods.

As an example general processing scheme, Figures 22A-22G illustrate portions of an integrated circuit layer representing various operations in a method involving self-aligned isotropic etching of preformed via or plug locations, according to an embodiment of the present invention. In each illustration of each of the operations, a plan view is shown on the left, while a corresponding cross-sectional view is shown on the right. These views will be referred to herein as corresponding cross-sectional views and plan views.

22A illustrates a plan view and corresponding cross-sectional view (taken along the a-a' axis) of a starting structure following pre-patterning of holes/trench 2204 in a substrate or layer 2202. In one embodiment, substrate or layer 2202 is an interlayer dielectric (ILD) material layer.

Although not depicted for simplicity, it should be understood that the holes/trench 2204 can expose underlying features, such as underlying metal lines. Furthermore, in one embodiment, the starting structure can be patterned with a grating pattern having holes/trench 2204 spaced at a constant pitch and having a constant width. The pattern can be fabricated, for example, by halving the pitch, or by quartering the pitch, etc. In the case where a via layer is fabricated, some of the holes/trench 2204 can be associated with underlying lower-level metallization lines.

FIG22B illustrates a plan view and corresponding cross-sectional view (taken along the b-b' axis) of the structure of FIG22A after filling the hole/trench 2204 with a sacrificial or permanent placeholder material 2206. In the case of using a permanent placeholder material, an ILD material can be used to fill the hole/trench 2204. In the case of using a sacrificial placeholder material, more flexibility in design options is provided. For example, in one embodiment, a material that would not otherwise be suitable for retention in the final structure, such as a structurally weak polymer or soft photoresist, can be used. 22B, the formation of a small recess 2208 of the sacrificial or permanent placeholder material 2206 in the hole/trench 2204 may be included to assist in subsequent processing. In one embodiment, the sacrificial or permanent placeholder material 2206 is a spin-on dielectric material.

FIG22C illustrates a plan view and corresponding cross-sectional view (taken along the c-c' axis) of the structure of FIG22B following the formation of patterned layer 2210. In one embodiment, patterned layer 2210 is a photosensitive material, such as a positive-tone photoresist layer. In another embodiment, patterned layer 2210 is an anti-reflective coating material. In one embodiment, patterned layer 2210 comprises a stack of material layers, including one or more photosensitive material layers and/or one or more anti-reflective coating material layers.

FIG22D illustrates a plan view and corresponding cross-sectional view (taken along the d-d' axis) of the structure of FIG22C after patterning the patterned layer 2210 to form an opening 2212 in the patterned layer 2210. Referring to FIG22D, the opening 2212 exposes the underlying portion of the sacrificial or permanent placeholder material 2206. In particular, the opening 2212 exposes the underlying portion of the sacrificial or permanent placeholder material 2206 only above the hole/trench 2204 where a via or plug is selected to be formed. In one embodiment, the opening 2212 in the patterned layer 2210 is substantially smaller than the exposed hole/trench 2204. As briefly described above, the formation of openings 2212 that are relatively smaller than the exposed holes/trench 2204 provides significantly increased tolerance to misalignment issues. In one embodiment, the patterned layer 2210 is a photosensitive material, and the openings 2212 are formed by a lithography process, such as a positive-tone lithography process.

FIG22E illustrates a plan view and corresponding cross-sectional view (taken along the e-e' axis) of the structure of FIG22D following removal of the sacrificial or permanent placeholder material 2206 in the locations exposed by the openings 2212 to form re-exposed holes/trench 2214. In one embodiment, the sacrificial or permanent placeholder material 2206 is removed by an isotropic etching process. In one such embodiment, the isotropic etching process involves the application of a wet etchant. The wet etchant is passed through the openings 2212 to access and etch the sacrificial or permanent placeholder material 2206. The etching process is isotropic in that material not exposed by the opening 2212 (but accessible through the opening 2212) is etched to selectively form re-exposed holes/trench 2214 in the desired locations for via or plug formation. In one embodiment, the wet etching process etches the sacrificial or permanent placeholder material 2206 without etching (or not substantially etching) the patterned layer 2210.

In one embodiment, the sacrificial or permanent placeholder material 2206 is a spin-on carbon hard mask material, and the etching process is a TMAH-based etching process. In another embodiment, the sacrificial or permanent placeholder material 2206 is a spin-on bottom antireflective coating (BARC) material, and the etching process is a TMAH-based etching process. In another embodiment, the sacrificial or permanent placeholder material 2206 is a spin-on bottom glass material, and the etching process is a wet etching process based on an organic solvent, acid, or base. In another embodiment, the sacrificial or permanent placeholder material 2206 is a spin-on metal oxide material, and the etching process is a wet etching process based on commercially available cleaning chemicals. In another embodiment, the sacrificial or permanent placeholder material 2206 is a CVD carbon material, and the etching process is an oxygen plasma ash based etching process.

FIG22F illustrates a plan view and corresponding cross-sectional view (taken along the f-f' axis) of the structure of FIG22E following removal of the patterned layer 2210. In one embodiment, the patterned layer 2210 is a photoresist layer, and the photoresist layer is removed by a wet stripping or plasma ashing process. The removal of the patterned layer 2210 completely exposes the re-exposure hole/trench 2214.

FIG22G illustrates a plan view and corresponding cross-sectional view (taken along the g-g' axis) of the structure of FIG22F , following the filling of the re-exposed hole/trench 2214 with a material layer 2216 and subsequent planarization. In one embodiment, material layer 2216 is used to form a plug and is a permanent ILD material. In another embodiment, material layer 116 is used to form a conductive via and is a metal fill layer. In such an embodiment, the metal fill layer is a single material layer or formed from multiple layers, including a conductive liner layer and a fill layer. Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) can be used to form this metal fill layer. In one embodiment, the metal fill layer is composed of a conductive material such as (but not limited to) Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au, or alloys thereof. If the material layer 116 is planarized (following deposition), a chemical mechanical polishing process can be used.

In one embodiment, material layer 2216 is a material suitable for forming conductive vias. In one such embodiment, sacrificial or permanent placeholder material 2206 is a permanent placeholder material, such as a permanent ILD material. In another such embodiment, sacrificial or permanent placeholder material 2206 is a sacrificial placeholder material that is subsequently removed and replaced with a material, such as a permanent ILD material. In another embodiment, material layer 2216 is a material suitable for forming dielectric plugs. In one such embodiment, sacrificial or permanent placeholder material 2206 is a sacrificial placeholder material that is subsequently removed or partially removed to enable metal line formation.

It should be understood that the resulting structure of FIG. 22G can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 22G may represent the final metal interconnect layer in an integrated circuit. Furthermore, it should be understood that the above example does not include etch stop or metal capping layers in the diagram, which may be required for patterning. However, for clarity of understanding, these layers are not included in the diagram as they do not affect the overall concept.

In another aspect, embodiments relate to a process flow for performing isotropic dry etching (in conjunction with a hole reduction process). In one such embodiment, a patterning scheme provides pinhole patterning in a mask layer, followed by filling all via locations with an organic polymer. As an example processing scheme, Figures 22H-22J illustrate oblique cross-sectional views of a portion of an integrated circuit layer, illustrating various operations in a method involving self-aligned isotropic etching of preformed via locations, according to an embodiment of the present invention.

FIG22H illustrates the starting structure after filling all possible via locations with placeholder material. Referring to FIG22H , a metallization layer 2252 (such as an ILD layer of the metallization layer) is formed over a substrate (not shown) and includes a plurality of metal lines 2254 therein. ILD material (which may be two or more different ILD materials 2256 and 2258) surrounds the locations where vias may be formed. Sacrificial placeholder material 2260 occupies the locations where all possible vias may be formed over metal lines 2252. A mask layer 2262 (such as a thin low-temperature oxide mask layer) is formed over the underlying structure. It should be understood that the sacrificial placeholder material 2260 does not appear above adjacent features, which can be accomplished by deposition and planarization or recessing processes.

FIG22I illustrates the structure of FIG22H after patterning the mask layer 2262 to form openings 2264 in the mask layer 2262. Referring to FIG22I, the openings 2264 expose the underlying portion of the sacrificial placeholder material 2260. In particular, the openings 2264 expose the underlying portion of the sacrificial placeholder material 2260 only at the locations where the vias are selected to be formed. In one embodiment, the openings 2264 in the mask layer 2262 are substantially smaller than the exposed sacrificial placeholder material 2260. As briefly described above, the formation of openings 2264 that are relatively smaller than the exposed sacrificial placeholder material 2260 provides significantly increased tolerance to misalignment issues. This process effectively shrinks the via locations to a pinhole size, allowing for the selection and patterning of the actual via locations. In one embodiment, the mask layer 2262 is patterned to form the openings 2262 by first forming and patterning a photosensitive material on the mask layer 2262 using a lithography process (e.g., a positive-tone lithography process), and then patterning the mask layer 2262 using an etching process.

FIG22J illustrates the structure of FIG22I after the sacrificial placeholder material 2260 is removed from the locations exposed by the openings 2264 to form exposed via locations 2266. In one embodiment, the sacrificial placeholder material 2260 is removed from the via locations 2266 by an isotropic etching process. In one such embodiment, the sacrificial placeholder material 2260 is an organic polymer, and the isotropic etching process is an isotropic plasma ash (oxygen plasma) or wet clean process.

Referring again to FIG. 22J , it should be understood that subsequent processing may involve removing mask layer 2262 and filling hole/trench 2266 with conductive via material. Simultaneously, the remaining sacrificial placeholder material 2260 not exposed by opening 2264 (i.e., not selected as a via location) may be replaced with permanent ILD material. The resulting structure may then be used as a foundation for forming subsequent metal lines/vias and ILD layers. Alternatively, the resulting structure may represent the final metal interconnect layer in an integrated circuit.

According to one or more embodiments of the present invention, as described above, the methods described herein may be based on the use of so-called "photobuckets," wherein each possible feature (e.g., a via or plug) is pre-patterned into a substrate. A photoresist is then filled into the patterned features and lithography is used only to select selected vias for via opening formation. The photobucket approach may allow for larger critical dimensions (CDs) and/or errors in overlap while retaining the ability to select the vias or plugs of interest. The lithography methods used to select a particular photobucket may include (but are not limited to) 193 nm immersion lithography (i193), extreme ultraviolet (EUV), and/or electron beam direct write (EBDW) lithography.

In summary, according to one or more embodiments of the present invention, a DSA approach or subtractive approach is made photosensitive. In one view, a form of photobucket is achieved in which lithography constraints can be relaxed and misalignment tolerances can be high because the photobucket is surrounded by non-photodegradable material. Furthermore, in one embodiment, instead of exposing to (for example) 30mJ/ ^cm2 , such a photobucket can be exposed to (for example) 3mJ/ ^cm2 . Normally this would result in very poor CD control and roughness. But in this case, the CD and roughness control will be defined by the photobucket geometry, which can be extremely well controlled and defined. Therefore, such a photobucket approach can be used to prevent imaging/dose trade-offs, which limit the yield of next generation lithography processes. In one embodiment, the photobucket material that is not selected to be removed is ultimately retained as a permanent ILD portion in the semiconductor structure. In another embodiment, the photobucket material that is not selected to be removed is ultimately exchanged for a permanent ILD portion in the semiconductor structure.

In one embodiment, the photobucket "ILD" composition is generally very different from a standard ILD and (in one embodiment) is highly self-aligned in two directions. More generally, in one embodiment, the term photobucket as used herein refers to the use of an ultrafast photoresist or electron beam resist or other photosensitive material, as formed in an etched opening. In such an embodiment, a thermal backfill of the polymer into the opening is used subsequent to the spin-on application. In one embodiment, the fast photoresist is made by removing an inhibitor from an existing photoresist material. In another embodiment, the photobucket is formed by an etch-back process and/or a lithography/reduction/etch process. It should be understood that the photobucket does not need to be filled with actual photoresist, as long as the material acts as a photosensitive switch. In one embodiment, lithography is used to expose the corresponding photobucket that is selected for removal. However, lithography constraints can be relaxed and the misalignment tolerance can be high because the photobucket is surrounded by non-photodegradable material. In one embodiment, the photobucket is exposed to extreme ultraviolet (EUV) light to expose the photobucket, wherein in a specific embodiment, EUV is in the range of 5-15 nanometers. Although many of the embodiments described herein relate to photobucket materials based on polymers, in other embodiments, photobucket materials based on nanoparticles are similarly implemented.

According to an embodiment of the present invention, a photobucket approach is described. One or more embodiments described herein relate to a subtractive approach for self-aligned via and plug patterning, and the resulting structures. In one embodiment, the process described herein is to enable the implementation of self-aligned metallization for back-end feature fabrication. Overlap issues expected for next generation via and plug patterning can be addressed by one or more of the approaches described herein. More specifically, one or more embodiments described herein involve using a subtractive method to pre-form each via and plug using etched trenches. An additional operation is then used to select which vias and plugs to retain. These operations can be illustrated using photobuckets, although a more traditional resist exposure and ILD backfill approach can also be used to perform the selection process.

In the first form, a first via and a second plug approach are used. As an example, Figures 23A-23L illustrate portions of an integrated circuit layer representing various operations in a method for subtractive self-aligned via and plug patterning, according to an embodiment of the present invention. In each of the figures depicting each of the described operations, cross-sectional and/or oblique views are shown. These views will be referred to herein as the corresponding cross-sectional and oblique views.

FIG23A illustrates a cross-sectional view of a starting structure 2300 after deposition (but before patterning) of a first hard mask material layer 2304 formed on an interlayer dielectric (ILD) layer 2302, according to an embodiment of the present invention. Referring to FIG23A , a patterned mask 2306 has spacers 2308 formed on or above (along the sidewalls of) the first hard mask material layer 2304.

FIG23B illustrates the structure of FIG23A following patterning of the first hard mask layer by pitch doubling, according to an embodiment of the present invention. Referring to FIG23B , the patterned mask 2306 is removed and the resulting pattern of the spacers 2308 is transferred (e.g., by an etching process) to the first hard mask material layer 2304 to form a first patterned hard mask 2310. In one such embodiment, the first patterned hard mask 2310 is formed with a grating pattern, as depicted in FIG23B . In one embodiment, the grating structure of the first patterned hard mask 2310 is a fine-pitch grating structure. In this particular embodiment, the fine pitch cannot be directly achieved by conventional lithography. For example, a pattern based on conventional lithography can be first formed (mask 2306), but the pitch can be halved by patterning using a spacer mask, as depicted in Figures 23A and 23B. Furthermore, although not shown, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern of the first patterned hard mask 2310 of Figure 23B can have hard mask lines separated by a constant pitch and having a constant width.

FIG23C illustrates the structure of FIG23B following the formation of a second patterned hard mask, according to an embodiment of the present invention. Referring to FIG23C , a second patterned hard mask 2312 is formed to intersect with the first patterned hard mask 2310. In one such embodiment, the second patterned hard mask 2312 is formed by depositing a second hard mask material layer having a different composition than the first hard mask material layer 2304. The second hard mask material layer is then planarized (e.g., by chemical mechanical polishing (CMP)) to provide the second patterned hard mask 2312.

FIG23D illustrates the structure of FIG23C subsequent to deposition of a hard mask capping layer, according to an embodiment of the present invention. Referring to FIG23D , a hard mask capping layer 2314 is formed on the first patterned hard mask 2310 and the first patterned hard mask 2312. In one such embodiment, the material composition and etch selectivity of the hard mask capping layer 2314 are different from those of the first patterned hard mask 2310 and the first patterned hard mask 2312.

FIG23E illustrates the structure of FIG23D subsequent to deposition of a hard mask capping layer, according to an embodiment of the present invention. Referring to FIG23E , a patterned hard mask capping layer 2314 is formed on the first patterned hard mask 2310 and the first patterned hard mask 2312. In one such embodiment, the patterned hard mask capping layer 2314 is formed with a grating pattern that is orthogonal to the grating pattern of the first patterned hard mask 2310 and the first patterned hard mask 2312, as shown in FIG23E . In one embodiment, the grating structure formed by the patterned hard mask capping layer 2314 is a fine-pitch grating structure. In this embodiment, a tight pitch cannot be achieved directly through conventional lithography. For example, a pattern based on conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Furthermore, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern of the patterned hard mask capping layer 2314 of FIG. 23E can have hard mask lines separated by a constant pitch and having a constant width.

FIG23F illustrates the structure of FIG23E following further patterning of the first patterned hard mask and subsequent formation of a plurality of photobuckets, according to an embodiment of the present invention. Referring to FIG23F, the first patterned hard mask 2310 is further patterned to form a first patterned hard mask 2316 using the patterned hard mask capping layer 2314 as a mask. The second patterned hard mask 2312 is not further patterned in this process. Thereafter, the patterned hard mask capping layer 2314 is removed, and photobuckets 2318 are formed in the resulting openings above the ILD layer 2302. The photobuckets 2318 (at this stage) represent all possible via locations in the resulting metallization layer.

FIG23G illustrates the structure of FIG23F after exposure and development of the photobucket to leave the selected via location, and subsequent etching of the via opening into the underlying ILD, according to an embodiment of the present invention. Referring to FIG23G, the selected photobucket 2318 is exposed and removed to provide the selected via location 2320. The via location 2320 receives a selective etching process (such as a selective plasma etching process) to extend the via opening into the underlying ILD layer 2302 to form a patterned ILD layer 2302'. The etching is selective to: the remaining photobucket 2318, the first patterned hard mask 2316, and the second patterned hard mask 2312.

Figure 23H illustrates the structure of Figure 23G following the removal of the remaining photobuckets, the subsequent formation of a hard mask material, and the subsequent formation of a second plurality of photobuckets, according to an embodiment of the present invention. Referring to Figure 23H, the remaining photobuckets are removed, for example, by a selective etching process. All openings formed (for example, the openings formed when the photobuckets 2318 and the through-hole locations 2320 are removed) are then filled with a hard mask material 2322, such as a carbon-based hard mask material. Thereafter, the first patterned hard mask 2316 is removed (for example, by a selective etching process), and the resulting openings are filled with a second plurality of photobuckets 2324. The photobuckets 2324 (at this stage) represent all possible plug locations in the resulting metallization layer. It should be understood that the second patterned hard mask 2312 is not further patterned at this stage in the process.

FIG23I illustrates the structure of FIG23H after the plug position selection, according to an embodiment of the present invention. Referring to FIG23I, the photobucket 2324 from FIG23H is removed from the position 2326 where the plug will not be formed. The photobucket 2324 is retained in the position selected to form the plug. In one embodiment, in order to form the position 2326 where the plug will not be formed, lithography is used to expose the corresponding photobucket 2324. The exposed photobucket can then be removed by a developer.

FIG23J illustrates the structure of FIG23I subsequent to the removal of the most recently formed hard mask from the via and line locations, in accordance with an embodiment of the present invention. Referring to FIG23J , the hard mask material 2322 depicted in FIG23I is removed. In one such embodiment, the hard mask material 2322 is a carbon-based hard mask material and is removed using a plasma ash process. As shown, the remaining features include the patterned ILD layer 2302′, the photobucket 2324 retained for plug formation, and the via opening 2328. Although not shown, it should be understood that in one embodiment, the second hard mask layer 2312 is also retained at this stage.

FIG23K illustrates the structure of FIG23J following the recessing of the patterned ILD layer in locations not protected by the plug-forming photobucket, according to an embodiment of the present invention. Referring to FIG23K , portions of the patterned ILD layer 2302′ not protected by the photobucket 2324 are recessed to provide metal line openings 2330, in addition to via openings 2328.

Figure 23L illustrates the structure of Figure 23K following metal fill, in accordance with an embodiment of the present invention. Referring to Figure 23L, metallization 2332 is formed in openings 2328 and 2332. In one such embodiment, metallization 2332 is formed by a metal fill and polish back process. Referring to the left-hand portion of Figure 23L, the structure is shown to include a lower portion including a patterned ILD layer 2302' having metal lines and vias (collectively shown as 2332) formed therein. An upper region 2334 of the structure includes a second patterned hard mask 2312 and a remaining (plug location) photobucket 2324. In one embodiment, the upper region 2334 is removed (e.g., by CMP or etch back) prior to subsequent fabrication. However, in an alternative embodiment, the upper region 2334 is retained in the final structure.

The structure of Figure 23L can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 23L can represent the last metal interconnect layer in an integrated circuit. It should be understood that the above-mentioned process operations can be performed in an alternative order, not every operation needs to be performed and/or additional process operations can be performed. Referring again to Figure 23L, self-aligned manufacturing by subtractive methods can be completed at this stage. The next layer manufactured in a similar manner may require another complete process start-up. Alternatively, other methods can be used at this stage to provide additional interconnect layers, such as traditional dual or single metal inlay methods.

In the second form, a plug-first, via-second approach is used. As an example, Figures 23M-23S illustrate portions of an integrated circuit layer representing various operations in a method for subtractive self-aligned via and plug patterning, according to another embodiment of the present invention. In each illustration of each of the operations, a plan view is shown at the top, while a corresponding cross-sectional view is shown at the bottom. These views will be referred to herein as the corresponding cross-sectional view and plan view.

FIG23M illustrates a plan view and corresponding cross-sectional views of a starting orthogonal grating formed on a substrate 2351, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a' and b-b', respectively, the starting grating structure 2350 includes a grating ILD layer 2352 having a first hard mask layer 2354 disposed thereon. A second hard mask layer 2356 is disposed on the first hard mask layer 2354 and is patterned to have a grating structure orthogonal to the underlying grating structure. Additionally, an opening 2358 remains between the grating structure of the second hard mask layer 2356 and the underlying grating formed by the ILD layer 2352 and the first hard mask layer 2354 .

FIG23N illustrates a plan view and corresponding cross-sectional views of the structure of FIG23M following the opening filling and etching back, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, the opening 2358 of FIG23M is filled with a dielectric layer 2360 (e.g., a silicon oxide layer). This dielectric layer 2360 can be formed by depositing an oxide film, such as by chemical vapor deposition (CVD), high-density plasma deposition (HDP), or dielectric spin-on coating. The deposited material may need to be etched back to achieve the relative height shown in FIG23N, leaving an upper opening 2358′.

FIG23O illustrates a plan view and corresponding cross-sectional view of the structure of FIG23N following the filling, exposure, and development of the photobucket to leave the selected plug position, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (a) and (b) taken along axis a-a' and b-b', respectively, the photobucket is formed in the opening 2358' above FIG23N. Thereafter, most of the photobucket is exposed and removed. However, the selected photobucket 2362 is not exposed and therefore remains to provide the selected plug position, as shown in FIG23O.

FIG23P illustrates a plan view and corresponding cross-sectional view of the structure of FIG23O following removal of a portion of the dielectric layer 2360, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (a) and (b), taken along axes a-a' and b-b', respectively, the portion of the dielectric layer 2360 not covered by the photobucket 2362 is removed. However, the portion of the dielectric layer 2360 not covered by the photobucket 2362 remains in the structure of FIG23P. In one embodiment, the portion of the dielectric layer 2360 not covered by the photobucket 2362 is removed by a wet etching process.

FIG23Q illustrates a plan view and corresponding cross-sectional views of the structure of FIG23P after photobucket filling, exposure, and development to leave selected via locations, according to an embodiment of the present invention. Referring to the plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and b-b', respectively, photobuckets are formed in the openings formed by the removal of portions of dielectric layer 2360. Thereafter, selected photobuckets are exposed and removed to provide selected via locations 2364, as shown in FIG23Q.

FIG23R illustrates a plan view and corresponding cross-sectional views of the structure of FIG23Q after a via opening is etched into the underlying ILD layer, according to an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, via location 2364 of FIG23Q undergoes a selective etch process (e.g., a selective plasma etch process) to extend via opening 2364 to opening 2364′, which is formed into the underlying ILD layer 2352.

Figure 23S illustrates a plan view and corresponding cross-sectional view of the structure of Figure 23R following removal of the second hard mask layer and remaining photobucket material, according to an embodiment of the present invention. Referring to the plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and bb', respectively, the second hard mask layer 2356 and any remaining photobucket material (i.e., photobucket material that has not yet been exposed and developed) are removed. The removal is performed selectively with respect to all other remaining features. In one such embodiment, the second hard mask layer 2356 is a carbon-based hard mask material, and the removal is performed by an _O2 plasma ash process. Referring again to FIG. 23S , what remains at this stage is the ILD layer 2352 with the via opening 2364′ formed therein, and the portion of the dielectric layer 2360 reserved for the plug location (e.g., reserved by the overlying photobucket material). Thus, in one embodiment, the structure of FIG. 23S includes an ILD layer 2352 patterned with via openings (for subsequent metal fill) and a dielectric layer 2360 location for creating the plug. The remaining opening 2366 can be filled with metal to form a metal line. It should be understood that the hard mask 2354 can be removed.

Thus, once filled with metal interconnect material, the structure of FIG. 23S can then be used as a foundation for forming subsequent metal lines/vias and ILD layers. Alternatively, once filled with metal interconnect material, the structure of FIG. 23S can represent the final metal interconnect layer in an integrated circuit. Referring again to FIG. 23S , self-aligned fabrication using a subtractive approach can be accomplished at this stage. Fabricating the next layer in a similar manner may require another complete process start-up. Alternatively, other approaches can be used at this stage to provide additional interconnect layers, such as traditional dual or single damascene approaches.

It should be understood that the methods described in connection with Figures 23A-23L and 23M-23S are not necessarily implemented to form vias aligned with underlying metallization layers. Thus, in some contexts, these process schemes may be viewed as involving blind shots from a top-down direction directed at any underlying metallization layer. In a third form, alignment with the underlying metallization layer is provided in a subtractive manner. For example, Figures 24A-24I illustrate a portion of an integrated circuit layer representing various operations in a method for subtractive self-aligned plug patterning, according to another embodiment of the present invention. In each of the figures depicting each operation, an oblique angled three-dimensional cross-sectional view is provided.

FIG24A illustrates a starting point structure 2400 for a subtractive via and plug process following deep metal line fabrication, in accordance with an embodiment of the present invention. Referring to FIG24A , structure 2400 includes metal lines 2402 with intermediate interlayer dielectric (ILD) lines 2404. It should also be understood that some of the lines 2402 may be associated with underlying vias for coupling to a previous interconnect layer. In one embodiment, the metal lines 2402 are formed by patterning trenches into the ILD material (e.g., the ILD material of line 2404). The trenches are then filled with metal and, if desired, planarized to the top of the ILD lines 2404. In one embodiment, the metal trench and fill process involves high-width features. For example, in one embodiment, the aspect ratio of the metal line height (h) to the metal line width (w) is approximately in the range of 5-10.

FIG24B illustrates the structure of FIG24A following recessing of the metal lines, according to an embodiment of the present invention. Referring to FIG24B , metal line 2402 is selectively recessed to provide first-level metal line 2406. Recessing is performed selectively for ILD line 2404. The recessing can be performed by etching using dry etching, wet etching, or a combination thereof. The degree of recessing can be determined by the target thickness of first-level metal line 2406 for use as a suitable conductive interconnect within the back-end-of-line (BEOL) interconnect structure.

Figure 24C illustrates the structure of Figure 24B following the formation of an interlayer dielectric (ILD) layer, according to an embodiment of the present invention. Referring to Figure 24C, an ILD material layer 2408 is deposited and (if necessary) planarized to a level above the recessed metal line 2406 and the ILD line 2404.

FIG24D illustrates the structure of FIG24C following deposition and patterning of a hard mask layer, according to an embodiment of the present invention. Referring to FIG24D , a hard mask layer 2410 is formed on the ILD layer 2408. In one such embodiment, the hard mask layer 2410 is formed with a grating pattern that is orthogonal to the grating pattern of the first-order metal lines 2406/ILD lines 2404, as shown in FIG24D . In one embodiment, the grating structure formed by the hard mask layer 2410 is a fine-pitch grating structure. In this embodiment, the fine pitch cannot be directly achieved through conventional lithography. For example, a pattern based on conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Furthermore, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern of the second hard mask layer 2410 of FIG. 24D can have hard mask lines separated by a constant pitch and having a constant width.

FIG24E illustrates the structure of FIG24D after trenches defined by the pattern of the hard mask of FIG24D are formed, according to an embodiment of the present invention. Referring to FIG24E , exposed areas of ILD layer 2408 (i.e., those not protected by 2410) are etched to form trenches 2412 and patterned ILD layer 2414. The etch stops on (and thus exposes) the top surfaces of first-level metal lines 2406 and ILD lines 2404.

FIG24F illustrates the structure of FIG24E after forming the photobuckets in all possible via locations, according to an embodiment of the present invention. Referring to FIG24F , photobuckets 2416 are formed in all possible via locations above the exposed portion of the recessed metal line 2406. In one embodiment, the photobuckets 2416 are formed to be substantially coplanar with the top surface of the ILD line 2404, as depicted in FIG24F . Furthermore, referring again to FIG24F , the hard mask layer 2410 can be removed from the patterned ILD layer 2414.

FIG24G illustrates the structure of FIG24F after selecting a via location, according to an embodiment of the present invention. Referring to FIG24G , when selecting a via location 2418, the photobucket 2416 from FIG24F is removed. In locations not selected for via formation, the photobucket 2416 is retained. In one embodiment, to form the via location 2418, lithography is used to expose the corresponding photobucket 2416. The exposed photobucket can then be removed using a developer.

FIG24H illustrates the structure of FIG24G after the conversion of the remaining photobucket to permanent ILD material, according to an embodiment of the present invention. Referring to FIG24H , the material of photobucket 2416 is modified (e.g., by crosslinking during a bake operation) in position to form final ILD material 2420. In one such embodiment, the crosslinking provides solubility switching during bake. The resulting, crosslinked material has inter-dielectric properties and can therefore be retained in the final metallization structure.

Referring again to FIG. 24H , in one embodiment, the resulting structure includes up to three different dielectric material regions (ILD lines 2404 + ILD lines 2414 + cross-linked photobuckets 2420) within a single plane 2450 of the metallization structure. In this embodiment, two or all of the ILD lines 2404, ILD lines 2414, and cross-linked photobuckets 2420 are composed of the same material. In another embodiment, the ILD lines 2404, ILD lines 2414, and cross-linked photobuckets 2420 are composed of different ILD materials. In either case, in a particular embodiment, differences such as vertical seams between the material of ILD line 2404 and ILD line 2414 (e.g., seam 2497) and/or vertical seams between ILD line 2404 and the cross-linked light bucket 2420 (e.g., seam 2498) and/or vertical seams between ILD line 2414 and the cross-linked light bucket 2420 (e.g., seam 2499) may be observed in the final structure.

FIG24I illustrates the structure of FIG24H subsequent to metal line and via formation, according to an embodiment of the present invention. Referring to FIG24I, metal line 2422 and via 2424 are formed over the metal fill of the opening of FIG24H. Metal line 2422 is coupled to underlying metal line 2406 via via 2424. In one embodiment, the opening is filled with a metal damascene or bottom-up fill to provide the structure shown in FIG24I. Thus, the metal (e.g., copper and associated barrier and seed layers) deposited to form the metal lines and vias in the manner described above may be that typically used in standard back-end-of-line (BEOL) processing. In one embodiment, the ILD lines 2414 may be removed in subsequent manufacturing operations to provide air gaps between the resulting metal lines 2424.

The structure of FIG24I can then be used as a foundation for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG24I may represent the final metal interconnect layer in an integrated circuit. Referring again to FIG24I , self-aligned fabrication using a subtractive approach can be performed at this stage. Fabricating the next layer in a similar manner may require another complete process start-up. Alternatively, other methods may be used at this stage to provide additional interconnect layers, such as traditional dual or single damascene methods.

According to embodiments of the present invention, multi-color photobuckets are described. One or more embodiments described herein relate to using multi-color photobuckets as a method for processing plug and via fabrication below the lithography pitch limit. One or more embodiments described herein relate to subtractive methods for self-aligned via and plug patterning, and the resulting structures. In one embodiment, the process described herein enables the implementation of self-aligned metallization for back-end process feature fabrication. Overlap issues anticipated for next generation via and plug patterning can be addressed by one or more of the methods described herein.

In exemplary embodiments, the approach described below is based on an approach using so-called photobuckets, where each possible feature (e.g., a via) is re-patterned into the substrate. Then, a photoresist is filled into the patterned features and lithography is used only to select selected vias for via opening formation. In a specific embodiment described below, lithography is used to define relatively large holes on a plurality of "multi-color photobuckets," which can then be opened by bulk exposure of a specific wavelength. The multi-color photobucket approach allows for larger critical dimensions (CDs) and/or errors in overlap, while retaining the ability to select the vias of interest. In one such embodiment, trenches are used to contain the resist itself, and a plurality of wavelengths of bulk exposure are used to selectively open the vias of interest.

More specifically, one or more embodiments described herein involve using a subtractive method to pre-form each via or via opening using an etched trench. An additional operation is then used to select which vias and plugs remain. These operations can be performed using a photobucket, although a more traditional resist exposure and ILD backfill approach can also be used to perform the selection process.

In one example, a self-aligned via opening method can be used. As an example process, Figures 25A-25H illustrate portions of an integrated circuit layer representing various operations in a method for subtractive self-aligned via patterning using multi-color photobuckets, according to an embodiment of the present invention. A cross-sectional view is shown in each of the figures for each of the described operations.

FIG25A illustrates a cross-sectional view of a starting structure 2500 after deposition (but before patterning) of a first hard mask material layer 2504 formed on an interlayer dielectric (ILD) layer 2502, according to an embodiment of the present invention. Referring to FIG25A , a patterned mask 2506 has spacers 2508 formed on or above (along the sidewalls of) the first hard mask material layer 2504.

FIG25B illustrates the structure of FIG25A following a first patterning of the first hard mask layer and subsequent filling with the first color bucket, according to an embodiment of the present invention. Referring to FIG25B , patterned mask 2506 and corresponding spacers 2508 are used together as a mask during an etch to form trenches 2510 through first hard mask material layer 2504 and partially into ILD layer 2502. Trench 2510 is then filled with the first color bucket 2512.

FIG25C illustrates the structure of FIG25B after a second patterning of the first hard mask layer and subsequent filling with a second color bucket, according to an embodiment of the present invention. Referring to FIG25C , patterned mask 2506 is removed and a second plurality of trenches 2514 are etched through first hard mask material layer 2504 and partially into ILD layer 2502, between spacers 2508. Thereafter, trenches 2514 are filled with a second color bucket material layer 2516.

Referring again to FIG. 25C , the negative pattern of spacers 2508 is thus transferred (e.g., by two etching processes that form trenches 2510 and 2514) to the first hard mask material layer 2504. In one such embodiment, spacers 2508 (and therefore trenches 2510 and 2514) are formed in a grating pattern, as depicted in FIG. 25C . In one embodiment, the grating pattern is a close-pitch grating pattern. In this particular embodiment, the close pitch cannot be directly achieved using conventional lithography. For example, a pattern based on conventional lithography can first be defined on mask 2506, but the pitch can be halved by patterning the mask using negative spacers, as depicted in FIG. 25A-25C . Even though not shown, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating patterns of the light buckets 2512 and 2516 are (collectively) separated by a constant pitch and have a constant width.

FIG25D illustrates the structure of FIG25C after planarization to isolate the first and second color buckets from each other, according to an embodiment of the present invention. Referring to FIG25D , the top portion of the second color bucket material layer 2516 and the spacer 2508 is planarized, for example, by chemical mechanical polishing (CMP), until the top surface of the first color bucket 2512 is exposed, forming a discrete second color bucket 2518 from the bucket material layer 2516. In one embodiment, the combination of the first color bucket 2512 and the second color bucket 2518 represents all possible via locations in the subsequently formed metallization structure.

Figure 25E illustrates the structure of Figure 25D following exposure and development of the first color light bucket to leave the selected through-hole location, according to an embodiment of the present invention. Referring to Figure 25E, a second hard mask 2520 is formed and patterned on the structure of Figure 25D. The patterned second hard mask 2520 reveals the selected first color light bucket 2512A. The selected light bucket 2512A is exposed to light and removed (i.e., developed) to provide the selected through-hole opening 2513A. It should be understood that the description herein of forming and patterning a hard mask layer involves (in one embodiment) a mask being formed on a later covering hard mask. Mask formation may involve the use of one or more layers suitable for lithography processing. When one or more photolithography layers are patterned, the pattern is transferred to the hard mask layer by an etching process to provide a patterned hard mask layer.

Referring again to FIG. 25E , it may not be possible to reveal only the selected light bucket 2512A when the second hard mask layer 2520 is patterned. For example, one or more adjacent (or nearby) second color light buckets 2518 may also be revealed. These additionally revealed light buckets may not be the desired locations for the final through-hole formation. However, any revealed second color light bucket 2518 (in one embodiment) is not modified when exposed to the illumination of the group used to pattern the first color light bucket 2512. For example, in one embodiment, the first color light bucket 2512 is susceptible to a large red exposure 2521 and can be developed to remove the selection of the first color light bucket 2512, as shown in FIG. 25E . In this embodiment, the second color light bucket 2518 is not susceptible to red heavy exposure and, therefore, cannot be developed and removed even if it is exposed during red heavy exposure, as shown in Figure 25E. In one embodiment, by having adjacent light buckets with different exposure resistance, a larger pattern and/or deviation tolerance can be provided to relax the restrictions associated with patterning the second hard mask layer 2520.

FIG25F illustrates the structure of FIG25E following exposure and development of the second color light bucket to leave additional selected through-hole locations, according to an embodiment of the present invention. Referring to FIG25F, a third hard mask 2522 is formed and patterned on the structure of FIG25E. The third hard mask 2522 can also fill the selected through-hole opening 2513A, as depicted in FIG25F. The patterned third hard mask 2522 reveals the selected second color light buckets 2518A and 2518B. The selected light buckets 2518A and 2518B are exposed to light and removed (i.e., developed) to provide selected through-hole openings 2519A and 2519B, respectively.

Referring again to FIG. 25F , it may not be possible to reveal only the selected light buckets 2518A and 2518B when the third hard mask layer 2522 is patterned. For example, one or more adjacent (or nearby) first color light buckets 2512 may also be revealed. These additionally revealed light buckets may not be the desired locations for the final through-hole formation. However, any revealed first color light bucket 2512 (in one embodiment) is not modified when exposed to the illumination of the group used to pattern the second color light bucket 2518. For example, in one embodiment, the second color light bucket 2518 is susceptible to a green heavy exposure 2523 and can be developed to remove the selection of the second color light bucket 2518, as shown in FIG. 25F . In this embodiment, the first color light bucket 2512 is not susceptible to green heavy exposure and, therefore, cannot be developed and removed even if it is exposed during green heavy exposure, as shown in Figure 25F. In one embodiment, by having adjacent light buckets with different exposure resistance, a larger pattern and/or deviation tolerance can be provided to relax other restrictions associated with patterning the third hard mask layer 2522.

FIG25G illustrates the structure of FIG25F following removal of the third hard mask layer and etching to form via locations, according to an embodiment of the present invention. Referring to FIG25G , the third hard mask layer 2522 is removed. In one such embodiment, the third hard mask layer 2522 is a carbon-based hard mask layer and is removed by an ashing process. Next, the pattern of via openings 2519A, 2513A, and 2519B is subjected to a selective etching process (e.g., a selective plasma etching process) to extend the via openings deeper into the underlying ILD layer 2502, forming a via-patterned ILD layer 2502′ having via locations 2524. The etch is selective to the remaining photobuckets 2512 and 2518 and to the spacers 2508.

FIG25H illustrates the structure of FIG25G before metal filling, according to an embodiment of the present invention. Referring to FIG25H, all remaining first and second color light buckets 2512 and 2518 are removed. The remaining first and second color light buckets 2512 and 2518 can be removed directly, or can first be exposed and developed to enable removal. The removal of the remaining first and second color light buckets 2512 and 2518 provides metal line trenches 2526, portions of which are coupled to the through hole locations 2524 in the patterned ILD layer 2502'. Subsequent processes may include the removal of the spacers 2508 and the hard mask layer 2504, and the metal filling of the metal line trenches 2526 and the through hole locations 2504. In one such embodiment, the metallization is formed by a metal fill and polish back process.

The structure of Figure 25H (when metal-filled) can then be used as a foundation for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 25H (when metal-filled) can represent the final metal interconnect layer in an integrated circuit. Referring again to Figure 25H, self-aligned fabrication using a subtractive approach can be completed at this stage. The next layer fabricated in a similar manner may require another complete process start-up. Alternatively, other methods can be used at this stage to provide additional interconnect layers, such as traditional dual or single damascene approaches.

Referring again to Figures 25A-25H, several options can be considered for providing the first color bucket 2512 and the second color bucket 2518. For example, in one embodiment, two different positive-tone organic photoresists are used. It should be understood that in such an embodiment, materials with different chemical structures can be selected for the first color bucket 2512 and the second color bucket 2518 to allow different coating, photoactivation and development processes to be used. As an example embodiment, a traditional 193nm lithography polymethacrylate resist system is selected for the first color bucket 2512, and a traditional 248nm polystyrene photoresist system is selected for the second color bucket 2518. The significant chemical difference between these two types of resins allows two different organic casting solvents to be used; this may be necessary because the material of the second color bucket 2518 is coated with the existing material of the first color bucket 2512. The casting solvent used for the first color bucket 2512 is not limited; and for the second color bucket 2518, an alcohol solvent can be used because it can still dissolve the PHS material but not the less polar polymethacrylate.

The combination of a polymethacrylate resin as the material of the first color light bucket 2512 and a polyhydroxystyrene resin as the material of the second color light bucket 2518 can (in one embodiment) enable two different exposure wavelengths to be used. Typical 193nm lithography polymers are based on polymethacrylates with 193nm absorbing photoacid generators (PAGs) because the polymers do not absorb strongly at this wavelength. On the other hand, polyhydroxystyrene may not be suitable because it strongly absorbs 193nm and prevents the activation of the PAG throughout the film. Then, in one embodiment, the material of the first color light bucket 2512 can be selectively activated and developed in the presence of 193nm photons. To emphasize the light velocity difference between the first color bucket 2512 and the second color bucket 2518, factors such as 193nm PAG absorption, PAG loading, and photoacid intensity can be tuned for each. In addition, a strong 193nm absorber can be added to the second color bucket 2518 (or selectively deposited on top of the second color bucket 2518) to reduce PAG activation in the bulk film. Following exposure, in a specific embodiment, development of the first color bucket 2512 is selectively performed with a standard TMAH developer, wherein minimal development of the second color bucket 2518 will occur.

In one embodiment, in order to selectively remove the second color light bucket 2518 (in the presence of the first color light bucket 2512), a second lower energy wavelength is used that only activates the PAG in the second color light bucket 2518 but not in the first color light bucket 2512. This can be achieved in two ways. First, in one embodiment, PAGs with different absorption characteristics are used. For example, trialkyl coronium salts have extremely low absorption at wavelengths such as 248nm, while triaryl coronium has extremely high absorption. Therefore, selectivity is achieved by using triaryl coronium or other 248nm absorbing PAGs in the second color light bucket 2518 and using trialkyl coronium or other non-248nm absorbing PAGs in the first color light bucket 2512. Alternatively, a sensitizer may be incorporated into the second color bucket 2518 that absorbs low energy photons selectively in the second color bucket 2518 and transfers energy to the PAG without activation occurring in the first color bucket 2512 (because no sensitizer is present).

In another embodiment, FIG25I illustrates an example dual-tone photoresist for one type of photobucket and an example single-tone photoresist for another type of photobucket, according to an embodiment of the present invention. Referring to FIG25I, in one embodiment, a dual-tone photoresist system (PB-1) is used for the material of the first color photobucket 2512. A single-tone (slow) photoresist system (PB-2) is used for the material of the second color photobucket 2518. The dual-tone photoresist can be characterized as having a photoresponse that is effectively shut down at higher doses due to the activation of the photoradical generator included in the system. The photogenerated radicals neutralize the photoacids and prevent polymer deprotection. In one embodiment, during the exposure of the first color bucket 2512, the dose is selected so that its two-tone resist (PB-1) operates as a fast positive tone system, while the single-tone resist (PB-2) has not yet received enough photons to be activated for solubility switching. This allows PB-1 to be removed with the TMAH developer without removing PB-2. In order to selectively remove PB-2 without removing PB-1, a higher dose is used for the second exposure (i.e., the exposure of the second color bucket 2518). The selected dose must activate enough PAG in PB-2 to allow dissolution in TMAH and to move PB-2 into the negative tone response region through the activation of PBG. In this scenario, the same PAG can be used for both PB-1 and PB-2, and the same exposure wavelength can be used for Exposures 1 and 2. It should be understood that PB-1 may need to be combined with a photoradical generator (PBG); however, it is likely that a different type of polymer will be required to allow for the application of PB-2 (once PB-1 has been applied). As described above, the use of a polymethacrylate-type etch resist for PB-1 and a PHS-type for PB-2 can meet this requirement.

It should be understood that the materials specified above for the first and second color light buckets 2512 and 2518, respectively, can be interchanged according to embodiments of the present invention. Together, the multi-color light bucket approach described above can be referred to as 1-D. A similar approach can be applied to a 2-D system using a cross grating, although the light bucket material will have to withstand etching and cleaning from the cross grating described above. The result will be a checkerboard-type pattern with smaller vias/plugs in the vertical direction, relative to those in the above-described approach. Furthermore, it should be understood that the approach described in connection with Figures 25A-25H is not necessarily performed to form vias aligned to the underlying metallization layer, although it can certainly be implemented in this way. In other contexts, these process schemes can be viewed as involving blind shooting from a top-down direction at any underlying metallization layer.

According to an embodiment of the present invention, a light bucket for a conductive sheet is described.

For example, FIG26A illustrates a plan view of a conventional back-end-of-the-line (BEOL) metallization layer. Referring to FIG26A , conventional BEOL metallization layer 2600 is shown with conductive lines or routing 2604 disposed in an interlayer dielectric layer 2602. The metal lines may generally run parallel to one another and may include cuts, breaks, or plugs 2606 in the continuity of one or more of the conductive lines 2604. To electrically couple two or more of the parallel metal lines, an upper or lower level routing 2608 is included in the preceding or next metallization layer. This upper or lower level routing 2608 may include a conductive line 2610 coupled to a conductive via 2612. It should be understood that because the upper or lower level routing 2608 is included in the previous or next metallization layer, the upper or lower level routing 2608 may consume vertical real estate of the semiconductor structure including the metallization layer.

Conversely, FIG26B illustrates a plan view of a back-end-of-the-line (BEOL) metallization layer having conductive tabs for coupling metal lines within the metallization layer, according to an embodiment of the present invention. Referring to FIG26B , BEOL metallization layer 2650 is shown with conductive lines or routing 2654 disposed within an interlayer dielectric layer 2652. The metal lines may generally run parallel to one another and may include cuts, breaks, or plugs 2656 in the continuity of one or more of the conductive lines 2654. To electrically couple two or more of the parallel metal lines, conductive tabs 158 are included within metallization layer 2650. It should be understood that because conductive sheet 2658 is included in the same metallization layer as conductive line 2654, the vertical real estate consumption of conductive sheet 2658 by the semiconductor structure including the metallization layer can be reduced relative to the structure of Figure 26A.

One or more embodiments described herein relate to light-bucket methods for metallization plugs and patterning of sheets. Such patterning schemes can be implemented to enable bidirectional spacer-based interconnects. The embodiments may be particularly suitable for electrically connecting two parallel lines of a metallization layer, where the two metal lines are fabricated using a spacer-based method that is further limited to including conductive connections between two adjacent lines in the same metallization layer. Generally, one or more embodiments relate to a method that utilizes a metallization technique to form a conductive sheet and a non-conductive spacer or interruption (plug) between the metals.

More specifically, one or more embodiments described herein relate to using a metal inlay method to form pads and plugs. Initially, every possible pad and plug location is first patterned in a hard mask layer. An additional operation is then used to select which pad and plug locations to retain. These locations are then transferred to the underlying interlayer dielectric layer. These operations can be illuminated using photobucketing. In a specific embodiment, a method for metal inlay patterning of vias, plugs, and pads is provided with self-alignment using a photobucketing approach and a selective hard mask.

According to an embodiment of the present invention, photobucket patterning is used to fabricate plugs and tabs in a self-aligned manner. A general overview process flow may involve (1) fabrication of a cross grating, followed by (2) photobucketing for plug definition and changing the photoresist to a "hard" material that can withstand downstream processing, followed by (3) grating tone inversion by backfilling with a fillable material, recessing the fillable material, and removing the original cross grating, followed by (4) photobucketing for "tab" definition, followed by (5) etching the pattern into the underlying interlayer dielectric (ILD) layer and polishing off the additional hard mask material. It should be understood that although the general process flow does not include vias, in one embodiment, the methods described herein can be implemented to extend to multiple via plugs, vias, and sheets using the same self-aligning grating.

For example, Figures 27A-27K illustrate oblique cross-sectional views representing various operations in a method of fabricating a back-end of line (BEOL) metallization layer having conductive pads for coupling metal lines of the metallization layer, according to an embodiment of the present invention.

Referring to FIG. 27A , the first operation in a cross-grating patterning scheme is performed on an interlayer dielectric (ILD) layer 2702 formed on a substrate 2700. A blanket hard mask 2704 is first formed on the ILD layer 2702. A first grating hard mask 2706 is formed along a first direction over the blanket hard mask 2704. In one embodiment, the first grating hard mask 2706 is formed with a grating pattern, as depicted in FIG. 27A . In one embodiment, the grating structure of the first grating hard mask 2706 is a fine-pitch grating structure. In this particular embodiment, the fine pitch cannot be directly achieved through conventional lithography. For example, a pattern based on conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Furthermore, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern of the first grating hard mask 2706 of FIG. 27A can have hard mask lines that are closely spaced at a constant pitch and have a constant width.

Referring to FIG. 27B , a second operation in the cross-grating patterning scheme is performed on an interlayer dielectric (ILD) layer 2702. A second grating hard mask 2708 is formed along a second direction overlying the hard mask 2704. The second direction is orthogonal to the first direction. The second grating hard mask 2708 has an overlying hard mask 2710. In one embodiment, the second grating hard mask 2710 is fabricated in a patterning process using the overlying hard mask 2710. The continuity of the second grating hard mask 2708 is interrupted by lines of the first grating hard mask 2706, such that portions of the first grating hard mask 2706 extend below the overlying hard mask 2710. In one embodiment, the second grating hard mask 2708 is formed to interleave with the first grating hard mask 2706. In one such embodiment, the second grating hard mask 2708 is formed by depositing a second hard mask material layer having a different composition than the first grating hard mask 2706. The second hard mask material layer is then planarized (e.g., by chemical mechanical polishing (CMP)) and then patterned using an overlying hard mask 2710 to provide the second grating hard mask 2708. As with the first grating hard mask 2706, in one embodiment, the grating structure of the second grating hard mask 2708 is a fine-pitch grating structure. In certain embodiments of this invention, a tight pitch cannot be achieved directly through conventional lithography. For example, a pattern based on conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Furthermore, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern of the second grating hard mask 2708 of FIG. 27A can have hard mask lines that are closely spaced at a constant pitch and have a constant width.

Referring to FIG. 27C , the plug photobucket patterning scheme is performed as the first photobucketing process. In one embodiment, photobuckets 2712 are formed on all exposed openings between the first grating hard mask 2706 and the second grating hard mask 2708. In one embodiment, a via patterning process is optionally performed before the plug photobucket patterning process. Via patterning can be direct patterning or can involve a separate photobucketing process.

Referring to Figure 27D, selected ones of the photobuckets 2712 are removed while the other photobuckets 2712 are retained, for example, by not exposing the selected photobuckets 2712 to a lithography and development process that opens all other photobuckets 2712. The exposed portion of the covering hard mask 2704 of Figure 27A is then etched to provide a first patterned hard mask 2714. The retained photobuckets 2712 (at this stage) represent the plug positions in the final metallization layer. That is, in the first photobucket process, the photobuckets are removed from the positions where the plugs will not be formed. In one embodiment, in order to form the positions where the plugs will not be formed, lithography is used to expose the corresponding photobuckets. The exposed photobuckets can then be removed by a developer.

Referring to FIG27E , a grating tone inversion process is performed. In one embodiment, a dielectric region 2716 is formed in all exposed areas of the structure of FIG27D . In one embodiment, the dielectric region 2716 is formed by depositing a dielectric layer and etching back to form the dielectric region 2716 .

27F , the portion of the first grating hard mask 2706 not covered by the overlying hard mask 2710 is then removed to leave only the portion 2706′ of the first grating hard mask 2706 remaining below the overlying hard mask 2710 .

27G , the sheet photobucket patterning scheme is performed as a second photobucketing process. In one embodiment, photobuckets 2718 are formed in all exposed openings formed when the exposed portions of the first grating hard mask 2706 are removed.

Referring to Figure 27H, selected ones of the photobuckets 2718 are removed while other photobuckets 2718 are retained, for example, by not exposing the photobuckets 2718 to a lithography and development process that opens the other photobuckets. The exposed portions of the first patterned hard mask 2714 of Figures 27D-27G are then etched to provide a second patterned hard mask 2715. The retained photobuckets 2718 (at this stage) represent positions where the conductive strips will not be in the final metallization layer. That is, in the second photobucket process, the photobuckets are removed from the positions where the conductive strips will ultimately be formed. In one embodiment, in order to form the positions where the conductive strips will be formed, lithography is used to expose the corresponding photobuckets. The exposed photobuckets can then be removed by a developer.

27I , the overlying hard mask 2710, the second grating hard mask 2708, and the dielectric region 2716 are removed. Subsequently, the portion of the second patterned hard mask 2715 exposed upon removal of the overlying hard mask 2710 is removed to provide a third patterned hard mask 2720, and the second grating hard mask 2708 and the dielectric region 2716 are removed. In one embodiment, the remaining photobuckets 2712 and 2718 are first cured (e.g., by a baking process) before removing the overlying hard mask 2710, the second grating hard mask 2708, and the dielectric region 2716. At this stage, selected portions of the photobuckets 2712, selected portions of the photobuckets 2718, and the remaining portion 2706′ of the first photograting hard mask 2706 remain on the third patterned hard mask 2720. In one embodiment, the overlying hard mask 2710, the second photograting hard mask 2708, and the dielectric region 2716 are removed using a selective wet etch process, and the portion of the second patterned hard mask 2715 exposed upon removal of the overlying hard mask 2710 is removed using a dry etch process to provide the third patterned hard mask 2720.

27J , the pattern of the third patterned hard mask 2720 is transferred to the upper portion of the ILD layer 2702 to form the patterned ILD layer 2722. In one embodiment, the plug and pad patterns of the third patterned hard mask 2720 are then transferred to the ILD layer 2702 to form the patterned ILD layer 2722. In one embodiment, an etching process is used to transfer the pattern into the ILD layer 2702. In one such embodiment, the selected ones of the photobuckets 2712, the selected ones of the photobuckets 2718, and the remaining portion 2706′ of the first photogate hard mask 2706 remaining on the third patterned hard mask 2720 are removed or destroyed during the etching process used to form the patterned ILD layer 2722. In another embodiment, selected portions of the photobuckets 2712, selected portions of the photobuckets 2718, and the remaining portion 2706' of the first photogate hard mask 2706 remaining on the third patterned hard mask 2720 are removed before or after etching to form the patterned ILD layer 2722.

27K , following the formation of patterned ILD layer 2732, conductive lines 2724 are formed. In one embodiment, conductive lines 2724 are formed using a metal fill and polish back process. During the formation of conductive lines 2724, conductive tabs 2728 are also formed that couple the two metal lines 2724. Thus, in one embodiment, the conductive coupling (tab 2728) between conductive lines 2724 is formed at the same time, in the same ILD layer 2722, and in the same plane as conductive lines 2724. Furthermore, plugs 2726 may be formed as breaks or interruptions in one or more of the conductive lines 2724, as depicted in FIG. 27K . In one such embodiment, plugs 2726 are regions of ILD layer 2702 that remain during pattern transfer to form patterned ILD layer 2722. In one embodiment, third patterning hard mask 2720 is removed, as depicted in FIG27K. In one such embodiment, third patterning hard mask 2720 is removed after forming conductive lines 2724 and pads 2728, for example, using a post-metallization chemical mechanical planarization (CMP) process.

Referring again to FIG. 27K , in one embodiment, a back-end-of-the-line (BEOL) metallization layer for a semiconductor structure includes an interlayer dielectric (ILD) layer 2722 disposed on a substrate 2700. A plurality of conductive lines 2724 are disposed in the ILD layer 2722 along a first direction. A conductive pad 2728 is disposed in the ILD layer 2722. The conductive pad couples two of the plurality of conductive lines 2724 along a second direction orthogonal to the first direction.

This configuration, as shown in FIG27K , cannot be achieved using conventional lithography (at small pitches, small widths, or both). Furthermore, self-alignment cannot be achieved using conventional processes. Furthermore, the configuration shown in FIG27K cannot be achieved in a case where a pitch-dividing scheme is used to ultimately provide the pattern of conductive lines 2724.

In one embodiment, conductive sheet 2728 is continuous with, but not adjacent to, the plurality of conductive lines, as depicted in FIG27K. In one embodiment, conductive sheet 2728 is coplanar with, as depicted in FIG27K. In one embodiment, the BEOL metallization layer further includes a dielectric plug 2726 disposed at an end of one of the plurality of conductive lines 2724, as depicted in FIG27K. In one embodiment, dielectric plug 2726 is continuous with, but not adjacent to, the ILD layer, as depicted in FIG27K. In one embodiment, although not shown, the BEOL metallization layer further includes a conductive via that is disposed underneath and electrically coupled to one of the plurality of conductive lines 2724.

The structure of Figure 27K can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 3K can represent the last metal interconnect layer in the integrated circuit. Referring to Figure 27K, this self-aligned fabrication by a metal inlay photobucket approach can be continued to fabricate the next metallization layer. Alternatively, other approaches can be used at this stage to provide additional interconnect layers, such as conventional dual or single metal inlay approaches. It should also be understood that, although not depicted, one or more of the conductive lines 2724 can be coupled to underlying conductive vias, which can be formed using additional photobucket operations. In one embodiment, as an alternative to the two-dimensional approach described above, a one-dimensional grating approach can also be implemented for plug and sheet (and possibly via) patterning. This one-dimensional approach is limited to only one direction. Thus, the pitch can be "tight" in one direction and "loose" in another.

One or more embodiments described herein relate to photobucket methods for subtractive plug and sheet patterning. Such patterning schemes can be implemented to enable bidirectional spacer-based interconnects. The embodiments may be particularly suitable for electrically connecting two parallel lines of a metallization layer, where the two metal lines are fabricated using a spacer-based method that may also be limited to include conductive connections between two adjacent lines in the same metallization layer. Generally, one or more embodiments relate to a method that utilizes a subtractive technique to form a conductive sheet and a non-conductive spacer or interruption between the metal (plug).

One or more embodiments described herein provide a method for subtractively patterning self-aligned vias, cuts, and/or sheets using a photobucketing method and a selective hard mask. Embodiments may involve using a so-called fabric patterning method to subtractively pattern self-aligned interconnects, plugs, and vias. The fabric method may involve implementing a fabric pattern of a hard mask, utilizing etch selectivity between hard mask materials. In specific embodiments described herein, a fabric processing scheme is implemented to subtractively pattern interconnects, cuts, and vias.

When describing one or more embodiments described herein, a general overview process flow may involve the following process sequence: (1) fabrication using a fabric process flow utilizing four "color" hard masks that are etch selective to each other, (2) removal of a first hard mask type for photobucketing of vias, (3) backfilling of the first hard mask material, (4) removal of a second hard mask type for photobucketing of cuts (or plugs), (5) backfilling of the second hard mask material, (6) removal of a third hard mask type for photobucketing of conductive pads, (7) subtractive etching of the cut and pad metal, and (8) hard mask removal and subsequent backfilling and polishing with permanent ILD material.

28A-28T illustrate oblique cross-sectional views representing various operations in a method of fabricating a back-end-of-line (BEOL) metallization layer having conductive pads for coupling metal lines of the metallization layer, according to an embodiment of the present invention.

28A , a grating patterning scheme is performed on a blanket hard mask layer 2802, which is formed on a metal layer 2800, which is formed on a substrate (not shown). A first grating hard mask 2804 is formed along a first direction over the blanket hard mask 2802. A second grating hard mask 2806 is formed along the first direction and alternates with the first grating hard mask 2804. In one embodiment, the first grating hard mask 2804 is formed from a material having a different etch selectivity than the material of the second grating hard mask 2806.

In one embodiment, first and second grating hard masks 2804 and 2806 are formed with grating patterns, as depicted in FIG28A. In one embodiment, the grating structures of the first and second grating hard masks 2804 and 2806 are fine-pitch grating structures. In this particular embodiment, the fine pitch cannot be directly achieved through conventional lithography. For example, a pattern based on conventional lithography can be formed first, but the pitch can be halved through patterning using spacer masks. Furthermore, the original pitch can be reduced to one-quarter through a second round of spacer mask patterning. Thus, the grating patterns of the first and second grating hard masks 2804 and 2806 of FIG. 28A may have hard mask lines that are closely spaced at a constant pitch and have a constant width.

28B , a sacrificial cross grating patterning process is performed and an overlying hard mask 2808 is formed with a grating pattern along a second direction, orthogonal to the first direction, i.e., orthogonal to the first and second grating hard masks 2804 and 2806 .

In one embodiment, the overlying hard mask 2808 is formed with a tight pitch grating structure. In this particular embodiment, the tight pitch cannot be directly achieved through conventional lithography. For example, a pattern based on conventional lithography can be formed first, but the pitch can be halved by patterning using spacer masks. Furthermore, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern of the overlying hard mask 2808 of FIG. 28B can have hard mask lines that are tightly spaced at a constant pitch and have a constant width.

Referring to FIG. 28C , fabric pattern formation is performed. Areas of the first hard mask 2804 exposed between the gratings of the overlying hard mask 2808 are selectively etched and replaced with areas of a third hard mask 2810. Areas of the second hard mask 2806 exposed between the gratings of the overlying hard mask 2808 are selectively etched and replaced with areas of a fourth hard mask 2812. In one embodiment, the third grating hard mask 2810 is formed from a material having an etch selectivity different from that of the materials of the first hard mask 2804 and the second hard mask 2806. In a further embodiment, the fourth hard mask 2812 is formed from a material having an etch selectivity different from that of the materials of the first hard mask 2804, the second hard mask 2806, and the third hard mask 2810.

28D , the overlying hard mask 2808 is removed. In one embodiment, the overlying hard mask 2808 is removed using an etching, ashing, or cleaning process that is selective to the first hard mask 2804, the second hard mask 2806, the third hard mask 2810, and the fourth hard mask 2812 to leave the fabric pattern, as shown in FIG28D .

Figures 28E-28H relate to a via patterning process. Referring to Figure 28E, the third hard mask 2810 is removed selectively to the first hard mask 2804, selectively to the second hard mask 2806, and selectively to the fourth hard mask 2812 to provide an opening 2814 exposing a portion of the hard mask 2802. In one embodiment, the third hard mask 2810 is removed selectively to the first hard mask 2804, selectively to the second hard mask 2806, and selectively to the fourth hard mask 2812 using a selective etching or cleaning process.

Referring to FIG28F, the via photobucket patterning scheme is performed as a first photobucketing process. In one embodiment, photobuckets are formed in all exposed openings 2814 of FIG28E. Selected photobuckets are removed to re-expose openings 2814 while other photobuckets 2816 are retained, for example, by not exposing photobuckets 2816 to a lithography and development process that opens all other first photobuckets (in the particular case shown, three photobuckets are retained and one is removed).

28G , the exposed portions of the covering hard mask 2802 are then etched to provide a first patterned hard mask 2820. Furthermore, the metal layer 2800 is etched through the openings to provide etched trenches 2818 in the first patterned metal layer 2822. The first patterned metal layer 2822 includes conductive vias 2824. After the subtractive metal etch, the remaining photobuckets 2816 are removed to re-expose the associated openings 2814.

28H , trenches 2818 and openings 2814 are backfilled with a hard mask material. In one embodiment, a material similar to or identical to the material of third hard mask 2810 is formed over the structure of FIG 28G and planarized or etched back to provide deep hard mask regions 2826 and shallow hard mask regions 2828. In one embodiment, deep hard mask regions 2826 and shallow hard mask regions 2828 are of the third material type (i.e., the material type of third hard mask 2810).

Figures 28I-28L relate to a patterning process for wire cutting or plug formation. Referring to Figure 28I, the first hard mask 2804 is removed selectively to the second hard mask 2806, the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type, and the fourth hard mask 2812 to provide an opening 2830 that exposes a portion of the first patterned hard mask 2820. In one embodiment, the first hard mask 2804 is removed selectively to the second hard mask 2806, the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type, and the fourth hard mask 2812 using a selective etching or cleaning process.

Referring to Figure 28J, a cut or plug photobucket patterning scheme is performed as a second photobucketing process. In one embodiment, photobuckets are formed in all exposed openings 2830 of Figure 28I. Selected photobuckets are removed to re-expose openings 2830 while other photobuckets 2832 are retained, for example, by not exposing photobuckets 2832 to a lithography and development process that opens all other second photobuckets (in the particular case shown, three photobuckets are retained and one is removed). The removed photobuckets (at this stage) represent the locations where the cuts or plugs will be in the final metallization layer. That is, in the second photobucket process, the photobuckets are removed from the locations where the plugs or cuts will ultimately be formed.

28K , the exposed portions of the first patterned hard mask 2820 are then etched to provide a second patterned hard mask 2834 having trenches 2836 formed therein. After the etching, the remaining light buckets 2832 are removed to re-expose the associated openings 2830.

28L , trenches 2834 and openings 2830 are backfilled with a hard mask material. In one embodiment, a material similar to or identical to the material of first hard mask 2804 is formed over the structure of FIG. 28K and planarized or etched back to provide deep hard mask regions 2838 and shallow hard mask regions 2840. In one embodiment, deep hard mask regions 2838 and shallow hard mask regions 2840 are of the first material type (i.e., the material type of first hard mask 2804).

28M , the fourth hard mask 2812 is removed selectively from the deep hard mask region 2838 and the shallow hard mask region 2840 of the first material type, selectively from the second hard mask 2806, and selectively from the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type. In one embodiment, the fourth hard mask 2812 is removed selectively from the deep hard mask region 2838 and the shallow hard mask region 2840 of the first material type, selectively from the second hard mask 2806, and selectively from the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type using a selective etching or cleaning process. A deep etch process is performed through the resulting opening and completely through the second patterned hard mask 2834 to form a third patterned hard mask 2842; and completely through the first patterned metal layer 2822 to form a second patterned metal layer 2844. Although not depicted, a second cutting or plug patterning process may be performed at this stage.

Referring to FIG. 28N , the deep openings formed in association with FIG. 28M are backfilled with a hard mask material. In one embodiment, a material similar to or identical to the material of fourth hard mask 2812 is formed over the structure of FIG. 28M and planarized or etched back to provide a deep hard mask region 2846. In one embodiment, deep hard mask region 2846 is of a fourth material type (i.e., the material type of fourth hard mask 2812). In an alternative embodiment, as shown in association with 2899 of FIG. 28S , described below, an ILD layer (e.g., a low-k dielectric layer) may first be filled and etched back to the level of the second patterned metal layer 2844. A fourth type of hard mask material (i.e., a shallow version of 2846) is then formed over the ILD layer.

Figures 28O-28R relate to the patterning process for forming the conductive sheet. Referring to Figure 28O, the second hard mask 2806 is removed, selectively from the deep hard mask region 2838 and the shallow hard mask region 2840 of the first material type, selectively from the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type, and selectively from the deep hard mask region 2846 of the fourth material type, to provide an opening 2848 exposing a portion of the third patterned hard mask 2842. In one embodiment, the second hard mask 2806 is removed selectively to the deep hard mask region 2838 and the shallow hard mask region 2840 of the first material type, selectively to the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type, and selectively to the deep hard mask region 2846 of the fourth material type using a selective etching or cleaning process.

Referring to FIG. 28P , the conductive sheet photobucket patterning scheme is performed as a third photobucketing process. In one embodiment, photobuckets are formed in all exposed openings 2848 of FIG. 28O . Selected photobuckets are removed to re-expose openings 2848 while other photobuckets 2850 are retained, for example, by not exposing the photobuckets 2850 to a lithography and development process that opens all other third photobuckets (in the particular case shown, one photobucket 2850 is retained and three are removed). The removed photobuckets (at this stage) represent locations where the conductive sheet will not be formed in the final metallization layer. That is, in the third photobucketing process, the photobuckets 2850 are retained in the locations where the conductive sheet will ultimately be formed.

28Q, the exposed portions of the third patterned hard mask 2842 are then etched through the openings 2848 to provide a fourth patterned hard mask 2852 having trenches 2854 formed therein. After this etching, the remaining light buckets 2850 are removed.

28R , the deep hard mask region 2838 and the shallow hard mask region 2840 of the first material type are removed selectively to the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type and selectively to the deep hard mask region 2846 of the fourth material type to further expose portions of the fourth patterned hard mask 2852. In one embodiment, the deep hard mask region 2838 and the shallow hard mask region 2840 of the first material type are removed selectively to the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type and selectively to the deep hard mask region 2846 of the fourth material type using a selective etching or cleaning process.

28S , a deep etch process is performed through the resulting opening and completely through the second patterned metal layer 2844 to form a third patterned metal layer 2856. At this stage, where an ILD layer 2899 was formed in the operation associated with FIG. 28N , as described above in the alternative embodiment, a portion of this ILD layer 2899 is visible in the structure of FIG. 28S .

Referring to portion (a) of FIG. 28T , in one embodiment, hard mask removal of the remaining hard mask portions 2828, 2846, and 2852 of FIG. 28S is performed, and the structure is subsequently planarized. In one embodiment, the height of deep hard mask region 2826 is reduced, but the region is not removed entirely, to form via cap 2858 and ILD 2860. Additionally, plug region 2862 is formed. In one embodiment, ILD 2899 is formed in association with FIG. 28N ; and in one such embodiment, plug region 2862 comprises a different material than ILD 2899. In another embodiment, ILD 2899 is not formed in association with FIG. 28N ; instead, ILD 2860 and the entire portion of plug 2862 are formed simultaneously and with the same material, for example, using an ILD backfill process. In one embodiment, the metallized portion of the structure includes metal line 2864, conductive via 2824 (with via cap 2858 thereon), and conductive sheet 2866, as depicted in portion (a) of FIG. 28T .

Referring to portion (a) of FIG. 28T , in one embodiment, an ILD backfill 2861 is formed over the structure of FIG. 28S . In one such embodiment, an ILD film is deposited and then etched back to provide the structure of portion (b) of FIG. 28T . In one embodiment, the hard mask of FIG. 28S is left in place, and templates for the next metallization layer can be performed. That is, the topography of the remaining hard mask can be used to template the next patterning process.

In either case, whether in portion (a) or (b) of FIG. 28T , the embodiments described herein include a remaining hard mask material ( 2858 or 2826 ) over the conductive via 2824 of the last metallization layer in the semiconductor structure. Furthermore, referring again to FIG. 28A-28T , it should be understood that the order of sawing, vias, and sheet patterning can be interchangeable. Also, while the example process flow shows one saw, one via, and one sheet pass, multiple passes of each type of patterning can be performed.

Referring again to portion (a) of FIG. 28T , in one embodiment, a back-end-of-the-line (BEOL) metallization layer for a semiconductor structure includes an interlayer dielectric (ILD) layer 2860. A plurality of conductive lines 2864 are arranged in the ILD layer 2860 along a first direction. A conductive patch 2866 couples two of the plurality of conductive lines 2864 along a second direction orthogonal to the first direction.

This configuration, as shown in FIG28T, cannot be achieved using conventional lithography (at small pitches, small widths, or both). Furthermore, self-alignment cannot be achieved using conventional processing schemes. Furthermore, the configuration shown in FIG28T cannot be achieved in a situation where a pitch-splitting scheme is used to ultimately provide the pattern of conductive lines 2864.

In one embodiment, conductive sheet 2866 and plurality of conductive lines 2864 are continuous, rather than adjacent. In one embodiment, conductive sheet 2866 and plurality of conductive lines 2864 are coplanar. In one embodiment, BEOL metallization further includes a plug of dielectric material 2862 disposed at an end of one of plurality of conductive lines 2866. In one embodiment, BEOL metallization further includes a conductive via.

The structure of FIG28T can then be used as a foundation for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG28T can represent the final metal interconnect layer in an integrated circuit. Referring again to FIG28T , this self-aligned fabrication using a subtractive photobucketing approach can be continued to fabricate the next metallization layer. Alternatively, other approaches can be used at this stage to provide additional interconnect layers, such as traditional dual or single damascene approaches.

According to an embodiment of the present invention, resist adaptation for tolerance to exposure misalignment is described. Resist adaptation may include one or more of internal suppression, grafted layer suppression, or top layer suppression. One or more embodiments described herein relate to a two-stage baked photoresist with a releasable inhibitor. Applications may be directed to one or more of extreme ultraviolet (EUV) lithography, general lithography applications, solutions to overlap problems, and general photoresist technology. In one embodiment, materials are described that are suitable for enhancing the performance of a photobucket-based approach. In this approach, the resist material is limited to a pre-patterned hard mask. Selected photobuckets are then removed using a high-resolution lithography tool (e.g., an EUV lithography tool). Certain embodiments may be implemented to improve the uniformity of the resist material response across a given photobucket.

To provide background, one goal of the photobucket approach can be to first diffuse any EUV-released acid across the exposed photobucket, thereby improving the consistency of the resist response across the selected photobucket. In past approaches, this goal has been achieved by using specialized materials that enable the acid to diffuse across the photobucket at a low enough temperature to avoid solubility switching reactions initiated by the acid. However, the activity of another resist component, namely the inhibitor, can prevent this advantage from being fully realized. In particular, the inhibitor can neutralize the acid before it can diffuse or spread across a given photobucket. To address these issues, according to one or more embodiments described herein, the standard inhibitor is replaced with an inhibitor that is releasable by extreme ultraviolet (UV) exposure, etc., which provides the ability to avoid premature acid neutralization.

More particularly, according to one or more embodiments described herein, a photobucket resist material including a UV release inhibitor is implemented to effectively provide a "two-stage PEB," wherein the effects of EUV exposure are effectively averaged across a given photobucket. These embodiments can enable a "digital" bucket response, where an entire photobucket is either cleared or not. In certain embodiments, this response is more tolerant to edge placement errors, where the aerial image is not perfectly aligned with the photobucket grid.

To illustrate one or more concepts disclosed herein, Figures 29A-29C illustrate cross-sectional views and corresponding plan views of various operations in a method for patterning a photobucket using a two-stage photoresist bake, according to an embodiment of the present invention.

29A , a pre-patterned hard mask 2904 is disposed over a substrate 2902. The pre-patterned hard mask 2904 has openings filled with a second-stage baked photoresist 2906. The second-stage baked photoresist 2906 is confined to the openings in the pre-patterned hard mask 2904, for example, to provide a grid at potential via locations.

Referring to FIG. 29B , selected photobuckets undergo exposure 2907 from a lithography tool. A secondary baked photoresist 2906 is exposed in a lithography tool (e.g., an EUV lithography tool) to select which vias should be opened. In one embodiment, the alignment between the lithography tool and the pre-patterned hard mask 2904 grid is imperfect, resulting in asymmetric exposures in the target photobucket and/or partial exposures in adjacent photobuckets. Exposure 2907 is shifted in aerial image 2908 as seen in the plan view.

Referring to Figure 29C, although the exposure of Figure 29B may have involved misalignment and partial exposure of non-selected photobuckets, only the selected photobuckets are cleared to form openings 2920, leaving the unselected photobuckets as closed photobuckets 2912. In one embodiment, the process is used to ensure that only the selected photobuckets are ultimately opened, following exposure 2907 of selected areas of the second-stage baked photoresist 2906, all second-stage baked photoresists 2906 are first baked to facilitate acid diffusion. Extreme ultraviolet (UV) suppression release is then performed to facilitate acid neutralization. A second bake is then performed to facilitate soluble switching, as described in more detail below. In a specific embodiment, the photoacid released from the first bake operation is diffused throughout the photobucket. UV exposure is performed to release the inhibitor and then a final soluble switching bake is performed. The process is described in detail below with reference to Figures 30A-30E.

As a result, the selected positions that received the larger exposure are eventually cleared to provide the open light bucket position 2920, which is continued after development. The non-selected positions that did not receive exposure (or were only partially exposed but to a lesser extent, in the case of misalignment) remain as the closed light bucket position 2912, which is continued after development.

To illustrate the opposite scenario where a conventional photoresist is used, FIG1D illustrates a cross-sectional view of a conventional resist photobucket structure following photobucket development following a misaligned exposure. Photobucket region 2954 is shown as only partially cleared 2950, leaving some residual photoresist 2952. In the case where photobucket 2954 is a selected photobucket, the misaligned exposure 2907 only partially clears the photobucket, which can result in subsequent poor quality manufacturing of conductive structures in such locations. In the case where photobucket 2954 is a non-selected photobucket, an undesired opening 2950 occurs, potentially resulting in the subsequent formation of conductive structures in undesired locations.

In a more detailed process description, Figures 30A-30E illustrate schematic views of various operations in a method of patterning using a photobucket including a two-stage photoresist bake, according to an embodiment of the present invention.

30A , the first 3002 and second 3004 photobuckets each include a photodegradable composition comprising an acid-removable protective photoresist material, a photoacid generating (PAG) component 3010, and a photoradical generating component 3012. In-alignment EUV or electron beam exposure 3006 is performed on the selected photobucket 3002 and the non-selected photobuckets 3004, substantially exposing the selected photobucket 3002 and partially exposing the non-selected photobuckets 3004 (but to a lesser extent). In a specific embodiment, the photoradical generating component 3012 is a UV-releasable inhibitor.

30B , a first bake is performed. In one embodiment, the first bake is performed at a temperature that is too low to cause a soluble switch. In one such embodiment, the bake is a diffusion-only bake, resulting in diffused material 3020 and 3022 in the barrels 3002 and 3004, respectively.

Referring to FIG. 30C , inhibitor 3014 is released to form materials 3024 and 3026 of photobuckets 3002 and 3004, respectively. In one embodiment, inhibitor 3014 is a UV-released inhibitor. In certain such embodiments, the UV-released inhibitor is released by UV bulk exposure (e.g., 365 nm exposure). In one embodiment, both photobuckets 3002 and 3004 are exposed to the same bulk exposure level.

Referring to FIG. 30D , a second bake is performed to provide materials 3028 and 3030 for photobuckets 3002 and 3004, respectively. In one embodiment, the second bake produces a soluble switch, wherein subcritical acid concentration is suppressed. In this manner, there is essentially no localized acid concentration. That is, undesirable deprotection of only partially exposed portions of the photobucket does not occur.

Referring to Figure 30E, photobuckets 3002 and 3004 are subjected to a development process. Selected photobucket 3002 is cleared during development to provide a cleared photobucket 3032. Unselected photobuckets 3004 are not cleared during development and a blocked photobucket 3034 remains. In this way, a digital photobucket response is achieved (only open or closed, no partial open) even in the event of an inaccurate exposure.

It should be understood that not all embodiments require a single composition to achieve a two-stage photoresist bake. In a first alternative example, Figure 30A' illustrates a schematic view of operations in another method of patterning using photobuckets, according to an embodiment of the present invention. Referring to Figure 30A', the first 3002' and second 3004' photobuckets each include a grafted photoradical generating component 3050 along the bottom and side walls of the first 3002' and second 3004' photobuckets. A photodegradable composition is formed within the grafted photoradical generating component 3050. The photodegradable composition includes an acid-removable protective photoresist material and a photoacid generating (PAG) component 3010'. Exposure 3006' and a multi-stage development process can then be performed in a manner similar to that described above.

In a second alternative example, Figure 30A" illustrates a schematic view of operations in another method of patterning using photobuckets, according to an embodiment of the present invention. Referring to Figure 30A", the first 3002" and second 3004" photobuckets each include a photodegradable composition, which includes an acid-removable photoresist material and a photoacid generating (PAG) component 3010". After performing a first bake, a layer 3060 including a base generating component is formed on the first 3002" and second 3004". The photobuckets 3002" and 3004" are then exposed to ultraviolet (UV) radiation. In this case, the base component does not need to be introduced via a photoradical generator, but can be deposited in a later process operation, for example, by vapor deposition of the base layer or exposure to a base atmosphere NMP.

The application of the above-mentioned photoresist composition and method can be implemented to produce a regular structure that covers all possible through-hole (or plug) locations, followed by selective patterning of only desired features. To provide further material details, in one embodiment, referring again to Figures 30A-30E, photobuckets 3002 and 3004 include a photodegradable composition. The photodegradable composition includes an acid-removable photoresist material that has substantial transparency at a certain wavelength. The photodegradable composition also includes a photoacid generating (PAG) component that has substantial transparency at the wavelength. The photodegradable composition includes a radical generating component that has substantial absorption at the wavelength. In an alternative embodiment, the acid-removable photoresist material is not substantially transparent at the wavelength.

In one embodiment, the radical-generating component is selected from the group consisting of: a photoradiation-generating component, an electron-radiation-generating component, a chemical radical-generating component, and a UV radical-generating component. In one embodiment, the radical-generating component is a sonication-generating component. In one embodiment, the radical-generating component is UV-absorbing. In one embodiment, the radical-generating component comprises a low-energy UV chromophore. In a particular embodiment of this type, the low-energy UV chromophore is selected from the group consisting of: anthracenylcarbamates, naphthalenylcarbamates, 2-nitrophenylcarbamates, arylcarbamates, coumarin, phenylglyoxylic acid, substituted acetophenones, and benzophenones. In one embodiment, the low-energy UV chromophore is a photo-releasing amine. In one embodiment, the radical-generating component includes a material selected from the group consisting of N,N-dicyclohexyl-2-nitrophenylcarbamate, N,N-disubstituted carbamates, and mono-substituted carbamates.

In one embodiment, the PAG component includes a material selected from the group consisting of triethyl, trimethyl, and other trialkylsulfonates, wherein the sulfonate group is selected from the group consisting of trifluoromethylsulfonate, nonafluorobutanesulfonate, and p-tolylsulfonate, or other examples of sulfonate anions containing _-SO₃ , limited to organic groups. In one embodiment, the acid-removable photoresist material is an acid-removable material selected from the group consisting of polymers, molecular glasses, carbosilanes, and metal oxides. In one embodiment, metal oxides are used and releasing groups are not required. In one embodiment, the acid-removable photoresist material comprises a material selected from the group consisting of polyhydroxystyrene, polymethyl methacrylate, a small molecular weight molecular glass version of polyhydroxystyrene or polymethyl methacrylate containing an ester functionality susceptible to acid-catalyzed deprotection of carboxylic acids, a carbosilane, and a metal oxide treatment functionality susceptible to acid-catalyzed deprotection or cross-linking.

In one embodiment, the wavelength is approximately 365 nm. In one embodiment, the acid-removable photoresist material is substantially absorbing at a wavelength of approximately 13.5 nm. In one embodiment, the acid-removable photoresist material is substantially absorbing at energies in the range of approximately 5-150 keV. In one embodiment, the molar ratio of the PAG component to the base-generating component is at least 50:1.

Referring again to Figures 30A-30E, 30A' and 30A", according to an embodiment of the present invention, a method of selecting a photobucket for semiconductor processing includes providing a structure having a first photobucket 3002 adjacent to a second photobucket 3004. The structure is exposed to extreme ultraviolet (EUV) or electron beam radiation 3006, wherein the first photobucket 3002 is exposed to the EUV or electron beam radiation 3006 to a greater extent than the second photobucket 3004. After exposing the structure to the EUV or electron beam radiation 3006, the first and A first bake of the second photobucket is performed, as described in connection with FIG30B . After the first bake, the structure is exposed to ultraviolet (UV) radiation, wherein the first photobucket is exposed to UV radiation to approximately the same degree as the second photobucket, as described in connection with FIG30C . After exposing the structure to UV radiation, a second bake of the first and second photobuckets is performed, as described in connection with FIG30D . After the second bake, the structure is developed. The development is performed by turning on the first photobucket and leaving the second photobucket closed, as described in connection with FIG30E .

In one embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam irradiation includes exposing the structure to energy having a wavelength of approximately 13.5 nanometers. In another embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam irradiation includes exposing the structure to energy in the range of 5-150 keV. In one embodiment, exposing the structure to UV irradiation includes exposing the structure to energy having a wavelength of approximately 365 nanometers. In one embodiment, the first bake is performed at a temperature in the range of approximately 50-120 degrees Celsius for a duration in the range of approximately 0.5-5 minutes. In one embodiment, the second bake is performed at a temperature in the range of approximately 100-180 degrees Celsius for a duration in the range of approximately 0.5-5 minutes.

In one embodiment, specifically referring to FIG. 30A , the first and second photobuckets each include a photodegradable composition comprising an acid-removable photoresist material, a photoacid-generating (PAG) component, and a photoradical-generating component. In one such embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam irradiation includes activating the PAG component. The first bake diffuses the acid formed from the activated PAG component throughout the first and second photobuckets. Exposing the structure to UV irradiation includes activating the photoradical-generating component. The second bake utilizes the radicals generated from the photoradical-generating component to suppress the total amount of acid formed in the second photobucket, but does not suppress the total amount of acid formed in the first photobucket.

In another embodiment, specifically referring to Figure 30A', the first and second photobuckets each include a grafted photoradical generating component (along the bottom and sidewalls of the first and second photobuckets) and a photodegradable component (formed within the grafted photoradical generating component). The photodegradable component includes an acid-removable protective photoresist material and a photoacid generating (PAG) component. In one such embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam irradiation includes activating the PAG component. The first bake diffuses the acid formed from the activated PAG component throughout the first and second photobuckets. Exposing the structure to UV irradiation includes activating the grafted photoradical generating component. The second bake utilizes the radicals generated from the photoradical generating component to suppress the total amount of acid formed in the second photobucket, but does not suppress the total amount of acid formed in the first photobucket.

In another embodiment, specifically referring to FIG. 30A , the first and second photobuckets each include a photodegradable composition comprising an acid-removable photoresist material and a photoacid generating (PAG) component. The method further includes forming a layer comprising a radical generating component on the first and second photobuckets after performing the first bake and before exposing the structure to ultraviolet (UV) irradiation. In one such embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam irradiation includes activating the PAG component. The first bake diffuses the acid formed from the activated PAG component throughout the first and second photobuckets. Exposing the structure to UV irradiation includes activating the radical generating component. The second bake utilizes the radicals generated from the radical generating component to suppress the total amount of acid formed in the second photobucket, but does not suppress the total amount of acid formed in the first photobucket.

In any of the above cases, in one embodiment, developing the structure comprises (in the case of positive tone development) immersion or application of a standard aqueous TMAH developer (e.g., in a concentration range of 0.1M-1M) or other aqueous or alcoholic developer based on tetramethylammonium hydroxide for 30-120 seconds, followed by rinsing with DI water. In another embodiment, in the case of negative tone development, developing the structure comprises immersion or application of an organic solvent (e.g., cyclohexanone, 2-heptanone, propylene glycol methyl ethyl acetate, or others), followed by rinsing with another organic solvent (e.g., hexane, heptane, cyclohexane, etc.).

In an exemplary embodiment, the approach described above is based on the use of a so-called photobucket approach, in which each possible feature (e.g., a via) is pre-patterned into the substrate. Then, a photoresist is filled into the patterned features and a lithography operation is used only to select selected vias for via opening formation. In a specific embodiment, a lithography operation is used to define relatively large holes on a plurality of photobuckets that include a second-stage baked photoresist, as described above. The second-stage baked photoresist photobucket approach allows for larger critical dimensions (CD) and/or overlap errors while retaining the ability to select the vias of interest.

According to embodiments of the present invention, image tone inversion of resists (e.g., for photobuckets) is described. One or more embodiments described herein relate to a material class having special properties that enable pattern inversion (e.g., hole to pillar inversion), and related processing methods and structures derived from the material class. The material class can be a soft material class, such as a photoresist-like material. As a general approach, the resist-like material is deposited in a pre-patterned hard mask. The resist-like material can then be selected using a high-resolution lithography tool (e.g., an extreme ultraviolet (EUV) processing tool). Alternatively, the resist-like material can be left permanently in the final fabricated structure, such as an interlayer dielectric (ILD) material or structure ("plug") that forms a break between metal lines. Overlap (edge layout) issues anticipated for next-generation plug patterning can be addressed by one or more of the approaches described herein.

More specifically, one or more embodiments described herein relate to the use of a spin-on dielectric (e.g., an ILD) having the unique property of enabling the filling of holes ("buckets") in a patterned photoresist layer without disrupting the photoresist layer pattern. First, the spin-on dielectric material is introduced into a solvent that does not dissolve or cause intermixing of the photoresist and dielectric materials. It is understood that good fillability of the holes is desirable. Initial crosslinking (or setting) of the spin-on dielectric film is accomplished under conditions where the photoresist and spin-on dielectric do not intermix and lose pattern information. Once the pattern is reversed, the material in the barrel is then converted (via baking/curing) to a dielectric with the desired properties (e.g., k-value, modulus, etch selectivity, etc.). Although not limited to such materials, spin-on dielectric materials based on 1,3,5-trisilacyclohexane (1,3,5-trisilacyclohexane) can be implemented to meet the above criteria. Crosslinking with solubility loss of this material (or other silicon-based dielectrics) can be initiated (thermally or at lower temperatures) by using acid, base, or Lewis acid catalyst processes. In one embodiment, this low-temperature catalysis is critical to the implementation of the methods described herein.

In one embodiment, the approach described herein involves exploiting the best imaging properties (e.g., from positive-tone materials) to produce negative-tone patterns, where the final film process is focused on material properties. The final material properties can be comparable to those of high-performance low-k dielectric/ILD materials. In contrast, state-of-the-art options for direct patterning of dielectric films are limited and are not expected to exhibit the necessary lithographic performance to be manufacturable in future scaling generations.

As described in more detail below in conjunction with Figures 31 and 32A-32H, according to the embodiments described herein, trenches in the ILD material are pre-patterned and filled with a chemically amplified photoresist. Using high-resolution lithography (e.g., EUV), selected holes within the trenches are exposed and removed via conventional positive tone processing. At this stage, the empty holes are treated with a pre-catalyst layer. In one such embodiment, the pre-catalyst layer is a self-polymerizing monolayer (SAM) containing an additional catalyst layer. The resulting decorated holes are then filled with a dielectric precursor with accompanying overloading. The localization (or proximity) of the catalyst in the holes results in selective crosslinking and setting of the dielectric only in those holes. The overburden and photoresist are removed, followed by final hardening of the dielectric (if required) and metallization process.

According to embodiments of the present invention, a key feature of the methods described herein involves the adaptation of varying pattern density and thickness of overburden. In one embodiment, this adaptation is enabled because crosslinking occurs only in/near the pores and the overburden is ultimately removed by planarization (e.g., by chemical mechanical polishing). In one embodiment, selective crosslinking of the dielectric material in the pores is achieved without incurring selective crosslinking in areas of overburden. In a specific embodiment, subsequent to positive-tone lithographic patterning and development, a hydrophilic Si—OH terminated surface is exposed in the pores and anywhere the photoresist has been removed. The hydrophilic surface can exist before the photoresist is applied or can be created during, for example, tetramethylammonium hydroxide (TMAH) development or subsequent cleaning. It is understood that the photoresist that has not been exposed and developed will remain mildly or strongly hydrophobic in nature, and therefore, the patterning process effectively creates hydrophilic and hydrophobic domains.

In one embodiment, the exposed hydrophilic surface is functionalized with a surface grafting agent that carries the catalyst or pre-catalyst required for cross-linking the dielectric material. Subsequent coating of the dielectric results in filling of the pores using overloading, as described above, and as explained in more detail below. Upon activation and controlled diffusion of the pre-catalyst using, for example, a low temperature bake, the dielectric material is selectively cross-linked in the pores, with minimal cross-linking occurring in the overloading, i.e., directly above the pores. The overloaded dielectric material can then be removed using dissolution in the casting solvent or another solvent. It should be understood that the removal process can also remove the photoresist, or the photoresist can be removed using another solvent or by an ashing process. In one embodiment, with the color tone reversed, the dielectric material may be baked/hardened at a relatively high temperature prior to metallization or other processing.

In one or more of the embodiments described herein, there are several ways to position the catalyst or pre-catalyst in the pores. For certain dielectric materials, a strong Bronsted acid is required. In other cases, a strong Lewis acid may be utilized. For simplicity of description herein, the term "acid" is used to refer to both scenarios. In one embodiment, direct absorption of the catalyst or pre-catalyst is utilized. In this scenario, the catalyst is coated onto a hydrophilic surface and is securely held there by H bonding or other electrostatic interactions. Subsequent coating of the dielectric material results in the acid and dielectric precursor being localized in the pores, where thermal or other activation initiates the desired crosslinking chemistry. In an exemplary embodiment, the reaction of a Si-OH-rich surface with the strong Lewis acid B(C ₆ F ₅ ) ₃ results in the formation of Si-OB(C ₆ F ₅ ) ₃ H ⁺ . This resulting Lewis acid is used to catalyze the crosslinking of hydrosilane precursor molecules at relatively lower temperatures than non-catalyzed processes. In one embodiment, the bulky catalyst employed minimizes diffusion into the overload region.

In another embodiment, the method involves covalent bonding of a catalyst or pre-catalyst via a silane chemical, such as chloro, alkoxy, and amine silanes, or other surface-grafting groups, which may include siloxanes, silyl chlorides, alkenes, alkynes, amines, phosphines, thiols, phosphonic acids, or carboxylic acids. In this case, the catalyst or pre-catalyst is covalently linked to the grafting agent. For example, well-known acid generators (e.g., light or heat) based on onium salts can be attached to siloxanes (e.g., [(MeO) _3Si - _CH2CH2CH2SR2 ][X], where R = alkyl or _aryl group and X = weakly coordinating anion, such as trifluoromethanesulfonate, nonaflate, _HB ( _C6F5 ) ₃ , _BF4 , _etc. ). The catalyst or pre-catalyst can be selectively attached to the ILD _of interest or selectively removed from the resist using thermal, dry, or wet etch processes. In yet another embodiment, a catalyst or pre-catalyst is introduced before the photoresist is applied using similar techniques. In this case, to be effective, the grafting material must not interfere with lithography and must withstand subsequent processing.

As an example means of illustrating the concepts described herein, FIG. 31 illustrates an oblique angled view of alternating interlayer dielectric (ILD) lines and resist lines, with a hole formed in one of the resist lines, according to an embodiment of the present invention. Referring to FIG. 31 , pattern 3100 includes alternating ILD lines 3102 and resist lines 3104. A hole 3106 is formed in one of the resist lines 3104, for example, by conventional lithography. As described below in connection with FIG. 32A-32H , patterns such as pattern 3100 can undergo tone inversion.

In an example process flow, Figures 32A-32H illustrate cross-sectional views of a manufacturing process involving image tone inversion with dielectrics using bottom-up cross-linking, according to an embodiment of the present invention.

FIG32A illustrates a cross-sectional view of the starting structure following pre-patterning of trenches 3204 in ILD material 3202. Selected trenches 3204 are filled with a chemically amplified photoresist 3206, while others are processed to provide unfilled trenches (or unfilled trench portions, as shown in FIG31 ). For example, in one embodiment, using high-resolution lithography (e.g., extreme ultraviolet (EUV) lithography), selected holes within the trenches 3204 are exposed and removed via conventional positive-tone processing.

Although not depicted for simplicity, it should be understood that unfilled trenches (or holes formed within filled trenches) can expose underlying features, such as underlying metal lines, in region 3208. Furthermore, in one embodiment, the starting structure can be patterned with a grating pattern having trenches spaced at a constant pitch and having a constant width. The pattern can be fabricated, for example, by halving or quartering the pitch. Some trenches may be associated with underlying vias or lower-level metallization lines.

FIG32B illustrates a cross-sectional view of the structure of FIG32A following the placement of a blank trench or hole with a pre-catalyst layer 3210 (which, in one embodiment, is a self-polymerizing monolayer (SAM) containing a catalyst material). In one such embodiment, as shown, pre-catalyst layer 3210 is formed on exposed portions of ILD 3202, but not on exposed portions of etch resist 3206 or any exposed metal (such as on region 3208). In one embodiment, pre-catalyst layer 3210 is formed by exposing the structure of FIG32A to pre-catalyst-forming molecules in a gas phase or dissolved in a solvent. In one embodiment, the pre-catalyst layer is a catalyst or a pre-catalyst layer formed by direct adsorption, as described above. In another embodiment, the pre-catalyst layer 3210 is a catalyst or a pre-catalyst layer formed by covalent adhesion.

FIG32C illustrates a cross-sectional view of the structure of FIG32B after the resulting decorative holes have been filled with dielectric material 3212. It should be understood that dielectric material 3212 has a portion 3212A that fills the trenches or holes and a portion 3212B that overlies the trenches or holes. Portion 3212B is referred to herein as an overburden. In one embodiment, dielectric material 3212 is a spin-on dielectric material.

In one embodiment, dielectric material 3212 is selected from the class of materials based on hydrosilane precursor molecules, where a catalyst mediates the reaction of Si-H bonds with a crosslinker such as water, tetraethoxysilane (TEOS), hexaethoxytrisilacyclohexane, or a similar multifunctional crosslinker. In one such embodiment, dielectric material 3212 includes trisilacyclohexane, which can be subsequently linked via O groups. In other embodiments, alkoxysilane-based dielectric precursors or semisiloxanes (SSQs) are used for dielectric material 3212.

FIG32D illustrates a cross-sectional view of the structure of FIG32C following crosslinking of portion 3212A of dielectric material 3212. In one embodiment, localization (or proximity) of the catalyst (e.g., pre-catalyst layer 3210) within unfilled trenches or pores results in selective crosslinking to form crosslinked regions 3214 and placement of portion 3212A of dielectric material 3212 only within those pores. That is, in one embodiment, portion 3212B of dielectric material 3212 is not crosslinked. In one embodiment, crosslinking to form region 3214 is achieved by a thermal curing process (i.e., by applying heat).

In one embodiment, dielectric material 3212 comprises trisilane, and the crosslinks used to form region 3214 include crosslinking trisilane molecules together through O groups. Referring to FIG. 33A , trisilane 3300 is illustrated. Referring to FIG. 33B , two crosslinked (XL) trisilane molecules 3300 form crosslinked material 3320. FIG. 33C illustrates an idealized representation of a linked trisilane structure 3340. It should be understood that structure 3340 is, in practice, a complex mixture of oligomers, but with the commonality being H-capped trisilane rings.

FIG32E illustrates a cross-sectional view of the structure of FIG32D following removal of the overburden region 3212B of the dielectric material 3212. FIG32F illustrates a cross-sectional view of the structure of FIG32E following removal of the etch resist 3206 selective to the cross-link region 3214. In one embodiment, as depicted, the etch resist 3206 is removed in a subsequent and different processing operation (e.g., a second wet chemical development operation) relative to the processing operation used to remove the overburden region 3212B of the dielectric material 3212 (e.g., a first wet chemical development operation). However, in another embodiment, the etch resist 3206 is removed during the same processing operation (e.g., a wet chemical development operation) used to remove the overburden regions 3212B of the dielectric material 3212. In one embodiment, the remaining cross-link regions 3214 are subjected to an additional curing process (e.g., additional heating subsequent to the cross-link curing process). In one embodiment, the additional curing is performed subsequent to the removal of the etch resist 3206 and the overburden regions 3212B.

FIG32G illustrates a cross-sectional view of the structure of FIG32F following the formation of a metal fill layer 3216. Metal fill layer 3216 can be formed in the opened trenches (or holes) from FIG32F and in the overburden region. The metal fill layer can be a single layer of material or can be formed from multiple layers, including a conductive liner layer and a fill layer. Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) can be used to form metal fill layer 3216. In one embodiment, the metal filling layer 3216 is composed of a conductive material, such as (but not limited to) Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au or alloys thereof.

FIG32H illustrates a cross-sectional view of the structure of FIG32G following planarization of the metal fill layer to form metal features 3218 (e.g., metal lines or vias). In one embodiment, planarization of the metal fill layer 3216 to form the metal features 3218 is performed using a chemical mechanical polishing process. The resulting structure is shown in FIG32H , in which the metal features 3218 are alternating with cross-link (dielectric) regions 3214 in the ILD material 3202.

It should be understood that the resulting structure of FIG. 32H can then be used as a foundation for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 32H could represent the final metal interconnect layer in an integrated circuit. Furthermore, it should be understood that the above example does not include etch stop or metal capping layers in the diagram, which may be required for patterning. However, for clarity, these layers are not included in the diagram as they do not affect the overall bottom-up fill concept.

32A-32H , this patterning scheme can be implemented as an integrated patterning approach that involves creating a regular structure covering all possible locations, followed by selective patterning of only desired features. The interconnect region 3214 represents a material that may remain in the final structure as an ILD between the ends of the metal lines (e.g., as a plug).

According to embodiments of the present invention, a diagonal hard mask patterning method is described. One or more embodiments described herein are directed to diagonal hard mask patterning for overlay improvement, particularly in the fabrication of back-end-of-line (BEOL) features for semiconductor integrated circuits. Applications for patterning based on the diagonal hard mask may include, but are not limited to, the following: 193 nm immersion lithography, extreme ultraviolet (EUV) lithography, interconnect fabrication, overlay improvement, overlay budgeting, plug patterning, and via patterning. Embodiments may be particularly useful for self-aligned fabrication of BEOL structures.

In one embodiment, the approach described herein relates to an integration scheme that allows for increased via and plug overlap tolerance relative to existing approaches. In one such embodiment, all potential vias and plugs are pre-patterned and filled with resist to form a plurality of photobuckets. Thereafter, in a particular embodiment, EUV or 193nm lithography is used to select certain via and plug locations for actual (final) via and plug fabrication. In one embodiment, diagonal patterning is used to increase the nearest neighbor distance, which results in an increase in the overlap budget by a factor of the square root of two. More specifically, one or more of the embodiments described herein relate to using a subtractive method to pre-form each via and plug using etched trenches. An additional operation is then used to select which vias and plugs remain. These operations are performed using a photobucket, although a more traditional resist exposure and ILD backfill approach could also be used to perform the selection process.

In one embodiment, a diagonal hard masking method can be implemented. As an example, Figures 34A-34X illustrate portions of an integrated circuit layer representing various operations in a method for self-aligned via and plug patterning using a diagonal hard mask, according to an embodiment of the present invention. In each of the figures illustrating each of the described operations, cross-sectional and/or plan and/or oblique views are shown. These views will be referred to herein as cross-sectional, plan, and oblique views, respectively.

FIG34A illustrates a cross-sectional view of a starting structure 3400 after deposition (but before patterning) of a first hard mask material layer 3404 formed on an interlayer dielectric (ILD) layer 3402, according to an embodiment of the present invention. Referring to FIG34A , a patterned mask 3406 has spacers 3408 formed on or above (along the sidewalls of) the first hard mask material layer 3404.

FIG34B illustrates a cross-sectional view of the structure of FIG34A following patterning of the first hard mask layer by pitch doubling, in accordance with an embodiment of the present invention. Referring to FIG34B , the patterned mask 3406 is removed and the resulting pattern of the spacers 3408 is transferred (e.g., by an etching process) to the first hard mask material layer 3404 to form a first patterned hard mask 3410. In one such embodiment, the first patterned hard mask 3410 is formed with a grating pattern, as depicted in FIG34B . In one embodiment, the grating structure of the first patterned hard mask 3410 is a fine-pitch grating structure. In this particular embodiment, the fine pitch cannot be directly achieved by conventional lithography. For example, a pattern based on conventional lithography can be first formed (mask 3406), but the pitch can be halved by patterning using a spacer mask, as depicted in Figures 34A and 34B. Furthermore, although not shown, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern of the first patterned hard mask 3410 of Figure 34B can have hard mask lines separated by a constant pitch and having a constant width.

FIG34C illustrates a cross-sectional view of the structure of FIG34B following formation of a second patterned hard mask, according to an embodiment of the present invention. Referring to FIG34C , a second patterned hard mask 3412 is formed to intersect with the first patterned hard mask 3410. In one such embodiment, the second patterned hard mask 3412 is formed by depositing a second hard mask material layer (e.g., having a different composition than the first hard mask material layer 3404). The second hard mask material layer is then planarized (e.g., by chemical mechanical polishing (CMP)) to provide the second patterned hard mask 3412.

FIG34D illustrates a cross-sectional view of the structure of FIG34C following deposition of a hard mask capping layer (third hard mask layer), according to an embodiment of the present invention. Referring to FIG34D , a hard mask capping layer 3414 is formed over the first patterned hard mask 3410 and the first patterned hard mask 3412. In one such embodiment, the material composition and etch selectivity of the hard mask capping layer 3414 are different from those of the first patterned hard mask 3410 and the first patterned hard mask 3412.

FIG34E illustrates an oblique angle view of the structure of FIG34D following patterning of the hard mask capping layer, according to an embodiment of the present invention. Referring to FIG34E , a patterned hard mask capping layer 3414 is formed on the first patterned hard mask 3410 and the first patterned hard mask 3412. In one such embodiment, the patterned hard mask capping layer 3414 is formed with a grating pattern that is orthogonal to the grating pattern of the first patterned hard mask 3410 and the first patterned hard mask 3412, as shown in FIG34E . In one embodiment, the grating structure formed by the patterned hard mask capping layer 3414 is a close-pitch grating structure. In such an embodiment, a tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Even further, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern of the patterned hard mask capping layer 3414 of FIG. 34E can have hard mask lines separated by a constant pitch and having a constant width. It should be understood that the description herein regarding forming and patterning a hard mask layer (or hard mask capping layers, such as hard mask capping layer 3414) involves (in one embodiment) a mask being formed over an overlying hard mask or hard mask capping layer. The mask formation may involve the use of one or more layers suitable for lithographic processing. Upon patterning the one or more lithographic layers, the pattern is transferred to the hard mask or hard mask capping layer by an etching process to provide a patterned hard mask or hard mask capping layer.

FIG34F illustrates an oblique angle view and corresponding plan view of the structure of FIG34E after further patterning of the first patterned hard mask, according to an embodiment of the present invention. Referring to FIG34F , the first patterned hard mask 3410 is further patterned to form a first patterned hard mask 3416 using a patterned hard mask capping layer 3414 as a mask. The second patterned hard mask 3412 is not further patterned in this process. In one embodiment, the first patterned hard mask 3410 is patterned to a depth sufficient to expose areas of the ILD layer 3402, as depicted in FIG34F .

FIG34G illustrates a plan view of the structure of FIG34F following removal of the hard mask capping layer and formation of a fourth hard mask layer, according to an embodiment of the present invention. Referring to FIG34G , hard mask capping layer (third hard mask layer) 3414 is removed, for example, by a wet etch process, a dry etch process, or a CMP process. A fourth hard mask layer 3418 is formed over the resulting structure by (in one embodiment) a deposition and CMP process. In one such embodiment, fourth hard mask layer 3418 is formed by depositing a material layer different from the material of second patterned hard mask layer 3412 and first patterned hard mask layer 3416.

FIG34H illustrates a plan view of the structure of FIG34G following deposition and patterning of the first diagonal hard mask layer, according to an embodiment of the present invention. Referring to FIG34H , a first diagonal hard mask layer 3420 is formed over the fourth hard mask layer 3418, the second patterned hard mask layer 3412, and the first patterned hard mask layer 3416 of FIG34G . In one embodiment, the first diagonal hard mask layer 3420 has a substantially or highly symmetrical diagonal pattern (e.g., at 45 degrees relative to the grating structure of the second patterned hard mask layer 3412) to cover the alternating lines of the fourth hard mask layer 3418. In one embodiment, the diagonal pattern of the first diagonal hard mask layer 3420 is printed at a minimum critical dimension (CD), i.e., without using pitch halving or pitch quartering. It should be understood that individual lines can be printed even larger than the minimum CD, as long as some area of the adjacent columns of the fourth hard mask layer 3418 remains visible. Regardless, the grating pattern of the first diagonal hard mask layer 3420 of FIG. 34H can have hard mask lines separated by a constant pitch and having a constant width. It should be understood that the description herein regarding forming and patterning diagonal hard mask layers (such as the first diagonal hard mask layer 3420) relates to (in one embodiment) the mask being formed over an overlying hard mask layer. The mask formation may involve the use of one or more layers suitable for lithographic processing. Upon patterning the one or more lithographic layers, the pattern is transferred to the hard mask layer by an etching process to provide a diagonally patterned hard mask layer. In a specific embodiment, the first diagonal hard mask layer is a carbon-based hard mask layer.

FIG34I illustrates a plan view of the structure of FIG34H following removal of the exposed areas of the fourth hard mask layer, according to an embodiment of the present invention. Referring to FIG34I , the exposed areas of the fourth hard mask layer 3418 are removed using the first diagonal hard mask layer 3420 as a mask. In one such embodiment, the exposed areas of the fourth hard mask layer 3418 are removed by an isotropic etch process (e.g., a wet etch process or a non-isotropic plasma etch process) such that any partial exposure results in complete removal of the partially exposed areas of the fourth hard mask material. In one embodiment, the areas where the fourth hard mask layer 3418 has been removed expose portions of the ILD layer 3402, as depicted in FIG34I .

FIG34J illustrates a plan view of the structure of FIG34I following removal of the first diagonal hard mask layer, according to an embodiment of the present invention. Referring to FIG34J , the first diagonal hard mask layer 3420 is removed to reveal the first patterned hard mask layer 3416 and the second patterned hard mask layer 3412. Also revealed are portions of the fourth hard mask layer 3418, which were protected from the isotropic etching by the first diagonal hard mask layer 3420. Thus, along alternating rows or down alternating columns of the resulting grid pattern of FIG34J , areas of the fourth hard mask layer 3418 alternate with exposed areas of the underlying ILD layer 3402. That is, the result is a checkerboard pattern of the ILD layer 3402 region and the fourth hard mask layer region 3418. Thus, an increase of a factor of the square root of two is achieved at the nearest neighbor distance 3422 (shown as the distance in direction b). In a specific embodiment, the first diagonal hard mask layer 3420 is a carbon-based hard mask material and is removed using a plasma ashing process.

FIG34K illustrates a plan view of the structure of FIG34J subsequent to the formation of the first plurality of photobuckets, according to an embodiment of the present invention. Referring to FIG34K , the first plurality of photobuckets 3424 are formed in the openings above the ILD layer 3402 such that no portion of the ILD layer 3402 remains exposed. The photobuckets 3424 (at this stage) represent the first half of all possible via locations in the resulting metallization layer.

FIG34L illustrates a plan view and corresponding cross-sectional view (taken along the a-a' axis) of the structure of FIG34K after subsequent exposure and development of the photobucket to form the selected via location and subsequent etching of the via opening into the underlying ILD layer, according to an embodiment of the present invention. Referring to FIG34L, the selected photobucket 3424 is exposed and removed to provide the selected via location 3426. The via location 3426 undergoes a selective etching process (such as a selective plasma etching process) to extend the via opening into the underlying ILD layer 3402, forming a patterned ILD layer 3402'. The etching is selective to the remaining (unexposed) photobucket 3424 , the first patterned hard mask layer 3416 , the second patterned hard mask layer 3412 , and the fourth hard mask layer 3418 .

FIG34M illustrates a plan view and corresponding cross-sectional view (taken along the b-b' axis) of the structure of FIG34L following removal of the remaining photobuckets and subsequent formation of a fifth hard mask material, according to an embodiment of the present invention. Referring to FIG34M, the remainder of the first plurality of photobuckets 3424 are removed, for example, by a selective etching or graying process. All exposed openings (e.g., openings formed when the photobuckets 3424 are removed along with the through-hole locations 3426) are then filled with a hard mask material 3428, such as a carbon-based hard mask material.

FIG34N illustrates a plan view and corresponding cross-sectional view (taken along the c-c' axis) of the structure of FIG34M after the remaining areas of the fourth hard mask layer have been removed, according to an embodiment of the present invention. Referring to FIG34N , all remaining areas of the fourth hard mask layer 3418 have been removed, for example, by a selective etching or graying process. In one embodiment, the areas where the fourth hard mask layer 3418 has been removed reveal portions of the patterned ILD layer 3402', as depicted in FIG34N .

FIG34O illustrates a plan view and corresponding cross-sectional view (taken along the d-d' axis) of the structure of FIG34N following formation of a second plurality of photobuckets, according to an embodiment of the present invention. Referring to FIG34O , a second plurality of photobuckets 3430 are formed in the openings above the patterned ILD layer 3402' such that no portion of the patterned ILD layer 3402' remains exposed. The photobuckets 3430 (at this stage) represent the second half of all possible via locations in the resulting metallization layer.

FIG34P illustrates a plan view and corresponding cross-sectional view (taken along the e-e' axis) of the structure of FIG34O after subsequent exposure and development of the photobucket to form the selected via locations, and subsequent etching of the via openings into the underlying ILD, according to an embodiment of the present invention. Referring to FIG34P , the selected photobucket 3430 is exposed and removed to provide the selected via locations 3432. The via location 3432 undergoes a selective etching process (e.g., a selective plasma etching process) to extend the via opening into the underlying patterned ILD layer 3402′, forming a further patterned ILD layer 3402″. The etching is selective to the remaining (unexposed) photobucket 3430, the first patterned hard mask layer 3416, the second patterned hard mask layer 3412, and the hard mask material 3428.

FIG34Q illustrates a plan view and corresponding cross-sectional view (taken along the f-f' axis) of the structure of FIG34P following removal of the fifth hard mask material, trench etching, and subsequent sacrificial layer formation, in accordance with an embodiment of the present invention. Referring to FIG34Q, the hard mask material layer 3428 is removed, revealing all of the original first and second halves of the potential via locations. The patterned ILD layer 3402″ is then patterned to form an ILD layer 3402″, which includes via openings 3432 and 3426, along with trenches 3436 in which the via openings are not formed. Trench 3436 will ultimately be used for metal line fabrication, as described below. Upon completion of the trench etch, all openings (including via openings 3426 and 3432 and trench 3436) are filled with sacrificial material 3434. In one such embodiment, hard mask material layer 3428 is a carbon-based hard mask material and is removed using a plasma ashing process. In one embodiment, sacrificial material 3434 is a flowable organic or inorganic material, such as a sacrificial light absorbing material (SLAM). Sacrificial material 3434 is formed to (or planarized to) the level of first patterned hard mask 3416 and second patterned hard mask 3412, as depicted in FIG34Q.

FIG34R illustrates a plan view of the structure of FIG34Q following deposition and patterning of a second diagonal hard mask layer, according to an embodiment of the present invention. Referring to FIG34R , a second diagonal hard mask layer 3438 is formed over the sacrificial material 3434, the second patterned hard mask layer 3412, and the first patterned hard mask layer 3416 arrangement of FIG34Q. In one embodiment, the second diagonal hard mask layer 3438 has a substantially or highly symmetrical diagonal pattern (e.g., at 45 degrees relative to the grating structure of the second patterned hard mask layer 3412) to cover the alternating lines of the first patterned hard mask layer 3416. In one embodiment, the diagonal pattern of the second diagonal hard mask layer 3438 is printed at a minimum critical dimension (CD), that is, without using pitch halving or pitch quartering. It should be understood that individual lines can be printed even larger than the minimum CD, as long as some area of adjacent columns of the first hard mask layer 3416 remains visible. Regardless, the grating pattern of the second diagonal hard mask layer 3438 of Figure 34R can have hard mask lines separated by a constant pitch and having a constant width. It should be understood that the description herein regarding forming and patterning diagonal hard mask layers (such as the second diagonal hard mask layer 3438) relates to (in one embodiment) the mask being formed over an overlying hard mask layer. The mask formation may involve the use of one or more layers suitable for lithographic processing. Upon patterning the one or more lithographic layers, the pattern is transferred to the hard mask layer by an etching process to provide a diagonally patterned hard mask layer. In a specific embodiment, the second diagonal hard mask layer 3438 is a carbon-based hard mask layer.

FIG34S illustrates a plan view and corresponding cross-sectional view (taken along the g-g' axis) of the structure of FIG34R following the removal of the exposed areas of the first patterned hard mask layer, the removal of the second diagonal hard mask layer, and the formation of the third plurality of photobuckets, according to an embodiment of the present invention. Referring to FIG34S , the exposed areas of the first hard mask layer 3416 are removed using the second diagonal hard mask layer 3438 as a mask. In one such embodiment, the exposed areas of the first patterned hard mask layer 3416 are removed by an isotropic etching process (e.g., a wet etching process or a non-isotropic plasma etching process) such that any partial exposure results in complete removal of the partially exposed areas of the first patterned hard mask layer 3416. Referring again to FIG34S, the second diagonal hard mask layer 3438 is removed to expose the sacrificial material 3434 and the second patterned hard mask layer 3412. Also exposed are the portions of the first hard mask layer 3416 that were protected from the isotropic etching by the second diagonal hard mask layer 3438. In a particular embodiment, the second diagonal hard mask layer 3438 is a carbon-based hard mask material and is removed by a plasma ashing process. Referring again to FIG. 34S , a third plurality of photobuckets 3440 are formed in the resulting openings above the patterned ILD layer 3402 '' so that no portion of the patterned ILD layer 3402 '' remains exposed. The photobuckets 3440 (at this stage) represent the first half of all possible plug locations in the resulting metallization layer. Thus, along each alternating row of the resulting grid pattern of FIG. 34S or down toward each alternating line of the resulting grid pattern of FIG. 34S , regions of the first patterned hard mask layer 3416 are alternately arranged with the photobuckets 3440. That is, the result is a checkerboard pattern in the area of the light bucket 3440 and the area of the first patterned hard mask layer 3416. In this way, an increase of a factor of the square root of two is achieved in the nearest neighbor distance 3442 (shown as the distance in direction b).

Figure 34T illustrates a plan view and corresponding cross-sectional view (taken along the h-h' axis) of the structure of Figure 34S following plug position selection and trench etching, according to an embodiment of the present invention. Referring to Figure 34T, the photobucket 3440 from Figure 34S is removed from the position 3442 where the plug will not be formed. The photobucket 3440 is retained in the position selected to form the plug. In one embodiment, in order to form the position 3442 where the plug will not be formed, lithography is used to expose the corresponding photobucket 3440. The exposed photobucket can then be removed by a developer. The patterned ILD layer 3402''' is then patterned to form an ILD layer 3402''', which includes trenches 3444 formed at locations 3442. The trenches 3444 will ultimately be used for metal line fabrication, as described below.

FIG34U illustrates a plan view and corresponding cross-sectional view (taken along the i-i' axis) of the structure of FIG34T following removal of the remaining third photobuckets and subsequent hard mask formation, according to an embodiment of the present invention. Referring to FIG34U, all remaining photobuckets 3440 are removed, for example, by an ashing process. Upon removal of all remaining photobuckets 3440, all openings (including trenches 3444) are filled with a hard mask material layer 3446. In one embodiment, the hard mask material layer 3446 is a carbon-based hard mask material.

FIG34V illustrates a plan view and corresponding cross-sectional view (taken along the j-j' axis) of the structure of FIG34V subsequent to the removal of the first patterned hard mask and the formation of the fourth plurality of photobuckets, according to an embodiment of the present invention. Referring to FIG34V, the first patterned hard mask layer 3416 is removed (e.g., by a selective dry or wet etch process), and a fourth plurality of photobuckets 3448 are formed in the resulting openings above the patterned ILD layer 3402''' such that no portion of the patterned ILD layer 3402''' remains exposed. The photobuckets 3448 (at this stage) represent the second half of all possible plug locations in the resulting metallization layer.

FIG34W illustrates a plan view and corresponding cross-sectional view (taken along the k-k' axis) of the structure of FIG34V following plug location selection and trench etching, according to an embodiment of the present invention. Referring to FIG34W , the photobucket 3448 from FIG34V is removed from the position 3450 where the plug will not be formed. The photobucket 3448 is retained in the position selected to form the plug. In one embodiment, in order to form the position 3450 where the plug will not be formed, lithography is used to expose the corresponding photobucket 3448. The exposed photobucket can then be removed by a developer. The patterned ILD layer 3402''' is then patterned to form an ILD layer 3402'''', which includes a trench 3452 formed at location 3450. The trench 3452 will ultimately be used for metal line fabrication, as described below.

FIG34X illustrates a plan view and corresponding first cross-sectional view (taken along the l-l' axis) and second cross-sectional view (taken along the m-m' axis) of the structure of FIG34W following the removal of the remaining fourth photobucket, the hard mask material layer, and the sacrificial material, and subsequent metal filling, according to an embodiment of the present invention. Referring to FIG34X, the remaining fourth photobucket 3448, the hard mask material layer 3446, and the sacrificial material 3434 are removed. In one such embodiment, the hard mask material layer 3446 is a carbon-based hard mask material, and both the hard mask material layer 3446 and the remaining fourth photobucket 3448 are removed using a plasma ashing process. In one embodiment, the sacrificial material 3434 is removed using a different etching process. Referring to the plan view of FIG34X, the metallization 3454 is formed to be interlaced and coplanar with the second patterned hard mask layer 3412. Referring to the first cross-sectional view taken along the l-l' axis of the plan view of FIG34X, the metallization 3454 fills the trenches 3452 and 3454 formed in the patterned interlayer dielectric layer 3402'''' (i.e., as corresponding to the cross-sectional view taken along the k-k' axis of FIG34W). Referring to the second cross-sectional view taken along the m-m' axis of the plan view of FIG. 34X , the metallization 3454 also fills the trenches 3436 and via openings 3432 and 3426 formed in the patterned interlayer dielectric layer 3402'''' (i.e., as corresponding to the cross-sectional view taken along the f-f' axis of FIG. 34Q ). Thus, the metallization 3454 is used to form a plurality of conductive lines and conductive vias in the interlayer dielectric layer for metallization structures (e.g., BEOL metallization structures).

In one embodiment, the metallization 3454 is formed by a metal fill and polish back process. In one such embodiment, the second patterned hard mask layer 3412 is reduced in thickness during the polish back process. In certain such embodiments, despite the reduction in thickness, a portion of the second patterned hard mask 3412 remains, as depicted in FIG34X. Thus, metal features 3456 (which are not conductive lines or conductive vias formed in the patterned interlayer dielectric layer 3402'''') remain interlaced with the second patterned hard mask layer and located on or above (but not in) the interlayer dielectric layer 3402'''', as also depicted in FIG34X. In an alternative embodiment (not shown), the second patterned hard mask 3412 is completely removed during the polishing pass. Consequently, metal features 3456 (which are neither conductive lines nor conductive vias) do not remain in the final structure. In either case, the structure of FIG. 34X can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 34X can represent the final metal interconnect layer in an integrated circuit.

It should be understood that the above-described process operations may be performed in an alternate order, that not every operation needs to be performed, and/or that additional process operations may be performed. Referring again to FIG. 34X , the metallization layer fabrication using a diagonal hard mask may be completed at this stage. The next layer fabricated in a similar manner may require another complete process initiation. Alternatively, other methods may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene methods.

In one embodiment, as used throughout this specification, an interlayer dielectric (ILD) material is comprised of (or includes) a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO ₂ )), silicon-doped oxides, silicon fluoride oxides, silicon carbon-doped oxides, various low-k dielectric materials known in the art, and combinations thereof. This interlayer dielectric material can be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In one embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. A common example is a structure using copper lines and which may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of several metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and so on. Thus, an interconnect may be a single material layer or may be formed from multiple layers, including a conductive liner layer and a fill layer. Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) can be used to form the interconnects. In one embodiment, the interconnects are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes referred to (in the art) as tracks, wiring, wires, metals, or simply interconnects.

In one embodiment, as also used throughout this specification, the hard mask material is composed of a dielectric material that is different from the interlayer dielectric material. In one embodiment, different hard mask materials can be used in different regions to provide different growth or etch selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer includes a layer of a silicon nitride (e.g., silicon nitride) or a layer of a silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material includes a metal. For example, the hard mask or other overlying material may include a layer of a titanium or other metal nitride (e.g., titanium nitride). Potentially smaller amounts of other materials (such as oxygen) may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used depending on the specific implementation. The hard mask layer may be formed by CVD, PVD, or by other deposition methods.

In one embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), EUV, and/or EBDW lithography, among others. Positive-tone or negative-tone resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topographical shielding portion, an antireflective coating (ARC), and a photoresist layer. In a particular such embodiment, the topographical shielding portion is a carbon hard mask (CHM) layer and the antireflective coating is a silicon ARC layer.

According to the embodiments described herein, optical and SEM metrology for photobuckets are described. It will be appreciated that the use of a pre-patterned hard mask to define the lithographic pattern can make overlay measurement challenging because the response to such patterned exposure is digital (binary) and the feature size is quantized. Therefore, the size of the underlying mask pattern becomes the smallest measurable unit of overlay, which is too large for effective process control. The approach described below not only enables overlay measurement that is much smaller than the size of the underlying pre-patterned hard mask, but also provides a signal response that is amplified by a multiple of the overlay shift, which enables extremely accurate overlay measurement.

To provide a structural framework for the concepts described herein, Figures 35A-35D illustrate cross-sectional views and corresponding top-down views of various operations in a patterning process using a pre-patterned hard mask, according to an embodiment of the present invention.

35A , a first pre-patterned hard mask 3502 and a second pre-patterned hard mask 3504 are formed over an underlying layer 3506. All possible via or plug locations are exposed as openings 3508 in the pre-patterned hard mask 3502 and the second pre-patterned hard mask 3504.

35B , a plurality of photoresist layer portions 3510 are formed in the openings 3508 of FIG. 35A .

35C , selected ones 3512 of the plurality of photoresist layer portions 3510 are exposed by lithographic exposure 3514. The selected ones 3512 of the plurality of photoresist layer portions 3510 exposed by lithographic exposure 3514 may represent via or plug locations that will ultimately be opened or selected.

However, according to an embodiment of the present invention, the lithographic exposure 3514 has an overlay error in the X direction of FIG35C. For example, the exposed photoresist layer 3512 on the left-hand side of the cross-sectional view is shifted to the right to the extent that a portion of its photoresist is not exposed by the lithographic exposure 3514. All exposed photoresist layers 3512 in the top-down view are shifted to the right to the extent that a portion of its photoresist is not exposed by the lithographic exposure 3514. Furthermore, the shift may be substantial enough to partially expose adjacent locations, as depicted in FIG35C.

35D, selected locations 3512 have had the exposed photoresist removed to provide openings 3516. Openings 3516 may be used for subsequent via or plug fabrication, depending on the particular layer of the semiconductor structure.

However, if underexposure of locations 3512 is performed due to overlay errors, some openings 3516 may be catastrophically not fully opened. Typically, exposure 3514 needs to provide a critical number of electrons or photons to completely remove selected ones 3512 of the plurality of photoresist layer portions 3510 to provide openings 3516. Some overlay errors can be tolerated, but significant overlay errors cannot. Furthermore, as described in more detail below, even if all openings 3516 are fully opened, successful fabrication of the next layer may depend, at least to some extent, on an overlay measurement of the openings 3516.

One or more embodiments described herein relate to methods involving the use of a multi-pitch grating structure on a layer to extract overlay information relative to an underlying layer. The embodiments described herein can be implemented to solve the problem of measuring overlay between a layer patterned on top of a pre-patterned hard mask (e.g., a via or plug) and an underlying pre-patterned hard mask layer (e.g., a photobucket) using an optical metrology tool. In one embodiment, the grating is patterned with two or more pitches that are different from, but parallel to, the underlying pre-patterned grating. Shifts in the overlay of the layer relative to the hard mask pattern result in an optical signal that shifts with the overlay and is proportional to the overlay error. In contrast, optical overlays typically involve real features and thus provide an analog response. Here, movement is quantified, unlike in analog motion. That is, the response is digital (e.g., digitized and amplified motion) because it is based on steps. In one embodiment, an "edge" pattern is measured.

Figures 36A-36E described below show the generation of optical signals using light buckets that respond to changes in overlay. It should be understood that traditional optical metrology tools measure relatively large targets (e.g., 20-30 microns). For the embodiments described herein, structures are generated from arrays of lines/spaces that are below the resolution limit of the viewing tool and which utilize the light bucket concept to generate moving edges that can be detected/measured using traditional overlay measurement algorithms. The final pattern seen by the metrology tool shows a measurable optical edge due to diffraction and scattering of light from the sub-resolution pattern as it moves with the overlay. Figure 36F shows a possible optical metrology marking for use with Figures 36A-36E.

FIG36A illustrates a top-down view of an overlay scenario, where the current layer is overlaid on a lower pre-patterned hard mask grid, according to an embodiment of the present invention.

36A , the lower layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604. A plurality of photoresist layer portions 3610 and a plurality of openings 3616 (which have been exposed and developed) are located between the first pre-patterned hard mask 3602 and the second pre-patterned hard mask 3604 structures. The current layer is represented by overlay image 3650A. Overlay image 3650A has an overlay shift of zero and a pitch difference of P/4. The pitch of overlay image 3650A of the current layer is shown as 25% larger (in the upper half 3652A) and 25% smaller (in the lower half 3654A) as an example embodiment. Wide unexposed features 3656A and 3658A are included in the current layer, as depicted in FIG. 36A .

FIG36B illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of one-quarter the pitch relative to the underlying pre-patterned hard mask grid, according to an embodiment of the present invention.

Referring to FIG. 36B , the lower layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604. A plurality of photoresist layer portions 3610 and a plurality of openings 3616 (which have been exposed and developed) are located between the first pre-patterned hard mask 3602 and the second pre-patterned hard mask 3604 structures. The current layer is represented by overlay image 3650B. Overlay image 3650B has a positive (+ve) overlay shift of P/4. Wide unexposed features 3656B and 3658B are included in the current layer, with the shift of these wide unexposed features 3656B and 3658B depicted in FIG. 36B .

FIG36C illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of half the pitch relative to the underlying pre-patterned hard mask grid, according to an embodiment of the present invention.

Referring to FIG. 36C , the lower layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604. A plurality of photoresist layer portions 3610 and a plurality of openings 3616 (which have been exposed and developed) are located between the first pre-patterned hard mask 3602 and the second pre-patterned hard mask 3604 structures. The current layer is represented by overlay image 3650C. Overlay image 3650C has a positive (+ve) overlay shift of P/2. Wide unexposed features 3656C and 3658C are included in the current layer, with the shift of these wide unexposed features 3656C and 3658C depicted in FIG. 36C .

FIG36D illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of an arbitrary value of Δ relative to the underlying pre-patterned hard mask grid, according to an embodiment of the present invention.

Referring to FIG. 36D , the lower layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604. A plurality of photoresist layer portions 3610 and a plurality of openings 3616 (which have been exposed and developed) are located between the first pre-patterned hard mask 3602 and the second pre-patterned hard mask 3604 structures. The current layer is represented by overlay image 3650D. Overlay image 3650D has an overlay shift of zero and a pitch difference of P+Δ. Wide unexposed features 3656D and 3658D are included in the current layer, as depicted in FIG. 36D .

36E illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of an arbitrary value of Δ relative to the underlying pre-patterned hard mask grid, where the measurable Δ can be made as small as desired by varying the resist sensitivity and/or the drawn feature size, according to embodiments of the present invention.

Referring to FIG. 36E , the lower layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604. A plurality of photoresist layer portions 3610 and a plurality of openings 3616 (which have been exposed and developed) are located between the first pre-patterned hard mask 3602 and the second pre-patterned hard mask 3604 structures. The current layer is represented by overlay image 3650E. Overlay image 3650E has an overlay shift of +Δ and a pitch difference of P+Δ. Wide unexposed features 3656E and 3658E are included in the current layer, with the shift of these wide unexposed features 3656E and 3658E depicted in FIG. 36E . In one embodiment, the measurement signal is amplified to the order of P for small overlapping shifts of Δ, and Δ can be as small as desired.

FIG36F illustrates an example metrology structure suitable for use in the manner described above with respect to FIG36A-36E, in accordance with an embodiment of the present invention. Referring to FIG36F, a metrology structure 3697 includes a layer 1 feature 3698 (e.g., the lower layer) and a layer 2 feature 3699 (e.g., the current layer). In one embodiment, the width of each of these features is approximately 20-30 microns, as depicted in FIG36F. Such a structure may be included in a dicing street or on a die in an interposer, for example. In one embodiment, a finished die may include a region having a beat of wide features formed by an array of vias or plugs in a collection of narrow features. The presence of two different beats in any direction may suggest the use of the above-described techniques to measure overlap. The above approach enables accurate measurement of overlay in a photobucket for each via or plug patterned layer using the technique. Embodiments can improve accuracy for future generations of technology while using current technology overlay measurement tools.

One or more embodiments described herein relate to methods involving the use of critical dimension scanning electron microscopy (CDSEM) techniques to measure overlap on a pre-patterned hard mask (e.g., a photobucket). The embodiments described herein can be implemented to solve the problem of measuring overlap between a via and/or plug layer patterned on top of a pre-patterned hard mask (e.g., a photobucket layer) and an underlying pre-patterned hard mask layer by using a scanning electron microscope (e.g., CDSEM). In one embodiment, the via or plug locations are patterned at a pitch that is slightly different from the pitch of the underlying pre-patterned hard mask. Due to the overlap mismatch, the position of the photobucket that is cleared depends on the amount of overlap mismatch.

FIG37A illustrates a top-down view of an overlay scenario, where the current layer is overlaid on a pre-patterned hard mask below, according to an embodiment of the present invention.

37A , the lower layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704. A plurality of photoresist layer portions 3710 and a plurality of openings 3716 (which have been exposed and developed) are located between the first pre-patterned hard mask 3702 and the second pre-patterned hard mask 3704 structures. The current layer is represented by overlay image 3750A. Overlay image 3750A has an overlay shift of zero X and zero Y. The pitch of overlay image 3750A of the current layer is 25% larger than that of the lower layer in the exemplary embodiment, i.e., patterned at a pitch of +Δ, where Δ = P/4. Region 3760A emphasizes the location of the "light bucket cluster" at zero overlap shift (PB _0,0 ).

37B illustrates a top-down view of an overlay scenario where the current layer has a positive overlay shift of one-quarter the pitch relative to the underlying pre-patterned hard mask grid in the X direction, according to an embodiment of the present invention.

Referring to FIG. 37B , the lower layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704. A plurality of photoresist layer portions 3710 and a plurality of openings 3716 (which have been exposed and developed) are located between the first pre-patterned hard mask 3702 and the second pre-patterned hard mask 3704 structures. The current layer is represented by overlay image 3750B. Overlay image 3750B has an overlay shift of X at _Px /4 and Y at zero. The pitch of overlay image 3750B of the current layer is 25% larger than that of the lower layer in the exemplary embodiment, i.e., patterned at pitch +Δ, where Δ = P/4. Region 3760B highlights the X=-2P _X and Y=0 position for the photobucket cluster for PB _0,0 . Region 3760B and the corresponding open/closed vertical rows are shifted to the left by an amount equal to twice the pitch. It should be understood that the open/closed rows will have a different contrast than the other rows due to the fact that their exposed photobucket density is different from the other rows in the region.

37C illustrates a top-down view of an overlay scenario where the current layer has a negative overlay of one-quarter the pitch of the underlying pre-patterned hard mask grid in the X direction, according to an embodiment of the present invention.

Referring to FIG. 37C , the lower layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704. A plurality of photoresist layer portions 3710 and a plurality of openings 3716 (which have been exposed and developed) are located between the first pre-patterned hard mask 3702 and the second pre-patterned hard mask 3704 structures. The current layer is represented by overlay image 3750C. Overlay image 3750C has an overlay shift of _-Px /4 in X and zero in Y. The pitch of overlay image 3750C of the current layer is 25% larger than that of the lower layer in the exemplary embodiment, i.e., patterned at a pitch of +Δ, where Δ = P/4. Region 3760C emphasizes the location of X = +2P _X and Y = 0 for the bucket cluster for PB _{0, 0.} Region 3760C and the corresponding open/closed vertical rows are shifted to the right by an amount equal to twice the pitch.

FIG37D illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of one-quarter the pitch of the underlying pre-patterned hard mask grid in the Y direction, according to an embodiment of the present invention.

37D , the lower layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704. A plurality of photoresist layer portions 3710 and a plurality of openings 3716 (which have been exposed and developed) are located between the first pre-patterned hard mask 3702 and the second pre-patterned hard mask 3704 structures. The current layer is represented by overlay image 3750D. Overlay image 3750D has an overlay shift of zero in X and P _Y /4 in Y. The pitch of overlay image 3750D of the current layer is 25% larger than that of the lower layer in the exemplary embodiment, i.e., patterned at pitch + Δ, where Δ = P / 4. Region 3760D highlights the location of X=0 and Y=-2P _Y for the bucket cluster for PB _0,0 . Region 3760D and the corresponding open/closed horizontal rows are shifted downward by an amount equal to twice the pitch.

37E illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of one-quarter the pitch of the underlying pre-patterned hard mask grid in the X direction and a positive overlap of one-quarter the pitch of the underlying pre-patterned hard mask grid in the Y direction, according to an embodiment of the present invention.

Referring to FIG. 37E , the lower layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704. A plurality of photoresist layer portions 3710 and a plurality of openings 3716 (which have been exposed and developed) are located between the first pre-patterned hard mask 3702 and the second pre-patterned hard mask 3704 structures. The current layer is represented by overlay image 3750E. Overlay image 3750E has an overlay shift of X at _Px /4 and Y at _Py /4. The pitch of overlay image 3750E of the current layer is 25% larger than that of the lower layer in the exemplary embodiment, i.e., patterned at pitch + Δ, where Δ = P/4. Region 3760E highlights the X=-2P _X and Y=-2P _Y positions for the bucket cluster for PB _0,0 . Region 3760E and the corresponding open/closed horizontal rows are shifted downward by an amount equal to twice the pitch. Additionally, region 3760E and the corresponding open/closed vertical rows are shifted left by an amount equal to twice the pitch.

Referring again to Figures 37A-37E, it will be appreciated that cross-sectional analysis of a semiconductor wafer can reveal alignment marks comprising vertical and horizontal arrays of vias and/or plugs within a plurality of gridded vias and plugs, as indicative of application of one or more embodiments described herein. Such structures can be included in saw streets or on the die within an interposer, for example. Application of this approach can enable accurate measurement of overlay in the photobuckets for each via and/or plug patterned layer intended for use with CDSEM metrology. It will also be appreciated that conventional overlay techniques will not work with this patterning.

According to an embodiment of the present invention, a novel structure is described for the fabrication of high-resolution phase-shifting masks (PSMs) for lithography, such as extreme ultraviolet (EUV) lithography. These PSM masks can be used for conventional (direct) lithography or complementary lithography.

Photolithography is often used in the manufacturing process to form a pattern in a layer of photoresist. In the photolithography process, a photoresist layer is deposited over the underlying layer to be etched. Typically, the underlying layer is a semiconductor layer, but it can be any type of hard mask or dielectric material. The photoresist layer is then selectively exposed to radiation through a photomask or reticle. The photoresist is then developed and those portions of the photoresist exposed to the radiation are removed, in the case of a "positive" photoresist.

The photomask or reticle used to pattern the wafer is placed in a photolithography exposure tool, commonly known as a "stepper" or "scanner." In the stepper or scanner machine, the photomask or reticle is placed between the radiation source and the wafer. The photomask or reticle is typically formed from a patterned chrominance (absorber layer) that is placed on a quartz substrate. The radiation passes substantially unattenuated through the quartz sections of the photomask or reticle in locations where there is no chrominance. Conversely, the radiation does not pass through the chrominance portion of the mask. Because the radiation incident on the mask either passes completely through the quartz sections or is completely blocked by the chrominance sections, this type of mask is called a binary mask. After the radiation selectively passes through the mask, the pattern on the mask is transferred to the photoresist by projecting the image of the mask into the photoresist through a series of lenses.

As the features on the photomask or reticle get closer together, diffraction effects kick in (when the size of the features on the mask is comparable to the wavelength of the light source). Diffraction blurs the image projected on the photoresist, resulting in poor resolution.

One of the most advanced methods for preventing diffraction patterns from interfering with the desired patterning of photoresists is to cover selected openings in the photomask or reticle with a transparent layer, known as a shifter. The shifter shifts one set of exposure rays out of phase with the adjacent set, thereby canceling out the interfering pattern from diffraction. This approach is known as phase-shifting masking (PSM). However, alternative mask manufacturing methods that reduce defects and increase yield during mask production are an important area of focus in lithography process development.

One or more embodiments of the present invention relate to methods for manufacturing lithographic masks and the resulting lithographic masks. To provide background, meeting the aggressive device scaling goals set by the semiconductor industry depends on the ability of lithographic masks to pattern smaller features with high fidelity. However, the means for patterning increasingly smaller features poses a significant challenge to mask manufacturing. In this regard, lithographic masks widely used today rely on the concept of phase shift mask (PSM) technology for patterning features. However, reducing defects while producing increasingly smaller patterns remains one of the greatest hurdles in mask manufacturing. The use of phase shift masks can have several disadvantages. First, the design of a phase shift mask is a rather complex process that requires significant resources. Second, due to the very nature of phase-shifting masks, it is difficult to inspect them for defects. These defects in phase-shifting masks arise from the current integration schemes used to produce the masks themselves. Conventional phase-shifting masks employ a cumbersome and somewhat defect-prone process to pattern a thick light-absorbing material and then transfer that pattern to a secondary layer that assists in phase shifting. To complicate matters, the absorber layer is plasma-etched twice, and therefore, adverse effects of plasma etching (such as loading effects, reactive ion etching delays, charging, and regeneration effects) lead to defects in the mask production.

Innovation in materials and novel integration techniques for producing defect-free lithographic masks remain high priorities to enable device scaling. Therefore, to exploit the full benefits of phase-shifting mask technology, a novel integration scheme that (i) patterns the shifter layer with high fidelity and (ii) patterns the absorber only once, during the final stages of fabrication, may be necessary. Furthermore, such a fabrication scheme could offer other advantages, such as flexibility in material selection, reduced substrate damage during fabrication, and increased yield in mask fabrication.

FIG38 illustrates a cross-sectional view of a lithographic mask structure 3801 according to an embodiment of the present invention. The lithographic mask 3801 includes a die mid-region 3810, a frame region 3820, and a die-frame interface region 3830. The die-frame interface region 3830 includes adjacent portions of the die mid-region 3810 and the frame region 3820. The die mid-region 3810 includes a patterned shifter layer 3806 disposed directly on the substrate 3800, wherein the patterned shifter layer has features including sidewalls. The frame region 3820 surrounds the die mid-region 3810 and includes a patterned absorber layer 3802 disposed directly on the substrate 3800.

The die frame interface region 3830 (disposed on the substrate 3800) includes a double-layer stack 3840. The double-layer stack 3840 includes an upper layer 3804 disposed on a lower patterned shifter layer 3806. The upper layer 3804 of the double-layer stack 3840 is composed of the same material as the patterned absorber layer 3802 of the frame region 3820.

In one embodiment, the top surface 3808 of the features of the patterned shifter layer 3806 has a height that is different from the top surface 3812 of the features in the die-frame interface region and different from the top surface 3814 of the features in the frame region. Furthermore, in one embodiment, the top surface 3812 of the features in the die-frame interface region has a height that is different from the top surface 3814 of the features in the frame region. The typical thickness of the patterned shifter layer 3806 ranges from 40 to 100 nm, while the typical thickness of the absorber layer ranges from 30 to 100 nm. In one embodiment, the absorber layer 3802 in the frame region 3820 has a thickness of 50 nm, the absorber layer 3804 disposed on the shifter layer 3806 in the die-frame interface region 3830 has a combined thickness of 120 nm, and the absorber thickness in the frame region is 70 nm. In one embodiment, the substrate 3800 is quartz, the patterned shifter layer includes a material such as (but not limited to) molybdenum silicide, molybdenum silicon oxynitride, molybdenum silicon nitride, silicon oxynitride, or silicon nitride, and the absorber material is chromium.

According to embodiments of the present invention, complementary electron beam lithography (CEBL) is described. One or more embodiments described herein relate to lithography methods and tools related to or suitable for complementary electron beam lithography (CEBL), including semiconductor processing considerations when implementing such methods and tools.

Complementary lithography leverages the capabilities of two lithography techniques (working together) to reduce the cost of patterning critical layers in logic devices at 20nm half-pitch and below, in high-volume manufacturing (HVM). The most cost-effective way to implement complementary lithography is to combine optical lithography with electron beam lithography (EBL). The process of transferring an integrated circuit (IC) design to the wafer is detailed as follows: optical lithography, used to print unidirectional lines (strictly unidirectional or mostly unidirectional) at a pre-defined pitch; pitch segmentation technology, used to increase line density; and EBL, used to "cut" the lines. EBL is also used to pattern other critical layers, particularly contacts and vias. Optical lithography can be used alone to pattern other layers. When used to complement photolithography, EBL is called CEBL, or complementary EBL. CEBL targets scribe lines and vias. By not attempting to pattern all layers, CEBL plays a complementary yet critical role in meeting industry patterning needs at advanced (smaller) technology nodes (e.g., 10nm or smaller, such as the 7nm or 5nm technology nodes). CEBL also extends the use of current photolithography techniques, tools, and facilities.

The embodiments disclosed herein can be used to manufacture a variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include (but are not limited to) processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a variety of electronic devices known in the art. For example, in computer systems (e.g., desktops, laptops, servers), mobile phones, personal electronic devices, and the like. The integrated circuits can be coupled to buses or other components in the system. For example, a processor can be coupled to a memory, a chipset, and the like via one or more buses. Each processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

As described above, electron beam (ebeam) lithography can be implemented to supplement standard lithography techniques to achieve desired scaling of features for integrated circuit fabrication. An ebeam lithography tool can be used to perform ebeam lithography. In one exemplary embodiment, FIG39 is a schematic cross-sectional view of an electron beam column of an ebeam lithography apparatus.

39 , electron beam array 3900 includes an electron source 3902 for providing a beam 3904 of electrons. The beam 3904 of electrons passes through a limiting aperture 3906 and then through high aspect ratio illumination optics 3908. The output beam 3910 then passes through a slit 3912 and can be controlled by a thin lens 3914 (which can be magnetic, for example). Finally, the beam 3904 passes through a shaped aperture 3916 (which can be a one-dimensional (1-D) shaped aperture) and then through a canceller aperture array (BAA) 3918. The BAA 3918 includes a plurality of physical apertures therein, such as openings formed in a thin sheet of silicon. It is possible that only a portion of the BAA 3918 is exposed to the electron beam at a given moment. Alternatively, or in combination, only a portion 3920 of the electron beam 3904 that passes through the BAA 3918 is allowed to pass through the final aperture 3922 (e.g., beam portion 3921 is shown as blocked) and (possibly) the stage feedback deflector 3924.

39 , the resulting electron beam 3926 ultimately impinges upon a point 3928 on the surface of a wafer 3930 (e.g., a silicon wafer used in IC manufacturing). Specifically, the resulting electron beam may impinge upon a photoresist layer on the wafer, but the embodiment is not so limited. A level scan 3932 moves the wafer 3930 relative to the beam 3926 in the direction of arrow 3934 shown in FIG. 39 . It should be understood that an electron beam tool may comprise a plurality of rows 3900 of the type shown in FIG. 39 . Also, the electron beam tool may have an associated base computer, and each row may further have a corresponding row computer.

In one embodiment, all or some of the openings or apertures in a canceller aperture array (BAA) can be switched on or off (e.g., by beam deflection) as the wafer/die moves underneath in a wafer travel or scan direction, as referenced below. In one embodiment, the BAA can be independently controlled as to whether each opening passes the electron beam to the sample or deflects the electron beam into, for example, a Faraday cup or blanking aperture. An electron beam row or apparatus including such a BAA can be built to deflect the overall beam coverage to only a portion of the BAA, and then individual openings in the BAA can be electrically configured to pass the electron beam ("on") or not ("off"). For example, undeflected electrons pass through to the wafer and expose the resist layer, while deflected electrons are trapped in a Faraday cup or a blanking aperture. It should be understood that references to "opening" or "opening height" refer to the size of the point that impacts the receiving wafer rather than the physical opening in the BAA, as the physical opening is substantially larger (e.g., on the order of microns) than the size of the point that ultimately results from the BAA (e.g., on the order of nanometers). Therefore, when the pitch of the BAA or the row of openings in the BAA is said to "correspond to" the pitch of the metal wire, this description actually refers to the relationship between the pitch of the impact points, as generated by the BAA, and the pitch of the wire being cut. As an example provided below, dots generated from BAA 4310 have the same pitch as the pitch of line 4300 (when both rows of BAA openings are considered together). Meanwhile, dots generated from just one row of the staggered array of BAA 4310 have a pitch that is twice the pitch of line 4300.

In one embodiment, a staggered beam aperture array is implemented to address electron beam machine throughput while also enabling minimum routing pitch. Without staggering, edge placement error (EPE) considerations dictate that a minimum pitch of twice the routing width cannot be cut because it is impossible to stack vertically in a single stack. For example, FIG40 illustrates aperture 4000 of a BAA relative to a line 4002 to be cut or having a via placed in a target location, as the line is scanned below aperture 4000 in the direction of arrow 4004. 40 , for a given line 4002 to be cut or a via to be placed, the EPE 4006 of the cutter opening (aperture) results in a rectangular opening in the BAA grid that is the pitch of the line.

Figure 41 illustrates two non-staggered apertures 4100 and 4102 of a BAA relative to two lines 4104 and 4106 to be cut or having vias placed in target locations, respectively, as lines are scanned under apertures 4100 and 4102 in the direction of arrow 4108. Referring to Figure 41 , when the rectangular opening 4000 of Figure 40 is placed in a single vertical row with other such rectangular openings (e.g., now 4100 and 4102), the allowable pitch of the lines to be cut is limited by 2x EPE 4110 plus the distance requirement 4112 between BAA openings 4100 and 4102 plus the width of one trace 4104 or 4106. The resulting spacing 4114 is shown by the arrows on the far right side of Figure 41. This one-line array can severely limit the pitch of the traces to substantially greater than 3-4 times the width of the trace, which can be unacceptable. Another, potentially unacceptable, alternative approach would be to cut a tighter pitch trace with two (or more) vias that have slightly offset trace locations; this approach can severely limit the throughput of the electron beam machine.

FIG42 , relative to FIG41 , illustrates two rows 4202 and 4204 of staggered apertures 4206 of a BAA 4200 relative to a plurality of lines 4208 to be cut or having vias placed in target locations, as lines 4208 are scanned beneath apertures 4206 along direction 4210, with the scan direction indicated by the arrow, in accordance with an embodiment of the present invention. Referring to FIG41 , staggered BAA 4200 includes two linear arrays 4202 and 4204 that are spatially staggered as shown. The two staggered arrays 4202 and 4204 cut (or place vias in) alternating lines 4208. Lines 4208 (in one embodiment) are placed on a tight grid at twice the trace width. As used throughout this disclosure, the term "staggered array" may refer to a staggering of openings 4206 that is staggered in one direction (e.g., vertically) and either has no overlap or has some overlap when viewed as scanned in an orthogonal direction (e.g., horizontally). In the latter case, the effective overlap provides tolerance for misalignment.

It should be understood that while the staggered array is shown herein as two vertical rows for simplicity, the openings or apertures in a single "row" need not be arranged vertically in a row. For example, in one embodiment, an staggered array is achieved as long as a first array collectively has a vertical pitch, and a second array interleaved with the first array in the scanning direction collectively has a vertical pitch. Therefore, references or descriptions herein to vertical rows may actually consist of one or more rows, unless a single row of openings or apertures is specified. In one embodiment, in the event that a "row" of openings is not a single row of openings, any offset within that "row" can be compensated for using strobe timing. In one embodiment, the key point is that the openings or apertures of its staggered array of BAAs are located at a specific pitch in a first direction, but are offset in a second direction to allow them to place cuts or vias without any gaps between the cuts or vias in the first direction.

Thus, one or more embodiments relate to a staggered beam aperture array, wherein the openings are staggered to allow EPE cutting and/or via requirements to be met, as opposed to an inline arrangement that does not take into account EPE technical requirements. Conversely, without staggering, edge placement error (EPE) issues mean that a minimum pitch of twice the trace width cannot be cut because it is impossible to stack vertically in a single stack. Instead, in one embodiment, the use of staggered BAAs enables electron beam writing of each trace location over 4000 times faster than independently. Furthermore, the staggered array allows the trace pitch to be twice the trace width. In a particular embodiment, the array has 4096 staggered openings over two rows so that EPE can be performed for each of the cut and via locations. It should be understood that a staggered array (as contemplated herein) may include two or more rows of staggered openings.

In one embodiment, the use of a staggered array leaves room for metal around the apertures of the BAA, which contains one or two electrodes, to deliver or guide the electron beam to the wafer, to a Faraday cup, or to obscure the aperture. That is, each opening can be controlled independently by the electrodes to pass or deflect the electron beam. In one embodiment, the BAA has 4096 openings, and the electron beam apparatus encompasses the full array of 4096 openings, each of which is electrically controlled. Energy throughput is enhanced by scanning the wafer beneath the openings (as indicated by the thick black arrows).

In a particular embodiment, the staggered BAA has two rows of staggered BAA openings. This array allows for tight pitch routing, where the routing pitch can be twice the routing width. Furthermore, all routing can be cut in a single pass (or vias can be formed in a single pass), thereby enabling flux on an electron beam machine. FIG21A illustrates two rows of staggered apertures (left) of a BAA with multiple lines of cuts (breaks in the horizontal lines) or vias (filled in the boxes) patterned using staggered BAAs (right), with the scan direction indicated by the arrows, according to an embodiment of the present invention.

Referring to FIG43A, the lines resulting from a single staggered array can be as described above, where the lines are of a single pitch and are patterned with cuts and vias. Specifically, FIG43A depicts a plurality of lines 4300 or open line locations 4302 where no lines exist. Vias 4304 and cuts 4306 can be formed along the lines 4300. The lines 4300 are shown relative to a BAA 4310 having a scan direction 4312. Thus, FIG43A can be viewed as a typical pattern produced by a single staggered array. The dotted lines show where cuts occur in the patterned lines (including total cuts to remove entire lines or line portions). Via locations 4304 are patterned vias that fall on top of the trace 4300.

It should be understood that an electron beam column including an interleaved beam aperture array (interleaved BAA) as described above may also include other features besides those described in conjunction with FIG. 39 . For example, in one embodiment, the sample stage may be rotated 90 degrees to accommodate alternating metallization layers that may be printed orthogonally to one another (e.g., rotated between the X and Y scanning directions). In another embodiment, the electron beam tool may be capable of rotating the wafer 90 degrees before loading it onto the stage.

FIG43B illustrates a cross-sectional view of a stack 4350 of metallization layers 4352 in an integrated circuit according to a metal line layout of the type shown in FIG43A , in accordance with an embodiment of the present invention. Referring to FIG43B , in an exemplary embodiment, the metal cross-section of interconnect stack 4350 is derived from a single BAA array of eight matching metal layers 4354, 4356, 4358, 4360, 4362, 4364, 4366, and 4368 below. It should be understood that the thicker/wider metal lines 4370 and 4372 above are not formed from a single BAA. Via location 4374 is depicted as connecting eight underlying matching metal layers 4354, 4356, 4358, 4360, 4362, 4364, 4366, and 4368.

In summary, in one embodiment, complementary lithography as described herein involves first fabricating a gridded layout using known or state-of-the-art lithography, such as 193 nm immersion lithography (193i). Pitch partitioning can be implemented to increase the density of lines in the gridded layout by a factor of n. The gridded layout formed using 193i lithography plus pitch partitioning by a factor of n can be designated as 193i+P/n pitch partitioning. The patterning of the pitch partitioned grid layout can then be patterned using electron beam direct write (EBDW) "cutting." In one such embodiment, 193 nm immersion scaling can be extended for many generations using cost-effective pitch partitioning. In one embodiment, complementary EBL is used to interrupt the grating continuity and pattern the vias. In another embodiment, complementary EUV is used to interrupt the grating continuity and pattern the vias.

FIG44 illustrates a computing device 4400 according to one embodiment of the present invention. Computing device 4400 includes a circuit board 4402. Circuit board 4402 may include several components, including, but not limited to, a processor 4404 and at least one communication chip 4406. Processor 4404 is physically and electrically coupled to circuit board 4402. In some embodiments, at least one communication chip 4406 is also physically and electrically coupled to circuit board 4402. In further embodiments, communication chip 4406 is part of processor 4404.

Depending on its application, computing device 4400 may include other components that may or may not be physically and electrically coupled to circuit board 4402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and mass storage devices (e.g., a hard drive, a compact disc (CD), a digital optical disc (DVD), etc.).

The communication chip 4406 enables wireless communication for transferring data to and from the computing device 4400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that transmit data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated device does not contain any wiring, although in some embodiments it may not. Communication chip 4406 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. Computing device 4400 may include multiple communication chips 4406. For example, the first communication chip 4406 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, while the second communication chip 4406 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 4404 of the computing device 4400 includes an integrated circuit die packaged within the processor 4404. In some embodiments of the present invention, the integrated circuit die of the processor includes one or more devices, such as MOSFET transistors, constructed in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to convert the electronic data into other electronic data that can be stored in registers and/or memory.

The communication chip 4406 also includes an integrated circuit die packaged within the communication chip 4406. According to another embodiment of the present invention, the integrated circuit die of the communication chip is constructed according to an embodiment of the present invention.

In a further embodiment, another component included in the computing device 4400 may include an integrated circuit die constructed according to an implementation method of an embodiment of the present invention.

In various implementations, computing device 4400 may be a laptop, a mini-notebook, a notebook, a thin and light notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-light mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 4400 may be any other electronic device that processes data.

Figure 45 illustrates an interposer 4500 that includes one or more embodiments of the present invention. Interposer 4500 is an intermediate substrate that bridges a first substrate 4502 to a second substrate 4504. The first substrate 4502 can be, for example, an integrated circuit die. The second substrate 4504 can be, for example, a memory module, a computer motherboard, or other integrated circuit die. Typically, the purpose of interposer 4500 is to extend connections to a wider pitch or to reroute connections to different connections. For example, interposer 4500 can couple an integrated circuit die to a ball grid array (BGA) 506, which can subsequently be coupled to the second substrate 4504. In some embodiments, the first and second substrates 4502/4504 are mounted to opposite sides of interposer 4500. In other embodiments, the first and second substrates 4502/4504 are mounted to the same side of the interposer 4500. And in further embodiments, three or more substrates are interconnected via the interposer 4500.

Interposer 4500 can be formed from epoxy, glass fiber reinforced epoxy, ceramic materials, or polymer materials such as polyimide. In further embodiments, the interposer can be formed from alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V or IV materials.

The interposer may include metal interconnects 4508 and through-holes 4510, including, but not limited to, through-silicon vias (TSVs) 4512. The interposer 4500 may further include embedded devices 4514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 4500. According to embodiments of the present invention, the apparatus or process disclosed herein may be used to manufacture the interposer 4500.

Thus, embodiments of the present invention include sub-10 nm pitch patterning and self-polymerizing devices.

Example 1: An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by partial body portions. A trench isolation layer is interposed between the plurality of semiconductor bodies and adjacent to lower portions of the plurality of semiconductor bodies but not adjacent to upper portions of the plurality of semiconductor bodies, wherein the trench isolation layer is located above the partial body portions. One or more gate electrode stacks are located on top surfaces of the upper portions of the plurality of semiconductor bodies and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies, as well as on portions of the trench isolation layer. A back-end-of-line (BEOL) metallization layer is over the one or more gate electrode stacks, the BEOL metallization layer including a plurality of alternating first and second conductive line types along the same direction, wherein the total composition of the first conductive line type is different from the total composition of the second conductive line type.

Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein lines of the first conductive line type are isolated at a pitch, and wherein lines of the second conductive line type are isolated at the pitch.

Example 3: The integrated circuit structure of Example 1 or 2, wherein the plurality of alternating first and second conductive line types are located in an interlayer dielectric (ILD) layer.

Example Embodiment 4: The integrated circuit structure of Example Embodiment 1 or 2, wherein the lines of the plurality of alternating first and second conductive line types are separated by air gaps.

Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, 3, or 4, wherein the total composition of the first conductive line type substantially comprises copper, and wherein the total composition of the second conductive line type substantially comprises a material selected from the group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au, and alloys thereof.

Example Embodiment 6: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, or 5, wherein each of the lines of the plurality of alternating first and second conductive line types includes a barrier layer along the bottom and sidewalls of the line.

Example Embodiment 7: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, or 5, wherein the lines of the plurality of alternating first and second conductive line types each include a barrier layer along a bottom of the line but not along a sidewall of the line.

Example Embodiment 8: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5, 6, or 7, wherein one or more of the lines of the plurality of alternating first and second conductive line types are connected to a lower via, which is connected to a lower metallization layer, the lower metallization layer being between the one or more gate electrode stacks and the BEOL metallization layer, and wherein one or more of the lines of the plurality of alternating first and second conductive line types are interrupted by a dielectric plug.

Example 9: The integrated circuit structure of Example 1, 2, 3, 4, 5, 6, 7, or 8, wherein the grating pattern has a constant pitch.

Example 10: The integrated circuit structure of Example 1, 2, 3, 4, 5, 6, 7, 8, or 9, further comprising source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and comprise a semiconductor material different from the semiconductor material of the semiconductor bodies.

Example 11: The integrated circuit structure of Example 1, 2, 3, 4, 5, 6, 7, 8, or 9, further comprising source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are located in the upper portions of the plurality of semiconductor bodies.

Example 12: The integrated circuit structure of Example 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, or 11, wherein each of the one or more gate electrode stacks includes a high-k gate dielectric layer and a metal gate electrode.

Example 13: The integrated circuit structure of Example 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, or 12, wherein the first conductive line type has a top surface having a metal composition different from the metal composition of the top surface of the second conductive line type.

Example 14: An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by partial body portions. A trench isolation layer is interposed between the plurality of semiconductor bodies and adjacent to lower portions of the plurality of semiconductor bodies but not adjacent to upper portions of the plurality of semiconductor bodies, wherein the trench isolation layer is located above the partial body portions. One or more gate electrode stacks are located on top surfaces of the upper portions of the plurality of semiconductor bodies and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies, as well as on portions of the trench isolation layer. A back-end-of-line (BEOL) metallization layer is over the one or more gate electrode stacks, the BEOL metallization layer including a plurality of alternating first and second conductive line types along the same direction, wherein each of the plurality of alternating first and second conductive line types includes a barrier layer along a bottom of the line but not along a sidewall of the line.

Example Embodiment 15: The integrated circuit structure of Example Embodiment 14, wherein the lines of the first conductive line type are isolated at a pitch, and wherein the lines of the second conductive line type are isolated at the pitch.

Example 16: The integrated circuit structure of Example 14 or 15, wherein the plurality of alternating first and second conductive line types are located in an interlayer dielectric (ILD) layer.

Example Embodiment 17: The integrated circuit structure of Example Embodiment 14 or 15, wherein the lines of the plurality of alternating first and second conductive line types are separated by air gaps.

Example Embodiment 18: The integrated circuit structure of Example Embodiment 14, 15, 16, or 17, wherein the total composition of the first conductive line type is the same as the total composition of the second conductive line type.

Example Embodiment 19: The integrated circuit structure of Example Embodiment 14, 15, 16, or 17, wherein the total composition of the first conductive line type substantially includes copper, and wherein the total composition of the second conductive line type substantially includes a material selected from the group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au, and alloys thereof.

Example Embodiment 20: The integrated circuit structure of Example Embodiment 14, 15, 16, 17, 18, or 19, wherein one or more of the lines of the plurality of alternating first and second conductive line types are connected to a lower via, which is connected to an underlying metallization layer, the underlying metallization layer being between the one or more gate electrode stacks and the BEOL metallization layer, and wherein one or more of the lines of the plurality of alternating first and second conductive line types are interrupted by a dielectric plug.

Example 21: The integrated circuit structure of Example 14, 15, 16, 17, 18, 19, or 20, wherein the grating pattern has a constant pitch.

Example Embodiment 22: The integrated circuit structure of Example Embodiment 14, 15, 16, 17, 18, 19, 20, or 21, further comprising source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and comprise a semiconductor material different from the semiconductor material of the semiconductor bodies.

Example 23: The integrated circuit structure of Example 14, 15, 16, 17, 18, 19, 20, or 21, further comprising source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are located in the upper portions of the plurality of semiconductor bodies.

Example Embodiment 24: The integrated circuit structure of Example Embodiment 14, 15, 16, 17, 18, 19, 20, 21, 22, or 23, wherein each of the one or more gate electrode stacks includes a high-k gate dielectric layer and a metal gate electrode.

Example 25: An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a first grating pattern interrupted by partial body portions. A trench isolation layer is interposed between the plurality of semiconductor bodies and adjacent to lower portions of the plurality of semiconductor bodies but not adjacent to upper portions of the plurality of semiconductor bodies, wherein the trench isolation layer is located above the partial body portions. One or more gate electrode stacks are located on top surfaces of the upper portions of the plurality of semiconductor bodies and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies, as well as on portions of the trench isolation layer. A first back-end-of-the-line (BEOL) metallization layer is formed over the one or more gate electrode stacks. The first BEOL metallization layer includes a second grating of alternating metal and dielectric lines in a first direction. A second BEOL metallization layer is formed over the first BEOL metallization layer. The second BEOL metallization layer includes a third grating of alternating metal and dielectric lines in a second direction. The second direction is orthogonal to the first direction. Each metal line of the third grating of the second BEOL metallization layer is formed on a dielectric layer. The dielectric layer includes alternating different regions of a first dielectric material and a second dielectric material corresponding to the alternating metal and dielectric lines of the first BEOL metallization layer. Each dielectric line of the third grating of the second BEOL metallization layer includes a continuous region of a third dielectric material that is different from the alternating different regions of the first dielectric material and the second dielectric material.

Example Embodiment 26: The integrated circuit structure of Example Embodiment 25, wherein the metal line of the second BEOL metallization layer is electrically coupled to the metal line of the first BEOL metallization layer by a via, the via having a center directly aligned with the center of the metal line of the first BEOL metallization layer and with the center of the metal line of the second BEOL metallization layer.

Example Embodiment 27: The integrated circuit structure of Example Embodiment 25 or 26, wherein the metal line of the second BEOL metallization layer is interrupted by a plug having a center directly aligned with the center of the dielectric line of the first BEOL metallization layer.

Example 28: The integrated circuit structure of Example 25, 26, or 27, wherein the first dielectric material, the second dielectric material, and the third dielectric material are not the same material.

Example Embodiment 29: The integrated circuit structure of Example Embodiment 25, 26, or 27, wherein only two of the first dielectric material, the second dielectric material, and the third dielectric material are the same material.

Example Embodiment 30: The integrated circuit structure of Example Embodiment 25, 26, 27, 28, or 29, wherein the alternating different regions of the first dielectric material and the second dielectric material are separated by seams, and wherein the continuous region of the third dielectric material is separated from the alternating different regions of the first dielectric material and the second dielectric material by seams.

Example 31: The integrated circuit structure of Example 25, 26, 27, or 30, wherein the first dielectric material, the second dielectric material, and the third dielectric material are all the same material.

Example 32: The integrated circuit structure of Example 25, 26, 27, 28, 29, 30, or 31, wherein the first grating pattern has a constant pitch.

Example Embodiment 33: The integrated circuit structure of Example Embodiment 25, 26, 27, 28, 29, 30, 31 or 32, further comprising source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and comprise a semiconductor material different from the semiconductor material of the semiconductor bodies.

Example 34: The integrated circuit structure of Example 25, 26, 27, 28, 29, 30, 31, or 32, further comprising source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are located in the upper portions of the plurality of semiconductor bodies.

Example Embodiment 35: The integrated circuit structure of Example Embodiment 25, 26, 27, 28, 29, 30, 31, 32, 33, or 34, wherein each of the one or more gate electrode stacks includes a high-k gate dielectric layer and a metal gate electrode.

Example Embodiment 36: The integrated circuit structure of Example Embodiment 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, or 35, wherein an etch stop layer or an additional dielectric layer separates the first BEOL metallization layer and the second BEOL metallization layer.

Example Embodiment 37: A method of manufacturing an integrated circuit structure includes forming a plurality of bone features on a substrate, forming a first set of spacers along sidewalls of each of the plurality of bone features, the first set of spacers having a first material composition different from the material composition of the plurality of bone features, forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a first material composition different from the material composition of the first set of spacers, A third group of spacers is formed along the sidewalls of each of the second group of spacers. The third group of spacers has a third material composition that is different from the first material composition, the second material composition, and the material composition of the plurality of bone characteristics. A fourth group of spacers is formed along the sidewalls of each of the third group of spacers. The fourth group of spacers has a third material composition that is different from the first material composition, the second material composition, and the material composition of the plurality of bone characteristics. The spacers are composed of the second material to form a fifth group of spacers laterally adjacent to the side walls of each of the fourth group of spacers. The fifth group of spacers is composed of the first material. After forming the fifth group of spacers, the plurality of bone features are removed. After removing the plurality of bone features, a sixth group of spacers is formed along the side walls of each of the first group of spacers and along the side walls of each of the fifth group of spacers. The sixth group of spacers is composed of the first material. The method further comprises forming a first set of spacers having the second material composition, forming final features in each opening between adjacent pairs of spacers of the sixth set of spacers, planarizing the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, the sixth set of spacers, and the final features to form a target base layer, and using the target base layer to form a metallization layer of a semiconductor structure.

Example Embodiment 38: The method of Example Embodiment 37, wherein forming the plurality of bone features comprises using standard lithography operations.

Example Embodiment 39: The method of Example Embodiment 37 or 38, wherein forming the plurality of backbone features comprises forming the plurality of features comprising a material selected from the group consisting of silicon nitride, silicon oxide, and silicon carbide.

Example embodiment 40: The method of example embodiment 37, 38 or 39, wherein forming the first set of spacers includes using an atomic layer deposition (ALD) process to deposit material of the first set of spacers that is conformal to the plurality of bone features, anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of the plurality of bone features.

Example Embodiment 41: The method of Example Embodiment 37, 38, or 39, wherein forming the first set of spacers comprises selectively growing material of the first set of spacers along the sidewalls of each of the plurality of bone features.

Example Embodiment 42: The method of Example Embodiment 37, 38, 39, 40, or 41, wherein each final feature has a side width greater than a side width of each spacer from the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, and the sixth set of spacers.

Example Embodiment 43: The method of Example Embodiment 37, 38, 39, 40, 41, or 42, wherein each final feature is formed by merging the growth of material formed along adjacent pairs of spacers of the sixth set of spacers.

Example Embodiment 44: The method of Example Embodiment 37, 38, 39, 40, 41, 42, or 43, wherein each last feature comprises the third material composition.

Example Embodiment 45: The method of Example Embodiment 37, 38, 39, 40, 41, 42, 43, or 44, wherein using the target base layer to form the metallization layer of the semiconductor structure includes removing all portions of the first material composition to form a first plurality of trenches, and forming a first plurality of conductive lines in the first plurality of trenches.

Example Embodiment 46: The method of Example Embodiment 45, wherein forming the metallization layer of the semiconductor structure using the target base layer further comprises removing all portions of the third material composition to form a second plurality of trenches, and forming a second plurality of conductive lines in the second plurality of trenches.

Example Embodiment 47: The method of Example Embodiment 46, wherein the first plurality of conductive lines and the second plurality of conductive lines are of the same composition.

Example Embodiment 48: The method of Example Embodiment 46, wherein the first plurality of conductive lines and the second plurality of conductive lines are of different compositions.

Example Embodiment 49: The method of Example Embodiment 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, or 48, further comprising forming an additional 20-200 sets of spacers between forming the fifth sets of spacers and the sixth sets of spacers and before removing the plurality of bone features.

Example embodiment 50: A target structure for fabricating an integrated circuit structure includes a first set of spacers above a hard mask layer above a substrate, the first set of spacers having a first material composition. A second set of spacers is located along the outer sidewalls of each of the first set of spacers, the second set of spacers having a second material composition different from the first material composition. A third set of spacers is located along the sidewalls of each of the second set of spacers, the third set of spacers having a third material composition different from the first material composition and different from the second material composition. A fourth set of spacers is located along the sidewalls of each of the third set of spacers, the fourth set of spacers having the second material composition. A fifth set of spacers is located laterally adjacent to the sidewalls of each of the fourth set of spacers, the fifth set of spacers having the first material composition. A sixth set of spacers is provided along the inner sidewalls of each of the first set of spacers and along the sidewalls of each of the fifth set of spacers, the sixth set of spacers having the second material composition. A final feature is provided in each opening between adjacent pairs of spacers in the sixth set of spacers.

Example Embodiment 51: The target structure of Example Embodiment 50, wherein the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, the sixth set of spacers, and the last features are substantially coplanar with each other.

Example Embodiment 52: The target structure of Example Embodiment 50 or 51, wherein each final feature has a side width greater than the side width of each spacer from the first group of spacers, the second group of spacers, the third group of spacers, the fourth group of spacers, the fifth group of spacers, and the sixth group of spacers.

Example 53: The target structure of Example 52, wherein the side width of each final feature is in the range of 6-12 nm.

Example Embodiment 54: The target structure of Example Embodiment 50, 51, 52, or 53, wherein each final feature has a seam approximately centered within the final feature.

Example Embodiment 55: The target structure of Example Embodiment 50, 51, 52, 53, or 54, wherein each final feature comprises the third material composition.

100: Starting structure 102: Interlayer dielectric (ILD) layer 104: Hard mask material layer 106: Patterned mask 108: Spacers 110: Patterned hard mask 402: Bulk semiconductor substrate 404: First patterned hard mask 406: Pitch 408: Second hard mask layer 410: Selective brush material layer 414: First polymer block 416: Second polymer block 416A: Portion 416B: Portion 418, 418', 418": Fins 420: Patterned substrate 422: Surface 424: Second patterned hard mask layer 426: Resulting pitch 428, 428’, 428”: Interlayer dielectric (ILD) layer 430: Patterned mask 432: Opening 434: Edge placement error (EPE) 436: Cut size 438: Position 440: Level 442: Level 444: Level 446: Protrusion 448: Recess 450: Patterned mask 452: Opening 454: Position 456: Level 458: Level 460: Level 462: Level 464: Protrusion 466: Recess 468, 468’, 468”: Interlayer dielectric (ILD) layer 472: Protrusion 474: Bottom fin portion 476: Recess height 600: Semiconductor structure or device 602: Substrate 604: Fin protrusion 604A, 604B: Source and drain regions 605: Sub-fin region 606: Isolation region 608: Gate line 614: Gate contact 616: Upper gate contact via 650: Gate electrode 652: Gate dielectric layer 654: Dielectric cap layer 660: Upper metal interconnect 670: Interlayer dielectric stack or layer 680: Interface 699: Residual protrusion 700: Target base layer 702: Patterned layer 704: Hard mask layer 706: Transfer layer 708: Base 710: Skeleton features 712: Intermediate group 714: Small features of the second material type 716: Small features of the first material type 718: Small features of the third material type 750: Target base layer 752: Patterned layer 754: Hard mask layer 756: Transfer layer 758: Base 760: Skeleton features 762: Intermediate group 764: Small features of the first material type 766: Small features of the second material type 768: Small features of the third material type 802: Base 804: Transfer layer 806: Hard mask layer 808: Skeleton features 810: First group of small features 812: Second group of small features 814: Third group of small features 816: Fourth set of small features 818: Additional spacer layer 820: Opening 822: Opening 824: Spacer 826: Spacer 828: Last wide feature 830: Metal line patterned feature 830': Metal line 832: Lower via patterned feature 834: Layer 836: Overlying hard mask capping layer 838: Second metal line patterned feature 840: Second lower via patterned feature 842: Overlying hard mask capping layer 850: Plug material 900: Starting point structure 902: Hard mask layer 904: Sacrificial layer 906: Interlayer dielectric (ILD) layer 908: Patterned hard mask layer 910: Patterned sacrificial layer 912: First line opening 914: Line termination region 916: Via opening 918: Patterned ILD layer 920: Interconnect 922: Conductive via 924: Line termination opening 926: Spacer material layer 928: Spacer 930: Line termination portion 932: Plug termination layer 934: Plug termination 936: Interconnect 938: Conductive via 940: Patterned ILD layer 942: Line termination opening 946/948: Interlayer dielectric (ILD) layer 999: Semiconductor structure 1000: Starting structure 1002: Metal line 1002': Line 1004: Interlayer dielectric line (ILD) 1006: Additional film 1008: Additional film 1010: Interlayer dielectric (ILD) line 1012: Hard mask 1014: Surface modification layer 1016: Intermediate line 1016A: Polymer 1016B: Polymer 1018: Permanent interlayer dielectric (ILD) layer 1020: Hard mask layer 1022A, 1022B, 1022C: Via location 1024A, 1024B, 1024C: Via 1026: ILD layer 1026': Recessed ILD layer 1028A, 1028B, 1028C: Plug location 1030: Metal line 1032: Via 1090: First material type 1092: Second material type 1097: Seam 1099: Seam 1100: Starting structure 1102: Metal line 1102': Line 1104: Interlayer dielectric line (ILD) 1106: Additional film 1108: Additional film 1110: Structure 1112: Structure 1114: Structure 1116: Conformal layer 1118: Structure 1119: ILD material layer 1120: Permanent interlayer dielectric (ILD) line 1120': Recessed ILD line 1122: Structure 1123: Conformal material layer 1124: Hard mask layer 1126: Structure 1128: Permanent ILD line 1128': Recessed ILD line 1130: Structure 1132: Trench 1134: Material layer 1136: Mask 1136A: Photoresist layer 1136B: Antireflective coating (ARC) 1136C: Topographic shielding portion 1137: Opening 1138: Second mask 1140: Metal line 1142, 1144: Retained plug 1199: Seam 1200: Semiconductor structure layer 1202: Metal line 1204: Interlayer dielectric (ILD) line 1206: First molecular species 1208: Second molecular species 1210: A/B surface 1212: C surface 1214: Triblock copolymer 1220: Separated structure 1222: First region 1224: Second region 1226: Third region 1250: Separated three-block BCP 1252: Axis 1260: Starting structure 1262: Metal line 1262': Line 1264: Interlayer dielectric line 1266: Additional film 1268: Additional film 1270: Three-block copolymer layer 1272: Region 1274: Second region 1276: Third region 1280: Layer 1282: Layer 1290: Lithography 1292: Some 1294: Region 1302: Metal line 1304: Dielectric layer 1306: Example 1308, 1310: Plug 1314: Dielectric Line 1400: Starting Point Structure 1402: Metal Line 1404: Interlayer Dielectric (ILD) Line 1406: Plug Cap 1408: First-Level Metal Line 1410: Hard Mask 1412: Second Hard Mask 1414: Trench 1416: Second ILD Line 1418: Opening 1420: Photobucket 1422: Via Location 1424: Area 1426: Hard Mask 1428: Photobucket 1430: Non-Plug Location 1432: Area 1434: Via Opening 1436: Metal Line 1438: Via 1496: Seam 1497: Seam 1498: Seam 1499: Seam 1500: Start plug grid structure 1502: ILD layer 1504: First hard mask layer 1506: Third hard mask layer 1508: Second hard mask layer 1510: Opening 1512: Photobucket 1514: Plug location 1516: Plug 1600: Start point structure 1602: Interlayer dielectric (ILD) layer 1604: Hard mask layer 1606: First metal line 1607: Conductive via 1608: Trench 1608A: Sidewall 1608B: Bottom 1610: Non-conformal dielectric cap layer 1610A: First section 1610B: Second portion 1612: Second metal line 1613: Via 1614: First hard mask layer 1616: Second hard mask layer 1630: Starting point structure 1632: Interlayer dielectric (ILD) layer 1634: Hard mask layer 1636: First metal line 1636A: Protrusion 1637: Conductive via 1638: Dielectric spacer 1640: Sacrificial hard mask layer 1642: Trench 1644: Sacrificial material 1646: Non-conformal dielectric cap layer 1648: Sacrificial cap layer 1650: Location 1652: Via location 1654: Second metal line 1656: Conductive via 1658: First placeholder material 1660: Second placeholder material 1662: First hard mask layer 1664: Second hard mask layer 1666: Upper ILD layer 1668: Opening 1670: Conductive via 1672: Portion 1700: Starting point structure 1702: Interlayer dielectric (ILD) layer 1704: Hard mask layer 1706: First metal line 1706A: Protrusion 1707: Conductive via 1708: Dielectric spacer 1710: Sacrificial hard mask layer 1712: Trench 1714: Sacrificial material 1715: Recessed sacrificial material 1716: Non-conformal dielectric cap layer 1716A: Upper portion 1722: Via location 1724: Second metal line 1726: Conductive via 1728: First placeholder material 1730: Second placeholder material 1732: First hard mask layer 1734: Second hard mask layer 1736: Upper ILD layer 1738: Opening 1740: Conductive via 1742: Portion 1800: Start point structure 1802: Metal line 1804: Dielectric line 1806: Etch stop layer 1808: Interlayer dielectric layer 1810: Patterned hard mask 1812: Patterned interlayer dielectric layer 1814: Metal line region 1816: Hard mask layer 1818: Etch stop layer 1820: Patterned buildup layer 1822: Patterned hard mask 1824: Hard mask 1826: Primary patterned memory layer 1828: Block line 1830: Insulation spacer forming material layer 1832: Spacer 1834: Secondary patterned memory layer 1836: Patterned etch stop layer 1838: Patterned hard mask layer 1840: Secondary patterned interlayer dielectric layer 1842: Patterned etch stop layer 1844: Via location 1846: Location 1848: Metal via 1850: Metal line 1900: Start point structure 1900’: Structure 1900”: Structure 1902: Metal Line 1904: Dielectric Line 1906: Hard Mask 1908: Next Patterned Layer 1910: Etch Stop 1912: Dielectric Layer 1914: Grating Structure 1916: Patterned Dielectric Layer 1918: Patterned Etch Stop 1920: Via Location 1922: Patterned Hard Mask 1924: Area 1926: Patterned Lithography Mask 1928: Area 1930: Lower Structure 1932: Metal Via 1934: Metal Line 1936: Metal Line 1938: Metal Line 1940: Hard Mask 2000: Starting point structure 2002: Interlayer dielectric (ILD) material layer 2004: First hard mask layer 2006: Second hard mask layer 2008: Third hard mask layer 2010: Lithographic patterned mask 2012: Patterned hard mask layer 2014: Patterned ILD layer 2016: Patterned hard mask layer 2018: Metal line 2020: Conductive via 2100: Metallization layer 2102: Metal line 2103: Underside via 2104: Dielectric layer 2105: Line termination or plug area 2106: Line trench 2108: Via trench 2110: Hard mask layer 2112: Trench 2114: Via trench 2120: Lower metallization layer 2122: Metal line 2124: Dielectric layer 2126: Interlayer dielectric (ILD) material layer 2128, 2128’: Trench 2130: Lower portion 2130’: Patterned lower portion 2132A, 2132B: Via trench 2134: Sacrificial material 2134’: Patterned and filled sacrificial material 2136: Patterned hard mask layer 2138: Dielectric material 2140A, 2140B: Dielectric plug 2142: Metal line 2144: Conductive via 2150: Seam 2152: Dielectric plug 2152A, 2152B: Dielectric plug 2154': Patterned dielectric layer 2202: Substrate or layer 2204: Hole/trench 2206: Placeholder material 2208: Slight recess 2210: Patterned layer 2212: Opening 2214: Re-exposed hole/trench 2216: Material layer 2252: Metallization layer 2254: Metal line 2256, 2258: ILD material 2260: Sacrificial placeholder material 2262: Mask layer 2264: Opening 2266: Via location 2300: Starting structure 2302: Interlayer dielectric (ILD) layer 2302': Patterned ILD layer 2304: First hard mask material layer 2306: Patterned mask 2308: Spacers 2310: First patterned hard mask 2312: Second patterned hard mask 2314: Hard mask cap layer 2316: First patterned hard mask 2318: Photobucket 2320: Via location 2322: Hard mask material 2324: Photobucket 2326: Location 2328: Via opening 2330: Metal line opening 2332: Metallization 2334: Upper region 2350: Start of grating structure 2351: Substrate 2352: Grating ILD layer 2354: First hard mask layer 2356: Second hard mask layer 2358: Opening 2358': Upper opening 2360: Dielectric layer 2362: Photobucket 2364: Via location 2364': Opening 2366: Remaining opening 2400: Starting point structure 2402: Metal line 2404: Interlayer dielectric (ILD) line 2406: First-level metal line 2408: ILD material layer 2410: Hard mask layer 2412: Trench 2414: Patterned ILD layer 2416: Photobucket 2418: Via location 2420: Final ILD material 2422: Metal line 2424: Via 2450: Single plane 2497: Seam 2498: Seam 2499: Seam 2500: Starting Structure 2502: Interlayer Dielectric (ILD) Layer 2502': Patterned ILD Layer 2504: First Hard Mask Material Layer 2506: Patterned Mask 2508: Spacer 2510: Trench 2512: First Color Photobucket 2512A: Selected First Color Photobucket 2513A: Selected Via Opening 2514: Trench 2516: Second Color Photobucket Material Layer 2518: Second Color Photobucket 2518A, 2518B: Selected Second Color Photobucket 2519A, 2519B: Via Opening 2520: Second Hard Mask 2521: Red Bulk Exposure 2522: Third Hard Mask 2523: Green bulk exposure 2524: Via location 2526: Metal line trench 2600: Traditional BEOL metallization layer 2602: Interlayer dielectric layer 2604: Conductive line or routing 2606: Cut, break, or plug 2608: Upper or lower level routing 2610: Conductive line 2612: Conductive via 2650: BEOL metallization layer 2652: Interlayer dielectric layer 2654: Conductive line or routing 2656: Cut, break, or plug 2658: Conductive tab 2700: Substrate 2702: Interlayer dielectric (ILD) layer 2704: Cover hard mask 2706: First grating hard mask 2706': Portion 2708: Second grating hard mask 2710: Overlying hard mask 2712: Photobucket 2714: First patterned hard mask 2715: Second patterned hard mask 2716: Dielectric region 2718: Photobucket 2720: Third patterned hard mask 2722: Patterned ILD layer 2724: Conductive line 2726: Plug 2728: Conductive sheet 2800: Metal layer 2802: Overlying hard mask layer 2804: First grating hard mask 2806: Second grating hard mask 2808: Overlying hard mask 2810: Third hard mask 2812: Fourth hard mask 2814: Opening 2816: Photobucket 2818: Etching trenches 2820: First patterning of hard mask 2822: First patterning of metal layer 2824: Conductive vias 2826: Deep hard mask area 2828: Shallow hard mask area 2830: Opening 2832: Photobucket 2834: Second patterning of hard mask 2836: Trench 2838: Deep hard mask area 2840: Shallow hard mask area 2842: Third patterning of hard mask 2844: Second patterning of metal layer 2846: Deep hard mask area 2848: Opening 2850: Photobucket 2852: Fourth patterning of hard mask 2854: Trench 2856: Third patterning of metal layer 2858: Via cap 2860: ILD 2861: ILD backfill 2862: Plug area 2864: Conductive line 2866: Conductive sheet 2899: ILD layer 2902: Substrate 2904: Pre-patterned hard mask 2906: Second-stage photoresist bake 2907: Exposure 2908: Shifted aerial image 2912: Closed photoresist 2920: Opening 2950: Partially cleared 2952: Residual photoresist 2954: Photoresist 3002, 3002’, 3002”: First photoresist 3004, 3004’, 3004”: Second photoresist 3006, 3006’: Exposure 3010, 3010’, 3010”: Photoacid Generator (PAG) Component 3012: Photoradical Generator Component 3014: Inhibitor 3020, 3022: Diffused Material 3024, 3026: Material 3028, 3030: Material 3032: Cleared Photobucket 3034: Blocked Photobucket 3050: Grafted Photoradical Generator Component 3060: Layer 3100: Pattern 3102: ILD Line 3104: Resist Line 3106: Hole 3202: ILD Material 3204: Trench 3206: Chemically Amplified Photoresist 3208: Region 3210: Pre-catalyst Layer 3212: Dielectric Material 3212A, 3212B: Portion 3214: Crosslinking region 3216: Metal fill layer 3218: Metal features 3300: Trisilane 3320: Crosslinking material 3340: Linked trisilane structure 3400: Starting structure 3402: Interlayer dielectric (ILD) layer 3402’, 3402”, 3402’’’, 3402’’’’, 3402’’’’: Patterned ILD layer 3404: First hard mask material layer 3406: Patterned mask 3408: Spacer 3410: First patterned hard mask 3412: Second patterned hard mask 3414: Hard Mask Capping Layer 3416: First Patterned Hard Mask 3418: Fourth Hard Mask Layer 3420: First Diagonal Hard Mask Layer 3422: Closest Neighbor Distance 3424: Photobucket 3426: Via Location 3428: Hard Mask Material 3430: Photobucket 3432: Via Location 3434: Sacrificial Material 3436: Trench 3438: Second Diagonal Hard Mask Layer 3440: Photobucket 3442: Closest Neighbor Distance 3444: Trench 3446: Hard Mask Material Layer 3448: Photobucket 3450: Location 3452: Trench 3454: Metallization 3456: Metal Features 3502: First pre-patterned hard mask 3504: Second pre-patterned hard mask 3506: Lower layer 3508: Opening 3510: Photoresist layer portion 3512: Selected 3514: Lithographic exposure 3516: Opening 3602: First pre-patterned hard mask 3604: Second pre-patterned hard mask 3610: Photoresist layer portion 3616: Opening 3650A, 3650B, 3650C, 3650D, 3650E: Overlay image 3652A: Upper half 3654A: Lower half 3656A, 3656B, 3656C, 3656D, 3656E: Wide unexposed feature 3658A, 3658B, 3658C, 3658D, 3658E: Wide unexposed feature 3697: Metrology structure 3698: Layer 1 feature 3699: Layer 2 feature 3702: First pre-patterned hard mask 3704: Second pre-patterned hard mask 3710: Photoresist layer portion 3716: Opening 3750A, 3750B, 3750C, 3750D, 3750E: Overlay image 3760A, 3760B, 3760C, 3760D, 3760E: Region 3800: Base 3801: Lithographic mask structure 3802: Patterned absorber layer 3804: Upper layer 3806: Patterned shifter layer 3808: Top surface 3810: Die mid-region 3812: Top surface 3814: Top surface 3820: Frame region 3830: Die-frame interface region 3840: Double-layer stack 3900: Electron beam 3902: Electron source 3904: Electron beam 3906: Limiting aperture 3908: Illumination optics 3910: Output beam 3912: Slit 3914: Thin lens 3916: Shaped aperture 3918: BAA 3920: Section 3921: Beam section 3922: Final aperture 3924: Stage feedback deflector 3926: Resulting electron beam 3928: Point 3930: Wafer 3932: Stage scan 3934: Arrow 4000: Aperture 4002: Line 4004: Arrow 4006: Edge placement error (EPE) 4100, 4102: Aperture 4104, 4106: Line 4108: Arrow 4110: EPE 4112: Distance requirement 4114: Spacing 4200: BAA 4202, 4204: Row 4206: Aperture 4208: Line 4210: Direction 4300: Line 4302: Opening location 4304: Via 4306: Cut 4310: BAA 4312: Scan direction 4350: Stack 4352: Metallization layer 4354,4356,4358,4360,4362,4364,4366,4368: Metal layer 4370,4372: Metal line 4374: Via location 4400: Computing device 4402: Circuit board 4404: Processor 4406: Communication chip 4500: Interposer 4502: First substrate 4504: Second substrate 4506: Ball grid array (BGA) 4508: Metal interconnect 4510: Through hole 4512: Through silicon via (TSV) 4514: Embedded device

FIG. 1A illustrates a cross-sectional view of a starting structure following deposition of a hard mask material layer formed on an inter-layer dielectric (ILD) layer, but before patterning.

FIG1B illustrates a cross-sectional view of the structure of FIG1A following patterning of the hard mask layer by halving the pitch.

FIG2 illustrates a cross-sectional view of a spacer-based sixfold patterning (SBSP) process involving a pitch partitioning of a factor of six.

FIG3 illustrates a cross-sectional view of a spacer-based ninefold patterning (SBNP) process scheme involving a pitch partitioning of a factor of nine.

4A-4N illustrate cross-sectional views of various operations in a method of manufacturing a non-planar semiconductor device, according to an embodiment of the present invention, wherein:

FIG. 5 illustrates the structure of FIG. 4N following exposure of the upper portion of the plurality of fins, according to an embodiment of the present invention.

FIG6A illustrates a cross-sectional view of a non-planar semiconductor device, according to an embodiment of the present invention.

FIG6B illustrates a plan view taken along the a-a' axis of the semiconductor device of FIG6A, according to an embodiment of the present invention.

7A and 7B illustrate cross-sectional views of a target base structure for enabling very fine pitch final patterning of semiconductor layers, according to an embodiment of the present invention.

8A-8H illustrate cross-sectional views representing various operations in a method of fabricating a target base structure for enabling a very fine pitch final patterning of semiconductor layers, according to an embodiment of the present invention.

8H' and 8H" illustrate cross-sectional views of an example structure following via and plug patterning, according to an embodiment of the present invention.

9A-9L illustrate oblique cross-sectional views of a portion of an integrated circuit layer illustrating various operations in a method involving pitch-splitting patterning for increased overlay tolerance for back-end-of-line (BEOL) interconnect fabrication, according to an embodiment of the present invention.

10A-10M illustrate portions of an integrated circuit layer showing various operations in a method of self-aligned via and metal patterning, according to an embodiment of the present invention.

11A-11M illustrate portions of an integrated circuit layer showing various operations in a method of self-aligned via and metal patterning, according to an embodiment of the present invention.

12A-12C illustrate oblique-angle cross-sectional views representing various operations in a method for forming self-aligned vias or contacts for back-end-of-line (BEOL) interconnects using a triblock copolymer, according to an embodiment of the present invention.

12D illustrates an oblique angled cross-sectional view representing operations in a method for forming self-aligned vias or contacts for back-end of line (BEOL) interconnects using a triblock copolymer, in accordance with an embodiment of the present invention.

12E illustrates an oblique angled cross-sectional view showing operations in another method of forming self-aligned vias or contacts for back-end of line (BEOL) interconnects using a triblock copolymer, according to another embodiment of the present invention.

FIG. 12F illustrates a triblock copolymer for forming self-aligned vias or contacts for back-end-of-line (BEOL) interconnects, according to an embodiment of the present invention.

12G and 12H illustrate plan views and corresponding cross-sectional views representing various operations in a method for forming self-aligned vias or contacts for back-end-of-the-line (BEOL) interconnects using a triblock copolymer, according to an embodiment of the present invention.

12I-12L illustrate plan views and corresponding cross-sectional views representing various operations in a method for forming self-aligned vias or contacts for back-end-of-the-line (BEOL) interconnects using a triblock copolymer, according to an embodiment of the present invention.

FIG13 illustrates a plan view and corresponding cross-sectional view of a self-aligned via structure subsequent to metal line, via, and plug formation, according to an embodiment of the present invention.

14A-14N illustrate portions of an integrated circuit layer representing various operations in a method of subtractive self-aligned via and plug patterning, according to an embodiment of the present invention.

15A-15D illustrate portions of an integrated circuit layer representing various operations in a method of subtractive self-aligned plug patterning, according to another embodiment of the present invention.

16A-16D illustrate cross-sectional views of a portion of an integrated circuit layer representing various operations in a method involving formation of a dielectric layer for back-end-of-line (BEOL) interconnect fabrication, according to an embodiment of the present invention.

16E-16P illustrate cross-sectional views of a portion of an integrated circuit layer representing operations in another method involving dielectric helmet formation for back-end-of-line (BEOL) interconnect fabrication, according to an embodiment of the present invention.

17A-17J illustrate cross-sectional views of a portion of an integrated circuit layer representing operations in another method involving dielectric shield formation for back-end-of-line (BEOL) interconnect fabrication, according to an embodiment of the present invention.

18A-18W illustrate plan views and corresponding oblique and cross-sectional views illustrating various operations in a metal via processing scheme for back-end-of-line (BEOL) interconnects, according to an embodiment of the present invention.

19A-19L illustrate plan views and corresponding oblique cross-sectional views illustrating various operations in a grid self-aligned metal via processing scheme for back-end-of-line (BEOL) interconnects, according to an embodiment of the present invention.

20A-20G illustrate plan views and corresponding cross-sectional views illustrating operations in a method of fabricating grating-based plugs and cutting for back-end-of-line (BEOL) interconnect feature formation, according to an embodiment of the present invention.

FIG21A illustrates a plan view and a corresponding cross-sectional view taken along the a-a' axis of a plan view of a metallization layer of a conventional semiconductor device.

FIG. 21B illustrates a cross-sectional view of a terminal or plug manufactured using currently known processing schemes.

FIG. 21C illustrates another cross-sectional view of a terminal or plug manufactured using currently known processing schemes.

21D-21J illustrate cross-sectional views illustrating various operations in a process for patterning metal ends for back-end-of-the-line (BEOL) interconnects, according to an embodiment of the present invention.

21K illustrates a cross-sectional view of a metallization layer of an interconnect structure of a semiconductor die including a dielectric terminal or plug having a seam therein, according to an embodiment of the present invention.

21L illustrates a cross-sectional view of a metallization layer of an interconnect structure of a semiconductor die including a dielectric line end or plug that is not adjacent to a conductive via, according to an embodiment of the present invention.

22A-22G illustrate portions of an integrated circuit layer representing various operations in a method involving self-aligned isotropic etching to preform via or plug locations, according to an embodiment of the present invention.

22H-22J illustrate oblique cross-sectional views showing a portion of an integrated circuit layer illustrating various operations in a method involving self-aligned isotropic etching of preformed via locations, according to an embodiment of the present invention.

23A-23L illustrate portions of an integrated circuit layer representing various operations in a method of subtractive self-aligned via and plug patterning, according to an embodiment of the present invention.

23M-23S illustrate portions of an integrated circuit layer representing various operations in a method of subtractive self-aligned via patterning, according to an embodiment of the present invention.

24A-24I illustrate portions of an integrated circuit layer representing various operations in a method of subtractive self-aligned via and plug patterning, according to an embodiment of the present invention.

25A-25H illustrate portions of an integrated circuit layer representing various operations in a method of subtractive self-aligned via patterning using multi-color photobuckets, according to an embodiment of the present invention.

FIG. 25I illustrates an example two-tone resist for one photobucket type and an example single-tone resist for another photobucket type, according to an embodiment of the present invention.

FIG26A illustrates a plan view of a conventional back-end-of-line (BEOL) metallization layer.

FIG26B illustrates a plan view of a back-end-of-line (BEOL) metallization layer having conductive pads for coupling metal lines of the metallization layer, according to an embodiment of the present invention.

27A-27K illustrate oblique cross-sectional views representing various operations in a method of fabricating a back-end-of-line (BEOL) metallization layer having conductive pads for coupling metal lines of the metallization layer, according to an embodiment of the present invention.

28A-28T illustrate oblique cross-sectional views representing various operations in a method of fabricating a back-end-of-line (BEOL) metallization layer having conductive pads for coupling metal lines of the metallization layer, according to an embodiment of the present invention.

29A-29C illustrate cross-sectional views and corresponding plan views of various operations in a method of patterning using a photobucket including a two-stage photoresist bake, according to an embodiment of the present invention.

FIG29D illustrates a cross-sectional view of a conventional resist photobucket structure after photobucket development following misaligned exposure.

30A-30E illustrate schematic views of various operations in a method of patterning using a photobucket including a two-stage photoresist bake, according to an embodiment of the present invention.

Figure 30A' illustrates a schematic diagram of operations in another method of patterning using light buckets, according to an embodiment of the present invention.

Figure 30A' illustrates a schematic diagram of operations in another method of patterning using light buckets, according to an embodiment of the present invention.

31 illustrates an oblique angle view of alternating interlayer dielectric (ILD) lines and resist lines with a hole formed in one of the resist lines, according to an embodiment of the present invention.

32A-32H illustrate cross-sectional views of a fabrication process involving image tone inversion with a dielectric using bottom-up cross-linking, according to an embodiment of the present invention.

FIG. 33A illustrates a trisilacyclohexane molecule, according to an embodiment of the present invention.

FIG. 33B illustrates two cross-linked (XL) trisilane molecules used to form a cross-linked material, according to an embodiment of the present invention.

FIG. 33C illustrates an idealized representation of a linked trisilane structure, according to an embodiment of the present invention.

34A-34X illustrate portions of an integrated circuit layer representing various operations in a method of self-aligned via and plug patterning using a diagonal hard mask, according to an embodiment of the present invention.

35A-35D illustrate cross-sectional views and corresponding top-down views representing various operations in a patterning process using a pre-patterned hard mask, according to an embodiment of the present invention.

FIG36A illustrates a top-down view of an overlay scenario, where the current layer is overlaid on a lower pre-patterned hard mask grid, according to an embodiment of the present invention.

FIG36B illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of one-quarter the pitch relative to the underlying pre-patterned hard mask grid, according to an embodiment of the present invention.

FIG36C illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of half the pitch relative to the underlying pre-patterned hard mask grid, according to an embodiment of the present invention.

FIG36D illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of an arbitrary value of Δ relative to the underlying pre-patterned hard mask grid, according to an embodiment of the present invention.

36E illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of an arbitrary value of Δ relative to the underlying pre-patterned hard mask grid, where the measurable Δ can be made as small as desired by varying the resist sensitivity and/or the drawn feature size, according to embodiments of the present invention.

FIG. 36F illustrates an example metrology structure suitable for use in the manner described above with respect to FIGs. 36A-36E, according to an embodiment of the present invention.

FIG37A illustrates a top-down view of an overlay scenario, where the current layer is overlaid on a pre-patterned hard mask below, according to an embodiment of the present invention.

FIG37B illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of one-quarter the pitch relative to the underlying pre-patterned hard mask grid in the X direction, according to an embodiment of the present invention.

37C illustrates a top-down view of an overlay scenario where the current layer has a negative overlay of one-quarter the pitch of the underlying pre-patterned hard mask grid in the X direction, according to an embodiment of the present invention.

FIG37D illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of one-quarter the pitch of the underlying pre-patterned hard mask grid in the Y direction, according to an embodiment of the present invention.

37E illustrates a top-down view of an overlay scenario where the current layer has a positive overlap of one-quarter the pitch of the underlying pre-patterned hard mask grid in the X direction and a positive overlap of one-quarter the pitch of the underlying pre-patterned hard mask grid in the Y direction, according to an embodiment of the present invention.

FIG38 illustrates a cross-sectional view of a lithography mask structure according to an embodiment of the present invention.

FIG39 is a schematic cross-sectional view of an electron beam column of an electron beam lithography apparatus.

FIG40 illustrates the apertures of a blocked aperture array (BAA) (left) relative to a line to be cut or having a via placed in a target location (right) as the line is scanned under the aperture.

Figure 41 illustrates two non-staggered apertures (left) of a BAA relative to two lines to be cut or with a through hole placed in the target location (right) when the line is scanned under the aperture.

42 illustrates two rows of staggered apertures (left) of a BAA relative to a plurality of lines to be cut or having through holes placed in target locations (right), with the scan direction indicated by arrows as the lines are scanned under the apertures, according to an embodiment of the present invention.

43A illustrates two rows of staggered apertures (left) of a BAA with cuts (breaks in horizontal lines) or multiple lines of vias (filled in boxes) patterned using staggered BAAs (right), with the scanning direction indicated by arrows, according to an embodiment of the present invention.

FIG43B illustrates a cross-sectional view of a metallization layer stack in an integrated circuit according to a metal line layout of the type shown in FIG21A, in accordance with an embodiment of the present invention.

Figure 44 illustrates a computing device according to one embodiment of the present invention.

Figure 45 illustrates an inserter that includes one or more embodiments of the present invention.

100: Start Structure

102: Interlayer dielectric (ILD) layer

104: Hard Mask Material Layer

106: Patterned Mask

108: Spacer

Claims (20)

A method for manufacturing an integrated circuit structure, the method comprising: forming a plurality of backbone features on a semiconductor substrate, a semiconductor layer, or a stack of semiconductor layers; forming a first set of spacers along the sidewalls of each of the plurality of backbone features, the first set of spacers having a first material composition different from the material composition of the plurality of backbone features; forming a second set of spacers along the sidewalls of each of the first set of spacers, the second set of spacers having a second material composition different from the first material composition and different from the material composition of the plurality of backbone features; forming the second set of spacers along the sidewalls of each of the first set of spacers, After forming the plurality of bone features, removing the plurality of bone features; forming a third set of spacers along the sidewalls of each of the first set of spacers after removing the plurality of bone features, the third set of spacers having the second material composition; forming final features in each opening between adjacent pairs of spacers in the third set of spacers; planarizing the first set of spacers, the second set of spacers, the third set of spacers, and the final features to form a target base layer; and using the target base layer to form a plurality of fins or three-dimensional bodies in the semiconductor substrate, the semiconductor layer, or the stack of semiconductor layers. The method of claim 1, wherein forming the plurality of bone features comprises using standard lithography operations. The method of claim 1, wherein forming the plurality of backbone features comprises forming the plurality of features comprising a material selected from the group consisting of silicon nitride, silicon oxide, and silicon carbide. The method of claim 1, wherein forming the first set of spacers comprises: using an atomic layer deposition (ALD) process to deposit a material of the first set of spacers that is conformal to the plurality of bone features; and anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of the plurality of bone features. The method of claim 1, wherein forming the first set of spacers comprises selectively growing material of the first set of spacers along the sidewalls of each of the plurality of bone features. The method of claim 1, wherein each last feature has a side width greater than the side width of each spacer from the first set of spacers, the second set of spacers, and the third set of spacers. The method of claim 1, wherein each final feature is formed by merging the growth of material formed along adjacent pairs of spacers of the third set of spacers. The method of claim 1, wherein each final feature comprises the third material composition. The method of claim 1, wherein forming the metallization layer of the semiconductor structure using the target base layer comprises: removing all portions of the first material composition to form a first plurality of trenches; and forming a first plurality of conductive lines in the first plurality of trenches. The method of claim 9, wherein using the target base layer to form the metallization layer of the semiconductor structure further comprises: forming a second plurality of trenches; and forming a second plurality of conductive lines in the second plurality of trenches. The method of claim 10, wherein the first plurality of conductive wires and the second plurality of conductive wires are composed of the same composition. The method of claim 10, wherein the first plurality of conductive wires and the second plurality of conductive wires are of different compositions. The method of claim 1, further comprising forming an additional set of spacers between the second set of spacers and the third set of spacers and before removing the plurality of bone features. A method for manufacturing an integrated circuit structure, the method comprising: forming a plurality of backbone features on a semiconductor substrate, a semiconductor layer, or a stack of semiconductor layers; forming a first set of spacers along the sidewalls of each of the plurality of backbone features, the first set of spacers having a first material composition different from the material composition of the plurality of backbone features; forming a second set of spacers along the sidewalls of each of the first set of spacers, the second set of spacers having a first material composition different from the material composition of the first set of spacers; A second material composition comprising a first material composition different from the material composition of the plurality of bone characteristics; a third set of spacers formed along the sidewalls of each of the second set of spacers, each of the third set of spacers comprising a third material composition different from the first material composition, the second material composition, and the material composition of the plurality of bone characteristics; a fourth set of spacers formed along the sidewalls of each of the third set of spacers, each of the fourth set of spacers comprising forming a fifth set of spacers laterally adjacent to the sidewalls of each of the fourth set of spacers, the fifth set of spacers having the first material composition; after forming the fifth set of spacers, removing the plurality of bone features; after removing the plurality of bone features, forming a sixth set of spacers along the sidewalls of each of the first set of spacers and along the sidewalls of each of the fifth set of spacers, the sixth set of spacers having the second material composition ; forming final features in each opening between adjacent pairs of the sixth set of spacers; planarizing the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, the sixth set of spacers, and the final features to form a target base layer; and using the target base layer to form a plurality of fins or three-dimensional bodies in the semiconductor substrate, the semiconductor layer, or the stack of semiconductor layers. The method of claim 14, wherein forming the plurality of bone features comprises using standard lithography operations. The method of claim 14, wherein forming the plurality of backbone features comprises forming the plurality of features comprising a material selected from the group consisting of silicon nitride, silicon oxide, and silicon carbide. The method of claim 14, wherein forming the first set of spacers comprises: using an atomic layer deposition (ALD) process to deposit a material of the first set of spacers that is conformal to the plurality of bone features; and anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of the plurality of bone features. The method of claim 14, wherein forming the first set of spacers comprises selectively growing material of the first set of spacers along the sidewalls of each of the plurality of bone features. The method of claim 14, wherein each last feature has a side width greater than the side width of each spacer from the first group of spacers, the second group of spacers, the third group of spacers, the fourth group of spacers, the fifth group of spacers, and the sixth group of spacers. The method of claim 14, wherein each final feature is formed by merging the growth of material formed along adjacent pairs of spacers of the sixth set of spacers.