TWI897745B - Electronic device and method of suppressing noise generated by buck ic - Google Patents
Electronic device and method of suppressing noise generated by buck icInfo
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Abstract
Description
本發明係關於一種電子裝置及抑制升降壓電路雜訊的方法,特別是一種設有抗雜訊電容的電子裝置及抑制升降壓電路雜訊的方法。The present invention relates to an electronic device and a method for suppressing noise in a buck-boost circuit, and in particular to an electronic device equipped with an anti-noise capacitor and a method for suppressing noise in a buck-boost circuit.
近年來,在電子產品中,根據使用者的需求而令電路板的設計越來越複雜,使得電路板上的電子元件所產生的雜訊干擾程度越來越嚴重,進而會影響電子元件的運作。In recent years, the design of circuit boards in electronic products has become increasingly complex to meet user needs. This has led to increasingly severe noise interference generated by the electronic components on the circuit boards, which in turn affects the operation of the electronic components.
一般來說,製造廠商會在電路板上加裝抑制雜訊的吸波材。然而,額外加裝吸波材會增加電子產品的製造成本,且會影響電路板的配置。因此,如何有效降低電子元件所產生的雜訊強度,即為研發人員應解決的問題之一。Typically, manufacturers install noise-reducing absorbers on circuit boards. However, this additional absorber increases the manufacturing cost of electronic products and affects the circuit board's configuration. Therefore, effectively reducing the noise intensity generated by electronic components is a challenge that researchers must address.
本發明在於提供一種電子裝置及抑制升降壓電路雜訊的方法,藉以有效降低電子裝置中的雜訊強度。The present invention provides an electronic device and a method for suppressing noise in a buck-boost circuit, thereby effectively reducing the noise intensity in the electronic device.
本發明之一實施例所揭露之電子裝置用以供一升降壓電路設置,並包含一機體、一電路板以及多個抗雜訊電容。電路板設置於機體,並用以供升降壓電路設置。電路板具有一電源層。電源層具有多個電源穿層部。這些抗雜訊電容設置於電源層之至少一側。至少部分這些抗雜訊電容分別位於靠近這些電源穿層部處。至少另一部分這些抗雜訊電容位於遠離這些電源穿層部處。位於遠離這些電源穿層部處之這些抗雜訊電容中任二相鄰者之間的間距用以小於等於升降壓電路所產生之雜訊的波長之八分之一。An electronic device disclosed in one embodiment of the present invention is configured for a buck-boost circuit and includes a housing, a circuit board, and a plurality of anti-noise capacitors. The circuit board is mounted on the housing and configured for the buck-boost circuit. The circuit board has a power supply layer. The power supply layer has a plurality of power supply through-layer portions. The anti-noise capacitors are disposed on at least one side of the power supply layer. At least some of the anti-noise capacitors are located near each of the power supply through-layer portions. At least another portion of the anti-noise capacitors is located away from each of the power supply through-layer portions. The distance between any two adjacent anti-noise capacitors located away from the power supply through-layers is designed to be less than or equal to one-eighth of the wavelength of the noise generated by the buck-boost circuit.
本發明之另一實施例所揭露之抑制升降壓電路雜訊的方法包含設置至少部分多個抗雜訊電容於靠近一電路板之一電源層的多個電源穿層部處以及設置至少另一部分這些抗雜訊電容於遠離這些電源穿層部處。其中,位於遠離這些電源穿層部處之這些抗雜訊電容中任二相鄰者之間的間距小於等於一升降壓電路所產生之雜訊的波長之八分之一。Another embodiment of the present invention discloses a method for suppressing noise in a buck-boost circuit, comprising disposing at least some of a plurality of anti-noise capacitors near a plurality of power-through-layer portions of a power layer of a circuit board and at least some of these anti-noise capacitors away from these power-through-layer portions. The distance between any two adjacent anti-noise capacitors located away from these power-through-layer portions is less than or equal to one-eighth the wavelength of the noise generated by the buck-boost circuit.
根據上述實施例之電子裝置及抑制升降壓電路雜訊的方法,由於至少部分這些抗雜訊電容分別位於靠近這些電源穿層部處,至少另一部分這些抗雜訊電容位於遠離這些電源穿層部處,且位於遠離這些電源穿層部處之這些抗雜訊電容中任二相鄰者之間的間距例如小於等於升降壓電路所產生之雜訊的波長之八分之一,故可有效降低電子裝置中的雜訊強度,且不會因設置過多抗雜訊電容而造成電子裝置的製造成本過高,亦不會因為設置過少抗雜訊電容而使抗雜訊效果不佳,更不會因為設置過少抗雜訊電容而造成電路的短路或斷路。According to the electronic device and the method for suppressing noise in the buck-boost circuit of the above embodiment, at least part of the anti-noise capacitors are located near the power supply through-layer portions, at least another part of the anti-noise capacitors are located far from the power supply through-layer portions, and the distance between any two adjacent anti-noise capacitors located far from the power supply through-layer portions is, for example, less than This is equivalent to one-eighth the wavelength of the noise generated by the buck-boost circuit, effectively reducing the noise intensity in electronic devices. This prevents excessive manufacturing costs from excessively high anti-noise capacitors, poor anti-noise performance from insufficient anti-noise capacitors, and prevents short circuits or open circuits from occurring due to insufficient anti-noise capacitors.
以上關於本發明內容的說明及以下實施方式的說明係用以示範與解釋本發明的原理,並且提供本發明的專利申請範圍更進一步的解釋。The above description of the content of the present invention and the following description of the embodiments are used to demonstrate and explain the principles of the present invention and provide further explanation of the scope of the patent application of the present invention.
請參閱圖1至圖3。圖1為根據本發明實施例所述之電子裝置的平面示意圖。圖2為圖1之電子裝置之雜訊頻率的折線圖。圖3為根據本發明實施例所述之抑制升降壓電路雜訊的方法的流程示意圖。Please refer to Figures 1 to 3. Figure 1 is a schematic plan view of an electronic device according to an embodiment of the present invention. Figure 2 is a line graph of the noise frequency of the electronic device of Figure 1. Figure 3 is a flow chart of a method for suppressing noise in a buck-boost circuit according to an embodiment of the present invention.
本實施例之電子裝置10用以供一升降壓電路(未繪示)設置,並包含一機體11、一電路板12以及多個抗雜訊電容13。電路板12設置於機體11,且電路板12之一側用以供升降壓電路設置。電路板12之另一側具有一電源層121,但不以此為限。電源層121具有多個電源穿層部1211。這些電源穿層部1211即對應於電源(source)、記憶體(memory)與通用序列匯流排(USB)的通孔。其中,電源層121沿X軸方向上的長度L1例如為130毫米,且電源層121沿Y軸方向上的長度L2例如為76毫米。The electronic device 10 of this embodiment is used for providing a buck-boost circuit (not shown) and includes a body 11, a circuit board 12, and a plurality of anti-noise capacitors 13. The circuit board 12 is provided on the body 11, and one side of the circuit board 12 is used for providing the buck-boost circuit. The other side of the circuit board 12 has a power layer 121, but is not limited thereto. The power layer 121 has a plurality of power through-layer portions 1211. These power through-layer portions 1211 correspond to through-holes for the power source, memory, and universal serial bus (USB). The length L1 of the power layer 121 along the X-axis direction is, for example, 130 mm, and the length L2 of the power layer 121 along the Y-axis direction is, for example, 76 mm.
這些抗雜訊電容13係根據電路板12的其他電子元件的配置,而將這些抗雜訊電容13至少部分設置於電源層121之一側,以及將這些抗雜訊電容13至少部分設置於電源層121之相對兩側。同理,電源層121之相對兩端亦根據電路板12的其他電子元件的配置,而使電源層121之一端設有一抗雜訊電容13,以及使電源層121之另一端設有二抗雜訊電容13。透過抗雜訊電容13之高阻抗反射的特性,可降低升降壓電路所產生的雜訊。These anti-noise capacitors 13 are positioned at least partially on one side of the power layer 121 and at least partially on opposite sides of the power layer 121, depending on the placement of other electronic components on the circuit board 12. Similarly, the power layer 121 is also positioned at opposite ends, with one anti-noise capacitor 13 positioned at one end and two anti-noise capacitors 13 positioned at the other end. The high-impedance reflective properties of the anti-noise capacitors 13 reduce noise generated by the buck-boost circuit.
至少部分這些抗雜訊電容13分別位於靠近這些電源穿層部1211處,且至少另一部分這些抗雜訊電容13位於遠離這些電源穿層部1211處。位於遠離這些電源穿層部1211處之這些抗雜訊電容13中任二相鄰者之間的間距例如小於等於升降壓電路所產生之雜訊的波長之八分之一。如此一來,例如在雜訊頻率為734至741兆赫(MHz)的範圍中,可將雜訊強度例如自-88.05 dBm降低至-94.03 dBm,甚至可將部分頻段之雜訊強度降低至-97.72 dBm。At least some of these anti-noise capacitors 13 are located near these power supply through-layer portions 1211, and at least another portion of these anti-noise capacitors 13 is located away from these power supply through-layer portions 1211. The distance between any two adjacent anti-noise capacitors 13 located away from these power supply through-layer portions 1211 is, for example, less than or equal to one-eighth of the wavelength of the noise generated by the buck-boost circuit. In this way, for example, within the noise frequency range of 734 to 741 MHz, the noise intensity can be reduced from -88.05 dBm to -94.03 dBm, and even to -97.72 dBm in some frequency bands.
舉例來說,選擇升降壓電路所產生之雜訊頻率為800兆赫的波長,即位於遠離這些電源穿層部1211處之這些抗雜訊電容13中任二相鄰者之間的間距小於等於2公分。此外,這些抗雜訊電容13根據與雜訊的共振頻率,而選擇電容值例如為180皮法(pF)的抗雜訊電容13。For example, the noise frequency generated by the buck-boost circuit is selected to have a wavelength of 800 MHz. This means that the distance between any two adjacent anti-noise capacitors 13 located far from the power supply through-layer portions 1211 is less than or equal to 2 cm. Furthermore, the capacitance of these anti-noise capacitors 13 is selected to have a resonant frequency with the noise, such as 180 pF.
在本實施例中,由於至少部分這些抗雜訊電容13分別位於靠近這些電源穿層部1211處,至少另一部分這些抗雜訊電容13位於遠離這些電源穿層部1211處,且位於遠離這些電源穿層部1211處之這些抗雜訊電容13中任二相鄰者之間的間距例如小於等於升降壓電路所產生之雜訊的波長之八分之一,故可有效降低電子裝置10中的雜訊強度,且不會因設置過多抗雜訊電容13而造成電子裝置10的製造成本過高,亦不會因為設置過少抗雜訊電容13而使抗雜訊效果不佳,更不會因為設置過少抗雜訊電容13而造成電路的短路或斷路。In this embodiment, at least part of the anti-noise capacitors 13 are located near the power through-layer portions 1211, and at least another part of the anti-noise capacitors 13 are located away from the power through-layer portions 1211. The distance between any two adjacent anti-noise capacitors 13 located away from the power through-layer portions 1211 is, for example, less than or equal to the step-up/step-down voltage. The wavelength of the noise generated by the circuit is one-eighth of that of the noise generated by the circuit, so the noise intensity in the electronic device 10 can be effectively reduced. The manufacturing cost of the electronic device 10 will not be too high due to the provision of too many anti-noise capacitors 13, nor will the anti-noise effect be poor due to the provision of too few anti-noise capacitors 13, nor will the circuit be short-circuited or open-circuited due to the provision of too few anti-noise capacitors 13.
在本實施例中,電路板12之一側用以供升降壓電路設置,且電路板12之另一側具有一電源層121,但不以此為限。在其他實施例中,也可以根據電路板的其他電子元件的配置,而使電路板之同一側設有升降壓電路與電源層。In this embodiment, one side of the circuit board 12 is used for the buck-boost circuit, and the other side of the circuit board 12 has a power supply layer 121, but the present invention is not limited to this. In other embodiments, the buck-boost circuit and the power supply layer can also be provided on the same side of the circuit board according to the configuration of other electronic components of the circuit board.
在本實施例中,這些抗雜訊電容13至少部分設置於電源層121之一側,以及將這些抗雜訊電容13至少部分設置於電源層121之相對兩側,但不以此為限。在其他實施例中,也可以根據電路板的其他電子元件的配置,而將這些抗雜訊電容皆設置於電源層之一側,或將這些抗雜訊電容皆設置於電源層之相對兩側。In this embodiment, the anti-noise capacitors 13 are at least partially disposed on one side of the power layer 121, and at least partially disposed on two opposite sides of the power layer 121, but the present invention is not limited thereto. In other embodiments, depending on the configuration of other electronic components on the circuit board, the anti-noise capacitors may be disposed entirely on one side of the power layer, or on two opposite sides of the power layer.
在本實施例中,電源層121之一端設有一抗雜訊電容13,以及使電源層121之另一端設有二抗雜訊電容13,但不以此為限。在其他實施例中,也可以根據電路板的其他電子元件的配置,而使電源層之相對兩端皆設有一抗雜訊電容,或使電源層之相對兩端皆設有二抗雜訊電容。In this embodiment, a single anti-noise capacitor 13 is provided at one end of the power layer 121, and a second anti-noise capacitor 13 is provided at the other end of the power layer 121, but this is not limiting. In other embodiments, depending on the configuration of other electronic components on the circuit board, a single anti-noise capacitor may be provided at both opposing ends of the power layer, or a second anti-noise capacitor may be provided at both opposing ends of the power layer.
在本實施例中,這些抗雜訊電容13的電容值為180皮法,但不以此為限。在其他實施例中,也可以根據這些抗雜訊電容與雜訊的共振頻率,而選擇電容值為150皮法的抗雜訊電容。In this embodiment, the capacitance value of these anti-noise capacitors 13 is 180 pF, but is not limited thereto. In other embodiments, an anti-noise capacitor with a capacitance value of 150 pF may be selected based on the resonance frequency of these anti-noise capacitors and the noise.
在本實施例中,抑制升降壓電路雜訊的方法包含但不限於下列步驟。首先,如步驟S100所述,設置至少部分多個抗雜訊電容13於靠近一電路板12之一電源層121的多個電源穿層部1211處。接著,如步驟S200所述,設置至少另一部分這些抗雜訊電容13於遠離這些電源穿層部1211處。其中,步驟S100與步驟S200不以前述的順序為限。此外,位於遠離這些電源穿層部1211處之這些抗雜訊電容13中任二相鄰者之間的間距例如小於等於一升降壓電路所產生之雜訊的波長之八分之一。如此一來,可降低升降壓電路所產生的雜訊強度。In this embodiment, the method for suppressing noise in a buck-boost circuit includes, but is not limited to, the following steps. First, as described in step S100, at least some of the plurality of anti-noise capacitors 13 are positioned near a plurality of power-through-layer portions 1211 of a power layer 121 of a circuit board 12. Next, as described in step S200, at least another portion of these anti-noise capacitors 13 are positioned away from these power-through-layer portions 1211. Steps S100 and S200 are not limited to the order described above. Furthermore, the distance between any two adjacent anti-noise capacitors 13 located far from the power supply through-layer portions 1211 is, for example, less than or equal to one eighth of the wavelength of the noise generated by a buck-boost circuit. This reduces the noise intensity generated by the buck-boost circuit.
根據上述實施例之電子裝置及抑制升降壓電路雜訊的方法,由於至少部分這些抗雜訊電容分別位於靠近這些電源穿層部處,至少另一部分這些抗雜訊電容位於遠離這些電源穿層部處,且位於遠離這些電源穿層部處之這些抗雜訊電容中任二相鄰者之間的間距例如小於等於升降壓電路所產生之雜訊的波長之八分之一,故可有效降低電子裝置中的雜訊強度,且不會因設置過多抗雜訊電容而造成電子裝置的製造成本過高,亦不會因為設置過少抗雜訊電容而使抗雜訊效果不佳,更不會因為設置過少抗雜訊電容而造成電路的短路或斷路。According to the electronic device and the method for suppressing noise in the buck-boost circuit of the above embodiment, at least part of the anti-noise capacitors are located near the power supply through-layer portions, at least another part of the anti-noise capacitors are located far from the power supply through-layer portions, and the distance between any two adjacent anti-noise capacitors located far from the power supply through-layer portions is, for example, less than This is equivalent to one-eighth the wavelength of the noise generated by the buck-boost circuit, effectively reducing the noise intensity in electronic devices. This prevents excessive manufacturing costs from excessively high anti-noise capacitors, poor anti-noise performance from insufficient anti-noise capacitors, and prevents short circuits or open circuits from occurring due to insufficient anti-noise capacitors.
雖然本發明以前述之諸項實施例揭露如上,然其並非用以限定本發明,任何熟習相像技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。Although the present invention is disclosed above with reference to the aforementioned embodiments, they are not intended to limit the present invention. Anyone skilled in the art may make slight modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be determined by the scope of the patent application attached to this specification.
10:電子裝置 11:機體 12:電路板 121:電源層 1211:電源穿層部 13:抗雜訊電容 L1,L2:長度 S100,S200:步驟10: Electronic device 11: Frame 12: Circuit board 121: Power supply layer 1211: Power supply through-layer 13: Anti-noise capacitor L1, L2: Length S100, S200: Steps
圖1為根據本發明實施例所述之電子裝置的平面示意圖。 圖2為圖1之電子裝置之雜訊強度的折線圖。 圖3為根據本發明實施例所述之抑制升降壓電路雜訊的方法的流程示意圖。 Figure 1 is a schematic plan view of an electronic device according to an embodiment of the present invention. Figure 2 is a line graph of the noise intensity of the electronic device shown in Figure 1. Figure 3 is a flow chart of a method for suppressing noise in a buck-boost circuit according to an embodiment of the present invention.
10:電子裝置 10: Electronic devices
11:機體 11: Body
12:電路板 12: Circuit board
121:電源層 121: Power supply layer
1211:電源穿層部 1211: Power supply through layer
13:抗雜訊電容 13: Anti-noise capacitor
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| US8377746B2 (en) * | 2008-02-19 | 2013-02-19 | Texas Instruments Incorporated | Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom |
| US11184981B2 (en) * | 2015-10-21 | 2021-11-23 | Adventive IP Bank | Method of supplying electrical power from rigid printed circuit board to another rigid printed circuit board in rigid-flex printed circuit board array |
| TWI851086B (en) * | 2023-03-16 | 2024-08-01 | 英業達股份有限公司 | Common mode filter and signal transmission circuit |
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