TWI897508B - Memory device and detection method for defeat status of memory cell - Google Patents

Abstract

A memory device and a detection method for detecting defeat status of memory cell are provided. The memory device is, for example a three dimensional NAND flash memory circuit, and provides a storage media with high-performance and high-capacity. The detection method includes: extracting a plurality of status data stored in a page buffer, finding setting status memory cells among memory cells, and obtaining status data; storing status data to a storage device; after first half levels programming operation are completed, setting one of latches to a selected latch; storing each setting status data to the selected latch; and checking each of the setting status memory cells according to each setting status data to determine whether each of the setting status memory cells is maintained in a setting status.

Description

Memory device and method for detecting failure status of memory cell

The present invention relates to a method for detecting the failure status of a memory device and a memory cell, and more particularly to a method for detecting the failure status of a memory device and a memory cell that can prevent data loss.

Refer to Figure 1 for a diagram illustrating a known flash memory word line failure. In the flash memory field, during programming, verification is required on the programmed memory cells to ensure that the data is correctly written to the memory cells. Furthermore, if data is found to be incorrectly written to the memory cells, it is written to another memory page to prevent data loss.

In conventional technology, after word line WLn is programmed multiple times, short circuits may occur between word line WLn and adjacent word lines WLn+1 and/or WLn-1 due to repeated biasing of word line WLn. This failure cannot be recovered through programming verification and error correction code (ECC) technology.

The present invention provides a memory device and a method for detecting the failure status of its memory cells, which can effectively detect failed memory cells caused by over-programming.

The present invention provides a method for detecting a failure state of a memory cell, comprising: searching a plurality of state data stored in a page buffer, finding a plurality of set-state memory cells in a set state among a plurality of memory cells, and obtaining a plurality of set-state data corresponding to the set-state memory cells; storing the state data in a storage device; executing a multi-level programmed action in the front After half of the level programming actions are completed, one of the multiple latches in the page buffer is set as a selected latch; the storage device is caused to transfer each configuration state data to the selected latch; and each configuration state memory cell is checked based on each configuration state data to determine whether each configuration state memory cell remains in the configuration state.

The memory device of the present invention includes a page buffer, a storage device, and a controller. The page buffer is coupled to at least one bit line of a memory block and includes multiple latches and a bit line bias and sensing circuit. The storage device is coupled to the page buffer. The controller is coupled to the storage device and the page buffer to execute the above-described method for detecting a memory cell failure.

Based on the above, the present invention performs memory cell failure detection during programming. This detects whether a set-state memory cell remains in its set state after programming, thereby determining whether the set-state memory cell is a failed memory cell. Furthermore, the memory device of the present invention can mask failed memory cells to prevent misuse and data loss, effectively enhancing data security.

300: Memory device

310~313: Latch

320: Bit line bias and sensing circuit

330: Storage device

340: Controller

BH0~BH4: Data Holder

BL: Bit Line

DBUS1, DBUS2: Buses

DLB, DL: Data

M31~M37: Transistors

ND: Node

PB: Page Buffer

PDL, PDLB, PL1~PL3, CNB, DSEL, BLC1, BLC2, BLDC: Control signals

S1~S10: Switch

S210~S250, S410~S4170: Steps

SEN: Sense signal

VDDI: voltage

VSS: Reference ground

WLn, WLn+1, WLn-1: character lines

Figure 1 shows the state of a known flash memory word line failure.

Figure 2 shows a flow chart of a method for detecting a memory cell failure state according to an embodiment of the present invention.

Figure 3A shows a schematic diagram of a memory device according to an embodiment of the present invention.

FIG3B is a schematic diagram illustrating an implementation of a bit line bias and sensing circuit according to an embodiment of the present invention.

Figures 4A and 4B illustrate a flow chart of the programming actions of an embodiment of the present invention.

Please refer to Figure 2, which illustrates a flow chart of a method for detecting a memory cell failure according to an embodiment of the present invention. The process flow of this embodiment is executed in conjunction with programmed actions of a memory device. In Figure 2, in step S210, the controller of the memory device may search multiple state data stored in the page buffer and locate multiple set-state memory cells in a set state among the multiple memory cells, obtaining multiple set-state data corresponding to the retrieved set-state memory cells. Next, in step S220, the controller may store the aforementioned set-state data in a storage device.

Next, in step S230, the controller may execute a multi-level programming action of the memory device. In the multi-level programming action, the controller may execute the programming action based on a pre-set bit order. Furthermore, after the first half of the bit-level programming actions are completed, the controller may set one of the multiple latches in the page buffer as a selected latch, wherein the selected latch is a free latch at this time. Please note that, referring to the table below, in the programming action, taking three bits as an example, the data stored in the latch corresponding to each bit level is: In the table above, latches L1-L3 store various data corresponding to different memory cell states. For example, for a memory cell in the erased state, latches L1-L3 can store logical values of 1, 0, and 1, respectively. For program level A, latches L1-L3 can store logical values of 1, 1, and 1, respectively. The same applies to the rest of the memory cell.

As can be seen from the table above, after the programming action for the memory cell at level C is completed, the data stored in latch L1 remains unchanged during the subsequent programming actions for the memory cells at levels D-G, with the logical value 0. In other words, latch L1 does not contribute to the level identification of the programming action during the subsequent programming actions. Therefore, after the programming actions for the first half of the levels are completed, latch L1 can be set as the selected latch.

Next, in step S240, the controller transfers the configuration data from the storage device to the corresponding selected latch. The controller then continues executing the programmed actions for the next half of the level.

In step S250, after all levels of programming are complete, the controller checks the corresponding set-state memory cells using the set-state data stored in the selected latches to determine whether these set-state memory cells are still in the set state. If the set-state memory cells are found to be still in the set state, this indicates that the memory cells have not experienced data loss due to a bit line failure. Conversely, if the set-state memory cells are found to be no longer in the set state, this indicates that the set-state memory cells have experienced data loss due to a bit line failure or bit line disturbance during the programming process.

Furthermore, when a set-state memory cell is detected as no longer maintaining its set state, the controller can set the corresponding set-state memory cell as a failed memory cell and mask the failed memory cell from use, thereby reducing the probability of data loss. Furthermore, in this embodiment, if the cumulative number of masked failed memory cells exceeds a preset threshold, the controller can mask the entire memory cell block from use to maintain data accuracy.

Incidentally, the aforementioned setting state can be an erase state. Alternatively, in the embodiment of the present invention, the aforementioned setting state can also be a programmed state of any level without any specific restrictions.

Please refer to Figure 3A , which shows a schematic diagram of a memory device according to an embodiment of the present invention. Memory device 300 includes a page buffer PB, a storage device 330 , and a controller 340 . Page buffer PB is coupled to the bit lines BL of a memory block. Page buffer PB includes latches 310 - 313 and a bit line bias and sense circuit 320 . Latches 310 - 313 are commonly coupled to bus DBUS1 , which in turn couples to bit line bias and sense circuit 320 via bus DBUS1 .

In detail, latches 310-313 each have bus holders BH0-BH3. Bus holder BH0 is coupled to bus DBUS1 via switches S1 and S2; bus holder BH1 is coupled to bus DBUS1 via switches S3 and S4; bus holder BH2 is coupled to bus DBUS1 via switches S5 and S6; and bus holder BH3 is coupled to bus DBUS1 via switches S7 and S8. Switches S1 and S2 are controlled by control signals PDL and PDLB, respectively; switches S3, S5, and S7 are controlled by control signals PL1-PL3, respectively; and switches S4, S6, and S8 are controlled by control signals PL1B-PL3B, respectively.

Bus DBUS1 can be coupled to storage device 330 via switches S9 and S10. Switches S9 and S10 can be controlled by control signals CNB and DSEL, respectively.

By sequentially turning on switches S9 and S10, data on bus DBUS1 can be transferred to storage device 330. Conversely, by sequentially turning on switches S10 and S9, data on storage device 330 can be transferred to bus DBUS1. Furthermore, when transferring data between latches 310-313, for example, latch 310 transferring data to latch 311, switches S1 and S2 are first turned on, allowing the differential data signals DL and DLB in data holder BH0 to be transferred to bus DBUS1. Next, switches S1 and S2 are turned off, and switches S3 and S4 are turned on, causing the data on bus DBUS1 to be written into data holder BH1 in latch 311.

On the other hand, the controller 340 can be used to generate the aforementioned control signals PDL, PDLB, PL1-PL3, and PL1B-PL3 to control data transfer between the page buffer PB and the storage device 330.

Furthermore, the bit line bias and sense circuit 320 can receive set state data (e.g., data DLB) provided by the latch 310 to bias the bit line BL. When the set state data is erased state data, the data DLB is, for example, a logical value of 0, and the bit line bias and sense circuit 320 can bias the corresponding bit line to a first voltage value. Conversely, when the set state data is not erased state data, the data DLB is, for example, a logical value of 1, and the bit line bias and sense circuit 320 can bias the corresponding bit line to a second voltage value, where the first voltage value can be greater than the second voltage value. In this embodiment, the latch 310 may be an output latch.

Storage device 330 can be a cache device. In this embodiment, storage device 330 includes a data holder BH4. Data holder BH4 can be coupled to bus DBUS1 via switch S10. In this embodiment, data holder BH4 can also be coupled to another bus DBUS2 via switch S10. Status data can be stored directly in data holder BH4. Alternatively, the status data can be pre-stored in another storage device and transferred from another bus DBUS2 to data holder BH4 for temporary storage via switch S10 when the data needs to be read. The data is then provided to bus DBUS1 via switch S10.

Corresponding to the operational flow shown in Figure 2 of this embodiment, in step S220, latch 310, acting as the output latch, may store setting state data DL, such as erase state data, in storage device 330 before programming to prevent the erase state data from being lost. In step S230, after half of the level programming is complete, latch 311 may be set as the selected latch. In step S240, storage device 330 may transfer the setting state data (erase state data) to the selected latch (i.e., latch 311).

In step 250, the selected latch (latch 311) transmits the stored erase state data to the output latch (latch 310). Furthermore, the output latch (latch 310) transmits the erase state data to the bit line bias and sense circuit 320. The bit line bias and sense circuit 320 applies a high voltage bias to the bit line BL based on the erase state data and senses the erased memory cells to determine whether the erased memory cells remain in the erased state.

Please refer to Figure 3B below, which shows a schematic diagram of an implementation of a bit line bias and sense circuit according to an embodiment of the present invention. The bit line bias and sense circuit 320 includes pull-up transistors M31 and M32 and pull-down transistors M33 and M34. Pull-up transistors M31 and M32 are connected in series between voltage VDDI and node ND. Pull-down transistors M34 and M33 are connected in series between reference ground VSS and node ND. Pull-up transistor M31 is controlled by data DLB and, when data DLB is a logical value of 0 (indicating an erase state), pulls the voltage of node ND up to voltage VDDI (at which time transistor M32 is turned on by control signal BLC2). The pull-down transistor M34 is controlled by the data DLB. When the data DLB is a logical value of 1 (indicating a non-erase state), the voltage of the node ND is pulled down to the ground voltage (at this time, the transistor M33 is turned on according to the control signal BLDC).

Node ND is coupled to bit line BL via transistor M35. Transistor M35 is turned on by control signal BLC1 and provides a voltage at node ND to bias bit line BL. This senses whether the set-state memory cell remains in the set state (erase state).

Furthermore, node ND is coupled to the control terminal of transistor M37 via transistor M36. When bit line BL is biased to a relatively high voltage, VDDI, the sense signal SEN at the control terminal of transistor M37 corresponds to voltage VDDI, turning on transistor M37. Conversely, when bit line BL is biased to a relatively low ground voltage, the sense signal SEN at the control terminal of transistor M37 corresponds to ground, turning off transistor M37. Bit line BL can also be charged to another voltage level lower than voltage VDDI. This other voltage level can be determined by control signals BLC1 and BLC2.

Furthermore, transistors M38 and M39 are connected in series between voltage VPW3 and transistor M37. Transistors M38 and M39 are controlled by signals PSTL and STB, respectively. Transistor M38 is turned on by signal PSTL and provides voltage VPW3 to charge bus DBUS1. In this embodiment, voltage VPW3 can have a different voltage value from voltage VDDI.

Please refer to Figures 4A and 4B below, which illustrate a flow chart of a programming action according to an embodiment of the present invention. First, a setting action is performed for the programming action of the memory device. In Figure 4A, in step S410, the storage device can load the data of the latch in the page buffer. In step S420, the status data DL=1 can be set and the status data DL can be transmitted to the storage device. In step S430, the programming action can be started, and in step S450, it is determined whether the programming action of the 2n ^-1 level has been completed, where n is the level number of the storage data of the memory cell.

If the determination result of step S450 is negative, step S440 is executed to continue the programmed action and step S450 is executed again until the determination result of step S450 is positive.

Next, in step S460, the storage device transmits status data DL = 1 to the selected latch and continues executing subsequent programming actions through step S470. In step S480, when all level programming actions have passed, the selected latch transmits the set status data to the output latch in step S490. In step S4100, the memory device selectively performs a read action corresponding to the set status information and enters node A.

In Figure 4B , continuing from Node A in Figure 4A , in step S4110 , the controller of the memory device may determine whether the memory cell is originally recorded in the set state. If the determination result is yes, step S4120 may be executed. Conversely, if the determination result is no, step S4130 may be executed.

In step S4130, the bit line can be set to a ground voltage and cleared in step S4160.

In step S4120, the bit line may be biased to a high voltage to perform a memory cell read operation. In step S4140, it is determined whether the memory cell remains in the set state. If the determination result is yes, step S4160 is executed; conversely, if the determination result is no, step S4150 is executed.

In step S4150, a memory cell is set as a failed memory cell. In step S4170, the controller may count the accumulated number of failed memory cells to determine whether it exceeds a threshold. If the accumulated number of failed memory cells exceeds the threshold, the controller may mask the corresponding memory block from use. If the accumulated number of failed memory cells does not exceed the threshold, the process may terminate.

In summary, the present invention stores the state information of the set-state memory cell in a selected latch after the programming of the first half of the levels is completed. After the programming of all levels is completed, the set-state memory cell is detected based on the set-state data to determine whether it remains in the set state and, thereby, whether the memory cell is invalid. This allows accurate detection of memory cell invalidation, effectively preventing data loss.

S210~S250: Steps

Claims (19)

A method for detecting a failure state of a memory cell includes: searching a plurality of state data stored in a page buffer, finding a plurality of set-state memory cells in a set state among a plurality of memory cells, obtaining a plurality of set-state data corresponding to the set-state memory cells; storing the set-state data in a storage device; executing a multi-level programmed action, wherein the first half of the After the programmed actions of the levels are completed, an idle latch among the plurality of latches in the page buffer is set as a selected latch; the storage device is caused to transfer each of the setting state data to the selected latch; and each of the setting state memory cells is checked according to each of the setting state data to determine whether each of the setting state memory cells remains in the setting state. The detection method as described in claim 1 further includes: when each of the set-state memory cells is not maintained in the set state, setting each of the set-state memory cells as a failed memory cell. The detection method as described in claim 2 further includes: counting a cumulative number of each of the set-state memory cells as failed memory cells, and when the cumulative number is greater than a threshold, setting the memory block corresponding to each of the set-state memory cells as a failed memory block. The detection method as described in claim 1, wherein each of the state data is an erased state data or a programmed state data of different levels. The detection method as described in claim 1, wherein the step of setting one of the latches in the page buffer as the selected latch includes: setting each latch that does not change the stored data in subsequent programming actions of the bit levels as the selected latch. The detection method as described in claim 1, wherein the step of checking each set-state memory cell according to each state data to determine whether each set-state memory cell remains in the set state includes: causing the selected latch to provide each set-state data to a bit line bias and sensing circuit; and causing the bit line bias and sensing circuit to check whether each set-state memory cell remains in the set state according to each set state data. The detection method as described in claim 6 further includes: when each of the set state data is erased state data, the bit line bias and sensing circuit biases the corresponding bit line to a first voltage value according to each of the set state data; and when each of the set state data is non-erased state data, the bit line bias and sensing circuit biases the corresponding bit line to a second voltage value according to each of the set state data, wherein the first voltage value is greater than the second voltage value. A memory device includes: a page buffer coupled to at least one bit line of a memory block, the page buffer including a plurality of latches and a bit line bias and sensing circuit; a storage device coupled to the page buffer; and a controller coupled to the storage device and the page buffer, configured to: retrieve a plurality of state data stored in the page buffer, find a plurality of set-state memory cells in a set state among a plurality of memory cells, and obtain a plurality of state data corresponding to the set-state memory cells. Setting state data; storing the state data in the storage device; executing a multi-level programming action, after the first half of the level programming actions are completed, setting a free lock among a plurality of latches in the page buffer as a selected latch; causing the storage device to transfer each of the setting state data to the selected latch; and checking each of the setting state memory cells based on each of the setting state data to determine whether each of the setting state memory cells remains in the setting state. In the memory device of claim 8, the controller is further configured to: when each of the set-state memory cells is not maintained in the set state, set each of the set-state memory cells as a failed memory cell. In the memory device of claim 9, the controller is further configured to count a cumulative number of failed memory cells for each of the set-state memory cells, and when the cumulative number is greater than a threshold, set the memory block corresponding to each of the set-state memory cells as a failed memory block. The memory device as described in claim 8, wherein each of the state data is an erase state data or a programmed state data of different levels. The memory device as described in claim 8, wherein the controller is further configured to: set each of the latches that does not change the stored data in subsequent programming actions of the levels as the selected latch. The memory device of claim 8, wherein the controller is further configured to: cause the selected latch to provide each of the setting state data to the bit line bias and sense circuit; and cause the bit line bias and sense circuit to check whether each of the setting state memory cells remains in the setting state based on each of the setting state data. A memory device as described in claim 8, wherein when each of the set state data is erased state data, the bit line bias and sensing circuit biases the corresponding bit line to a first voltage value according to each of the set state data; when each of the set state data is non-erased state data, the bit line bias and sensing circuit biases the corresponding bit line to a second voltage value according to each of the set state data, wherein the first voltage value is greater than the second voltage value. The memory device of claim 8, wherein the latches are coupled to a bus, an output latch of the latches is coupled to the bit line bias and sense circuit, and provides each setting state data to the bit line bias and sense circuit. The memory device of claim 15, wherein the storage device comprises: a data holder coupled to the bus through a first switch and coupled to a database through a second switch. A memory device as described in claim 15, wherein the bit line bias and sensing circuit includes: a pull-up transistor coupled between a first voltage and a first node; and a pull-down transistor coupled between a second voltage and the first node; wherein the first node is coupled to the bit line via a first switch, the pull-up transistor or the pull-down transistor is turned on according to the set state data to perform a biasing action on the bit line, and the first voltage is greater than the second voltage. A memory device as described in claim 17, wherein the bit line bias and sensing circuit further includes: a sensing switch coupled to the first node through a second switch and coupled in series with a transistor, wherein the transistor series is coupled to the bus; when the biasing action is completed, the sensing switch is coupled to the bit line through the second switch and the sensing action is activated. The memory device of claim 8, wherein the memory block is an in-place flash memory block.