TWI897546B - Mosfet device with gate slots and method of manufacturing the same - Google Patents

Abstract

A MOSFET device with gate slots is provided in the present invention, wherein the gate of MOSFET device is provided with two gate slots respectively at edges at two sides of a channel area and extending to the bottom of gate, and gate spacers are formed on sidewalls of the gate but not on sidewalls of the two gate slots.

Description

Metal oxide semiconductor field effect transistor device with gate groove and manufacturing method thereof

The present invention generally relates to a metal oxide semiconductor field effect transistor (MOSFET) device, and more particularly, to a MOSFET device having a gate slot to address the double hump effect.

The metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor widely used in various circuits today. It consists of a metal-oxide-semiconductor diode (i.e., the gate and channel terminals) and two closely adjacent p-n junctions (i.e., the source and drain terminals). Taking the enhancement-mode MOSFET as an example, when a sufficiently large potential difference is applied between the gate and source of the MOSFET, the electric field induces charges on the semiconductor surface beneath the oxide layer, forming an inverting channel for current to flow. This allows the transistor channel to be switched on and off by controlling the gate voltage.

As semiconductor device dimensions continue to shrink, the effective channel length and width of MOSFETs are shrinking, leading to a MOS device failure mode known as the double-hump effect becoming increasingly prominent. The double-hump effect, named for the two distinct peaks on the Id-Vg characteristic curve of a MOS device, arises from the fact that during the MOS device's channel-turn-on operation, the channel edges (in the channel width direction) turn on before the inner channel. The double-hump effect can be caused by defects in the semiconductor material or its manufacturing process, resulting in a lower critical voltage at the channel edges, causing them to turn on before other parts during transistor turn-on. The doublet effect not only affects the basic characteristics and operational accuracy of semiconductor components, but can also impact the performance, power consumption, and reliability of the entire circuit. Therefore, minimizing and avoiding this effect is crucial during semiconductor design and manufacturing to ensure that components can operate stably and reliably under expected operating conditions.

The industry has proposed several methods to overcome the double peak problem, such as forming gate slots at the channel edges to prevent them from conducting during operation. However, these conventional solutions still have some issues. For example, they require the formation of a photoresist during the subsequent fabrication of source/drain (S/D), lightly doped drains (LDD), and metal silicide structures to shield the gate slots and prevent these structures from forming at these edges and affecting the intrinsic electrical properties. However, as semiconductor device sizes continue to shrink, the design of this photoresist is limited by the capabilities of the lithography process, and it may violate design rules and become unfeasible. Therefore, technicians in this field must research and develop new methods to eliminate the bimodal effect.

In view of the aforementioned shortcomings of the existing technology, the present invention proposes a novel MOSFET structure and manufacturing method. Its unique feature is that the gate segmentation step is performed after the source/drain (S/D), lightly doped drain (LDD), and metal silicide are formed. This ensures that the gate recesses formed to eliminate the doublet effect do not affect the formation of these areas, eliminating the need for additional masks and being compatible with existing CMOS processes.

One aspect of the present invention is to provide a metal oxide semiconductor field effect transistor device with a gate recess, comprising: a semiconductor substrate having an active region defined by a shallow trench isolation structure extending in a first direction; and a gate located on the semiconductor substrate and extending in a second direction across the active region, wherein the active region crossed by the gate is a channel region. The active regions on both sides of the gate are the source and drain, respectively. The gate has two gate grooves, one located on the edge of the channel region on both sides in the second direction and extending to the bottom of the gate. The sidewalls of the gate are provided with gate spacers. The source and drain are respectively located in the active region outside the gate spacers, but the gate spacers are not formed on the sidewalls of the two gate grooves.

Another aspect of the present invention is to provide a method for manufacturing a metal oxide semiconductor field effect transistor device with a gate groove, comprising: providing a semiconductor substrate having a shallow trench isolation structure defining an active region, wherein the active region extends in a first direction; forming a gate line on the semiconductor substrate and extending in a second direction across the active region, wherein the active region overlapping the gate line is a channel region; A gate spacer is formed on the sidewall of the gate line; a source electrode and a drain electrode are respectively formed on the active region outside the gate spacer on both sidewalls of the gate line; and after the source electrode and the drain electrode are formed, a photolithography process is performed to cut the gate line into a plurality of gate electrodes. The photolithography process also forms two gate grooves in each gate electrode. The two gate grooves are respectively located on the edges of the channel region on both sides in the second direction and extend to the bottom of the gate electrode.

These and other objects of the present invention will become more apparent after the reader has read the following detailed description of the preferred embodiment described with reference to various figures and drawings.

100:Semiconductor substrate

102: Shallow Trench Isolation Structure

104: Active Zone

104a: Channel Area

104b: Source

104c: Drain

106: Gate line

106a: Gate

108: High-k dielectric layer

110: Barrier Layer

112: Polysilicon layer

114: Hard Mask Layer

116: Next door

118: Metal silicide layer

120: Contact etch stop layer

122: Interlayer dielectric layer

124: Metal Gate Line

124a: Gate

126: Gate groove

127: Work function layer

128: Metal layer

130: Contacts

132: Interlayer dielectric layer

D1: First Direction

D2: Second Direction

Figures 1A, 2A, 3A, 4A, 5A, 6A, and 7A are top plan views illustrating a manufacturing process for a MOSFET device with a gate recess according to a first embodiment of the present invention. Figures 1B, 2B, 3B, 4B, 5B, 6B, and 7B are cross-sectional views illustrating a manufacturing process for a MOSFET device with a gate recess according to a first embodiment of the present invention, taken along lines X-X', Y-Y', and Z-Z' in the corresponding top plan views. Figure 8 is A schematic cross-sectional view of a MOSFET device with a gate recess according to another embodiment of the present invention; FIG. 9 is a schematic cross-sectional view of a MOSFET device with a gate recess according to another embodiment of the present invention; FIG. 10 is a schematic cross-sectional view of a MOSFET device with a gate recess according to another embodiment of the present invention; FIG. 11 is a schematic cross-sectional view of a MOSFET device with a gate recess according to another embodiment of the present invention; and FIG. 12 is a schematic cross-sectional view of a MOSFET device with a gate recess according to another embodiment of the present invention.

Please note that all illustrations in this manual are for illustrative purposes only. For the sake of clarity and ease of illustration, the sizes and proportions of the components in the illustrations may be exaggerated or reduced. Generally speaking, the same reference symbols in the drawings will be used to indicate corresponding or similar components and features in modified or different embodiments.

The following describes in detail exemplary embodiments of the present invention, illustrating the described features with reference to the accompanying figures to facilitate understanding and implementation of the technical effects. The reader should understand that the description herein is provided by way of example only and is not intended to limit the present invention. The various embodiments of the present invention and non-conflicting features within the embodiments may be combined or rearranged in various ways. Modifications, equivalents, or improvements to the present invention will be apparent to those skilled in the art and are intended to be within the scope of the present invention.

Readers should readily understand that the meanings of “on,” “above,” and “over” in this case should be interpreted broadly, such that “on” means not only “directly on” something but also “on” something with intervening features or layers, and that “on” or “above” means not only “on” or “above” something but also “on” or “above” something without intervening features or layers (i.e., directly on something). Furthermore, for descriptive convenience, spatially relative terms such as "under," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

As used herein, the term "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than that of the lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any opposing horizontal surfaces at the top and bottom surfaces. A layer may extend horizontally, vertically, and/or along an inclined surface. A substrate may be a layered structure that may include one or more layers and/or may have one or more layers thereon, above, and/or below it. A layer may include multiple layers. For example, the interconnect layer may include one or more conductor and contact layers (in which contacts, interconnects, and/or vias are formed, etc.) and one or more dielectric layers.

Readers can generally understand the terms used in this disclosure at least in part from their usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used in a singular sense to describe any feature, structure, or characteristic, or can be used in a plural sense to describe a combination of features, structures, or characteristics. Similarly, depending at least in part on the context, terms such as "a," "an," "the," or "said" can also be understood to convey either singular or plural usage. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

Readers should further understand that when words such as "include" and/or "comprising" are used in this specification, they specify the presence of the described features, regions, entireties, steps, operations, elements, and/or components, but do not exclude the presence or possibility of addition of one or more other features, regions, entireties, steps, operations, elements, components, and/or combinations thereof.

The following embodiments will illustrate the manufacturing process of the MOSFET device with a gate recess according to the present invention with reference to diagrams. Figures 1A through 7A are top views, and Figures 1B through 7B are cross-sectional views, including three cross-sections taken along lines X-X', Y-Y', and Z-Z' in Figures 1A through 7A. These diagrams provide a clear understanding of the evolution of the various components and features of the MOSFET device according to the present invention during manufacturing, as well as their relative positions and connections.

First, please refer to Figures 1A and 1B. At the outset, a semiconductor substrate 100 is provided as the foundation for the MOSFET device. In the present embodiment, the material of semiconductor substrate 100 is preferably a silicon substrate, such as a P-type doped epitaxial silicon substrate. However, other silicon-containing substrates may also be used, including Group III-V silicon-coated substrates (such as GaN-on-silicon) or silicon-on-insulator (SOI) substrates, or other doped substrates, without limitation. A shallow trench isolation structure (STI) 102 is formed on a semiconductor substrate 100, defining a plurality of active areas 104 (i.e., areas of the semiconductor substrate 100 exposed from the shallow trench isolation structure 102, with two active areas 104 shown as an example, but not limited to this). The shallow trench isolation structure 102 may be made of silicon oxide. In one embodiment, the active areas 104 may be rectangular, with their long axes extending in a first direction D1. After defining the active areas 104, an ion implantation process may be performed to form well regions (not shown) in the active areas 104. For example, if an NMOS device is to be formed in the active region 104, a P-type dopant (such as boron (B) or germanium (Ge)) can be implanted therein to form a P-type well region. If a PMOS device is to be formed in the active region 104, an N-type dopant (such as arsenic (As) or phosphorus (P)) can be implanted therein to form an N-type well region.

Please refer to Figures 2A and 2B. After the active region 104 is defined, a gate line 106 is then formed on the semiconductor substrate 100. The gate line 106 extends across multiple active regions 104 in a second direction D2, which is preferably orthogonal to the first direction D1. In the embodiment of the present invention, the gate line 106 is a stacked pattern that includes, from the semiconductor substrate 100 upward, a barrier layer 110, a polysilicon layer 112, and a top hard mask layer 114. The barrier layer 110 can be made of titanium nitride (TiN), and the hard mask layer 114 can be made of silicon _nitride ( _Si3N4 ). A high-k dielectric layer 108 serves as a gate insulator between the gate line 106 and the semiconductor substrate 100. The material can be zirconium oxide ( _ZrO2 ), aluminum oxide ( _Al2O3 ), or niobium oxide ( _Nb2O5 ). A barrier layer 110 prevents impurities from diffusing into the _high -k dielectric layer ₁₀₈ during fabrication. The polysilicon layer 112 serves as a dummy gate, which can be replaced with a metal gate in subsequent fabrication steps. In an embodiment, the aforementioned material layers are sequentially formed on the semiconductor substrate 100 through a suitable deposition process, such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. A photolithography process is then performed to pattern these material layers until the underlying high-k dielectric layer 108 is exposed. The hard mask layer 114 can be patterned in this photolithography process, acting as a mask. The gate line pattern is then transferred to the underlying material layer, thereby forming the gate line 106. It can be seen that the gate line 106 defines each active region 104 into three regions, located directly below and on both sides of the gate line 106.

Please refer to Figures 3A and 3B. After the gate line 106 is formed, a lightly doped process can be performed to dope the active region 104 on both sides of the gate line 106 to form lightly doped drains (LDDs, not shown). For example, if an NMOS device is to be formed in the active region 104, N-type dopants can be doped to form N-type LDDs. If a PMOS device is to be formed in the active region 104, P-type dopants can be doped to form P-type LDDs. LDDs can improve electric field distribution, avoid electric field concentration, and reduce hot carrier effects. After LDD formation, spacers 116 are formed on the sidewalls of gate line 106. Spacers 116 can be formed by first forming a conformal spacer layer on the surface of gate line 106 and then performing an etch-back process. The spacer material can be silicon oxide, silicon nitride, or a combination thereof. The purpose of spacers 116 is to precisely control the effective length of the gate and to isolate the source and drain to be formed subsequently. In some embodiments, a silicon germanium layer or structure (SiGe, not shown) may be formed on the exposed active region 104 on both sides of the gate line 106 after the spacers 116 are formed. SiGe has a higher electron mobility than pure silicon and can introduce a strain effect to change the lattice constant of the silicon crystal, thereby improving the overall performance of the transistor.

Refer again to Figures 3A and 3B. After the spacers 116 are formed, another doping process is performed to dope the active region 104 on both sides of the gate line 106 to form the source 104b and drain 104c. Similar to LDDs, if an NMOS device is to be formed in the active region 104, N-type dopants can be doped to form the N-type source 104b and drain 104c. If a PMOS device is to be formed in the active region 104, P-type dopants can be doped to form the P-type source 104b and drain 104c. The source 104b and drain 104c are connected to the adjacent LDD, but their doping concentration is much greater than that of the LDD. After the source 104b and drain 104c are formed, a self-aligned block (SAB) process can be performed to form a metal silicide layer 118 on the previously formed source 104b and drain 104c. The SAB process may include forming a protective oxide layer to cover the non-silicide target area, depositing a metal layer (such as titanium nitride (TiN), cobalt (Co), or nickel-platinum alloy (NiPt)) on the exposed silicon active region 104, and performing one or more rapid thermal annealing (RTA) processes to react the metal layer with the contacting silicon material to form a metal silicide. It can be seen that after the process, the originally formed source 104b and drain 104c are covered by the metal silicide layer 118, which effectively reduces the series resistance and contact resistance of the source 104b and drain 104c, thereby improving the performance and electrical properties of the transistor. Since the polysilicon layer 112 of the gate line 106 is covered by the hard mask layer 114 and the spacer 116, no metal silicide will form on its surface.

Please refer to Figures 4A and 4B. After the gate line 106 is formed, a contact etch stop layer (CESL) 120 and an interlayer dielectric (ILD) 122 are sequentially formed. The materials of the contact etch stop layer 120 and the interlayer dielectric 122 can be, but are not limited to, silicon nitride and silicon oxide, respectively, and can be formed through a suitable CVD process. The contact etch stop layer 120 is conformally formed on the surface of the semiconductor substrate 100, including the aforementioned spacers 116, metal silicide layer 118, and shallow trench isolation structure 102. The contact etch stop layer 120 precisely controls the depth and dimensions of the contact holes to be formed later, improving electrical properties while preventing damage to sensitive underlying device structures during the photolithography process. The interlayer dielectric layer 122 fills the space surrounding the gate line 106, allowing for the formation of device contacts within it during subsequent processing. After the contact etch stop layer 120 and the interlayer dielectric layer 122 are formed, a planarization process, such as chemical mechanical planarization (CMP), can be performed to remove the contact etch stop layer 120 and the interlayer dielectric layer 122 above a certain vertical height. In this embodiment, the contact etch stop layer 120 and interlayer dielectric layer 122 above the polysilicon layer 112 of the gate line 106 are removed by the CMP process, including the hard mask layer 114 on top of the gate line 106. This exposes the polysilicon layer 112 of the gate line 106 after planarization and aligns it with the top surfaces of the surrounding spacers 116, contact etch stop layer 120, and interlayer dielectric layer 122, facilitating the subsequent replacement metal gate (RMG) process.

Please refer to Figure 5A and Figure 5B. After the contact etch stop layer 120 and the interlayer dielectric layer 122 are formed, a metal gate replacement process (RMG) is performed to replace the gate line 106 based on polysilicon with a metal gate line 124. The metal gate replacement process specifically involves performing dry and/or wet etching to remove the exposed polysilicon layer 112 and barrier layer 110, forming a work function layer 127 in the vacant gate line groove and filling it with a metal layer 128. The work function layer 127 and the metal layer 128 now form the metal gate line 124, replacing the original gate line 106. The high-k dielectric layer 108 still separates the metal gate 124 from the underlying semiconductor substrate 100, forming a high-k metal gate (HKMG) structure. The work function layer 127 can adjust the energy band required by the NMOS or PMOS device, thereby adjusting the device's threshold voltage and electron injection efficiency. Metal layer 128 serves as the main metal gate, possessing excellent electrical conductivity, enabling efficient transmission of electronic signals and providing a stable current path during device operation. Similarly, the work function layer 127 and metal layer 128 that extend beyond the height of the interlayer dielectric layer 122 are removed through a planarization process, aligning them with surrounding structures.

Please refer to Figures 6A and 6B. After the metal gate line 124 is replaced, a photolithography process is then performed to remove portions of the metal layer 128 and work function layer 127, cutting the metal gate line 124 into multiple gate segments 124a. Each gate 124a, together with the active region 104 it crosses, forms the desired MOSFET device. The area covered by the gate 124a is the channel region 104a, and the uncovered areas on either side are the source 104b and drain 104c, respectively. It should be noted that in this embodiment of the present invention, the gate segmentation process also forms two gate slots 126 in each gate 124a, also by removing portions of the metal layer 128 and work function layer 127. As shown, the two gate slots 126 are designed to be located on either side of the channel region 104a in the second direction D2. The gate slots 126 extend to the bottom of the gate, exposing the underlying high-k dielectric layer 108, and do not extend to the edges of the gate 124a in the first direction D1. The high-k dielectric layer 108 is also exposed between the gates 124a, while both sides of the original gate line in the first direction D1 are still covered by the interlayer dielectric layer 122.

In the embodiment of the present invention, due to the presence of the gate groove 126, during the on-state operation of the MOSFET element, the edge portions of the channel region 104a where the gate groove 126 is located in the gate width direction (i.e., the second direction D2) are unable to form a conductive channel because no operating voltage is applied to form an electric field. Therefore, these portions will not be turned on before the interior of the channel region due to the lower critical voltage, thereby avoiding the MOS failure mode of the double peak effect, which is the technical problem solved by the solution of the present invention. Furthermore, unlike prior art, in this embodiment, the gate 124a is segmented and the gate recess 126 is formed after the source 104b, drain 104c, and metal silicide layer 118 are formed. Therefore, there is no need for additional masks to shield the gate recess 126, as in conventional methods. This eliminates the limitations of lithography process capabilities and design rules, allowing the present method to be applied to CMOS processes at finer scales. This is another advantage of the present invention. Furthermore, because the gate recess 126 is formed after the spacers 116 in this process, the spacers 116 are not present on the surface, which is a key feature of the present invention.

Please refer to Figures 7A and 7B. After the gate 124a is segmented and the gate groove 126 is formed, contacts 130 are formed in the interlayer dielectric layer 122 to connect the transistor gate 124a and the source 104b/drain 104c, enabling them to be connected to the upper back-end metal lines. This step may specifically include first forming another interlayer dielectric layer 132 on the semiconductor substrate 100. In this embodiment of the present invention, the interlayer dielectric layer 132 located in the gate line region covers the surface of the exposed gate 124a metal layer 128. The interlayer dielectric layer 132 also fills the previously formed gate groove 126 and the space between the gate 124a, contacting the high-k dielectric layer 108 at the bottom of the groove. Meanwhile, the interlayer dielectric layer 132 located in the area outside the gate line covers the interlayer dielectric layer 122. Both can be made of the same material, silicon oxide. Next, a photolithography process is performed to form contact holes in the interlayer dielectric layer 132 and the interlayer dielectric layer 122, extending to the desired gate 124a and source/drain 104b/104c. These contact holes extend to the metal silicide layer 118 on the source/drain 104b/104c and the metal layer 128 on the gate 124a. These contact holes are then filled with a conductive metal, such as tungsten (W) or titanium (Ti), to form the contact 130.

Please now refer to Figure 8, which is a schematic cross-sectional view of a MOSFET device according to another embodiment of the present invention. The structure of this embodiment is similar to that of the embodiment shown in Figure 7B, differing only in that the gate recess 126 is formed through the underlying high-k dielectric layer 108, exposing the interface between the channel region 104a and the shallow trench isolation structure 102. The gate recess 126 design of this embodiment similarly achieves the desired effect of eliminating the doublet effect of the present invention.

Please refer now to Figure 9, which is a schematic cross-sectional view of a MOSFET device according to another embodiment of the present invention. The structure of this embodiment is similar to that of the embodiment shown in Figure 7B, except that the contact etch stop layer 120 is formed after the gate 124a is segmented and the gate recess 126 is formed. Thus, the contact etch stop layer 120 is conformally formed on the surface of the gate recess 126, including the side surfaces and bottom surface, and contacts the high-k dielectric layer 108 on the bottom surface. The contact etch stop layer 120 that exceeds the height of the gate 124a metal layer 128 can also be removed by CMP.

Please refer now to Figure 10, which is a schematic cross-sectional view of a MOSFET device according to yet another embodiment of the present invention. The structure of this embodiment is similar to that of the embodiment shown in Figure 9 above, differing only in that the gate recess 126 is formed through the underlying high-k dielectric layer 108, exposing the interface between the channel region 104a and the shallow trench isolation structure 102. The resulting contact etch-stop layer 120 contacts the channel region 104a and shallow trench isolation structure 102 at the bottom of the recess, rather than the high-k dielectric layer 108.

Please refer now to Figure 11, which is a schematic cross-sectional view of a MOSFET device according to another embodiment of the present invention. The inventive concepts of this invention are also applicable to MOSFET structures that do not utilize a high-k metal gate (HKMG). As shown in Figure 11, for polysilicon gates that do not undergo metal gate replacement, a gate recess 126 can also be formed to eliminate the double-peak effect. In this embodiment, a metal silicide layer 118 is formed on the top surface of gate 106a, similar to source 104b and drain 104c, to reduce series resistance and contact resistance. The contact etch stop layer 120 formed subsequently is formed on the metal silicide layer 118, and the other features are the same.

Please refer now to Figure 12, which is a schematic cross-sectional view of a MOSFET device according to yet another embodiment of the present invention. The structure of this embodiment is similar to that of the embodiment shown in Figure 11, except that the contact etch stop layer 120 is formed after the gate 106a is segmented and the gate recess 126 is formed. Thus, the contact etch stop layer 120 is conformally formed on the gate recess 126 and the metal silicide layer 118 on top of the gate 106a.

From the above process and illustrated structure, it can be seen that the present invention eliminates the double-peak effect in conventional techniques by forming gate recesses in the gate at the edge of the channel region in the width direction. Furthermore, this gate recess process is performed after the source/drain electrodes and metal silicide are formed. This eliminates the need for additional masks to shield the gate recesses, as is the case with conventional methods. Therefore, this method is not limited by lithography process capabilities and design rules, which is the key to the advancement and effectiveness of the present invention.

The above description is merely a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention should fall within the scope of the present invention.

100:Semiconductor substrate

104a: Channel Area

104b: Source

104c: Drain

116: Next door

120: Contact etch stop layer

124a: Gate

126: Gate groove

128: Metal layer

130: Contacts

132: Interlayer dielectric layer

D1: First Direction

D2: Second Direction

Claims (18)

A metal oxide semiconductor field effect transistor device with a gate groove comprises: a semiconductor substrate having an active region defined by a shallow trench isolation structure extending in a first direction; and a gate located on the semiconductor substrate and extending in a second direction across the active region, the active region crossed by the gate being a channel region, and the active regions located on both sides of the gate being a channel region. The active region is divided into a source and a drain, wherein the gate has two gate grooves respectively located on the edges of the two sides of the channel region in the second direction and extending to the bottom of the gate, and the sidewalls of the gate have gate partitions. The source and the drain are respectively located in the active region outside the gate partitions, but the gate partitions are not formed on the sidewalls of the two gate grooves. The metal oxide semiconductor field effect transistor device with gate grooves as described in claim 1 further includes a high-k dielectric layer located between the gate and the semiconductor substrate, wherein the two gate grooves pass through the high-k dielectric layer to expose the channel region and the shallow trench isolation structure. The metal oxide semiconductor field effect transistor device with a gate groove as described in claim 1 further includes a high-k dielectric layer located between the gate and the semiconductor substrate, wherein the two gate grooves expose the high-k dielectric layer. The metal oxide semiconductor field effect transistor device with gate grooves as described in claim 1 further includes a contact etch stop layer formed in the two gate grooves. The metal oxide semiconductor field effect transistor device with gate grooves as described in claim 4, wherein the contact etch stop layer in the two gate grooves is located on and directly contacts a high-k dielectric layer. The metal oxide semiconductor field effect transistor device with gate grooves as described in claim 4, wherein the contact etch stop layer in the two gate grooves is located on the channel region and the shallow trench isolation structure and is in direct contact with them. A metal oxide semiconductor field effect transistor device with a gate groove as described in claim 4, wherein the contact etch stop layer is conformally located on the surfaces of the two gate grooves but not on the top surface of the gate. The metal oxide semiconductor field effect transistor device with a gate groove as described in claim 4, wherein the contact etch stop layer is formed on the gate spacer, the source and the drain. The metal oxide semiconductor field effect transistor device with a gate groove as described in item 1 of the patent application scope, wherein the gate is a metal gate. A metal oxide semiconductor field effect transistor device with a gate groove as described in claim 1, wherein the gate is a polysilicon gate. A method for manufacturing a metal oxide semiconductor field effect transistor device with a gate groove comprises: providing a semiconductor substrate, wherein the semiconductor substrate has a shallow trench isolation structure defining an active region, wherein the active region extends in a first direction; forming a gate line on the semiconductor substrate and extending in a second direction across the active region, wherein the active region overlapping the gate line is a channel region; forming a gate line on the sidewall of the gate line; A gate partition is formed; a source and a drain are respectively formed on the active region outside the gate partition on both side walls of the gate line; and after the source and the drain are formed, a photolithography process is performed to cut the gate line into a plurality of gates. The photolithography process simultaneously forms two gate grooves in each of the gates. The two gate grooves are respectively located on the edges of the channel region on both sides in the second direction and extend to the bottom of the gate. The method for manufacturing a metal oxide semiconductor field effect transistor device with a gate groove as described in claim 11 further includes a high-k dielectric layer located between the gate and the semiconductor substrate, wherein the two gate grooves pass through the high-k dielectric layer to expose the semiconductor substrate and the shallow trench isolation structure. The method for manufacturing a metal oxide semiconductor field effect transistor device with a gate groove as described in claim 11 further includes a high-k dielectric layer located between the gate and the semiconductor substrate, wherein the two gate grooves expose the high-k dielectric layer. The method for manufacturing a metal oxide semiconductor field effect transistor device with a gate groove as described in item 11 of the patent application further includes forming a conformal contact etch stop layer on the gate, the source and the drain after the photolithography process, so that the contact etch stop layer is conformally formed on the surface of the two gate grooves. A method for manufacturing a metal oxide semiconductor field effect transistor device with a gate groove as described in item 14 of the patent application, wherein the material of the gate line is polysilicon, and further includes performing a metal replacement process to replace the gates with metal gates after the contact etch stop layer is formed. The method for manufacturing a metal oxide semiconductor field effect transistor device with a gate groove as described in item 11 of the patent application further includes forming a conformal contact etch stop layer on the gate line, the source and the drain after the source and the drain are formed and before the photolithography process, so that the contact etch stop layer will not be formed on the surface of the two gate grooves. A method for manufacturing a metal oxide semiconductor field effect transistor device with a gate groove as described in item 16 of the patent application scope, wherein the material of the gate line is polysilicon, and further includes performing a metal replacement process to replace the gate line with a metal gate line after the contact etch stop layer is formed and before the photolithography process, and the photolithography process cuts the metal gate line into multiple metal gate segments. The method for manufacturing a metal oxide semiconductor field effect transistor device with a gate groove as described in item 11 of the patent application further includes: sequentially forming a conformal contact etch stop layer and an interlayer dielectric layer on the gate line, the source, and the drain; and performing a planarization process to remove the contact etch stop layer and the interlayer dielectric layer at the height of the top surface of the gate line, thereby exposing the gate line and making the top surface of the gate line flush with the contact etch stop layer and the interlayer dielectric layer.