TWI897341B - semiconductor memory devices - Google Patents

Abstract

An embodiment provides a semiconductor memory device capable of high-speed operation. The semiconductor memory device of the embodiment includes: first and second memory cells connected to a first word line; first and second sense amplifiers each including a first and second transistor; and first and second bit lines connected between the first memory cell and the first transistor and between the second memory cell and the second transistor, respectively. During a read operation, a first voltage is applied to the gates of the first and second transistors while the first and second sense amplifiers determine data. A second voltage, higher than the read voltage, is applied to the word line before the read voltage is applied. While the second voltage is applied to the word line, a third voltage higher than the first voltage is applied to the gate of the first transistor, and a voltage lower than the third voltage is applied to the gate of the second transistor.

Description

semiconductor memory devices

The embodiment relates to a semiconductor memory device.

NAND (Not AND) type flash memory is known, which is obtained by three-dimensionally stacking memory cells.

An embodiment provides a semiconductor memory device capable of high-speed operation.

A semiconductor memory device in an embodiment includes first and second memory cells, a first word line, first and second sense amplifiers, and first and second bit lines. The first word line is connected to the first and second memory cells. The first and second sense amplifiers include first and second transistors, respectively. The first bit line connects the first memory cell to the first transistor. The second bit line connects the second memory cell to the second transistor. During a read operation, when the first and second sense amplifiers respectively determine the data stored in the first and second memory cells, a first voltage is applied to the gates of the first and second transistors. A second voltage higher than the read voltage is applied to the first word line immediately before the read voltage is applied. While the second voltage is being applied to the first word line, a third voltage higher than the first voltage is applied to the gate of the first transistor, and a fourth voltage lower than the third voltage is applied to the gate of the second transistor.

10: Semiconductor memory device

11: Memory Cell Array

12: Column decoder module

12A: Column decoder module

12B: Column decoder module

13: Sense amplifier module

14: Input and output circuits

15: Register

15A: Status register

15B: Address register

15C: Command register

16:Logic Controller

17: Sequencer

18: Ready/Busy Control Circuit

19: Voltage generating circuit

20: p-channel MOS transistor

21~27: n-channel MOS transistors

22A: Transistor

22B: Transistor

28: Capacitor

30: Inverter

31: Inverter

32: n-channel MOS transistor

33: n-channel MOS transistor

40~43: Conductor

44: Conductor

45: Block insulation film

46: Insulating film (charge storage layer)

47: Tunnel oxide film

48: Semiconductor Materials

50: P-type well region

51: Diffusion area

52: Diffusion area

53: Conductor

54: Conductor

55: Conductor

55A: Conductor

55B: Conductor

55C: Conductor

56: Conductor

56A: Conductor

56B: Conductor

56C: Conductor

60: Select transistor

61: Select transistor

62A~62D: Variable resistor section

63A~63D: Transistors

64A: Resistor element

64B: Resistor element

64C: Resistor element

64D: Resistor element

ADD: Address information

ALE: Address Lock Enable signal

AR: Readout voltage

AR1~AR5: Area

BC: Through-hole contact

BL: Bit Line

BL0~BLm: bit lines

BLC: Control signal

BLC1: Control signal

BLC2: Control signal

BLC3: Control signal

BLCa: Control signal

BLCb: Control signal

BLK: Block

BLK0~BLKn: Block

BLkick: Voltage

BLkickh: Voltage

BLX: Control signal

BR: Read voltage

CGkick: Jump amount

CLE: Command Lock Enable Signal

CLK: Clock

CMD: Command

COM:node

CR: Read voltage

CR: Region

DAT: Data

DR:BLC driver

DR1: BLC driver

DR2: BLC driver

DR3: BLC driver

GC: Wiring layer

HLL: Control signal

HR:Region

HU: Through-hole contact

I/O (I/O1~I/O8): input and output signals

INV:node

LAT:node

LBUS: Bus

LI: Contact plug

M1: Wiring layer

M2: Wiring layer

MH:Semiconductor Pillar

MT: Memory cell transistor

MT0~MT7: Memory cell transistors

ND1~ND5: Nodes

NS:NAND string

RBn: Ready/Busy signal

RDA: Column Decoder

RDB: Column Decoder

S1~S4: Control signal

SA: Sensor Amplifier

SAG: Sense Amplifier Group

SAU: Sense Amplifier Unit

SAU0~SAU7: Sense amplifier unit

SDL, LDL, UDL, XDL: Lock circuits

SEG1~SEG5: Segment

SELL: Control signal

SELR: Control signal

SEN: Node

SGD: Select Gate Line

SGD0~SGD3: Select gate line

SGS: Selecting Gate Lines

SL: source line

SRC:node

ST: Slit

ST1: Select transistor

ST2: Select transistor

STB: Control signal

STI: Control signal

STL: Control signal

STS: Status Information

SU: String Unit

SU0~SU3: String unit

t0: time

t1: Moment

t2: Moment

t3: Moment

t4: Moment

t5: Moment

TR: Transistor

TRC: Through-hole contact

Vblc: voltage

VblcL: voltage

VBLL: voltage

VBLoff: voltage

VBLon: voltage

Vblx: voltage

VblxL: voltage

VC: Through-hole contact

Vdd: voltage

Vread: Read the conduction voltage

Vss: voltage

WL: word line

WL0~WL7: word lines

XXL: Control signal

/CE: Chip enable signal

/RE: Read enable signal

/WE: Write enable signal

/WP: Write protection signal

FIG1 is a block diagram showing an example of the overall structure of a semiconductor memory device according to the first embodiment.

FIG2 is a circuit diagram showing an example of the configuration of a memory cell array included in the semiconductor memory device of the first embodiment.

FIG3 is a diagram showing an example of the threshold distribution and data allocation of memory cell transistors included in the semiconductor memory device of the first embodiment.

FIG4 is a block diagram showing a detailed configuration example of a column decoder module included in the semiconductor memory device of the first embodiment.

FIG5 is a block diagram showing a detailed configuration example of a sense amplifier module and a voltage generating circuit included in the semiconductor memory device of the first embodiment.

FIG6 is a circuit diagram showing an example of the configuration of a sense amplifier module included in the semiconductor memory device of the first embodiment.

FIG7 is a diagram showing an example of a planar layout of a memory cell array included in the semiconductor memory device of the first embodiment.

Figure 8 is a cross-sectional view of the memory cell array along line VIII-VIII shown in Figure 7.

FIG9 is a diagram showing an example of the cross-sectional structure of a memory cell array and a row decoder module included in the semiconductor memory device of the first embodiment.

FIG10 is a diagram showing an example of a cross-sectional structure of a sense amplifier module included in the semiconductor memory device of the first embodiment.

FIG11 is a table showing an example of the read operation of the semiconductor memory device according to the first embodiment.

FIG12 is a diagram showing an example of waveforms of a read operation of the semiconductor memory device according to the first embodiment.

FIG13 is a diagram showing an example of a waveform of a readout operation in a comparative example of the first embodiment.

FIG14 is a block diagram showing a detailed configuration example of a memory cell array and a column decoder module included in the semiconductor memory device of the second embodiment.

FIG15 is a circuit diagram showing an example of the configuration of a sense amplifier module included in the semiconductor memory device of the second embodiment.

FIG16 is a diagram showing an example of a cross-sectional structure of a sense amplifier module included in a semiconductor memory device according to the second embodiment.

FIG17 is a table showing an example of the read operation of the semiconductor memory device according to the second embodiment.

FIG18 is a block diagram showing a detailed configuration example of a memory cell array and a row decoder module included in the semiconductor memory device of the third embodiment.

FIG19 is a block diagram showing a detailed configuration example of a sense amplifier module and a voltage generating circuit included in the semiconductor memory device of the third embodiment.

FIG20 is a table showing an example of the read operation of the semiconductor memory device according to the third embodiment.

FIG21 is a diagram showing an example of waveforms of a read operation of the semiconductor memory device according to the third embodiment.

FIG22 is a block diagram showing a detailed configuration example of a sense amplifier module and a voltage generating circuit included in the semiconductor memory device of the fourth embodiment.

FIG23 is a diagram showing an example of a cross-sectional structure of a sense amplifier module included in a semiconductor memory device according to a fourth embodiment.

FIG24 is a diagram showing an example of waveforms of a read operation of the semiconductor memory device according to the fourth embodiment.

FIG25 is a block diagram showing a detailed configuration example of a memory cell array and a row decoder module included in the semiconductor memory device of the fifth embodiment.

FIG26 is a block diagram showing a detailed configuration example of a sense amplifier module and a voltage generating circuit included in the semiconductor memory device of the fifth embodiment.

FIG27 is a diagram showing an example of waveforms of a read operation of the semiconductor memory device according to the fifth embodiment.

FIG28 is a circuit diagram showing an example of the configuration of a sense amplifier module included in the semiconductor memory device of the sixth embodiment.

FIG29 is a table showing an example of the read operation of the semiconductor memory device according to the sixth embodiment.

FIG30 is a diagram showing an example of waveforms of a read operation of a semiconductor memory device according to a variation of the first embodiment.

The following describes embodiments with reference to the drawings. The drawings are schematic. Furthermore, in the following description, components having substantially the same function and configuration are designated by the same reference symbols. Numerals following the characters constituting a reference symbol, and characters following the characters constituting a reference symbol, are used to distinguish between components having the same configuration and referenced by reference symbols containing the same characters and numbers. When it is not necessary to distinguish between components indicated by reference symbols containing the same characters and numbers, those components are referenced by reference symbols containing only the same characters and numbers.

[1] First implementation form

The following describes a semiconductor memory device according to a first embodiment.

[1-1]Composition

[1-1-1] Overall structure of semiconductor memory device 10

Figure 1 is a block diagram showing an example of the overall configuration of a semiconductor memory device 10 according to the first embodiment. As shown in Figure 1 , semiconductor memory device 10 includes a memory cell array 11, column decoder modules 12A and 12B, a sense amplifier module 13, input/output circuits 14, registers 15, a logic controller 16, a sequencer 17, a ready/busy control circuit 18, and a voltage generation circuit 19.

The memory cell array 11 includes blocks BLK0 through BLKn (n is a natural number greater than or equal to 1). Block BLK is a collection of multiple non-volatile memory cells associated with bit lines and word lines, serving as a unit for erasing data. The semiconductor memory device 10 can, for example, utilize an MLC (Multi-Level Cell) approach, enabling each memory cell to store more than two bits of data.

Row decoder modules 12A and 12B select target blocks BLK for various operations based on the block addresses stored in address register 15B. Furthermore, row decoder modules 12A and 12B transmit the voltage supplied from voltage generation circuit 19 to the selected blocks BLK. Row decoder modules 12A and 12B are described in detail below.

The sense amplifier module 13 can output data DAT read from the memory cell array 11 to an external controller via the input/output circuit 14. Furthermore, the sense amplifier module 13 can transmit write data DAT received from the external controller via the input/output circuit 14 to the memory cell array 11.

The I/O circuit 14 can, for example, transmit and receive 8-bit wide I/O signals (I/O1-I/O8) with an external controller. For example, the I/O circuit 14 transmits write data DAT contained in the I/O signal received from the external controller to the sense amplifier module 13, and transmits read data DAT transmitted from the sense amplifier module 13 to the external controller as I/O signal.

Register 15 includes a status register 15A, an address register 15B, and a command register 15C. Status register 15A, for example, holds status information STS from sequencer 17 and transmits this status information STS to I/O circuit 14 based on instructions from sequencer 17. Address register 15B holds address information ADD transmitted from I/O circuit 14. The block address, row address, and page address contained in address information ADD are used by row decoder module 12, sense amplifier module 13, and voltage generator circuit 19, respectively. Command register 15C holds command CMD transmitted from I/O circuit 14.

The logic controller 16 can control the input/output circuit 14 and sequencer 17 based on various control signals received from an external controller. Examples of the various control signals include the chip enable signal /CE, the command lock enable signal CLE, the address lock enable signal ALE, the write enable signal /WE, the read enable signal /RE, and the write protect signal /WP. The /CE signal activates the semiconductor memory device 10. The CLE signal notifies the input/output circuit 14 that the signal input to the semiconductor memory device 10 in parallel with the assertion of the CLE signal is the command CMD. Signal ALE notifies I/O circuit 14 that the signal input to semiconductor memory device 10 concurrently with asserted signal ALE is address information ADD. Signals /WE and /RE, for example, instruct I/O circuit 14 to input and output I/O signals, respectively. Signal /WP is used, for example, to place semiconductor memory device 10 in a protection state when power is turned on or off.

The sequencer 17 controls the overall operation of the semiconductor memory device 10 based on the command CMD stored in the command register 15C. For example, the sequencer 17 controls the column decoder module 12, the sense amplifier module 13, and the voltage generating circuit 19, and performs various operations such as writing and reading.

Ready/busy control circuit 18 generates a ready/busy signal RBn based on the operating status of sequencer 17. Signal RBn notifies the external controller whether semiconductor memory device 10 is ready to accept commands from the external controller or busy, indicating it is not accepting commands.

The voltage generating circuit 19 generates the required voltages under the control of the sequencer 17 and supplies these voltages to the memory cell array 11, the row decoder module 12, the sense amplifier module 13, and the like. For example, based on the page address stored in the address register 15B, the voltage generating circuit 19 applies the required voltages to the signal lines corresponding to the selected word lines and the signal lines corresponding to the unselected word lines.

[1-1-2] Composition of Memory Cell Array 11

FIG2 is a circuit diagram showing an example of the configuration of the memory cell array 11 included in the semiconductor memory device 10 according to the first embodiment, and illustrates an example of the detailed circuit configuration of a block BLK within the memory cell array 11. As shown in FIG2 , the block BLK includes, for example, string units SU0 to SU3.

Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0-BLm (m is a natural number greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MT0-MT7 and select transistors ST1 and ST2.

The memory cell transistor MT has a control gate and a charge storage layer, allowing for non-volatile data storage. The memory cell transistors MT0-MT7 included in each NAND string NS are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. The control gates of the memory cell transistors MT0-MT7 included in the same block BLK are respectively connected to word lines WL0-WL7. Furthermore, in the following description, the collection of 1-bit data stored by multiple memory cell transistors MT connected to the common word line WL in each string unit SU is referred to as a "page." Therefore, when two bits of data are stored in one memory cell transistor MT, the collection of multiple memory cell transistors MT connected to the common word line WL in one string unit SU stores two pages of data.

Select transistors ST1 and ST2 are used to select string cells SU during various operations. The drains of select transistors ST1 in NAND strings NS corresponding to the same row address are commonly connected to the corresponding bit line BL. The gates of select transistors ST1 in string cells SU0-SU3 are commonly connected to select gate lines SGD0-SGD3, respectively. Within the same block BLK, the sources of select transistors ST2 are commonly connected to source line SL, and the gates of select transistors ST2 are commonly connected to select gate line SGS.

In the circuit configuration of the memory cell array 11 described above, word lines WL0-WL7 are provided in each block BLK. Bit lines BL0-BLm are shared across multiple blocks BLK. Source lines SL are shared across multiple blocks BLK. Furthermore, the number of string units SU included in each block BLK and the number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS are merely examples and can be designed to any desired number. The number of word lines WL and select gate lines SGD and SGS varies based on the number of memory cell transistors MT and select transistors ST1 and ST2.

Furthermore, in the circuit configuration of the memory cell array 11 described above, the threshold distribution formed by the threshold voltages of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is, for example, the distribution shown in FIG3 . FIG3 illustrates an example of the threshold distribution, readout voltage, and data allocation when one memory cell transistor MT stores two bits of data. The vertical axis corresponds to the number of memory cell transistors MT, and the horizontal axis corresponds to the threshold voltage Vth of the memory cell transistor MT.

As shown in Figure 3, the memory cell transistors (MTs) form four threshold distributions based on the two bits of data being stored. These four threshold distributions are referred to as the "ER" level, "A" level, "B" level, and "C" level, in ascending order of threshold voltage. In the MLC method, for example, the "ER" level, "A" level, "B" level, and "C" level are assigned data values of "10 (Lower), Upper)", "11", "01", and "00", respectively.

Furthermore, in the threshold distributions described above, readout voltages are set between adjacent threshold distributions. For example, readout voltage AR is set between the maximum threshold voltage of the "ER" level and the minimum threshold voltage of the "A" level, and is used to determine whether the threshold voltage of memory cell transistor MT is included in the threshold distribution of the "ER" level or in a threshold distribution above the "A" level. The other readout voltages BR and CR are set similarly to readout voltage AR. A readout on-state voltage Vread is set for voltages higher than the maximum threshold voltage in the highest threshold distribution. Applying the read-out conduction voltage Vread to the gate of the memory cell transistor MT turns on regardless of the stored data.

Furthermore, the number of bits of data stored in a single memory cell transistor MT and the data allocation for the threshold distribution of the memory cell transistor MT described above are merely examples and are not limiting. For example, data of one bit or three or more bits can be stored in a single memory cell transistor MT, and various other data allocations can be applied to the threshold distributions.

[1-1-3] Configuration of column decoder module 12

FIG4 is a block diagram showing a detailed configuration example of row decoder modules 12A and 12B included in the semiconductor memory device 10 of the first embodiment, and illustrates the relationship between each block BLK included in the memory cell array 11 and the row decoder modules 12A and 12B. As shown in FIG4 , the row decoder module 12A includes a plurality of row decoders RDA, and the row decoder module 12B includes a plurality of row decoders RDB.

Multiple row decoders RDA are provided for even-numbered blocks (e.g., BLK0, BLK2, ...), and multiple row decoders RDB are provided for odd-numbered blocks (e.g., BLK1, BLK3, ...). Specifically, different row decoders RDA are associated with blocks BLK0 and BLK2, and different row decoders RDB are associated with blocks BLK1 and BLK3.

Each block BLK is applied with a voltage supplied from the voltage generating circuit 19 via one of the row decoders RDA and RDB. Row decoder RDA applies a voltage to the word lines WL of even-numbered blocks from one side of the word lines WL's extension direction, while row decoder RDB applies a voltage to the word lines WL of odd-numbered blocks from the other side of the word lines WL's extension direction. Furthermore, as shown in FIG4 , regions AR1 and AR2 are defined for the configuration described above.

Areas AR1 and AR2 are defined by dividing the memory cell array 11 along the direction in which word lines WL extend (the direction in which blocks BLK extend). Area AR1 corresponds to the area on one side of the word lines WL, and area AR2 corresponds to the area on the other side of the word lines WL. Memory cell array 11 is connected to row decoder module 12A in area AR1, and to row decoder module 12B in area AR2. In the following description, areas closer to the area connected to row decoder RDA or RDB corresponding to each block BLK are referred to as "near," and areas farther away are referred to as "far." That is, for example, in block BLK0, area AR1 corresponds to the Near side, and area AR2 corresponds to the Far side. Similarly, in block BLK1, area AR2 corresponds to the Near side, and area AR1 corresponds to the Far side.

[1-1-4] Configuration of the Sense Amplifier Module 13 and the Voltage Generating Circuit 19

FIG5 is a block diagram showing a detailed configuration example of the sense amplifier module 13 and the voltage generating circuit 19 included in the semiconductor memory device 10 of the first embodiment. As shown in FIG5 , the sense amplifier module 13 includes a plurality of sense amplifier groups SAG, and the voltage generating circuit 19 includes BLC drivers DR1 and DR2.

The sense amplifier group SAG, for example, includes sense amplifier units SAU0-SAU7 arranged along the direction in which the bit lines BL extend. Each sense amplifier unit SAU is connected to one bit line BL. That is, the number of sense amplifier units SAU included in the sense amplifier module 13 corresponds to the number of bit lines BL. Hereinafter, the set of sense amplifier units SAU arranged in the region AR1 and connected to the bit lines BL corresponding to the NAND strings NS is referred to as the sense amplifier segment SEG1, and the set of sense amplifier units SAU arranged in the region AR1 and connected to the bit lines BL corresponding to the NAND strings NS is referred to as the sense amplifier segment SEG2.

For example, during a read operation, when an even-numbered block is selected, the sense amplifier unit SAU corresponding to region AR1 reads data from memory cells located on the near side of the selected block, while the sense amplifier unit SAU corresponding to region AR2 reads data from memory cells located on the far side of the selected block. Similarly, when an odd-numbered block is selected, the sense amplifier unit SAU corresponding to region AR1 reads data from memory cells located on the far side of the selected block, while the sense amplifier unit SAU corresponding to region AR2 reads data from memory cells located on the near side of the selected block.

BLC drivers DR1 and DR2 generate control signals BLC1 and BLC2, respectively, based on a voltage generated by a charge pump (not shown). Furthermore, BLC driver DR1 supplies control signal BLC1 to sense amplifier unit SAU included in segment SEG1, while BLC driver DR2 supplies control signal BLC2 to sense amplifier unit SAU included in segment SEG2.

The detailed circuit configuration of each sense amplifier unit SAU described above is, for example, as shown in Figure 6 . Figure 6 illustrates an example of the detailed circuit configuration of a sense amplifier unit SAU within the sense amplifier module 13. As shown in Figure 6 , the sense amplifier unit SAU includes a sense amplifier portion SA, which is connected to each other so as to enable data transmission and reception, and latch circuits SDL, LDL, UDL, and XDL.

The sense amplifier section SA senses the data read from the corresponding bit line BL during a read operation and determines whether the read data is "0" or "1." As shown in Figure 6, the sense amplifier section SA includes a p-channel MOS (Metal Oxide Semiconductor) transistor 20, n-channel MOS transistors 21-27, and a capacitor 28.

One end of transistor 20 is connected to the power line, and the gate of transistor 20 is connected to node INV. One end of transistor 21 is connected to the other end of transistor 20, and the other end of transistor 21 is connected to node COM. A control signal BLX is input to the gate of transistor 21. One end of transistor 22 is connected to node COM, and the other end of transistor 22 is connected to the corresponding bit line BL. A control signal BLC is input to the gate of transistor 22. One end of transistor 23 is connected to node COM, and the other end of transistor 23 is connected to node SRC. The gate of transistor 23 is connected to node INV. One end of transistor 24 is connected to the other end of transistor 20, and the other end of transistor 24 is connected to node SEN. A control signal HLL is input to the gate of transistor 24. One end of transistor 25 is connected to node SEN, and the other end of transistor 25 is connected to node COM. A control signal XXL is input to the gate of transistor 25. One end of transistor 26 is grounded, and the gate of transistor 26 is connected to node SEN. One end of transistor 27 is connected to the other end of transistor 26, and the other end of transistor 27 is connected to bus LBUS. A control signal STB is input to the gate of transistor 27. One end of capacitor 28 is connected to node SEN, and the other end of capacitor 28 is input to clock pulse CLK.

Latch circuits SDL, LDL, UDL, and XDL temporarily hold read data. Latch circuit XDL is connected to input/output circuit 14 and is used to input/output data between sense amplifier unit SAU and input/output circuit 14. As shown in Figure 6, latch circuit SDL includes inverters 30 and 31, and n-channel MOS transistors 32 and 33.

Inverter 30 has an input terminal connected to node LAT, and an output terminal connected to node INV. Inverter 31 has an input terminal connected to node INV, and an output terminal connected to node LAT. Transistor 32 has one terminal connected to node INV and the other terminal connected to bus LBUS, and a control signal STI is input to its gate. Transistor 33 has one terminal connected to node LAT and the other terminal connected to bus LBUS, and a control signal STL is input to its gate. The circuit configuration of latch circuits LDL, UDL, and XDL is similar to that of latch circuit SDL, and therefore their description is omitted.

In the configuration of the sense amplifier unit SAU described above, the power supply voltage of the semiconductor memory device 10, i.e., voltage Vdd, is applied to the power line connected to one end of the transistor 20, and the ground voltage of the semiconductor memory device 10, i.e., voltage Vss, is applied to the node SRC. Furthermore, the various control signals described above are generated, for example, by the sequencer 17.

Furthermore, the configuration of the sense amplifier module 13 of the first embodiment is not limited thereto. For example, the number of latch circuits included in the sense amplifier unit SAU can be designed to be any number. In this case, the number of latch circuits is determined based on the number of bits of data held by a single memory cell transistor MT. Furthermore, the above description uses the example of a one-to-one correspondence between the sense amplifier unit SAU and the bit line BL, but this is not limiting. For example, multiple bit lines BL may be connected to a single sense amplifier unit SAU via a selector.

[1-1-5] Structure of semiconductor memory device 10

The following describes the structures of the memory cell array 11, the column decoder module 12, and the sense amplifier module 13 included in the semiconductor memory device 10 of the first embodiment.

Figure 7 shows an example planar layout of the memory cell array 11 of the first embodiment, and also shows an example planar layout of one string unit SU0 within the memory cell array 11. In the following figures, the X-axis corresponds to the direction in which the word lines WL extend, the Y-axis corresponds to the direction in which the bit lines BL extend, and the Z-axis corresponds to the vertical direction relative to the substrate surface.

As shown in Figure 7, string units SU0 are arranged between adjacent contact plugs LI extending in the X direction. Contact plugs LI are placed within the narrow gaps that insulate adjacent string units SU. Specifically, in the memory cell array 11, multiple contact plugs LI are arranged in the Y direction in an area not shown, with string units SU placed between adjacent contact plugs LI.

In the structure of this string unit SU0, regions CR and HR are defined in the X direction. Region CR functions as the actual data retention region, and a plurality of semiconductor pillars MH are provided in region CR. One semiconductor pillar MH corresponds to, for example, one NAND string NS. Region HR is used to connect the various wirings provided in the string unit SU0 to the column decoder module 12A. Specifically, in the string unit SU0, for example, a conductor 41 that functions as a select gate line SGS, eight conductors 42 that function as word lines WL0 to WL7, and a conductor 43 that functions as a select gate line SGD are provided so as to have portions that do not overlap with upper-layer conductors. Furthermore, the ends of the conductors 41-43 are connected to the row decoder module 12A located below the string unit SU via conductive through-hole contacts VC.

An example of a cross-sectional structure of the memory cell array 11 described above is shown in Figures 8 and 9. Figures 8 and 9 illustrate an example of a cross-sectional structure of a string unit SU0 within the memory cell array 11. Figure 8 shows a cross section taken along line VIII-VIII in Figure 7. Figure 9 shows a cross section taken along the X direction of Figure 7, selectively illustrating the structure associated with word line WL0 (conductive body 42) in region HR. In the following figures, interlayer insulating films are omitted, and Figure 9 omits the structure of semiconductor pillars MH in region CR.

As shown in Figure 8, in memory cell array 11, a conductive body 40, functioning as a source line SL, is disposed above a P-type well region 50 formed in a semiconductor substrate. A plurality of contact plugs LI are disposed above conductive body 40. Between adjacent contact plugs LI and above conductive body 40, conductive body 41, eight layers of conductive body 42, and conductive body 43 are disposed sequentially in the Z direction.

Conductors 40-43 are plate-like in shape, extending in the X and Y directions, while contact plug LI is plate-like in shape, extending in the X and Z directions. Furthermore, a plurality of semiconductor pillars MH are provided to penetrate conductors 41-43. Specifically, semiconductor pillars MH are formed so as to extend from the top surface of conductor 43 to the top surface of conductor 40.

Semiconductor pillar MH comprises, for example, a block insulating film 45, an insulating film (charge storage layer) 46, a tunnel oxide film 47, and a conductive semiconductor material 48. Specifically, tunnel oxide film 47 is provided around semiconductor material 48, insulating film 46 is provided around tunnel oxide film 47, and block insulating film 45 is provided around insulating film 46. Furthermore, semiconductor material 48 may also comprise different materials.

In this structure, the portion where the conductor 41 intersects the semiconductor pillar MH functions as the select transistor ST2, the portion where the conductor 42 intersects the semiconductor pillar MH functions as the memory cell transistor MT, and the portion where the conductor 43 intersects the semiconductor pillar MH functions as the select transistor ST1.

A conductive via contact BC is provided on the semiconductor material 48 of the semiconductor pillar MH. A conductive body 44, functioning as a bit line BL, is provided on the via contact BC, extending in the Y direction. In each string unit SU, one semiconductor pillar MH is connected to one conductive body 44. That is, in each string unit SU, for example, a plurality of conductive bodies 44 arranged in the X direction are each connected to a different semiconductor pillar MH.

As shown in Figure 9, in region HR, n ⁺ impurity diffusion regions 51 and 52 are formed within the surface of P-type well region 50. A conductive body 53 is provided between diffusion regions 51 and 52 and on P-type well region 50, interposed with a gate insulating film (not shown). Diffusion regions 51 and 52, and conductive body 53, respectively, function as the source, drain, and gate electrodes of transistor TR. Transistor TR is included in row decoder module 12A. A via contact VC is provided on diffusion region 51. Via contact VC passes through conductors 40-42 and connects to conductor 54. Via contact VC and conductors 40-42 are insulated by an insulating film. Conductor 54 is, for example, located in a wiring layer between the wiring layer where conductors 43 and 44 are located, and is connected to conductor 42 corresponding to word line WL0 via conductive via contact HU. The distance between via contact HU and semiconductor pillar MH varies depending on the area where semiconductor pillar MH is located. The near side and far side described in Figure 4 are defined based on the distance between via contact HU and semiconductor pillar MH.

With this configuration, column decoder module 12A can supply voltage to conductor 42 corresponding to word line WL0 via transistor TR. Semiconductor memory device 10 includes multiple transistors TR and conductor 54 (not shown) corresponding to conductors 41-43. Column decoder module 12A supplies voltage to conductors corresponding to various wirings via these transistors TR. Hereinafter, the wiring layer in which conductor 53 corresponding to the gate electrode of transistor TR is formed will be referred to as wiring layer GC, and the wiring layer in which conductor 44 corresponding to bit line BL is formed will be referred to as wiring layer M1.

The planar layout of the string unit SU corresponding to the odd-numbered blocks BLK is, for example, the planar layout of the string unit SU0 shown in Figure 7 , flipped about the Y-axis. Specifically, the unit region CR is located between the lead-out region HR corresponding to the even-numbered blocks and the lead-out region HR corresponding to the odd-numbered blocks. The remaining structure of the string unit SU corresponding to the odd-numbered blocks BLK is identical to that of the string unit SU corresponding to the even-numbered blocks, so a detailed description is omitted.

Furthermore, the structure of the memory cell array 11 of the first embodiment is not limited to that described above. For example, in the above description, the select gate lines SGS and SGD include a single layer of conductive material 41 and 43, respectively. However, the select gate lines SGS and SGD may also include multiple layers of conductive material. Furthermore, the number of conductive materials 42 through which a semiconductor pillar MH passes is not limited to this. For example, by setting the number of conductive materials 42 through which a semiconductor pillar MH passes to nine or more, the number of memory cell transistors MT included in a NAND string NS can be set to nine or more.

Next, the cross-sectional structure of the sense amplifier module 13 will be described using Figure 10. Figure 10 shows an example of the cross-sectional structure of the region of the sense amplifier module 13 where the gate electrode of the transistor 22 is formed. As shown in Figure 10, conductive bodies 55A and 55B, which function as the gate electrode of the transistor 22, are provided on the P-type well region 50 via a gate insulating film (not shown).

Conductors 55A and 55B are provided on wiring layer GC. Conductor 55A extends across area AR1 in the X direction, while conductor 55B extends across area AR2 in the X direction. Conductors 55A and 55B are insulated by slits ST. A through-hole contact TRC is provided at the end of conductor 55A, and conductor 56A is provided above this through-hole contact TRC. A through-hole contact TRC is provided at the end of conductor 55B, and conductor 56B is provided above this through-hole contact TRC. Conductors 56A and 56B are formed, for example, on wiring layer M2, which is above wiring layer M1.

Furthermore, conductors 56A and 56B are connected to BLC drivers DR1 and DR2, respectively, in areas not shown. Specifically, BLC driver DR1 applies a voltage corresponding to control signal BLC1 to conductor 55A via conductor 56A and through-hole contact TRC, while BLC driver DR2 applies a voltage corresponding to control signal BLC2 to conductor 55B via conductor 56B and through-hole contact TRC. Furthermore, while the description uses the example of conductors 55 and 56 being connected via a single through-hole contact TRC, this is not limiting. For example, conductors 55 and 56 may be connected via multiple through-hole contacts TRC.

[1-2]Action

The semiconductor memory device 10 of the first embodiment performs a kick operation during read operation. A kick operation is a voltage application method in which the driver's drive voltage is temporarily set to a value higher than a target voltage and then reduced to the target voltage after a predetermined period of time. The kick operation is performed, for example, on a word line WL or control signals BLX and BLC. For example, when the kick operation is performed on control signals BLX and BLC, the current supplied to the bit line BL increases, charging the bit line BL. Furthermore, hereinafter, during a kick operation, the voltage higher than the target voltage applied before the target voltage is applied is referred to as the kick voltage, and the difference between the target voltage and the kick voltage is referred to as the kick amount.

Furthermore, in the first embodiment, when the kickback operation is performed on the control signal BLC, the control method of the control signals BLC1 and BLC2 changes depending on whether an even-numbered block or an odd-numbered block is selected.

Figure 11 shows an example of a method for controlling control signals BLC1 and BLC2 during a kick operation on word lines WL. As shown in Figure 11 , when the selected block is an even-numbered block, sequencer 17 kicks control signal BLC1 but not control signal BLC2. On the other hand, when the selected block is an odd-numbered block, sequencer 17 kicks control signal BLC2 but not control signal BLC1.

That is, the sequencer 17 of the semiconductor memory device 10 controls the BLC drivers DR1 and DR2, for example, so that a kick action is performed on the control signal BLC supplied to the sense amplifier segment SEG corresponding to the Near side, and a kick action is not performed on the control signal BLC supplied to the sense amplifier segment SEG corresponding to the Far side.

FIG12 shows an example of waveforms during read operation of the semiconductor memory device 10 according to the first embodiment. FIG12 illustrates the waveform of the selected word line WL corresponding to the block BLK, the waveforms of the bit lines BL corresponding to the near and far sides, and the waveforms of various control signals when an even-numbered block is selected. Regarding the waveform of the word line WL shown in FIG12 , the solid line corresponds to the waveform corresponding to the near side, and the dashed line corresponds to the waveform corresponding to the far side. Regarding the waveform of the control signal BLC, the solid line corresponds to the waveform of the control signal BLC1, and the dashed line corresponds to the waveform of the control signal BLC2. Furthermore, in the following description, when there is no need to distinguish between control signals BLC1 and BLC2, the operations of control signals BLC1 and BLC2 are collectively described as the operations of control signal BLC.

In the following description, the N-channel MOS transistors to which various control signals are input are turned on when an "H" level voltage is applied to their gates, and turned off when an "L" level voltage is applied to their gates. Furthermore, the memory cell transistor MT corresponding to the selected word line WL is referred to as the selected memory cell.

As shown in Figure 12, in the initial state before time t0, for example, the voltages of word line WL and control signals BLX and BLC1 are set to Vss, the voltages of control signals HLL, XXL, and STB are set to the "L" level, and the voltage of bit line BL is set to Vss.

When the read operation begins at time t0, the row decoder module 12A applies, for example, a read-on voltage Vread to the selected word line WL. The voltage of the word line WL on the Near side changes faster than that on the Far side.

Sequencer 17 sets the voltage of control signal BLX to VblxL and the voltage of control signal BLC to VblcL. Consequently, memory cell transistor MT, to which voltage Vread is applied, transistor 21, to which voltage VblxL is applied, and transistor 22, to which voltage VblcL is applied, are turned on. This causes current to flow from sense amplifier module 13 to bit line BL, causing the voltage of bit line BL to rise to voltage VBLL.

At time t1, sequencer 17 sets the voltage of control signal BLX to voltage Vblx, the voltage of control signal BLC to voltage Vblc, and control signal HLL to the "H" level. Voltage Vblx is higher than voltage VblxL, and voltage Vblc is higher than voltage VblcL. At this time, sequencer 17 can also perform a kick operation on control signals BLX and BLC. In this case, a voltage higher than the required voltage by voltage BLkick, for example, is temporarily applied to control signals BLX and BLC. Because transistors 21 and 22, whose gate voltages have risen, flow more current, causing the voltage on bit line BL to rise. When a selected memory cell is turned on, the voltage on bit line BL reaches VBLon. When the selected memory cell is turned off, the voltage on bit line BL reaches VBLoff, which is higher than VBLon. When control signal HLL reaches an "H" level, transistor 24 turns on and node SEN is charged. When node SEN is fully charged, sequencer 17 turns control signal HLL back to an "L" level.

At time t2, sequencer 17 sets control signal XXL to an "H" level. When control signal XXL reaches an "H" level, the potential of node SEN changes based on the state of the selected memory cell. Sequencer 17 then sets control signal STB to an "H" level and, based on the state of node SEN, determines whether the threshold voltage of the selected memory cell is greater than voltage AR. The determination result is stored in the latch circuit within sense amplifier unit SAU. Sequencer 17 then sets control signal XXL to an "L" level.

At time t3, the row decoder module 12A applies, for example, a read voltage CR to the word line WL. At this time, a kick action is applied to the word line WL and the control signals BLX and BLC1. Specifically, the row decoder module 12A temporarily applies a kick voltage CR+CGkick to the selected word line WL. This kick voltage CR+CGkick represents, for example, the voltage on the near side of the word line WL. Meanwhile, the voltage on the far side of the word line WL rises to voltage CR due to a delay caused by the RC (resistance and capacitance) of the wiring, for example, without exceeding voltage CR. The kick amount CGkick can be set to any value.

While applying the kick voltage to the selected word line WL, the sequencer 17 temporarily increases the voltage of the control signal BLX by, for example, the voltage BLkick, temporarily increases the voltage of the control signal BLC1 by a voltage BLkickh higher than the voltage BLkick, and maintains the voltage of the control signal BLC2 at the voltage Vblc.

If the threshold voltage of the selected memory cell corresponding to the near side does not reach voltage CR, the selected memory cell to which the kick voltage is applied remains in the on state or changes from the off state to the on state, causing the voltage on bit line BL to reach voltage VBLon. On the other hand, if the threshold voltage of the selected memory cell corresponding to the near side exceeds voltage CR, the voltage on the near side of word line WL is higher than voltage CR, causing the corresponding memory cell to falsely turn on. False on refers to the phenomenon in which a memory cell transistor MT with a threshold voltage higher than a specific read voltage is inadvertently turned on by the kick voltage. At this point, the voltage on the bit line BL drops. However, due to the increase in current supplied to the bit line BL caused by the kickback action on the control signals BLX and BLC1, the voltage on the bit line BL quickly recovers to VBLoff.

If the threshold voltage of the selected memory cell corresponding to the Far side does not reach voltage CR, the selected memory cell to which voltage CR is applied remains in the on state or changes from the off state to the on state, so the voltage of bit line BL becomes voltage VBLon. On the other hand, if the threshold voltage of the selected memory cell corresponding to the Far side is greater than voltage CR, the voltage on the Far side of word line WL does not exceed voltage CR, thereby preventing the corresponding selected memory cell from being erroneously turned on. In other words, when the threshold voltage of the selected memory cell corresponding to the Far side is greater than voltage CR, the voltage of the corresponding bit line BL is maintained at voltage VBLoff. The operation of the control signal HLL at time t3 is the same as the operation of the control signal HLL at time t1.

At time t4, sequencer 17 sets control signal XXL to an "H" level. When control signal XXL reaches an "H" level, the potential of node SEN changes based on the state of the selected memory cell. Sequencer 17 then sets control signal STB to an "H" level. Based on the state of node SEN, sequencer 17 determines whether the threshold voltage of the selected memory cell is greater than voltage CR and stores the determination result in the latch circuit within sense amplifier unit SAU. Sequencer 17 then sets control signal XXL to an "L" level.

At time t5, the row decoder module 12A and sequencer 17 restore the word line WL and control signals BLX and BLC to their initial states, completing the page read operation.

In the readout operation described above, the operation when selecting an odd-numbered block is the same as the operation in which row decoder module 12B executes row decoder module 12A, with the operation of control signal BLC1 and the operation of control signal BLC2 swapped. Therefore, the description is omitted.

[1-3] Effects of the first implementation form

According to the semiconductor memory device 10 of the first embodiment described above, the read operation can be accelerated. The following describes the detailed effects of the semiconductor memory device 10 of the first embodiment.

In semiconductor memory devices that three-dimensionally stack memory cells, for example, as shown in Figures 7 and 8, a plate-shaped conductor 42 is used as a word line WL. Word lines WL with this structure tend to have a large RC delay. When a voltage is applied to one end of the word line WL, the voltage rises at different rates in the region closer to the driver (the near side) and farther from the driver (the far side). Therefore, the semiconductor memory device sometimes performs a kickback operation, such as a voltage boost, to assist the voltage rise on the far side of the word line WL, where the voltage rises more slowly.

Here, an example of a read operation of a semiconductor memory device in a comparative example of the first embodiment is described using FIG13 . FIG13 shows an example of waveforms of word lines WL on the near and far sides, various control signals, and bit line BL. Compared to the waveforms of the read operation described using FIG12 , the difference lies in the use of a common control signal BLC for both the near and far sides.

As shown in Figure 13, when the word line WL is triggered at time t3, the voltage on the near side of word line WL exceeds voltage CR. Consequently, when the threshold voltage of the selected memory cell corresponding to the near side exceeds voltage CR, the corresponding memory cell is mistakenly turned on. The voltage on the bit line BL corresponding to the mistakenly turned on memory cell drops (overdischarge), and the bit line BL is charged by the triggering of the control signal BLC, restoring it to voltage VBLoff. The stabilization time of the bit line BL, taking into account the effect of this overdischarge, can be shortened as the triggering amount of the control signal BLC increases.

Meanwhile, at time t3, the voltage on the Far side of word line WL reaches voltage CR, without exceeding voltage CR. When the threshold voltage of the selected memory cell corresponding to the Far side does not reach voltage CR, the bit line BL corresponding to the memory cell that has transitioned from the disconnected state to the connected state drops from voltage VBLoff to voltage VBLon. At this time, the corresponding bit line BL is charged (overcharged) by the kick action of control signal BLC. Therefore, the voltage of bit line BL drops to voltage VBLon after the kick action in response to control signal BLC ends. Taking this overcharge into account, the stabilization time of bit line BL can be shortened as the kick amount of control signal BLC is minimized.

Thus, when performing a kick operation on word line WL, the optimal kick amount for control signal BLC differs on the near side and the far side. However, in the comparative example, since the common control signal BLC is used on both the near and far sides, the effects of overdischarge on the near side and overcharge on the far side are traded off. Therefore, for the kick operation on control signal BLC in the comparative example, a smaller kick amount BLkick than the optimal kick amount BLkickh for control signal BLC on the near side is used, such that the bit lines BL corresponding to the near side and the bit lines BL corresponding to the far side have the same stability time.

In contrast, the semiconductor memory device 10 of the first embodiment uses different control signals BLC for the sense amplifier unit SAU corresponding to the near side of the word line WL and the sense amplifier unit SAU corresponding to the far side of the word line WL. Furthermore, the semiconductor memory device 10 of the first embodiment is controlled such that, when a kick operation is performed on the word line WL during a read operation, for example, the kick operation is performed on the control signal BLC supplied to the sense amplifier unit SAU corresponding to the near side of the word line WL, while the kick operation is not performed on the control signal BLC supplied to the sense amplifier unit SAU corresponding to the far side of the word line WL.

Thus, the semiconductor memory device 10 of the first embodiment can, for example, apply a higher kick voltage to the control signal BLC corresponding to the near side than in a normal kick operation, thereby suppressing overdischarge of the bit line BL corresponding to the near side. Furthermore, the semiconductor memory device 10 of the first embodiment does not perform a kick operation on the control signal BLC corresponding to the far side, thereby suppressing overcharge of the bit line BL corresponding to the far side. Therefore, the semiconductor memory device 10 of the first embodiment can shorten the stabilization time of the voltage of the bit line BL when performing a kick operation on the word line WL, thereby speeding up the read operation.

Furthermore, the above description uses the example of a case where, when performing a kick operation on a word line WL, the BLC driver DR1 corresponding to the near side performs the kick operation, while the BLC driver DR2 corresponding to the far side does not. However, this is not limiting. For example, the kick operation may be performed using both the BLC driver DR1 corresponding to the near side and the BLC driver DR2 corresponding to the far side, with a difference in the kick amount. In this case, for example, the kick voltage of the BLC driver DR1 corresponding to the near side is set higher than the kick voltage of the BLC driver DR2 corresponding to the far side. Even in this case, the semiconductor memory device 10 can achieve the same effects as described above.

[2] Second implementation form

The semiconductor memory device 10 of the second embodiment divides the sense amplifier module 13 into three regions, and controls the control signal BLC for each region. The following describes the differences between the semiconductor memory device 10 of the second embodiment and the first embodiment.

[2-1]Composition

FIG14 is a block diagram showing an example of the configuration of the memory cell array 11 and the row decoder module 12 included in the semiconductor memory device 10 of the second embodiment. Compared to the configuration described using FIG4 in the first embodiment, the range of the defined area is different.

Specifically, as shown in Figure 14 , the memory cell array 11 of the second embodiment defines an area AR3 between areas AR1 and AR2. Area AR3 is positioned, for example, so that its distance from the row decoder RDA in even-numbered blocks BLK is the same as its distance from the row decoder RDB in odd-numbered blocks BLK. That is, within each block BLK, area AR3 is positioned such that its distance from the corresponding row decoder RD is midway between "Near" and "Far."

FIG15 is a block diagram showing a detailed configuration example of the sense amplifier module 13 and the voltage generating circuit 19 included in the semiconductor memory device 10 of the second embodiment. Compared to the configuration described using FIG5 in the first embodiment, the sense amplifier module 13 further includes a sense amplifier segment SEG3, and the voltage generating circuit 19 further includes a BLC driver DR3.

As shown in Figure 15, segment SEG3 is located between segments SEG1 and SEG3. The sense amplifier unit SAU included in segment SEG3 is connected to the bit line BL corresponding to the NAND string NS located in area AR3. The BLC driver DR3 generates a control signal BLC3 based on a voltage generated by a charge pump (not shown). The BLC driver DR3 then supplies the generated control signal BLC3 to the sense amplifier unit SAU included in segment SEG3.

FIG16 is a diagram showing an example of a cross-sectional structure of the sense amplifier module 13 included in the semiconductor memory device 10 according to the second embodiment. Compared to the structure described using FIG10 in the first embodiment, a structure corresponding to the region AR3 is added.

Specifically, as shown in Figure 16, in the second embodiment, a conductor 55C is provided on the P-type well region 50, interposed between a gate insulating film (not shown). Conductor 55C extends in the X direction throughout region AR3 and is disposed between conductors 55A and 55B in wiring layer GC. Conductor 55C is insulated from conductors 55A and 55B, respectively, by slits ST. A through-hole contact TRC is provided on conductor 55C, and a conductor 56C is provided on this through-hole contact TRC. Conductor 56C is formed, for example, on wiring layer M2 and is connected to BLC driver DR3 in a region (not shown). That is, BLC driver DR3 applies a voltage corresponding to control signal BLC3 to conductor 55C via conductor 56C and through-hole contact TRC. The remaining configuration of semiconductor memory device 10 of the second embodiment is the same as that of semiconductor memory device 10 of the first embodiment, and therefore, a detailed description thereof will be omitted.

[2-2]Action

The read operation of the semiconductor memory device 10 of the second embodiment is identical to the read operation of the semiconductor memory device 10 of the first embodiment, with the addition of an operation corresponding to the sense amplifier segment SEG3. Specifically, similar to the semiconductor memory device 10 of the first embodiment, the semiconductor memory device 10 of the second embodiment controls whether the control signal BLC is triggered for each sense amplifier segment SEG during the trigger operation on the word line WL. An example of a method for controlling the trigger operation for each segment SEG of the second embodiment is shown in FIG17.

As shown in Figure 17, when the selected block is an even-numbered block BLK, a kick action is performed on control signal BLC1, while a kick action is not performed on control signals BLC2 and BLC3. On the other hand, when the selected block is an odd-numbered block, a kick action is performed on control signal BLC2, while a kick action is not performed on control signals BLC1 and BLC3. Specifically, the sequencer 17 of the semiconductor memory device 10 controls the BLC drivers DR1-DR3 so that a kick operation is performed on the segments SEG corresponding to the word line WL on the near side of the selected block, while a kick operation is not performed on the segments SEG corresponding to the word line WL on the far side of the selected block, or on the segment SEG3 corresponding to the word line WL in the center of the block BLK. The remaining operations of the semiconductor memory device 10 of the second embodiment are the same as those of the semiconductor memory device 10 of the first embodiment, and therefore, description thereof is omitted.

[2-3] Effects of the second implementation form

As described above, the semiconductor memory device 10 of the second embodiment, similar to the semiconductor memory device 10 of the first embodiment, controls the control signal BLC corresponding to segments SEG1 and SEG2 corresponding to the near side or the far side, and further controls the control signal BLC3 for segment SEG3 between segments SEG1 and SEG2. Specifically, the semiconductor memory device 10 of the second embodiment can control the BLC driver DR3 such that the control signal BLC3 corresponding to segment SEG3 performs the same operation as for either the near side or the far side.

In this way, the semiconductor memory device 10 of the second embodiment can more finely control the presence or absence of the kick operation according to the distance from the row decoder module 12 than the first embodiment. Therefore, similarly to the first embodiment, the semiconductor memory device 10 of the second embodiment can shorten the stabilization time of the voltage of the bit line BL when the kick operation is performed on the word line WL, thereby speeding up the read operation.

Furthermore, the above description uses the example of performing the same operation on either the near side or the far side for control signal BLC3 corresponding to segment SEG3 during readout, but the present invention is not limited to this. For example, the sequencer 17 may also perform a kick operation on control signal BLC3 independently of the selected block, and the kick amount of the kick operation on control signal BLC3 may not reach the kick amount of control signal BLC corresponding to the near-side segment SEG. Even in this case, the semiconductor memory device 10 of the second embodiment can still achieve the effects described above.

[3] The third implementation form

The semiconductor memory device 10 of the third embodiment adjusts the kick amount of the control signal BLC for each sense amplifier segment by providing a variable resistor in the wiring supplying the control signal BLC. The following describes the differences between the semiconductor memory device 10 of the third embodiment and the first and second embodiments.

[3-1]Composition

FIG18 is a block diagram showing an example configuration of a memory cell array 11 and a row decoder module 12 included in a semiconductor memory device 10 according to a third embodiment. Compared to the configuration described using FIG4 in the first embodiment, the range of the defined area is different.

Specifically, as shown in Figure 18 , the memory cell array 11 of the second embodiment defines areas AR1 through AR5. Specifically, areas AR1 through AR5 are defined along the extending direction of the block BLK. Area AR1 corresponds to the row decoder module 12A side, and area AR5 corresponds to the row decoder module 12B side. For example, in block BLK0, area AR1 corresponds to the near side, and area AR5 corresponds to the far side. Similarly, in block BLK1, area AR5 corresponds to the near side, and area AR1 corresponds to the far side.

FIG19 is a block diagram showing a detailed configuration example of the sense amplifier module 13 and voltage generating circuit 19 included in the semiconductor memory device 10 of the third embodiment. As shown in FIG19 , in the third embodiment, the sense amplifier module 13 includes, for example, sense amplifier segments SEG1 through SEG5, select transistors 60 and 61, and variable resistor sections 62A through 62D.

Sense amplifier groups SAG1-SAG5 each include a sense amplifier unit SAU connected to the bit lines BL corresponding to the NAND strings NS located in regions AR1-AR5. A control signal BLC1 is supplied to one end of select transistor 60 via BLC driver DR1, while a control signal BLC2 is supplied to one end of select transistor 61 via BLC driver DR2. Control signals SELL and SELR are input to the gates of select transistors 60 and 61, respectively. Variable resistors 62A-62D are connected in series between the other ends of select transistors 60 and 61. Variable resistor 62A includes a transistor 63A and a resistor element 64A connected in parallel between nodes ND1 and ND2. Variable resistance section 62B includes transistor 63B and resistor 64B connected in parallel between nodes ND2 and ND3. Variable resistance section 62C includes transistor 63C and resistor 64C connected in parallel between nodes ND3 and ND4. Variable resistance section 62D includes transistor 63D and resistor 64D connected in parallel between nodes ND4 and ND5. Control signals S1 to S4 are input to the gates of transistors 63A to 63D, respectively.

In the above configuration, in the sense amplifier module 13 of the third embodiment, the voltages at nodes ND1 through ND5 are supplied to the sense amplifier units SAU within segments SEG1 through SEG5 in the form of control signals BLC for those segments. Furthermore, the various control signals described above are generated, for example, by a sequencer 17.

[3-2]Action

The waveforms of the various control signals used in the read operation of the semiconductor memory device 10 in the third embodiment are the same as those described in FIG. 12 in the first embodiment. Specifically, in the third embodiment, the sequencer 17 controls the control signal BLC for the segments SEG corresponding to the word lines WL on the near side, similarly to the first embodiment.

Furthermore, during the read operation of the third embodiment, the sequencer 17 changes the direction of the applied control signal BLC based on the selected block BLK and adjusts the kick amount of each segment SEG based on the address of the selected word line WL. In the following description, the plurality of word lines WL are categorized into two groups. For example, the plurality of word lines WL are categorized into a first group having a relatively large RC (Resistor Capacitor) time constant and a second group having a relatively small RC time constant.

FIG20 illustrates an example of a method for controlling the kickback operation in the third embodiment. In the following description, during the read operation, the sequencer 17 maintains the control signals S1-S4 at an "H" level. During the kickback operation, the control signals S1-S4 are controlled as follows.

As shown in FIG20 , when the selected block is an even-numbered block, sequencer 17 sets control signals SELL and SELR to "H" and "L," respectively, and transistors 60 and 61 to the on and off states, respectively. Control signal BLC1 is then supplied to each module within sense amplifier module 13 via transistor 60. Furthermore, when word line WL of group 1 is selected, sequencer 17 sets control signals S1, S2, S3, and S4 to, for example, "H," "H," "L," and "L," respectively, and transistors 63A and 63B are turned on, while transistors 63C and 63D are turned off. Therefore, the control signal BLC1 supplied via transistor 60 passes through transistors 63A and 63B in variable resistor sections 62A and 62B, respectively, and through resistor elements 64C and 64D in variable resistor sections 62C and 62D, respectively. On the other hand, when word line WL of the second group is selected, sequencer 17 sets control signals S1, S2, S3, and S4 to, for example, "H" level, "L" level, "L" level, and "L" level, respectively, turning on transistor 63A and turning off transistors 63B, 63C, and 63D. Therefore, the control signal BLC supplied via transistor 60 passes through transistor 63A in variable resistance section 62A, and passes through resistor elements 64B, 64C, and 64D in variable resistance sections 62B, 62C, and 62D, respectively.

When an odd-numbered block is selected, sequencer 17 sets control signals SELL and SELR to "L" and "H," respectively, and transistors 60 and 61 to the off and on states, respectively. Control signal BLC2 is then supplied to each module within sense amplifier module 13 via transistor 61. Furthermore, when word line WL of group 1 is selected, sequencer 17 sets control signals S1, S2, S3, and S4 to "L," "L," "H," and "H," respectively, and transistors 63C and 63D to the on state, while transistors 63A and 63B are off. Therefore, control signal BLC2 supplied via transistor 61 passes through transistors 63D and 63C in variable resistor sections 62D and 62C, respectively, and through resistor elements 64B and 64A in variable resistor sections 62B and 62A, respectively. Meanwhile, when word line WL of the second group is selected, sequencer 17 sets control signals S1, S2, S3, and S4 to, for example, "L," "L," "L," and "H," respectively, turning on transistor 63D and off transistors 63A, 63B, and 63C. Therefore, the control signal BLC2 supplied via transistor 61 passes through transistor 63D in variable resistance section 62D and passes through resistor elements 64C, 64B, and 64A in variable resistance sections 62C, 62B, and 62A, respectively.

As described above, when the selected block is an even-numbered block, control signal BLC1 is supplied from node ND1 toward node ND5 via transistor 60. When the selected block is an odd-numbered block, control signal BLC2 is supplied from node ND5 toward node ND1 via transistor 61. Furthermore, the path of control signal BLC between nodes ND1 through ND5 is changed based on the address of the selected word line WL.

FIG21 shows an example of waveforms when an even-numbered block and the first group of word lines WL are selected during a read operation of the semiconductor memory device 10 according to the third embodiment. The waveforms also show the waveforms of the near-side and far-side word lines WL, the waveform of the control signal BLC1 at nodes ND1 to ND5, and the waveform of the control signal STB.

As shown in Figure 21, the waveforms of the word lines WL on the Near and Far sides, and the waveform of the control signal STB, are identical to those described in the first embodiment using Figure 12. The waveform of the control signal BLC1 at node ND1 is identical to the waveform of the control signal BLC1 described in the first embodiment using Figure 12. The waveform of the control signal BLC1 at node ND2 attenuates due to the signal supplied from node ND1 via transistor 63A, reducing the kickback at time t3. The waveform of the control signal BLC1 at node ND3 attenuates due to the signal supplied from node ND2 via transistor 63B, further reducing the kickback at time t3, i.e., eliminating the kickback effect. The waveform of control signal BLC1 at nodes ND4 and ND5 is identical to the waveform of control signal BLC1 at node ND3, for example, because the signals are supplied via transistors 63C and 63D. Thus, control signal BLC varies the kick amount at each node ND and is supplied to sense amplifier unit SAU in the corresponding segment SEG. The remaining operations of the semiconductor memory device 10 of the third embodiment are identical to those of the semiconductor memory device 10 of the first embodiment, and therefore their explanation is omitted.

Furthermore, the above description uses the example of maintaining control signals S1-S4 at an "H" level during the read operation and controlling control signals S1-S4 during the kick operation. However, this is not limiting. For example, sequencer 17 may control control signals S1-S4 throughout the entire read operation, as shown in FIG20 .

[3-3] Effects of the third implementation form

As described above, the semiconductor memory device 10 of the third embodiment is divided into smaller sense amplifier segments SEG than the semiconductor memory device 10 of the first embodiment, and the direction of the control signal BLC is changed based on the address of the selected block BLK. Specifically, for example, when an even-numbered block is selected, the sequencer 17 supplies the control signal BLC in the same direction as the word line WL, thereby turning transistors 60 and 61 on and off, respectively.

Furthermore, the sense amplifier module 13 of the third embodiment includes variable resistor sections 62A-62D, which adjust the kickback of the control signal BLC for each segment SEG based on the characteristics of the selected word line WL. Specifically, the sequencer 17 turns off the transistor 63 within the variable resistor section 62 in the Near-side region and turns on the transistor 63 within the variable resistor section 62 in the Far-side region. When transistor 63 is in the Off-state, the control signal BLC passes through the resistor element 64, attenuating the kickback and reducing the kickback. When transistor 63 is in the On-state, the control signal BLC passes through the transistor 63, suppressing voltage fluctuations.

Thus, the semiconductor memory device 10 of the third embodiment can adjust the kick amount of the control signal BLC supplied to each segment SEG. Therefore, similar to the first and second embodiments, the semiconductor memory device 10 of the third embodiment can shorten the stabilization time of the voltage on the bit line BL when performing a kick operation on the word line WL, thereby speeding up the read operation.

Furthermore, the above description uses the example of dividing the memory cell array 11 into regions AR1 to AR5 and the sense amplifier module 13 including four variable resistor sections 62, but the present invention is not limited to this. For example, the number of variable resistor sections 62 included in the sense amplifier module 13 is designed based on the number of regions AR in the memory cell array 11 that are divided and controlled.

Furthermore, the above description uses BLC drivers DR1 and DR2 as an example, but the present invention is not limited to this. For example, the semiconductor memory device 10 can also change the direction of the control signal BLC supplied to the sense amplifier module 13 by controlling transistors 60 and 61 connected to the common BLC driver DR.

[4] The fourth implementation form

The semiconductor memory device 10 of the fourth embodiment shares wiring for supplying the control signal BLC within the sense amplifier module 13, and different control signals BLC are applied to one and the other of the arranged sense amplifier groups SAG. The following describes the differences between the semiconductor memory device 10 of the fourth embodiment and those of the first through third embodiments.

[4-1]Composition

FIG22 is a block diagram showing a detailed configuration example of the sense amplifier module 13 and voltage generating circuit 19 included in the semiconductor memory device 10 of the fourth embodiment. Compared to the configuration illustrated in FIG5 in the first embodiment, the BLC drivers DR1 and DR2 are commonly connected to the sense amplifier unit SAU within the sense amplifier module 13.

Specifically, as shown in Figure 22, the sense amplifier units SAU0-SAU7 of each sense amplifier group SAG are connected in common, for example, via wiring that intersects the bit line BL. Furthermore, one end of these wirings is commonly connected to the BLC driver DR1, and the other end is commonly connected to the BLC driver DR2. In other words, the wiring that supplies the control signal BLC to each sense amplifier unit SAU within the sense amplifier module 13 is connected to the BLC driver DR1 at one end and to the BLC driver DR2 at the other end. Furthermore, the BLC driver DR1 applies a voltage corresponding to the control signal BLC1 from one side of the sense amplifier module 13, while the BLC driver DR2 applies a voltage corresponding to the control signal BLC2 from the other side of the sense amplifier module 13.

FIG23 is a diagram showing an example of a cross-sectional structure of the sense amplifier module 13 included in the semiconductor memory device 10 of the fourth embodiment. In the structure described using FIG10 in the first embodiment, the conductive bodies 55 and 56 are integrally formed.

Specifically, as shown in Figure 23, a conductor 55 is integrally formed in the wiring layer GC, and a conductor 56 is integrally formed in the wiring layer M2. A plurality of through-hole contacts TRC are provided between the conductors 55 and 56. Furthermore, in an area not shown, one end of the conductor 56 is connected to the BLC driver DR1, and the other end of the conductor 56 is connected to the BLC driver DR1. Furthermore, voltages corresponding to control signals BLC1 and BLC2 are applied to one end and the other end of the conductor 56, respectively, and these voltages are applied to the conductor 55 via the through-hole contacts TRC. Since the remaining configuration of the semiconductor memory device 10 of the fourth embodiment is the same as that of the semiconductor memory device 10 of the first embodiment, a detailed description thereof will be omitted.

[4-2]Action

The semiconductor memory device 10 of the fourth embodiment operates similarly to the semiconductor memory device 10 described using FIG. 11 in the first embodiment. The presence or absence of the kick operation for control signals BLC1 and BLC2 is controlled based on the selected block BLK. Specifically, for example, when the selected block is an even-numbered block, the kick operation is performed on control signal BLC1, while the kick operation is not performed on control signal BLC2. On the other hand, when the selected block is an odd-numbered block, the kick operation is performed on control signal BLC2, while the kick operation is not performed on control signal BLC1.

FIG21 shows an example of waveforms when an even-numbered block and word lines WL of the first group are selected during a read operation of the semiconductor memory device 10 according to the fourth embodiment. The waveforms of the near-side and far-side word lines WL, the waveforms of the control signals BLC1 and BLC2, and the waveform of the control signal STB are shown.

As shown in FIG21 , the waveforms of the Neat and Far word lines WL and the waveform of the control signal STB are identical to those described in the first embodiment using FIG12 . The waveform of the control signal BLC1 is identical to the waveform of the control signal BLC1 described in the first embodiment using FIG12 , and the waveform of the control signal BLC2 is identical to the waveform of the control signal BLC2 described in the first embodiment using FIG12 . Furthermore, in the semiconductor memory device 10 of the fourth embodiment, when a kick operation is performed on the word line WL at time t3 , the BLC driver DR1 temporarily applies a voltage higher than the voltage Vblc by a voltage BLkickh, while the BLC driver DR2 maintains the voltage Vblc. Since the remaining operations of the semiconductor memory device 10 of the fourth embodiment are the same as those of the semiconductor memory device 10 of the first embodiment, their description will be omitted.

[4-3] Effects of the 4th Implementation Form

As described above, the semiconductor memory device 10 of the fourth embodiment includes BLC drivers DR1 and DR2. These BLC drivers DR1 and DR2 are capable of applying voltages to one end and the other end of a wiring line that supplies a control signal BLC to the sense amplifier module 12, respectively. Furthermore, when performing a kickback operation on the word line WL, the BLC drivers DR1 and DR2 apply different voltages to the one end and the other end of the wiring line.

Specifically, the semiconductor memory device 10 of the fourth embodiment is controlled such that, during a kick operation on a word line WL, the kick operation is performed in the BLC driver DR when the control signal BLC is applied from the near side, while the kick operation is not performed in the BLC driver DR when the control signal BLC is applied from the far side.

Thus, similar to the first through third embodiments, the semiconductor memory device 10 of the fourth embodiment can adjust the kick amount of the control signal BLC in response to changes in the kick amount of the word line WL corresponding to the distance from the column decoder module 12. Therefore, similar to the first through third embodiments, the semiconductor memory device 10 of the fourth embodiment can shorten the stabilization time of the voltage on the bit line BL during a kick operation, thereby accelerating the read operation.

[5] Fifth implementation form

In the semiconductor memory device 10 of the fifth embodiment, when the column decoder modules 12A and 12B drive each block BLK from both sides, the control signal BLC is controlled for each designated region. The following describes the differences between the semiconductor memory device 10 of the fifth embodiment and the first through fourth embodiments.

[5-1]Composition

FIG25 is a block diagram showing an example configuration of the memory cell array 11 and row decoder module 12 included in the semiconductor memory device 10 of the fifth embodiment. Compared to the configuration described using FIG15 in the second embodiment, the configuration of the row decoder modules 12A and 12B differs.

Specifically, as shown in FIG25 , the row decoder module 12A of the fifth embodiment includes row decoders RDA corresponding to blocks BLK0-BLKn, and row decoder module 12B includes row decoders RDB corresponding to blocks BLK0-BLKn. In other words, in the fifth embodiment, each block BLK is driven from both sides of the block BLK by row decoder modules 12A and 12B. Specifically, for example, row decoder RDA receives a voltage from one end of the conductor 42 corresponding to the word line WL, while row decoder RDB receives a voltage from the other end. In the following description, the area closest to the row decoders RDA and RDB in each block BLK is referred to as the "edge," and the area encompassing the center of the block BLK is referred to as the "center." Specifically, areas AR1 and AR2 correspond to the edge, and area AR3 corresponds to the center.

FIG26 is a block diagram showing a detailed configuration example of the sense amplifier module 13 and voltage generating circuit 19 included in the semiconductor memory device 10 of the fourth embodiment. Compared to the configuration described using FIG15 in the second embodiment, the BLC driver DR3 is omitted, and the connection relationship between the BLC drivers DR1 and DR2 and each sense amplifier segment SEG is different.

Specifically, as shown in FIG26 , in the fifth embodiment, BLC driver DR1 supplies the generated control signal BLC1 to the sense amplifier unit SAU included in segments SEG1 and SEG2, while BLC driver DR2 supplies the generated control signal BLC2 to the sense amplifier unit SAU included in segment SEG3. The remaining configuration of the semiconductor memory device 10 of the fifth embodiment is the same as that of the semiconductor memory device 10 of the first embodiment, and therefore, a detailed description thereof will be omitted.

[5-2]Action

The semiconductor memory device 10 of the fifth embodiment performs a kick operation on a word line WL during a read operation. For example, the kick operation is performed under the control signal BLC1, but not under the control signal BLC2.

FIG27 shows an example of waveforms of a read operation of the semiconductor memory device 10 according to the fifth embodiment, including waveforms of word lines WL in the center and edge portions, waveforms of control signals BLC1 and BLC2, and a waveform of the control signal STB.

As shown in Figure 27, the waveforms of the word line WL in the center portion and the waveform of the control signal BLC1 are identical to those of the word line WL on the near side and the waveforms of the control signal BLC1 described in the first embodiment using Figure 12. The waveforms of the word line WL in the edge portion and the waveforms of the control signal BLC2 are identical to those of the word line WL on the far side and the waveforms of the control signal BLC2 described in the first embodiment using Figure 12. In other words, sequencer 17 controls the control signal BLC for the sense amplifier segments SEG1 and SEG2 corresponding to the edge portion in the same manner as for the near side described in the first embodiment, and controls the control signal BLC for the sense amplifier segment SEG3 corresponding to the center portion in the same manner as for the far side described in the first embodiment. The remaining operations of the semiconductor memory device 10 of the fifth embodiment are the same as those of the semiconductor memory device 10 of the first embodiment, and therefore their description is omitted.

[5-3] Effects of the 5th Implementation Form

As described above, the semiconductor memory device 10 of the fifth embodiment has a configuration in which the column decoder modules 12A and 12B drive the word lines WL from both sides. Thus, when the word lines WL are driven from both sides, for example, the waveforms of the word lines WL in the two edge portions shown in FIG. 25 are identical to the waveforms of the word lines WL on the near side described in the first embodiment, while the waveform of the word lines WL in the center portion is identical to the waveform of the word lines WL on the far side described in the first embodiment.

Therefore, in the semiconductor memory device 10 of the fifth embodiment, when performing a kick operation on the word line WL, the sequencer 17 controls the control signal BLC corresponding to the edge portion in the same manner as described in the first embodiment for the near side, and controls the control signal BLC corresponding to the center portion in the same manner as described in the first embodiment for the far side.

Thus, the semiconductor memory device 10 of the fifth embodiment can optimize the kick of the control signal BLC in the edge and center regions and shorten the stabilization time of the bit line BL voltage. Consequently, the semiconductor memory device 10 of the fifth embodiment can achieve faster read operations, similar to the first embodiment.

Furthermore, the above description exemplifies the case where a kick operation is not performed on the control signal BLC2 in the center portion when performing a kick operation on the word line WL. However, the present invention is not limited to this embodiment. For example, the sequencer 17 may also perform a kick operation on the control signal BLC2, and the kick amount of the control signal BLC2 corresponding to the center portion may be set smaller than the kick amount of the control signal BLC1 corresponding to the edge portion. Even in this case, the semiconductor memory device 10 of the fifth embodiment can achieve the effects described above.

[6] Sixth implementation form

The semiconductor memory device 10 of the sixth embodiment is an example of a configuration of the sense amplifier module 13 in the first through fifth embodiments that varies the kick amount. The following describes the differences between the semiconductor memory device 10 of the sixth embodiment and the first through fifth embodiments.

[6-1]Composition

FIG28 shows an example of the configuration of a sense amplifier module 13 included in a semiconductor memory device according to the sixth embodiment, and illustrates an example of the circuit configuration of a sense amplifier unit SAU. As shown in FIG28 , the sense amplifier unit SAU of the sixth embodiment differs from the configuration of the sense amplifier unit SAU described using FIG6 in the first embodiment in that the configuration of the sense amplifier portion SA differs.

Specifically, the sense amplifier module 13 of the sixth embodiment includes transistors 22A and 22B. Transistors 22A and 22B are connected in parallel between the node COM and the corresponding bit line BL. A control signal BLCa is input to the gate of transistor 22A, and a control signal BLCb is input to the gate of transistor 22B. In other words, the sense amplifier section SA of the sixth embodiment is configured to include a plurality of transistors 22 connected in parallel, and these plurality of parallel-connected transistors 22 can be independently controlled by the sequencer 17.

Furthermore, regarding the multiple transistors 22 connected in parallel, for example, one transistor corresponds to the transistor used in normal operation, while the other transistors correspond to the transistors used only in the kick-off operation. This is not limited to this, and multiple transistors 22 connected in parallel can also be used in normal operation.

[6-2]Action

In the sixth embodiment, the sense amplifier unit SAU changes the kickback amount by controlling transistors 22A and 22B via a sequencer 17. An example of a control method for transistors 22A and 22B in the sixth embodiment is shown in FIG29.

As shown in Figure 29, to increase the kick amount, sequencer 17, for example, sets control signals BLCa and BLCb to "H" and turns on transistors 22A and 22B. This increases the amount of current flowing between node COM and the corresponding bit line BL, accelerating the charging speed of bit line BL. On the other hand, to decrease the kick amount, sequencer 17 sets control signals BLCa and BLCb to "H" and "L," respectively, and turns on and off transistors 22A and 22B, respectively. This reduces the amount of current flowing between node COM and the corresponding bit line BL, slowing the charging speed of bit line BL. The remaining operations of the semiconductor memory device 10 of the sixth embodiment are the same as those of the semiconductor memory device 10 of the first embodiment, and therefore their description will be omitted.

[6-3] Effects of the 6th Implementation Form

As described above, the sense amplifier module 13 of the sixth embodiment can finely adjust the kick amount of the control signal BLC during the kick operation of the word line WL. Thus, the semiconductor memory device 10 of the sixth embodiment can apply the optimal kick amount to the control signal BLC during various operations.

[7] Variations, etc.

A semiconductor memory device 10 of an embodiment includes first and second memory cells (MT, FIG2), a first word line (WL, FIG2), first and second sense amplifiers (SAU, FIG5), and first and second bit lines (BL, FIG2). The first word line is connected to the first and second memory cells. The first and second sense amplifiers include first and second transistors (22, FIG6), respectively. The first bit line connects the first memory cell to the first transistor. The second bit line connects the second memory cell to the second transistor. During the read operation, as the first and second sense amplifiers determine the data stored in the first and second memory cells, respectively, a first voltage (Vblc, Figures 12 and 13) is applied to the gates of the first and second transistors. Before the read voltage is applied to the first word line, a kick voltage (CR+CGkick, Figure 12) higher than the read voltage is applied. During the first period of the kick voltage application to the first word line, a second voltage (Vblc+BLkick, Figure 12) higher than the first voltage is applied to the gate of the first transistor. During this first period, the voltage applied to the gate of the second transistor is lower than the second voltage (Vblc, Figure 13). This makes it possible to provide a semiconductor memory device capable of high-speed operation.

Furthermore, while the above embodiment illustrates an example in which a lower read voltage is applied during the read operation, the present invention is not limited to this embodiment. For example, as shown in FIG30 , a higher read voltage may be applied to determine the threshold voltage of the memory cell transistor MT. FIG30 shows an example waveform of a read operation of the semiconductor memory device 10 according to a variation of the first embodiment, and shows the waveforms of the selected word line WL, the control signal BLC1 corresponding to the near side, the control signal BLC2 corresponding to the far side, and the control signal STB.

As shown in Figure 30 , the row decoder module 12 applies a read voltage CR to the selected word line WL at time t0 and a read voltage AR at time t1. Furthermore, due to the kickback operation, a voltage higher than the CGKick voltage is temporarily applied to the near side of the word line WL before reaching the read voltage CR. Meanwhile, the far side of the word line WL directly reaches the read voltage CR due to the RC time constant. Control signal BLC1, corresponding to the Near side, performs a kick operation when read voltage CR is applied to word line WL. Control signal BLC2, corresponding to the Far side, does not perform a kick operation when read voltage CR is applied to word line WL. Furthermore, when control signal STB is asserted after applying each read voltage, sense amplifier unit SAU determines the threshold voltage of memory cell transistor MT, terminating the read operation at time t3. Thus, the above-described embodiment is applicable to all situations in which a kick operation is performed on word line WL.

Furthermore, while the above embodiment illustrates a case where all bit lines BL are targeted for read operations, the present invention is not limited to this embodiment. For example, the semiconductor memory device 10 may be configured such that read operations are performed separately for odd-numbered bit lines and even-numbered bit lines. In this case, the sense amplifier modules 13 are provided, for example, corresponding to the odd bit lines and the even bit lines. Furthermore, different control signals BLC are supplied to the sense amplifier modules 13 corresponding to the odd bit lines and the even bit lines, respectively. The above embodiment is also applicable to semiconductor memory devices 10 having such configurations.

Furthermore, the above embodiments describe the operation of reading upper page data as an example, but the present invention is not limited to this. For example, the operation described in the above embodiments can also be applied to the operation of reading lower page data. Furthermore, the above embodiments describe the case where a memory cell stores two bits of data as an example, but the present invention is not limited to this. For example, a memory cell can also store one bit of data or three or more bits of data. Even in such cases, the read operations described in the first through sixth embodiments can be performed.

Furthermore, in the above embodiment, the voltage applied to the word line WL during the kick operation and the kick amount of the voltage corresponding to the control signal BLC are described as being approximately constant, but this is not limiting. For example, these voltages may also vary based on the address of the selected word line WL. Specifically, when the memory cell has a three-dimensional layered structure, for example, the RC time constants of the word lines WL in the upper and lower layers may differ, and thus the appropriate kick amounts may differ. In this case, the semiconductor memory device 10 can improve the read speed of the operation by applying an optimized kick amount to the word lines WL in each layer.

Furthermore, while the above embodiment illustrates an example in which row decoder module 12 is disposed below memory cell array 11, the present invention is not limited thereto. For example, memory cell array 11 may be formed on a semiconductor substrate, with row decoder modules 12A and 12B positioned so as to sandwich memory cell array 11. Even in this case, the operations described in the above embodiment can be performed.

Furthermore, while the above embodiment describes the semiconductor memory device 10 as reading data page by page, the present invention is not limited to this embodiment. For example, the semiconductor memory device 10 may read multiple bits of data stored in a memory cell at once. Even in this case, since a kickback operation may be applied during the read operation, the semiconductor memory device 10 can still apply the operation described in the above embodiment.

Furthermore, in the above embodiment, a timing diagram illustrating the waveform of the word line WL during the read operation is used. However, the waveform of the word line WL is, for example, the same waveform as the waveform of the signal line that supplies voltage to the column decoder module 12. That is, in the above embodiment, the voltage applied to the word line WL and the period during which the voltage is applied to the word line WL can be roughly understood by examining the voltage of the corresponding signal line. Furthermore, the voltage of the word line WL may become lower than that of the corresponding signal line due to a voltage drop across the pass transistors included in the column decoder module 12.

Furthermore, while the above embodiments illustrate the use of a MONOS film for memory cells, this is not limiting. For example, even when using memory cells with floating gates, the same effects can be achieved by performing the read and write operations described in the above embodiments.

Furthermore, in the above embodiment, the example of a through-hole contact VC electrically connected to each conductor 42 passes through the conductor 42, but the present invention is not limited to this. For example, the through-hole contact VC corresponding to each conductor 42 may be formed from a conductor 42 on a different wiring layer, passing through the conductor 40 and connected to the corresponding diffusion region 52. Furthermore, the above description uses the example of a through-hole contact BC, VC, HU, and TRC formed by a single column, but the present invention is not limited to this. For example, these through-hole contacts may be formed by connecting two or more columns. Furthermore, when connecting two or more columns in this manner, they may pass through different conductors.

Furthermore, in the above embodiment, the memory cell array 11 may also have other configurations. Other configurations of the memory cell array 11 are described, for example, in U.S. Patent Application No. 12/407,403, filed on March 19, 2009, entitled “Three-Dimensional Laminated Non-Volatile Semiconductor Memory.” Also, the present invention is described in U.S. Patent Application No. 12/406,524, filed on March 18, 2009, entitled "Three-Dimensional Laminated Non-Volatile Semiconductor Memory," U.S. Patent Application No. 12/679,991, filed on March 25, 2010, entitled "Non-Volatile Semiconductor Memory Device and Method of Fabricating the Same," and U.S. Patent Application No. 12/532,030, filed on March 23, 2009, entitled "Semiconductor Memory and Method of Fabricating the Same." The entire contents of these patent applications are incorporated by reference into the specification of this application.

Furthermore, in the above embodiment, the block BLK is used as the unit of data deletion, but the present invention is not limited to this embodiment. Other deletion operations are described in U.S. Patent Application No. 13/235,389, filed on September 18, 2011, entitled "Non-Volatile Semiconductor Memory Device," and U.S. Patent Application No. 12/694,690, filed on January 27, 2010, entitled "Non-Volatile Semiconductor Memory Device." The entire contents of these patent applications are incorporated by reference into the specification of this application.

Furthermore, in this specification, the term "connected" refers to an electrical connection, including, for example, the presence of other components. Furthermore, in this specification, the term "blocked" refers to the state of the switch being in the off state, including, for example, the flow of a small current such as transistor leakage current.

Furthermore, in each of the above-mentioned embodiments,

(1) In the read operation, the voltage applied to the word line selected in the "A" level read operation is, for example, between 0 and 0.55V. However, this is not limited thereto and may be set to any range of 0.1 to 0.24V, 0.21 to 0.31V, 0.31 to 0.4V, 0.4 to 0.5V, and 0.5 to 0.55V.

The voltage applied to the selected word line during the "B" level read operation is, for example, between 1.5 and 2.3V. However, this is not a limitation and may be set to any range from 1.65 to 1.8V, 1.8 to 1.95V, 1.95 to 2.1V, or 2.1 to 2.3V.

The voltage applied to the selected word line during the "C" level read operation is, for example, between 3.0V and 4.0V. However, this is not a limitation and may be set to any range from 3.0V to 3.2V, 3.2V to 3.4V, 3.4V to 3.5V, 3.5V to 3.6V, or 3.6V to 4.0V.

The read operation time (tRead) can be set, for example, to 25-38μs, 38-70μs, or 70-80μs.

(2) As described above, the write operation includes a programming operation and a verification operation. The voltage initially applied to the selected word line during the programming operation is, for example, between 13.7 and 14.3 V. This is not limited to this, and may be, for example, between 13.7 and 14.0 V and 14.0 and 14.6 V. The voltage applied to the non-selected word line during the programming operation may be, for example, between 6.0 and 7.3 V. This is not limited to this, and may be, for example, between 7.3 and 8.4 V, or may be set to 6.0 V or less.

During a write operation, the voltage initially applied to the selected word line when an odd-numbered word line is selected is different from the voltage initially applied to the selected word line when an even-numbered word line is selected. During a write operation, the applied conduction voltage may also be varied depending on whether the unselected word line is an odd-numbered word line or an even-numbered word line.

When the programming mode is set to ISPP (Incremental Step Pulse Program), the programming voltage boost amplitude can be set to approximately 0.5V, for example. The write operation time (tProg) can also be set to, for example, 1700-1800μs, 1800-1900μs, or 1900-2000μs.

(3) During the erase operation, the voltage initially applied to the well formed on the upper portion of the semiconductor substrate and on which the memory cell is disposed is, for example, between 12.0 and 13.6 V. This is not limiting and may be, for example, between 13.6 and 14.8 V, 14.8 and 19.0 V, 19.0 and 19.8 V, or 19.8 and 21.0 V.

The erase time (tErase) can be set, for example, to 3000-4000μs, 4000-5000μs, or 4000-9000μs.

(4) The structure of the memory cell has a charge storage layer with a tunnel insulating film having a dielectric film thickness of 4 to 10 nm arranged on a semiconductor substrate (silicon substrate). The charge storage layer can be a multilayer structure of an insulating film such as SiN or SiON having a film thickness of 2 to 3 nm and a polysilicon having a film thickness of 3 to 8 nm. In addition, a metal such as Ru can also be added to the polysilicon. An insulating film is provided on the charge storage layer. The insulating film, for example, has a silicon oxide film having a film thickness of 4 to 10 nm sandwiched between a lower High-k film having a film thickness of 3 to 10 nm and an upper High-k film having a film thickness of 3 to 10 nm. As a High-k film, HfO and the like can be cited. Furthermore, the silicon oxide film can be thicker than the High-k film. A control electrode with a thickness of 30-70 nm is formed on the insulating film, using a dielectric film with a thickness of 3-10 nm. The materials used here are metal oxide films such as TaO and metal nitride films such as TaN. W (tungsten) can be used for the control electrode. Furthermore, an air gap can be formed between the memory cells.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments are capable of being implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention and are also included within the scope of the invention described in the patent application and its equivalents.

[Related Applications]

This application claims priority from Japanese Patent Application No. 2017-176641 (filing date: September 14, 2017). This application incorporates all of the contents of the base application by reference.

13: Sense amplifier module

19: Voltage generating circuit

AR1: Region

AR2: Area

BL: Bit Line

BLC1: Control signal

BLC2: Control signal

DR1: BLC driver

DR2: BLC driver

SAG: Sense Amplifier Group

SAU0~SAU7: Sense amplifier unit

SEG1: Segment

SEG2: Segment

Claims (18)

A semiconductor memory device comprises: a first memory cell and a second memory cell; a first word line connected to the first memory cell; a second word line connected to the second memory cell; a first sense amplifier and a second sense amplifier, each comprising a first transistor and a second transistor, respectively; a first bit line connected between the first memory cell and the first transistor; a second bit line connected between the first memory cell and the first transistor; word line connected between the second memory cell and the second transistor; a controller configured to perform a first read operation and a second read operation; a first conductor extending in a first direction and serving as the first word line; a second conductor extending in the first direction and serving as the second word line; a first column extending in a second direction and passing through The controller is further configured to apply a first voltage to the gate of the first transistor in the first readout operation and to apply a second voltage, which is lower than the first voltage, to the gate of the second transistor in the second readout operation. The device of claim 1, wherein the controller is further configured to: in the first read operation, before applying the read voltage to the first word line, apply a third voltage higher than the read voltage to the first word line when applying the first voltage to the gate of the first transistor. The device of claim 2, wherein the controller is further configured to: in the first read operation, apply the second voltage to the gate of the first transistor when the read voltage is applied to the first word line. The device of claim 1, wherein the controller is further configured to: in the first read operation, after applying the first voltage to the gate of the first transistor, apply a fourth voltage lower than the first voltage to the gate of the first transistor. The device of claim 1, wherein the second memory cell is included in a block different from the block including the first memory cell. The device of claim 1, wherein a spacing between the third column and the first column in the first direction is shorter than a spacing between the fourth column and the second column in the first direction. The device of claim 1, wherein the first conductor and the second conductor are separated from each other in a third direction intersecting the first direction and the second direction. The device of claim 1, wherein the controller is further configured to apply a voltage to the first word line via the third column, and the voltage is applied to the first word line from one side in the first direction. The device of claim 8, wherein the controller is further configured to apply a voltage to the second word line via the fourth column, and the voltage is applied to the second word line from the other side in the first direction. A semiconductor memory device comprises: a first memory cell and a second memory cell; a first word line connected to the first memory cell; a second word line connected to the second memory cell; a first sense amplifier comprising a first transistor; a first bit line connected to the first memory cell, the second memory cell, and the first transistor; a controller configured to perform a first read operation and a second read operation; a first conductor extending in a first direction and serving as the first word line; a second conductor extending in the first direction and serving as the second word line; a first pillar extending in a second direction and passing through the first conductor, The intersection between the first column and the first conductor is the first memory cell; the second column is arranged to extend through the second conductor in the second direction, and the intersection between the second column and the second conductor is the second memory cell; and the third column is arranged on the first conductor and electrically connected to the first conductor; the fourth column is arranged on the second conductor and electrically connected to the second conductor; wherein the controller is further configured to: in the first read operation, apply a first voltage to the gate of the first transistor, and in the second read operation, apply a second voltage lower than the first voltage to the gate of the first transistor. As in the device of claim 10, the controller is further configured to: in the first read operation, before applying the read voltage to the first word line, when applying the first voltage to the gate of the first transistor, apply a third voltage higher than the read voltage to the first word line. The device of claim 11, wherein the controller is further configured to: in the first read operation, apply the second voltage to the gate of the first transistor when the read voltage is applied to the first word line. As in the device of claim 10, the controller is further configured to: in the first read operation, after applying the first voltage to the gate of the first transistor, apply a fourth voltage lower than the first voltage to the gate of the first transistor. The device of claim 10, wherein the second memory cell is included in: a block different from a block including the first memory cell. A device as claimed in claim 10, wherein the distance between the third column and the first column in the first direction is shorter than the distance between the fourth column and the second column in the first direction. The device of claim 10, wherein the first conductor and the second conductor are separated from each other in a third direction intersecting the first direction and the second direction. The device of claim 10, wherein the controller is further configured to apply a voltage to the first word line via the third column, and the voltage is applied to the first word line from one side in the first direction. The device of claim 17, wherein the controller is further configured to apply a voltage to the second word line via the fourth column, and the voltage is applied to the second word line from the other side in the first direction.