TWI897133B - Power module structure - Google Patents

Abstract

A power module structure is provided. The power module structure includes a substrate, a copper layer, a metal layer, and a chip. The copper layer is disposed on the substrate. The metal layer is disposed on the copper layer. The area of ​​the metal layer is smaller than that of ​​the copper layer. The chip is disposed on the metal layer. The area of ​​the chip is smaller than that of ​​the metal layer.

Description

Power module structure

The present disclosure relates to a power module structure, and more particularly to a power module structure with a metal heat conducting material disposed below a chip.

Currently, ceramic substrates are often used as chip carriers in power modules. However, when high-power chips are placed on the substrate, localized hot spots can form on the underlying ceramic substrate, making it difficult for heat to dissipate.

According to one embodiment of the present disclosure, a power module structure is provided, comprising: a substrate; a copper layer disposed on the substrate; a metal layer disposed on the copper layer, wherein the area of the metal layer is smaller than the area of the copper layer; and a chip disposed on the metal layer, wherein the area of the chip is smaller than the area of the metal layer.

In some embodiments, the substrate comprises aluminum oxide. In some embodiments, the metal layer comprises copper, silver, or aluminum. In some embodiments, the metal layer has a rectangular, circular, polygonal, or trapezoidal shape. In some embodiments, the metal layer contacts the copper layer. In some embodiments, the chip comprises a power device. In some embodiments, the chip contacts the metal layer.

According to one embodiment of the present disclosure, a power module structure is provided, comprising: a substrate; a copper layer disposed on the substrate; a chip disposed on the copper layer; and a metal layer disposed on the copper layer, surrounding the chip, wherein the area of the metal layer is smaller than the area of the copper layer.

In some embodiments, the chip and the metal layer have different thicknesses. In some embodiments, the chip and the metal layer are in contact with the copper layer. In some embodiments, the chip is in contact with the metal layer.

According to one embodiment of the present disclosure, a power module structure is provided, comprising: a substrate; a copper layer disposed on the substrate; a first metal layer disposed on the copper layer, wherein the area of the first metal layer is smaller than the area of the copper layer; a second metal layer disposed on the copper layer, wherein the area of the second metal layer is smaller than the area of the copper layer, and the second metal layer is disposed separately from the first metal layer; a first chip disposed on the first metal layer, wherein the area of the first chip is smaller than the area of the first metal layer; and a second chip disposed on the second metal layer, wherein the area of the second chip is smaller than the area of the second metal layer.

In some embodiments, the first metal layer and the second metal layer have shapes including rectangles, circles, polygons, or trapezoids. In some embodiments, the first metal layer and the second metal layer have different shapes. In some embodiments, the first metal layer and the second metal layer have different thicknesses. In some embodiments, the first metal layer and the second metal layer are in contact with the copper layer. In some embodiments, the first chip is in contact with the first metal layer. In some embodiments, the second chip is in contact with the second metal layer.

Generally speaking, the copper layer on a ceramic substrate must consider the etching capability of the process and the warping caused by thermal expansion. Therefore, the thickness of the copper layer must be limited. However, when installing a high-power chip, an overly thin copper layer will generate local hot spots, making it difficult for heat to dissipate. In the power module structure disclosed herein, an additional metal layer with high thermal and electrical conductivity is provided below (or around) the chip, causing the copper layer on the substrate to be locally thickened. This allows heat to be evenly transferred to the metal layer and expand the heat dissipation area before being more efficiently transferred downward. The metal layer disclosed herein acts as an accessory for the chip, amplifying its heat source, achieving uniform heat dissipation and increasing the heat dissipation area, and is connected to the copper layer on the substrate.

This disclosure utilizes a metal layer larger than the heat source, placed in contact with the heat source, to achieve uniform temperature transfer. Uniform heat transfer means a minimal temperature difference between the center and edge of the metal layer, creating a phenomenon where the metal layer tends to be isothermal (forming a temperature-stabilizing plate). Furthermore, the bonding between the metal layer and the upper copper layer increases the substrate's bending strength, reducing substrate warping.

The metal layer disclosed herein can be locally thickened according to the circuit layout. Multiple metal layers can be simultaneously disposed on the copper layer, and each metal layer can be designed to have different shapes and thicknesses according to product requirements.

This disclosure primarily involves adding a metal layer between the chip and substrate, allowing the heat from the chip to be evenly distributed during the transfer process. This not only avoids localized high temperatures but also effectively increases the heat dissipation area, cooling the chip. The advantages of this disclosure include increased chip heat dissipation, reduced substrate warping, flexible thickening of the local copper layer, and reduced copper material usage.

The following disclosure provides many different embodiments for implementing different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the disclosed embodiments describe a first feature component formed on or above a second feature component, it may include embodiments in which the first feature component and the second feature component are in direct contact, and may also include embodiments in which additional feature components are formed between the first feature component and the second feature component, so that the first feature component and the second feature component may not be in direct contact.

It should be understood that additional steps may be implemented before, during, or after the method, and in other embodiments of the method, some steps may be replaced or omitted.

In addition, spatially relative terms such as "below," "beneath," "lower," "above," "above," "higher," and similar terms may be used. These spatially relative terms are used to facilitate description of the relationship between one component or features and another component or features in the diagrams. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 45 degrees or in other orientations, the spatially relative adjectives used therein will also be interpreted based on the rotated orientation. In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, unless otherwise specified, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact but having another structure disposed therebetween. Furthermore, such terms may include situations where both structures are movable or both structures are fixed.

In the specification, the terms "about," "approximately," "mostly," "substantially," "same," and "similar" generally indicate that a characteristic value is within plus or minus 15%, plus or minus 10%, plus or minus 5%, plus or minus 3%, plus or minus 2%, plus or minus 1%, or plus or minus 0.5% of a given value. The quantities given herein are approximate quantities, that is, in the absence of specific descriptions of "about," "approximately," "mostly," "substantially," the meanings of "about," "approximately," "mostly," "substantially" are implied.

It should be understood that although the terms "first," "second," "third," etc. are used herein to describe different elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be referred to as a second element, component, region, layer, or section without departing from the technology of the present disclosure.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the present disclosure.

Referring to FIG. 1 , according to one embodiment of the present disclosure, a power module structure 10 is provided. FIG. 1 is a schematic cross-sectional view of the power module structure 10 .

As shown in Figure 1, power module structure 10 includes a substrate 12, a first copper layer 14, a second copper layer 16, a metal layer 18, and a chip 20. First copper layer 14 is disposed on first surface 12a of substrate 12. Second copper layer 16 is disposed on second surface 12b of substrate 12, which is opposite first surface 12a. Metal layer 18 is disposed on first copper layer 14. Chip 20 is disposed on metal layer 18. It is noteworthy that area A1 of metal layer 18 is smaller than area A2 of first copper layer 14, and area A3 of chip 20 is smaller than area A1 of metal layer 18.

In some embodiments, the material of substrate 12 includes aluminum oxide, but the present disclosure is not limited thereto; other suitable substrate materials are also applicable to the present disclosure. In some embodiments, when substrate 12 is made of aluminum oxide (a ceramic material), the composite material composed of substrate 12, first copper layer 14, and second copper layer 16 is called a ceramic substrate. This substrate serves as a carrier for chip 20 and has high thermal conductivity and electrical insulation properties.

In some embodiments, the metal layer 18 is made of a metal material with high thermal and electrical conductivity, such as copper, silver, or aluminum, but the present disclosure is not limited thereto. Other suitable metal materials are also applicable to the present disclosure. In some embodiments, the metal layer 18 is shaped like a rectangle, a circle, a polygon, or a trapezoid, but the present disclosure is not limited thereto. Other suitable metal layer shapes are also applicable to the present disclosure. The shapes of the metal layer 18 are further described below with reference to the figures (Figures 2A-2C).

In some embodiments, the metal layer 18 contacts (bonds) the first copper layer 14. In some embodiments, the metal layer 18 and the first copper layer 14 are bonded by soldering or diffusion bonding. In some embodiments, in the soldering bonding method, the metal layer 18 and the first copper layer 14 are bonded by solder paste 22.

In some embodiments, the chip 20 includes power devices, such as high-power devices.

In some embodiments, the chip 20 is in contact with (bonded to) the metal layer 18. In some embodiments, the chip 20 is bonded to the metal layer 18 via a silver paste 24, for example, the chip 20 is bonded to the metal layer 18 via a non-pressure sintering silver paste.

Referring to FIG. 2A , according to one embodiment of the present disclosure, a power module structure 110 is provided. FIG. 2A is a perspective view of the power module structure 110 , primarily illustrating the shape of the metal layer in the power module structure 110 .

As shown in FIG2A , power module structure 110 includes substrate 112, first copper layer 114, second copper layer 116, metal layer 118, and chip 120. First copper layer 114 and second copper layer 116 are disposed on opposite surfaces of substrate 112. Metal layer 118 is disposed on first copper layer 114. Chip 120 is disposed on metal layer 118. As shown in FIG2A , the area of metal layer 118 is smaller than that of first copper layer 114, and the area of chip 120 is smaller than that of metal layer 118.

In some embodiments, the material of substrate 112 includes aluminum oxide, but the present disclosure is not limited thereto; other suitable substrate materials are also applicable to the present disclosure. In some embodiments, when substrate 112 is aluminum oxide (a ceramic material), the composite material composed of substrate 112, first copper layer 114, and second copper layer 116 is called a ceramic substrate. This serves as a carrier for chip 120 and has high thermal conductivity and electrical insulation properties.

In some embodiments, the material of the metal layer 118 includes a metal material with high thermal conductivity and electrical conductivity, such as copper, silver, or aluminum, but the present disclosure is not limited thereto, and other suitable metal materials are also applicable to the present disclosure.

It is worth noting that in FIG. 2A , the shape of the metal layer 118 located below the chip 120 is rectangular, but the present disclosure is not limited thereto. Other suitable metal layer shapes, such as circular, polygonal, or trapezoidal, are also applicable to the present disclosure.

In some embodiments, the metal layer 118 contacts (bonds) the first copper layer 114. In some embodiments, the metal layer 118 and the first copper layer 114 are bonded by soldering or diffusion bonding. In some embodiments, in the soldering bonding method, the metal layer 118 and the first copper layer 114 are bonded by solder paste 122.

In some embodiments, the chip 120 includes power devices, such as high-power devices.

In some embodiments, the chip 120 is in contact with (bonded to) the metal layer 118. In some embodiments, the chip 120 is bonded to the metal layer 118 via a silver paste 124, for example, the chip 120 is bonded to the metal layer 118 via a non-pressure sintering silver paste.

Referring to FIG. 2B , according to one embodiment of the present disclosure, a power module structure 210 is provided. FIG. 2B is a perspective view of the power module structure 210 , primarily illustrating the shape of the metal layer in the power module structure 210 .

As shown in FIG2B , the power module structure 210 includes a substrate 212, a first copper layer 214, a second copper layer 216, a metal layer 218, a chip 220, a solder paste 222, and a silver paste 224. The configuration, materials, dimensional relationships between the components, and the bonding method between the components in the power module structure 210 shown in FIG2B are similar to those of the power module structure 110 shown in FIG2A and will not be repeated here. The main difference between the embodiment shown in FIG2B and the embodiment shown in FIG2A is the shape of the metal layer. In FIG2B , the shape of the metal layer 218 located below the chip 220 is circular, but the present disclosure is not limited to this, and other suitable metal layer shapes are also applicable to the present disclosure.

Please refer to FIG. 2C , which shows a power module structure 310 according to an embodiment of the present disclosure. FIG. 2C is a perspective view of the power module structure 310 , mainly illustrating the shape of the metal layer in the power module structure 310 .

As shown in FIG2C , the power module structure 310 includes a substrate 312, a first copper layer 314, a second copper layer 316, a metal layer 318, a chip 320, a solder paste 322, and a silver paste 324. The configuration, materials, dimensional relationships between the components, and the bonding method between the components in the power module structure 310 shown in FIG2C are similar to those of the power module structure 110 shown in FIG2A and will not be repeated here. The main difference between the embodiment shown in FIG2C and the embodiment shown in FIG2A is the shape of the metal layer. In FIG2C , the shape of the metal layer 318 located below the chip 320 is a trapezoid, but the present disclosure is not limited to this, and other suitable metal layer shapes are also applicable to the present disclosure.

As shown in FIG. 2C , when the metal layer 318 in the power module structure 310 is trapezoidal in shape, the heat diffusion area will gradually expand from the contact surface between the chip 320 and the metal layer 318 toward the first copper layer 314 .

Referring to FIG. 3 , according to one embodiment of the present disclosure, a power module structure 410 is provided. FIG. 3 is a perspective view of the power module structure 410 .

As shown in FIG3 , power module structure 410 includes a substrate 412, a first copper layer 414, a second copper layer 416, a metal layer 418, and a chip 420. First copper layer 414 and second copper layer 416 are disposed on opposite surfaces of substrate 412. Chip 420 is disposed on first copper layer 414. Metal layer 418 is disposed on first copper layer 414 and surrounds chip 420. Furthermore, as shown in FIG3 , the area of metal layer 418 is smaller than that of first copper layer 414.

In some embodiments, the material of substrate 412 includes aluminum oxide, but the present disclosure is not limited thereto; other suitable substrate materials are also applicable to the present disclosure. In some embodiments, when substrate 412 is made of aluminum oxide (a ceramic material), the composite material composed of substrate 412, first copper layer 414, and second copper layer 416 is called a ceramic substrate. This serves as a carrier for chip 420 and has high thermal conductivity and electrical insulation properties.

In some embodiments, chip 420 includes power devices, such as high-power devices.

In some embodiments, the chip 420 is in contact with (bonded to) the first copper layer 414. In some embodiments, the chip 420 is bonded to the first copper layer 414 via a silver paste (not shown), for example, the chip 420 is bonded to the first copper layer 414 via non-pressure sintering silver paste.

In some embodiments, the material of metal layer 418 includes a metal material with high thermal and electrical conductivity, such as copper, silver, or aluminum, but the present disclosure is not limited thereto. Other suitable metal materials are also applicable to the present disclosure. In addition, as shown in FIG. 3 , the shape of metal layer 418 surrounding chip 420 in power module structure 410 is polygonal, but the present disclosure is not limited thereto. Other suitable metal layer shapes, such as rectangular, circular, or trapezoidal, are also applicable to the present disclosure.

In some embodiments, the metal layer 418 contacts (bonds) the first copper layer 414. In some embodiments, the metal layer 418 and the first copper layer 414 are bonded by soldering or diffusion bonding. In some embodiments, in the soldering bonding method, the metal layer 418 and the first copper layer 414 are bonded by solder paste (not shown).

In some embodiments, the thickness T1 of the chip 420 is the same as the thickness T2 of the metal layer 418. In some other embodiments, the thickness T1 of the chip 420 is different from the thickness T2 of the metal layer 418. For example, the thickness T1 of the chip 420 is less than the thickness T2 of the metal layer 418, as shown in FIG. 3 , or the thickness T1 of the chip 420 is greater than the thickness T2 of the metal layer 418 (not shown).

In some embodiments, chip 420 is in contact with metal layer 418, as shown in FIG. 3 .

Referring to FIG. 4 , according to one embodiment of the present disclosure, a power module structure 510 is provided. FIG. 4 is a perspective view of the power module structure 510 .

As shown in FIG4 , power module structure 510 includes a substrate 512, a first copper layer 514, a second copper layer 516, a plurality of metal layers (e.g., a first metal layer 518a, a second metal layer 518b, a third metal layer 518c, a fourth metal layer 518d, and a fifth metal layer 518e), and a plurality of chips (e.g., a first chip 520a, a second chip 520b, a third chip 520c, a fourth chip 520d, and a fifth chip 520e). The first copper layer 514 and the second copper layer 516 are disposed on opposite surfaces of the substrate 512. A first metal layer 518a, a second metal layer 518b, a third metal layer 518c, a fourth metal layer 518d, and a fifth metal layer 518e are each disposed on the first copper layer 514 and separated from one another. A first chip 520a is disposed on the first metal layer 518a, a second chip 520b is disposed on the second metal layer 518b, a third chip 520c is disposed on the third metal layer 518c, a fourth chip 520d is disposed on the fourth metal layer 518d, and a fifth chip 520e is disposed on the fifth metal layer 518e. As can be seen from Figure 4, the areas of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are respectively smaller than the area of the first copper layer 514, the area of the first chip 520a is smaller than the area of the first metal layer 518a, the area of the second chip 520b is smaller than the area of the second metal layer 518b, the area of the third chip 520c is smaller than the area of the third metal layer 518c, the area of the fourth chip 520d is smaller than the area of the fourth metal layer 518d, and the area of the fifth chip 520e is smaller than the area of the fifth metal layer 518e.

In some embodiments, the material of substrate 512 includes aluminum oxide, but the present disclosure is not limited thereto; other suitable substrate materials are also applicable to the present disclosure. In some embodiments, when the material of substrate 512 is aluminum oxide (a ceramic material), the composite plate composed of substrate 512, first copper layer 514, and second copper layer 516 is called a ceramic substrate. It serves as a carrier for first chip 520a, second chip 520b, third chip 520c, fourth chip 520d, and fifth chip 520e, and has high thermal conductivity and electrical insulation properties.

In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e include metal materials with high thermal and electrical conductivity, such as copper, silver, or aluminum, but the present disclosure is not limited thereto, and other suitable metal materials are also applicable to the present disclosure. In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e include rectangular, circular, polygonal, or trapezoidal shapes, but the present disclosure is not limited thereto, and other suitable metal layer shapes are also applicable to the present disclosure. In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e have the same shape. In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e have different shapes. In some embodiments, the shapes of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are partially the same and partially different. For example, the shape of the first metal layer 518a is circular, the shape of the second metal layer 518b is rectangular, the shape of the third metal layer 518c is rectangular, the shape of the fourth metal layer 518d is polygonal, and the shape of the fifth metal layer 518e is rectangular, as shown in Figure 4.

In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are respectively in contact with (bonded to) the first copper layer 514. In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are respectively bonded to the first copper layer 514 by soldering or diffusion bonding. In some embodiments, in a soldering bonding method, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are respectively bonded to the first copper layer 514 via solder paste (not shown).

In some embodiments, the first chip 520a, the second chip 520b, the third chip 520c, the fourth chip 520d, and the fifth chip 520e include power devices, such as high-power devices.

In some embodiments, first chip 520a is in contact with (bonded to) first metal layer 518a, second chip 520b is in contact with (bonded to) second metal layer 518b, third chip 520c is in contact with (bonded to) third metal layer 518c, fourth chip 520d is in contact with (bonded to) fourth metal layer 518d, and fifth chip 520e is in contact with (bonded to) fifth metal layer 518e. In some embodiments, the chips and metal layers are bonded using silver paste (not shown), for example, non-pressure sintering silver paste.

In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e have the same thickness. In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e have different thicknesses. In some embodiments, the thicknesses of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are partially the same and partially different. For example, the thickness H1 of the first metal layer 518a is the same as the thickness H4 of the fourth metal layer 518d, the thickness H2 of the second metal layer 518b is the same as the thickness H3 of the third metal layer 518c and the thickness H5 of the fifth metal layer 518e, and the thickness H1 of the first metal layer 518a is different from the thickness H2 of the second metal layer 518b, the thickness H3 of the third metal layer 518c, and the thickness H5 of the fifth metal layer 518e, as shown in Figure 4.

Generally speaking, the copper layer on a ceramic substrate must consider the etching capability of the process and the warping caused by thermal expansion. Therefore, the thickness of the copper layer must be limited. However, when installing a high-power chip, an overly thin copper layer will generate local hot spots, making it difficult for heat to dissipate. In the power module structure disclosed herein, an additional metal layer with high thermal and electrical conductivity is provided below (or around) the chip, causing the copper layer on the substrate to be locally thickened. This allows heat to be evenly transferred to the metal layer and expand the heat dissipation area before being more efficiently transferred downward. The metal layer disclosed herein acts as an accessory for the chip, amplifying its heat source, achieving uniform heat dissipation and increasing the heat dissipation area, and is connected to the copper layer on the substrate.

This disclosure utilizes a metal layer larger than the heat source, placed in contact with the heat source, to achieve uniform temperature transfer. Uniform heat transfer means a minimal temperature difference between the center and edge of the metal layer, creating a phenomenon where the metal layer tends to be isothermal (forming a temperature-stabilizing plate). Furthermore, the bonding between the metal layer and the upper copper layer increases the substrate's bending strength, reducing substrate warping.

The metal layer disclosed herein can be locally thickened according to the circuit layout. Multiple metal layers can be simultaneously disposed on the copper layer, and each metal layer can be designed to have different shapes and thicknesses according to product requirements.

This disclosure primarily involves adding a metal layer between the chip and substrate, allowing the heat from the chip to be evenly distributed during the transfer process. This not only avoids localized high temperatures but also effectively increases the heat dissipation area, cooling the chip. The advantages of this disclosure include increased chip heat dissipation, reduced substrate warping, flexible thickening of the local copper layer, and reduced copper material usage.

The components of some of the above-mentioned embodiments are provided so that those with ordinary skill in the art to which this disclosure belongs can better understand the perspectives of the embodiments of this disclosure. Those with ordinary skill in the art to which this disclosure belongs should understand that they can use the embodiments of this disclosure as a basis to design or modify other processes and structures to achieve the same purposes and/or advantages as the embodiments introduced herein. Those with ordinary skill in the art to which this disclosure belongs should also understand that such equivalent structures do not deviate from the spirit and scope of this disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined as defined by the scope of the patent application attached hereto. In addition, although this disclosure has been disclosed above with several preferred embodiments, they are not intended to limit this disclosure.

Reference throughout this specification to features, advantages, or similar language does not imply that all features and advantages that may be achieved with the present disclosure should or may be achieved in any single embodiment of the present disclosure. Rather, language referring to features and advantages is to be understood as meaning that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussion of features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.

Furthermore, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. Based on the description herein, one skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages may be identified in some embodiments that may not be present in all embodiments of the present disclosure.

10,110,210,310,410,510: Power module structure 12,112,212,312,412,512: Substrate 12a: First surface of substrate 12b: Second surface of substrate 14,114,214,314,414,514: First copper layer 16,116,216,316,416,516: Second copper layer 18,118,218,318,418: Metal layer 20,120,220,320,420: Chip 22,122,222,322: Solder paste 24,124,224,324: Silver paste 518a: First metal layer 518b: Second metal layer 518c: Third metal layer 518d: Fourth metal layer 518e: Fifth metal layer 520a: First chip 520b: Second chip 520c: Third chip 520d: Fourth chip 520e: Fifth chip A1: Area of metal layer A2: Area of first copper layer A3: Area of chip H1: Thickness of first metal layer H2: Thickness of second metal layer H3: Thickness of third metal layer H4: Thickness of fourth metal layer H5: Thickness of fifth metal layer T1: Thickness of chip T2: Thickness of metal layer

The following describes the disclosed embodiments in detail with reference to the accompanying figures. It should be noted that the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of components may be exaggerated or reduced to clearly illustrate the technical features of the disclosed embodiments. Figure 1 is a schematic cross-sectional view of a power module structure according to an embodiment of the disclosed embodiment; Figure 2A is a perspective view of a power module structure according to an embodiment of the disclosed embodiment; Figure 2B is a perspective view of a power module structure according to an embodiment of the disclosed embodiment; Figure 2C is a perspective view of a power module structure according to an embodiment of the disclosed embodiment; Figure 3 is a perspective view of a power module structure according to an embodiment of the disclosed embodiment; and Figure 4 is a perspective view of a power module structure according to an embodiment of the disclosed embodiment.

10: Power module structure 12: Substrate 12a: First surface of substrate 12b: Second surface of substrate 14: First copper layer 16: Second copper layer 18: Metal layer 20: Chip 22: Solder paste 24: Silver paste A1: Metal layer area A2: First copper layer area A3: Chip area

Claims (18)

A power module structure includes: a substrate; a copper layer continuously disposed on the substrate, the copper layer having an area equal to that of the substrate; a metal layer disposed on the copper layer, wherein the metal layer has an area smaller than that of the copper layer, and the metal layer and the copper layer are bonded by solder paste; and a chip disposed on the metal layer, wherein the chip has an area smaller than that of the metal layer, and the chip and the metal layer are bonded by silver paste. The power module structure of claim 1, wherein the material of the substrate includes aluminum oxide. In the power module structure of claim 1, the material of the metal layer includes copper, silver, or aluminum. The power module structure of claim 1, wherein the shape of the metal layer includes a rectangle, a circle, a polygon, or a trapezoid. The power module structure of claim 1, wherein the metal layer contacts the copper layer. A power module structure as claimed in claim 1, wherein the chip includes a power element. The power module structure of claim 1, wherein the chip contacts the metal layer. A power module structure includes: a substrate; a copper layer continuously disposed on the substrate, and the area of the copper layer is equal to the area of the substrate; a chip disposed on the copper layer; and a metal layer disposed on the copper layer, surrounding the chip, and the area of the metal layer is smaller than the area of the copper layer, and the metal layer and the copper layer are bonded by solder paste. The power module structure of claim 8, wherein the chip and the metal layer have different thicknesses. The power module structure of claim 8, wherein the chip and the metal layer are in contact with the copper layer. The power module structure of claim 8, wherein the chip contacts the metal layer. A power module structure includes: a substrate; a copper layer continuously disposed on the substrate, the copper layer having an area equal to that of the substrate; a first metal layer disposed on the copper layer, wherein the area of the first metal layer is smaller than that of the copper layer, and the first metal layer and the copper layer are bonded by solder paste; a second metal layer disposed on the copper layer, wherein the area of the second metal layer is smaller than that of the copper layer, the second metal layer and the copper layer are bonded by solder paste, and the second metal layer is disposed separately from the first metal layer; A first chip is disposed on the first metal layer, wherein the area of the first chip is smaller than the area of the first metal layer, and the first chip and the first metal layer are bonded by silver paste; and a second chip is disposed on the second metal layer, wherein the area of the second chip is smaller than the area of the second metal layer, and the second chip and the second metal layer are bonded by silver paste. The power module structure of claim 12, wherein the shapes of the first metal layer and the second metal layer include rectangle, circle, polygon, or trapezoid. The power module structure of claim 12, wherein the first metal layer and the second metal layer have different shapes. The power module structure of claim 12, wherein the first metal layer and the second metal layer have different thicknesses. The power module structure of claim 12, wherein the first metal layer and the second metal layer are in contact with the copper layer. The power module structure of claim 12, wherein the first chip contacts the first metal layer. The power module structure of claim 12, wherein the second chip contacts the second metal layer.