TWI896122B - Electronic package - Google Patents

Abstract

The present invention provides an electronic package, which includes: a carrier structure having a core layer and a circuit layer provided on the core layer; an electronic component arranged on the carrier structure and electrically connected to the circuit layer; and a heat dissipation structure disposed on the electronic component. By providing the difference in thermal expansion coefficient between the heat dissipation structure and the core layer less than 7ppm/℃ reduces the problems of warpage and cracking of the electronic package.

Description

Electronic packaging

The present invention relates to a semiconductor package structure, in particular to an electronic package with a heat dissipation structure.

As the demand for electronic products increases in functionality and processing speed, semiconductor chips, as core components of electronic products, must have higher densities of electronic components and circuits. Consequently, semiconductor chips generate greater amounts of heat during operation.

To quickly dissipate heat, the industry typically incorporates a heat sink into semiconductor packages. This heat sink is typically bonded to the backside of the chip via a heat sink, such as a thermal interface material (TIM). The heat generated by the semiconductor chip is dissipated through the heat sink and the heat sink.

As shown in Figure 1, the conventional method for manufacturing a semiconductor package 1 begins by flip-chip bonding a semiconductor chip 11 with its active surface 11a on a package substrate 10 (i.e., via conductive bumps 110 and underfill 111). A heat sink 13 is then bonded to the inactive surface 11b of the semiconductor chip 11 via a heat spreader 12, with its top plate 130 attached to the package substrate 10. Support legs 131 of the heat sink 13 are mounted on the package substrate 10 via an adhesive layer 14. During operation, heat generated by the semiconductor chip 11 is transferred via the heat spreader 12 to the top plate 130 of the heat sink 13, dissipating the heat to the exterior of the semiconductor package 1.

However, due to the significant difference in the coefficient of thermal expansion (CTE) between the heat sink 13 and the package substrate 10, the semiconductor package 1 experienced stress and tension after high and low temperature cycling testing, causing cracks in the package substrate 10 and even leading to abnormalities in subsequent electrical tests.

Therefore, how to overcome the aforementioned problems of learning technology has become an urgent issue that needs to be solved.

In view of the various deficiencies of the aforementioned prior art, the present invention provides an electronic package comprising: a carrier structure having a core layer and a circuit layer bonded to the core layer; an electronic component disposed on the carrier structure and electrically connected to the circuit layer; and a heat dissipation structure disposed on the electronic component, wherein the heat dissipation structure has a first deformation trend, and the carrier structure has a second deformation trend, and the first deformation trend is the same as the second deformation trend.

In the aforementioned electronic package, the supporting structure has an insulating layer covering the circuit layer; the insulating layer is green paint.

In the aforementioned electronic package, the supporting structure is a package substrate having the core layer; the circuit layer is a redistribution circuit layer.

In the aforementioned electronic package, the electronic component is a semiconductor chip having an active surface and an inactive surface opposite to each other. The active surface is electrically connected to the supporting structure and the circuit layer via a plurality of conductive bumps in a flip-chip manner.

In the aforementioned electronic package, the heat dissipation structure comprises a top plate and a support portion extending from the top plate, wherein the top plate is disposed on the electronic component via a heat conductor.

In the aforementioned electronic package, the difference in thermal expansion coefficient between the heat sink structure and the core layer is less than 7 ppm/°C. Furthermore, the first deformation trend is that the edge of the heat sink structure is higher than the center, or the edge of the heat sink structure is lower than the center, and the second deformation trend is that the edge of the support structure is higher than the center, or the edge of the support structure is lower than the center.

In summary, the electronic package of the present invention includes an electronic component, a supporting structure, and a heat dissipation structure. By minimizing the difference in thermal expansion coefficients between the heat dissipation structure and the core layer of the supporting structure, the deformation trends of the supporting structure and the heat dissipation structure are aligned, thereby reducing the bending stress of the electronic package and avoiding cracking of the protective layer (green paint).

1: Semiconductor Package

10: Package substrate

11: Semiconductor Chip

11a: Action surface

11b: Non-active surface

110: Conductive bumps

111: Primer

12: Heat sink

13: Heat sink

130: Top plate

131: Support your feet

14: Adhesive layer

2: Electronic packaging

21: Load-bearing structure

21a: First surface

21b: Second surface

210: Core Layer

211: Line layer

212: Insulating layer

22: Electronic components

22a: Action surface

22b: Non-active surface

220: Conductive bumps

221: Primer

23: Heat dissipation structure

231: Top Plate

232: Supporting part

24: Heat conductor

25: Binding layer

W1: First deformation trend

W2: Second deformation trend

Figure 1 is a schematic cross-sectional view of a conventional semiconductor package.

Figure 2 is a schematic cross-sectional view of the electronic package of the present invention.

Figure 3 is a schematic diagram showing the deformation of the electronic package of the present invention.

The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand the other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structures, proportions, and sizes depicted in the figures accompanying this specification are intended solely to facilitate understanding and reading by those skilled in the art. They are not intended to limit the implementation of this invention and therefore have no substantive technical significance. Any structural modifications, changes in proportions, or adjustments to sizes, provided they do not affect the effectiveness and objectives of this invention, shall remain within the scope of the technical disclosure of this invention. Furthermore, terms such as "above," "first," "second," and "one" used in this specification are used solely for clarity of description and are not intended to limit the scope of implementation of the present invention. Any changes or adjustments to these terms, without substantially altering the technical content, should be considered within the scope of implementation of the present invention.

Figure 2 is a schematic cross-sectional view of the electronic package 2 of the present invention. It primarily comprises at least one electronic component 22 mounted on a supporting structure 21, and a heat dissipation structure 23 connected to the electronic component 22 via a heat conductor 24.

The carrier structure 21 defines a first surface 21a and a second surface 21b opposite to each other, and includes a core layer 210, a circuit layer 211 bonded to the core layer 210, and an insulation layer 212 covering the circuit layer 211.

In this embodiment, the carrier structure 21 is, for example, a package substrate having the core layer 210 , the circuit layer 211 is, for example, a redistribution layer (RDL), and the insulating layer 212 is, for example, a green paint (Solder Mask).

The electronic component 22 may be, for example, an active component, a passive component, a package module, or a combination thereof. The active component may be, for example, a semiconductor chip, and the passive component may be, for example, a resistor, a capacitor, or an inductor.

In this embodiment, the electronic component 22 is a semiconductor chip having an active surface 22a and an inactive surface 22b. The active surface 22a is electrically connected to the carrier structure 21 and the circuit layer 211 via a plurality of conductive bumps 220 in a flip-chip manner. An underfill 221 is formed between the first surface 21a of the carrier structure 21 and the active surface 22a to cover each of the conductive bumps 220. However, there are many ways to electrically connect the electronic component 22 to the carrier structure 21, not limited to the above.

The heat dissipation structure 23 is, for example, a heat sink, a heat dissipation lid, or other components or structures with equivalent functions. In this embodiment, a heat dissipation lid is used as an example. The heat dissipation structure 23 comprises a top sheet 231 and a support portion 232 extending from the top sheet 231. The support portion 232 is bonded to the first surface 21a of the support structure 21 surrounding the electronic component 22 via a bonding layer 25, such that the top sheet 231 faces the inactive surface 22b of the electronic component 22.

The heat conductor 24 is disposed between the inactive surface 22b of the electronic component 22 and the top plate 231 of the heat sink 23 to more efficiently transfer heat generated by the electronic component 22 to the heat sink 23 and then dissipate it into the environment. In one embodiment, the heat conductor 24 is a thermal interface material (TIM) layer primarily composed of indium (In) or an indium-silver (In/Ag) alloy.

The present invention mainly makes the difference in the coefficient of thermal expansion (CTE) between the heat dissipation structure 23 and the core layer 210 of the supporting structure 21 less than 7ppm/℃, so that even if the electronic package 2 is subjected to thermal stress during the manufacturing process, the heat dissipation structure 23 has a first deformation trend W1 (the first deformation trend can be that the edge of the heat dissipation structure is higher than the center or the edge of the heat dissipation structure is lower than the center), and the supporting structure 21 has a second deformation trend W2. The second deformation trend W2 (the second deformation trend can be when the edge of the supporting structure is higher than the center or lower than the center), while the first deformation trend W1 and the second deformation trend W2 are the same (as shown in Figure 3). This reduces the stress on the electronic package 2 due to warping, thereby preventing cracks in the insulating layer 212 of the supporting structure 21 (i.e., the green paint on the package substrate), which could lead to abnormalities during subsequent electrical testing.

In summary, the electronic package of the present invention includes an electronic component, a supporting structure, and a heat dissipation structure. By minimizing the difference in thermal expansion coefficients between the heat dissipation structure and the core layer of the supporting structure and aligning the deformation trends of the supporting structure and the heat dissipation structure, the stress on the electronic package due to warping is reduced and cracking of the protective layer (green paint) is avoided.

The above embodiments are provided to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection for the present invention shall be as set forth in the patent application described below.

2: Electronic packaging

21: Load-bearing structure

21a: First surface

21b: Second surface

210: Core Layer

211: Line layer

212: Insulating layer

22: Electronic components

22a: Action surface

22b: Non-active surface

220: Conductive bumps

221: Primer

23: Heat dissipation structure

231: Top Plate

232: Supporting part

24: Heat conductor

25: Binding layer

Claims (11)

An electronic package comprising: The load-bearing structure comprises a core layer and a circuit layer connected to the core layer; An electronic component is disposed on the supporting structure and electrically connected to the circuit layer; and A heat dissipation structure is disposed on the electronic component, wherein the heat dissipation structure has a first deformation trend, the supporting structure has a second deformation trend, and the first deformation trend is the same as the second deformation trend. The electronic package as described in claim 1, wherein the supporting structure has an insulating layer covering the circuit layer. The electronic package as described in claim 2, wherein the insulating layer is green paint. The electronic package as described in claim 1, wherein the supporting structure is a package substrate having the core layer. The electronic package as claimed in claim 1, wherein the circuit layer is a redistribution circuit layer. The electronic package as described in claim 1, wherein the electronic component is a semiconductor chip having an active surface and an inactive surface opposite to each other, and wherein the active surface is electrically connected to the supporting structure and the circuit layer via a plurality of conductive bumps in a flip-chip manner. The electronic package of claim 1, wherein the heat dissipation structure comprises a top plate and a support portion extending from the top plate. The electronic package as described in claim 7, wherein the top sheet is disposed on the electronic component via a heat conductor. The electronic package as described in claim 1, wherein the difference in thermal expansion coefficient between the heat dissipation structure and the core layer is less than 7 ppm/°C. The electronic package as described in claim 1, wherein the first deformation trend is that the edge of the heat dissipation structure is higher than the center or the edge of the heat dissipation structure is lower than the center. The electronic package as described in claim 1, wherein the second deformation trend is that the edge of the supporting structure is higher than the center or the edge of the supporting structure is lower than the center.