TWI895755B - Electronic device - Google Patents

Abstract

An electronic device is provided, which comprises: a substrate; and a transistor disposed on the substrate. The transistor comprises: a gate electrode; a semiconductor layer at least partially overlapping the gate electrode, the semiconductor layer comprising a first sub-semiconductor layer and a second sub-semiconductor layer, the second sub-semiconductor layer disposed on the first sub-semiconductor layer, and the second sub-semiconductor comprising indium, gallium and zinc; a drain electrode electrically connected to the semiconductor layer; and a source electrode electrically connected to the semiconductor layer; wherein in the second sub-semiconductor layer, an atomic percent of indium is less than an atomic percent of gallium, and the atomic percent of gallium is less than an atomic percent of zinc.

Description

electronic devices

The present disclosure relates to an electronic device, particularly an electronic device that requires high voltage operation.

Thin-film transistors (TFTs) are now used in a variety of electronic devices, such as displays, mobile phones, laptops, video cameras, music players, mobile navigation devices, televisions, video walls, and electronic paper. However, the TFTs used in these devices are typically designed for low-voltage operation and cannot withstand high voltages. High-voltage operation can easily cause the TFTs to burn out, damaging the device.

Therefore, there is an urgent need to provide an electronic device that can be used for high voltage operation.

The present disclosure provides an electronic device comprising: a substrate; and a transistor disposed on the substrate, the transistor comprising: a gate; a semiconductor layer at least partially overlapping the gate, the semiconductor layer comprising a first sub-semiconductor layer and a second sub-semiconductor layer, the second sub-semiconductor layer disposed on the first sub-semiconductor layer and comprising indium, gallium, and zinc; a drain electrically connected to the semiconductor layer; and a source electrically connected to the semiconductor layer; wherein, in the second sub-semiconductor layer, the atomic percentage of indium is less than the atomic percentage of gallium, and the atomic percentage of gallium is less than the atomic percentage of zinc.

The present disclosure further provides an electronic device comprising: a substrate; and a transistor disposed on the substrate, the transistor comprising: a gate; a semiconductor layer at least partially overlapping the gate, the semiconductor layer comprising a first sub-semiconductor layer and a second sub-semiconductor layer, the second sub-semiconductor layer disposed on the first sub-semiconductor layer and comprising indium, gallium, and zinc; a drain electrically connected to the semiconductor layer; and a source electrically connected to the semiconductor layer; wherein the thickness of the drain is less than the thickness of the semiconductor layer, and the thickness of the source is less than the thickness of the semiconductor layer.

1:Substrate

2: Transistor

21: Gate

22: Gate insulation layer

23: Semiconductor layer

231: First sub-semiconductor layer

231a: Lower surface

232: Second sub-semiconductor layer

232a: Upper surface

24:Jiji

24a: Upper surface

24b: Lower surface

25:Source

25a: Upper surface

25b: Lower surface

3: Insulating layer

31: First insulating layer

32: Second insulating layer

33: The third insulating layer

4: Metal layer

5: Conductor layer

COM1: Electrode

COM2: Another electrode

Cw: Working capacitance

Cst: Storage capacitor

DL: Data Line

P: Pixel unit

SL: Scan Line

V:Through hole

V1: First through hole

V2: Second through hole

V3: Third through hole

TFT: Transistor

T1, T2, T3: Thickness

Z: Normal direction

Figure 1 is a schematic cross-sectional view of an electronic device according to one embodiment of the present disclosure.

Figure 2 is a diagram showing the relationship between gate voltage and drain current for an electronic device according to an embodiment of the present disclosure and a comparative example.

FIG3 is a diagram showing the relationship between gate voltage and drain current at different voltages for an electronic device according to an embodiment of the present disclosure.

Figure 4 is an equivalent circuit diagram of a pixel of an electronic device according to one embodiment of the present disclosure.

The following describes the implementation of this disclosure through specific embodiments. Those skilled in the art will readily understand its other advantages and benefits from the information provided in this specification. This disclosure may also be implemented or applied through various other specific embodiments, and the details herein may be modified and altered to accommodate different viewpoints and applications without departing from the spirit of this invention.

It should be noted that, unless otherwise specified, "having an element" in this document is not limited to having a single element, but may include one or more elements. Furthermore, the use of ordinal numbers such as "first" and "second" in the specification and patent claims to modify elements in the patent claims does not, in itself, imply or represent any prior ordinal number of the claimed elements, nor does it represent the order of one claimed element relative to another, or the order of manufacturing methods. The use of such ordinal numbers is solely to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

Throughout this disclosure and the accompanying patent claims, certain terms are used to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same component by different names. This document does not intend to distinguish between components that have the same function but are named differently. In the following description and patent claims, words such as "including," "comprising," and "having" are open-ended and should be interpreted as meaning "including, but not limited to..." Therefore, when the terms "including," "containing," and/or "having" are used in the description of this disclosure, they specify the presence of corresponding features, regions, steps, operations, and/or components, but do not preclude the presence of one or more corresponding features, regions, steps, operations, and/or components.

As used herein, the terms "about," "approximately," "substantially," and "substantially" generally mean within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The quantities given herein are approximate quantities, meaning that the meanings of "about," "approximately," "substantially," and "substantially" are implied even without specific mention of "about," "approximately," "substantially," or "substantially." Furthermore, the terms "ranging from a first value to a second value" or "ranging between a first value and a second value" mean that the range includes the first value, the second value, and any values therebetween.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with the background or context of the relevant art and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined herein.

Furthermore, relative terms, such as "below" or "bottom" and "above" or "top," may be used in the embodiments to describe the relative relationship of one element in the drawings to another element. It will be understood that if the device in the drawings is turned upside down, the element described as being on the "below" side will become the element on the "above" side. When a corresponding component (such as a film layer or region) is referred to as being "on" another component, it can be directly on the other component, or there can be other components between the two components. On the other hand, when a component is referred to as being "directly on" another component, there are no components between the two components. Furthermore, when a component is referred to as being "on" another component, the two components have a top-to-bottom relationship in a top-down view, and the component can be above or below the other component, depending on the orientation of the device.

In this disclosure, distance and thickness can be measured using an optical microscope, or from cross-sectional images obtained using an electron microscope, but this disclosure is not limited thereto. Furthermore, any two values or directions used for comparison may have a certain degree of error. If a first value is equal to a second value, this implies that there may be an error of approximately 10% between the first and second values. If the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees. If the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

The electronic device may include, but is not limited to, a display device, a backlight device, an antenna device, a sensor device, or a splicing device. The electronic device may be a bendable or flexible electronic device. The display device may be a non-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device. The sensor device may be a device that senses capacitance, light, heat, or ultrasound, but is not limited to these. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited to these. It should be noted that the electronic device may be any combination of the aforementioned arrangements, but is not limited to these arrangements.

It should be noted that the technical solutions provided in the different embodiments below can be replaced, combined, or mixed with each other to constitute another embodiment without violating the spirit of this disclosure.

Figure 1 is a schematic cross-sectional view of an electronic device according to one embodiment of the present disclosure.

In one embodiment of the present disclosure, as shown in FIG1 , an electronic device may include: a substrate 1; and a transistor 2 disposed on the substrate 1. The transistor 2 may include: a gate 21; a semiconductor layer 23 at least partially overlapping the gate 21, the semiconductor layer 23 including a first sub-semiconductor layer 231 and a second sub-semiconductor layer 232, the second sub-semiconductor layer 232 disposed on the first sub-semiconductor layer 231 and comprising indium, gallium, and zinc; a drain 24 electrically connected to the semiconductor layer 23; and a source 25 electrically connected to the semiconductor layer 23. The electronic device disclosed herein can improve the high-voltage resistance of transistor 2 by designing the semiconductor layer 23 into multiple layers, allowing the electronic device to be used in high-voltage operations and reducing the risk of burnout.

In this disclosure, substrate 1 can be a rigid substrate or a flexible substrate. The material of substrate 1 may include quartz, glass, wafer, sapphire, resin, epoxy, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polymethylmethacrylate (PMMA), other plastic materials, or combinations thereof, but this disclosure is not limited thereto. In this disclosure, the materials of the gate 21, drain 24, and source 25 may be the same or different. The materials of the gate 21, drain 24, and source 25 may each include gold, silver, copper, palladium, platinum (Pt), ruthenium (Ru), aluminum, cobalt, nickel, titanium, molybdenum (Mo), manganese, zinc, alloys thereof, or combinations thereof, but this disclosure is not limited thereto.

In one embodiment of the present disclosure, the first semiconductor sub-layer 231 may include indium, gallium, zinc, and oxygen, wherein the atomic ratio of indium, gallium, zinc, and oxygen in the first semiconductor sub-layer 231 is 1:1:1:4. Thus, the atomic percentage of indium is 14%, the atomic percentage of gallium is 14%, the atomic percentage of zinc is 14%, and the atomic percentage of oxygen is 58%. If oxygen is ignored, the atomic percentages of indium, gallium, and zinc are 33%, 33%, and 33%. In one embodiment of the present disclosure, the material of the first semiconductor sub-layer 231 is indium gallium zinc oxide (IGZO). In the present disclosure, the thickness of the first sub-semiconductor layer 231 may be between 800Å and 2000Å, for example, between 800Å and 1800Å, between 800Å and 1500Å, between 800Å and 1200Å, between 1000Å and 2000Å, between 1000Å and 1500Å, or between 1000Å and 1200Å, but the present disclosure is not limited thereto. By designing the thickness of the first sub-semiconductor layer 231 within a specific range, the high-voltage resistance of the transistor 2 can be improved, reducing the risk of electronic component burnout.

In the present disclosure, the atomic ratio of indium, gallium, and zinc in the second semiconductor sub-layer 232 may be 1:3:2-8, for example, 1:3:6-8, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the atomic ratio of indium, gallium, and zinc in the second semiconductor sub-layer 232 may be 1:3:2. In one embodiment of the present disclosure, if oxygen is ignored in the second semiconductor sub-layer 232, the atomic ratio of indium, gallium, and zinc may be 1:3:6. In this way, the atomic percentage of indium may be less than the atomic percentage of gallium, and the atomic percentage of gallium may be less than the atomic percentage of zinc, for example, the atomic percentage of indium is 10%, the atomic percentage of gallium is 30%, and the atomic percentage of zinc is 60%, but the present disclosure is not limited thereto. By carefully designing the atomic ratios of indium, gallium, and zinc in the second semiconductor sub-layer 232, the high-voltage resistance of transistor 2 can be improved, reducing the risk of electronic device burn-in. In one embodiment of the present disclosure, the material of the second semiconductor sub-layer 232 is indium gallium zinc oxide (IGZO). In the present disclosure, the thickness of the second semiconductor sub-layer 232 may be between 800 Å and 2000 Å, for example, between 800 Å and 1800 Å, between 800 Å and 1500 Å, between 800 Å and 1200 Å, between 1000 Å and 2000 Å, between 1000 Å and 1500 Å, or between 1000 Å and 1200 Å, but the present disclosure is not limited thereto. By designing the thickness of the second semiconductor sub-layer 232 within a specific range, the high-voltage resistance of transistor 2 can be improved, reducing the risk of electronic component burnout. In this disclosure, if oxygen is negligible, the atomic percentage of indium in the second semiconductor sub-layer 232 (10%) can be less than the atomic percentage of indium in the first semiconductor sub-layer 231 (33%).

In this disclosure, "the semiconductor layer 23 and the gate 21 at least partially overlap" means that, in the normal direction Z of the substrate 1, the projection of the semiconductor layer 23 on the substrate 1 and the projection of the gate 21 on the substrate 1 at least partially overlap. In one embodiment of this disclosure, in the normal direction Z of the substrate 1, the projection area of the semiconductor layer 23 on the substrate 1 is smaller than the projection area of the gate 21 on the substrate 1.

In the present disclosure, as shown in FIG1 , the transistor 2 may further include: a gate insulating layer 22 disposed on the gate 21. In the present disclosure, the gate insulating layer 22 may be made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or a combination thereof, but the present disclosure is not limited thereto.

In the present disclosure, as shown in FIG1 , the electronic device may further include: an insulating layer 3 disposed on the transistor 2; and a metal layer 4 disposed on the insulating layer 3. The metal layer 4 may be electrically connected to the drain 24 through the insulating layer 3. More specifically, the metal layer 4 may be electrically connected to the drain 24 through a through hole V in the insulating layer 3. In one embodiment of the present disclosure, the insulating layer 3 may be a multi-layer design. For example, as shown in Figure 1, the insulating layer 3 may further include: a first insulating layer 31; a second insulating layer 32 disposed on the first insulating layer 31; and a third insulating layer 33 disposed on the second insulating layer 32. The metal layer 4 may be electrically connected to the drain 24 via a first via V1 in the first insulating layer 31, a second via V2 in the second insulating layer 32, and a third via V3 in the third insulating layer 33. In this disclosure, as shown in FIG1 , the electronic device may further include a conductive layer 5 disposed on the metal layer 4. The conductive layer 5 may be electrically connected to the drain 24 through the metal layer 4.

In the present disclosure, the insulating layer 3 may be an organic material, an inorganic material, or a combination thereof. Suitable inorganic materials may include, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or a combination thereof, but the present disclosure is not limited thereto. Suitable organic materials may include, for example, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polybenzoxazole (PBO), benzocyclobutene (ECB), polyfluoroalkoxy (PFA), epoxy resin, photoresist, polymer, or a combination thereof, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the materials of the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 may be the same or different. For example, the materials of the first insulating layer 31 and the third insulating layer 33 may be inorganic materials, and the material of the second insulating layer 32 may be organic materials, but the present disclosure is not limited thereto.

In this disclosure, the material of the metal layer 4 may include gold, silver, copper, palladium, platinum (Pt), ruthenium (Ru), aluminum, cobalt, nickel, titanium, molybdenum (Mo), manganese, zinc, alloys thereof, or combinations thereof, but this disclosure is not limited thereto. In this disclosure, the material of the conductive layer 5 may be a transparent conductive material, such as indium zinc oxide (IZO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), aluminum zinc oxide (AZO), or combinations thereof, but this disclosure is not limited thereto.

In one embodiment of the present disclosure, the thickness T1 of the drain electrode 24 is less than the thickness T3 of the semiconductor layer 23, and the thickness T2 of the source electrode 25 is less than the thickness T3 of the semiconductor layer 23. More specifically, as shown in FIG1 , in the normal direction Z of the substrate 1 , the drain electrode 24 has a thickness T1, the source electrode 25 has a thickness T2, and the semiconductor layer 23 has a thickness T3, wherein the thickness T1 is less than the thickness T3 (T1<T3), and the thickness T2 is less than the thickness T3 (T2<T3). In one embodiment of the present disclosure, the thickness T1 of the drain electrode 24 refers to the distance between the upper surface 24a and the lower surface 24b of the drain electrode 24 in the normal direction Z of the substrate 1 (e.g., the maximum distance). The thickness T2 of the source electrode 25 refers to the distance between the upper surface 25a and the lower surface 25b of the source electrode 25 in the normal direction Z of the substrate 1 (e.g., the maximum distance). The thickness T3 of the semiconductor layer 23 refers to the total thickness of the first and second sub-semiconductor layers 231 and 232 in the normal direction Z of the substrate 1. More specifically, the thickness T3 of the semiconductor layer 23 is the distance (e.g., the maximum distance) between the upper surface 232a of the second sub-semiconductor layer 232 and the lower surface 231a of the first sub-semiconductor layer 231. It should be noted that the thickness measurement location for any layer should avoid the end region of the layer or the overlapping region with other layers, as the thickness in these regions is generally non-uniform.

In this disclosure, suitable methods can be used to prepare the gate 21, gate insulation layer 22, semiconductor layer 23, drain 24, source 25, insulation layer 3, metal layer 4, and conductive layer 5. Suitable methods include electroplating, chemical plating, chemical vapor deposition, sputtering, coating, photolithography, or a combination thereof, but this disclosure is not limited thereto. The coating method can be, for example, dip coating, spin coating, roller coating, doctor blade coating, spray coating, or a combination thereof, but this disclosure is not limited thereto.

In the present disclosure, although not shown in the figures, the electronic device may further include a counter substrate, a color filter layer, a cover substrate, a touch layer, a display medium layer, a polarizer, a common electrode, other suitable electronic components, other suitable components, or a combination thereof. The electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may, for example, include an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, or a quantum dot light-emitting diode (quantum dot LED), but the present disclosure is not limited thereto. The electronic device disclosed herein is applicable to high-voltage operation. Examples of such electronic devices include backlight devices, splicing devices, antenna devices, sensor devices, liquid crystal displays, organic light-emitting diode displays, sub-millimeter light-emitting diode displays, micro-light-emitting diode displays, cholesterol-free liquid crystal displays, or electrophoretic displays, but the disclosure is not limited thereto.

Figure 2 is a diagram showing the relationship between gate voltage and drain current for an electronic device according to an embodiment of the present disclosure and a comparative example.

The electronic device shown in Figure 1 was used as an example in this experiment. The first semiconductor sub-layer 231 was IGZO with an atomic ratio of indium, gallium, and zinc of 1:1:1. The second semiconductor sub-layer 232 was IGZO with an atomic ratio of indium, gallium, and zinc of 1:3:6. Furthermore, the thickness of the first and second semiconductor sub-layers 231 and 232 was 1000 Å, respectively. The comparative electronic device of this experiment was fabricated using a design similar to that described above. The semiconductor layer 23 of the comparative electronic device was a single-layer design, while the other components were the same as those of the embodiment. Specifically, in the comparative electronic device, the semiconductor layer 23 included only the first sub-semiconductor layer 231 and did not include the second sub-semiconductor layer 232. The first sub-semiconductor layer 231 was IGZO, with an atomic ratio of indium, gallium, and zinc of 1:1:1. The thickness of the first sub-semiconductor layer 231 was 1000 Å.

At an ambient temperature of 25°C, a voltage of 56V was applied to the electronic devices of the embodiment and comparative example, respectively, to observe the relationship between the gate 21 voltage and the drain 24 current of each electronic device. The results are shown in Figure 2. Figure 2 shows that when the electronic device's semiconductor layer 23 is a single-layer design (i.e., the comparative example), the transistor 2 is easily burned out by the high voltage, affecting the reliability of the electronic device. In contrast, when the electronic device's semiconductor layer 23 is a double-layer design (i.e., the embodiment), the transistor 2 can withstand the high voltage, thereby improving the reliability of the electronic device.

FIG3 is a diagram showing the relationship between gate voltage and drain current at different voltages for an electronic device according to an embodiment of the present disclosure.

The electronic device shown in Figure 1 was used in this experiment. The first semiconductor sublayer 231 was IGZO, with an atomic ratio of indium, gallium, and zinc of 1:1:1. The second semiconductor sublayer 232 was IGZO, with an atomic ratio of indium, gallium, and zinc of 1:3:6. Furthermore, the thickness of the first and second semiconductor sublayers 231 and 232 was 1000 Å, respectively.

At an ambient temperature of 25°C, different voltages (e.g., 0.1V, 28V, and 56V) were applied to the electronic device to observe the relationship between the gate 21 voltage and the drain 24 current at different voltages. The results are shown in Figure 3. Figure 3 shows that when the electronic device's semiconductor layer 23 is a double-layer design, the electronic device operates normally when voltages ranging from 0.1V to 56V are applied to transistor 2, with no observed degradation such as transistor 2 burnout.

Figure 4 is an equivalent circuit diagram of a pixel of an electronic device according to one embodiment of the present disclosure.

In one embodiment of the present disclosure, an electronic device may include a plurality of pixel units P disposed on a substrate 1 (as shown in FIG1 ). One of these pixel units P may be designed as, for example, the equivalent circuit diagram shown in FIG4 . As shown in FIG4 , the pixel unit P may include: a transistor TFT; a working capacitor Cw; and a storage capacitor Cst. The structure of the transistor TFT may be as shown in FIG1 as transistor 2 . The transistor TFT is electrically connected to the working capacitor Cw and the storage capacitor Cst, respectively. The first end of the working capacitor Cw is electrically connected to the first end of the storage capacitor Cst, the second end of the working capacitor Cw is electrically connected to an electrode COM1, and the second end of the storage capacitor Cst is electrically connected to another electrode COM2. In one embodiment of the present disclosure, the electrode COM1 and the other electrode COM2 can receive the same common voltage or different voltages.

In one embodiment of the present disclosure, an electronic device may include a plurality of scan lines SL and a plurality of data lines DL disposed on a substrate (as shown in FIG1 ). The scan lines SL and the data lines DL are arranged orthogonally to each other and form a pixel unit P. As shown in FIG4 , scan line signals and data line signals are transmitted to a transistor TFT via the scan lines SL and the data lines DL, respectively, thereby driving the pixel unit P to display an image. More specifically, the scan lines SL are electrically connected to the gate electrode of the transistor TFT to transmit the scan line signal to the transistor TFT, while the data lines DL are electrically connected to the source electrode of the transistor TFT to transmit the data line signal to the transistor TFT. Here, this embodiment illustrates the electronic device as a display device, but the present disclosure is not limited thereto. The electronic device disclosed herein can withstand high voltage operation, but is not limited to display devices.

The above specific embodiments should be interpreted as merely illustrative and not limiting the remainder of this disclosure in any way. Features from different embodiments may be mixed and matched as long as they do not conflict with each other.

1: Substrate 2: Transistor 21: Gate 22: Gate Insulation Layer 23: Semiconductor Layer 231: First Sub-Semiconductor Layer 231a: Lower Surface 232: Second Sub-Semiconductor Layer 232a: Upper Surface 24: Drain 24a: Upper Surface 24b: Lower Surface 25: Source 25a: Upper Surface 25b: Lower Surface 3: Insulation Layer 31: First Insulation Layer 32: Second Insulation Layer 33: Third Insulation Layer 4: Metal Layer 5: Conductive Layer V: Via V1: First Via V2: Second Via V3: Third Via T1, T2, T3: Thickness Z: Normal Direction

Claims (14)

An electronic device comprises: a substrate; and a transistor disposed on the substrate, the transistor comprising: a gate; a semiconductor layer at least partially overlapping the gate, the semiconductor layer comprising a first sub-semiconductor layer and a second sub-semiconductor layer, the second sub-semiconductor layer disposed on the first sub-semiconductor layer and comprising indium, gallium, and zinc; a drain electrically connected to the semiconductor layer; and a source electrically connected to the semiconductor layer; wherein, in the second sub-semiconductor layer, the atomic percentage of indium is less than the atomic percentage of gallium, and the atomic percentage of gallium is less than the atomic percentage of zinc. The electronic device of claim 1, wherein the thickness of the second sub-semiconductor layer is between 800Å and 2000Å. The electronic device of claim 1, wherein in the second semiconductor sub-layer, the atomic ratio of indium, gallium, and zinc is 1:3:6-8. The electronic device of claim 1, wherein the first semiconductor sub-layer comprises indium, and wherein the atomic percentage of indium in the second semiconductor sub-layer is less than the atomic percentage of indium in the first semiconductor sub-layer. The electronic device of claim 1, wherein the first semiconductor sub-layer comprises indium, gallium, and zinc, wherein the atomic ratio of indium, gallium, and zinc in the first semiconductor sub-layer is 1:1:1. The electronic device of claim 1, wherein the thickness of the first sub-semiconductor layer is between 800Å and 2000Å. The electronic device of claim 1 further comprises: an insulating layer disposed on the transistor; and a metal layer disposed on the insulating layer, wherein the metal layer is electrically connected to the drain through the insulating layer. An electronic device comprises: a substrate; and a transistor disposed on the substrate, the transistor comprising: a gate; a semiconductor layer at least partially overlapping the gate, the semiconductor layer comprising a first sub-semiconductor layer and a second sub-semiconductor layer, the second sub-semiconductor layer disposed on the first sub-semiconductor layer and comprising indium, gallium, and zinc; a drain electrically connected to the semiconductor layer; and a source electrically connected to the semiconductor layer; wherein the drain has a thickness less than that of the semiconductor layer, and the source has a thickness less than that of the semiconductor layer. The electronic device of claim 8, wherein the thickness of the second sub-semiconductor layer is between 800Å and 2000Å. The electronic device of claim 8, wherein in the second semiconductor sub-layer, the atomic ratio of indium, gallium, and zinc is 1:3:6-8. The electronic device of claim 8, wherein the first semiconductor sub-layer comprises indium, and wherein the atomic percentage of indium in the second semiconductor sub-layer is less than the atomic percentage of indium in the first semiconductor sub-layer. The electronic device of claim 8, wherein the first semiconductor sub-layer comprises indium, gallium, and zinc, wherein the atomic ratio of indium, gallium, and zinc in the first semiconductor sub-layer is 1:1:1. The electronic device of claim 8, wherein the thickness of the first sub-semiconductor layer is between 800Å and 2000Å. The electronic device of claim 8 further comprises: an insulating layer disposed on the transistor; and a metal layer disposed on the insulating layer, wherein the metal layer is electrically connected to the drain through the insulating layer.