TWI895006B - Memory device and data accessing method thereof - Google Patents

Abstract

A memory device and a data accessing method thereof are provided. The data reading method includes: applying a read voltage on a first read selection word line during a first time period; activating at least one first memory cell string during a first data reading time period in the first time period; applying the read voltage on a second read selection word line during a second time period, wherein the first time period and the second time period are partially overlapped; and activating at least one second memory cell string during a second data reading time period in the second time period, wherein the first data reading time period is not overlapped with the second data reading time period.

Description

Memory device and data access method thereof

The present invention relates to a memory device and a data access method thereof, and in particular to a memory device and a data access method thereof capable of improving data reading rate.

In conventional NAND flash memory devices, to read data from a memory cell block, a read voltage is applied to the selected word line in the memory cell block, and a pass voltage is applied to the unselected word lines in the memory cell block. Once the read and pass voltages stabilize, the memory cell string is turned on to read the data stored in the selected memory cell. To perform the next data read operation, the read voltage and pass voltage must be reapplied to the word lines in the memory cell block to be read. The device then waits for the read voltage and pass voltage to reach a stable value before reading the stored data in the selected memory cell. This means that when continuously reading data from multiple memory cell blocks, the repeated waiting for the read voltage and pass voltage to stabilize consumes a significant amount of waiting time, reducing the operating efficiency of the memory device.

The present invention provides a memory device and a data access method thereof, which can improve the data reading rate.

The data access method of the memory device of the present invention includes: applying a read voltage to a first read selected word line of a first memory cell block in a first time interval; enabling at least a first memory cell string in the first memory cell block in a first data read time interval in the first time interval; applying a read voltage to a second read selected word line of a second memory cell block in a second time interval, wherein the first time interval and the second time interval partially overlap; and enabling at least a second memory cell string in the second memory cell block in a second data read time interval in the second time interval, wherein the first data read time interval and the second data read time interval do not overlap with each other.

Another data access method for a memory device of the present invention includes: distinguishing a plurality of memory cell blocks according to a plurality of word lines of the memory device; setting a first memory cell block and a second memory cell block in the memory cell blocks according to a read order; performing a preset operation on the word lines of the second memory cell block when at least one first memory cell string in the first memory cell block is enabled for a read operation; and, after the read operation on the at least one first memory cell string in the first memory cell block is completed, enabling at least one second memory cell string in the second memory cell block.

The memory device of the present invention includes a plurality of memory cell blocks and a controller. The controller is coupled to the memory cell blocks and is used to execute the data access method described above.

Based on the above, the memory device of the present invention can execute a preset action on the word line of the next memory cell block to be accessed, continuously performing data read operations on different memory cell blocks during partially overlapping first and second time intervals. In this way, the first data read time intervals and second data read time intervals corresponding to different memory cell blocks can be generated in a continuous manner, effectively improving memory cell data read efficiency.

Please refer to Figure 1, which illustrates a flow chart of a data access method for a memory device according to one embodiment of the present invention. In this embodiment, the memory device includes multiple memory cell blocks, each of which has one or more memory cell strings. The multiple memory cells in each memory cell string can be coupled to multiple word lines. In this embodiment, the memory device can be a NAND flash memory device.

In the data access method of this embodiment, in step S110, a controller of a memory device may apply a read voltage to a first read-selected word line of a first memory cell block among a plurality of memory cell blocks during a first time interval. Next, in step S120, the controller may enable at least one first memory cell string in the first memory cell block during a first data read time interval within the first time interval. Consequently, data stored in memory cells corresponding to the first read-selected word line in one or more first memory cell strings in the enabled first memory cell block can be read during the first data read time interval.

Furthermore, in step S130, the controller of the memory device may apply a read voltage to a second read-selected word line of a second memory cell block among the plurality of memory cell blocks during a second time period. The second time period may be different from the first time period. Specifically, the second time period may partially overlap with the first time period, but not completely.

Next, in step S140, the controller may enable at least one second memory cell string in the second memory cell block during a second data read time period within the second time period. Thus, data stored in memory cells corresponding to the second read-selected word line in one or more second memory cell strings in the enabled first memory cell block can be read during the second data read time period.

It is worth noting that in this embodiment, the first data read time period and the second data read time period do not overlap at all. During the first data read time period, the data read from the memory cells corresponding to the first read-selected word line can be transmitted via the corresponding bit lines. During the second data read time period, the data read from the memory cells corresponding to the second read-selected word line can also be transmitted via the corresponding bit lines. In this embodiment, the memory cells corresponding to the first read-selected word line and the memory cells corresponding to the second read-selected word line can correspond to the same bit line.

In this embodiment, when a data read operation on a first memory cell block has not yet been completed during a first time interval, the controller of the memory device can preliminarily apply a read voltage to a second read-selected word line of a second memory cell block during a second time interval that overlaps the first time interval. In this manner, after the data read operation on the memory cells of the first memory cell block executed during the first data read time interval within the first time interval is completed, the controller of the memory device can immediately execute a data read operation on the memory cells of the second memory cell block during the second data read time interval that follows the first data read time interval. In this way, the efficiency of reading data stored in memory cells across multiple memory blocks can be effectively improved.

Please refer to Figure 2, which shows a schematic diagram of a memory device according to an embodiment of the present invention. Memory device 200 includes a plurality of memory cell blocks B1-B3 and a controller 210. Controller 210 is coupled to memory cell blocks B1-B3. In this embodiment, each memory cell block B1-B3 includes a plurality of memory cell strings (e.g., memory cell string MS1). The memory cell strings in each memory cell block B1-B3 are respectively coupled to a plurality of bit lines BL0-BLM. The bit lines BL0-BLM are also respectively coupled to a plurality of page buffers (PB) 221-22M.

Multiple memory cells in memory cell block B1 are coupled to word lines WL10-WL1N; multiple memory cells in memory cell block B2 are coupled to word lines WL20-WL2N; and multiple memory cells in memory cell block B3 are coupled to word lines WL30-WL3N. Multiple memory cell strings in memory cell blocks B1, B2, and B3 correspond to each other and are coupled to bit lines BL0-BLM, respectively. In other words, the three corresponding memory cell strings in memory cell blocks B1, B2, and B3 can be coupled to the same shared bit line.

Regarding the implementation details of memory cell string MS1, memory cell string MS1 includes multiple memory cells MC connected in series, and a memory cell string select switch SS1 and a ground select switch GS1 coupled to both ends of memory cell string MS1. The control terminals of the memory cells MC are coupled to multiple word lines WL10 to WL1N, respectively. The ground select switch GS1 is coupled between the multiple memory cells MC and the reference ground terminal GND. The memory cell string select switch SS1 is coupled between the memory cells MC and the corresponding bit line BL0. The ground select switch GS1 is controlled by a control signal GSL1, while the memory cell string select switch SS1 is controlled by a control signal SSL1.

In this embodiment, the controller 210 can be a processor with computing capabilities, or the controller 210 can be any form of digital circuit, or a hardware circuit designed using a hardware description language (HDL) or any other digital circuit design method known to those skilled in the art, and implemented using a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC).

For details on the data read operation of memory device 200, please refer to Figures 2 and 3 , where Figure 3 illustrates waveforms of the memory device according to an embodiment of the present invention. In Figure 3 , controller 210 of memory device 200 may first perform a data read operation on memory cell block B1. Furthermore, during a first time period TP1, controller 210 may apply a read voltage Vread to a selected read word line in memory cell block B1 that is selected for data read, and apply a pass voltage Vpass to unselected word lines other than the selected read word line.

Then, in the first time period TP1, after the read voltage Vread and the pass voltage Vpass have risen to a stable voltage value, the controller 210 may apply control signals SSL1 and GSL1 to the ground selection switch and the memory cell string selection switch in the memory cell string in the memory cell block B1, respectively, in the first read time period tR1, and through the control signals SSL1 and GSL1 having relatively high voltage values, the ground selection switch and the memory cell string selection switch in the memory cell string in the memory cell block B1 are turned on, and the memory cell string in the memory cell block B1 is turned on.

In this embodiment, the pass voltage Vpass can be greater than the read voltage Vread. When the memory cell strings in memory cell block B1 are turned on, the memory cells in memory cell block B1 that receive the pass voltage Vpass (unselected memory cells) are fully turned on without affecting the current on the corresponding bit lines. The memory cells that receive the read voltage Vread (selected memory cells) can generate current on the bit lines based on the stored data. Therefore, by sensing the current on bit lines BL0-BLM, the memory device 200 can determine the data stored in the selected memory cells corresponding to the multiple memory cell strings in memory cell block B1.

It is worth noting that, in this embodiment, the second time period TP2 partially overlaps with the first time period TP1, and the second time period TP2 may also partially overlap with the first read time period tR1 within the first time period TP1. That is, while the data read operation of the memory cell block B1 is being executed, the controller may, during the second time period TP2, apply a read voltage Vread to the read-selected word line in the memory cell block B2 that is selected for data read, and apply a pass voltage Vpass to unselected word lines other than the read-selected word line.

As shown in Figure 3, the read voltage Vread and pass voltage Vpass corresponding to the second memory cell block can be pre-applied to the corresponding word lines in memory cell block B2 while memory cell block B1 is performing a data read operation, thereby performing a preset operation on the word lines of memory cell block B1. Furthermore, before the completion of the first read time period tR1, the read voltage Vread and pass voltage Vpass on each word line in memory cell block B2 can reach a stable state. In this way, after the first read time interval tR1 is completed, the controller 210 can provide control signals SSL2 and GSL2 with relatively high voltage values in the second read time interval tR2 to turn on the ground selection switch and the memory cell string selection switch in the memory cell string in the memory cell block B2, and perform the data reading operation of the memory cells in the memory cell block B2.

In this embodiment, the second read time period tR2 may occur after the first read time period tR1. The second read time period tR2 may be adjacent to the first read time period tR1.

It is worth noting that in this embodiment of the present invention, the controller 210 of the memory device 200 may continue to read data from the memory cells in the memory cell block B2 before continuing to read data from the memory cells in the memory cell block B3. The controller 210 may pre-provide a read voltage Vread and a pass voltage Vpass to each word line of the memory cell block B3 during a third time period TP3 that partially overlaps with the second time period TP2 and the second read time period tR2. In a third read time period tR3 following the second read time period tR2, control signals SSL3 and GSL3 having relatively high voltage values are provided to turn on the ground select switch and the memory cell string select switch in the memory cell string in the memory cell block B3, thereby performing a data read operation on the memory cells in the memory cell block B3.

As can be seen from the above-described embodiments, the memory device 200 of the present invention can quickly switch between different memory cell blocks B1-B3 to perform data read operations. Furthermore, by providing the read voltage Vread and the pass voltage Vpass to the next memory cell block to be read before the data read operation of the previous block is completed, the waiting time for the read voltage Vread and the pass voltage Vpass to rise to a stable state is effectively reduced, thereby improving the data read rate of the memory device 200.

In the embodiment of FIG. 3 , after performing a data read operation on memory cell block B3, controller 210 may subsequently perform data read operations on memory cell blocks B1, B2, or other memory cell blocks not shown. In this embodiment of the present invention, controller 210 may sequentially perform data read operations on any two different memory cell blocks. FIG. 3 illustrates sequentially performing data read operations on memory cell blocks B1 through B3. This is for illustrative purposes only and is not intended to limit the scope of the present invention.

It is worth noting that the data reading operation of the embodiment of the present invention can also be applied to other types of memory devices and is not limited to being applied to NAND flash memory devices.

Furthermore, in other embodiments of the present invention, a set of demand data can be split into multiple data pages and pre-stored in different memory cell blocks in a predetermined order. Thus, when data is to be read from the demand data, the embodiment of FIG. 3 of the present invention can be applied to quickly read data from each memory cell block based on the storage order of the multiple data pages. This allows for rapid data retrieval, improving system performance.

In summary, the memory device of the present invention pre-applies the corresponding read voltage and pass voltage to the word line of the next memory cell block to be read, while the data read operation of the current memory cell block is in progress. This eliminates the waiting time for the read voltage and pass voltage on the word line to stabilize during consecutive memory cell block data read operations, effectively improving memory cell data read efficiency.

200: Memory device 210: Controller 221-22M: Page buffer B1-B3: Memory cell block BL0-BLM: Bit line GND: Ground reference GS1: Ground select switch GSL1-GSL3, SSL1-SSL3: Control signals MC: Memory cell MS1: Memory cell string S110-S140: Step SS1: Memory cell string select switch TP1-TP3, tR1-tR3: Time interval Vpass: Pass voltage Vread: Read voltage WL10-WL3N: Word line

Figure 1 illustrates a flow chart of a data access method for a memory device according to an embodiment of the present invention. Figure 2 illustrates a schematic diagram of a memory device according to an embodiment of the present invention. Figure 3 illustrates an operational waveform diagram of the memory device according to an embodiment of the present invention.

S110~S140: Steps

Claims (19)

A data access method for a memory device comprises: Applying a read voltage to a first read-selected word line of a first memory cell block during a first time period; Enabling at least a first memory cell string in the first memory cell block during a first data read time period within the first time period; Applying the read voltage to a second read-selected word line of a second memory cell block during a second time period, wherein the first time period and the second time period partially overlap; and At least one second memory cell string in the second memory cell block is enabled in a second data read time interval within the second time interval, wherein the first data read time interval and the second data read time interval do not overlap with each other. The data access method of claim 1, wherein the first data read time interval is adjacent to the second data read time interval. The data access method of claim 1 further comprises: Applying a pass voltage to a plurality of first unselected word lines of the first memory cell block during the first time period; and Applying the pass voltage to a plurality of second unselected word lines of the second memory cell block during the second time period. The data access method of claim 3, wherein the pass voltage is greater than the read voltage. The data access method of claim 1, wherein the step of enabling the at least one first memory cell string in the first memory cell block comprises: Raising a first control signal and a second control signal during the first data read time period to respectively enable a ground select switch and a memory cell string select switch of the at least one first memory cell string. The data access method of claim 1, wherein the step of enabling the at least one second memory cell string in the second memory cell block comprises: Raising a first control signal and a second control signal during the second data read time period to respectively enable a ground select switch and a memory cell string select switch of the at least one second memory cell string. The data access method of claim 1 further comprises: Applying the read voltage to a third read-selected word line of a third memory cell block during a third time period, wherein the second time period and the third time period partially overlap; and Enabling at least one third memory cell string in the third memory cell block during a third data read time period within the third time period, wherein the first read time period, the second data read time period, and the third data read time period do not overlap. A memory device comprises: a plurality of memory cell blocks; and a controller coupled to the memory cell blocks and configured to: apply a read voltage to a first read-selected word line of a first memory cell block during a first time period; enable at least a first memory cell string in the first memory cell block during a first data read time period within the first time period; apply the read voltage to a second read-selected word line of a second memory cell block during a second time period, wherein the first time period and the second time period partially overlap; and At least one second memory cell string in the second memory cell block is enabled in a second data read time interval within the second time interval, wherein the first data read time interval and the second data read time interval do not overlap with each other. The memory device of claim 8, wherein the first data read time interval is adjacent to the second data read time interval. The memory device of claim 8, wherein the controller is further configured to: apply a pass voltage to a plurality of first unselected word lines of the first memory cell block during the first time period; and apply the pass voltage to a plurality of second unselected word lines of the second memory cell block during the second time period. The memory device of claim 10, wherein the pass voltage is greater than the read voltage. The memory device of claim 8, wherein the at least one first memory cell string includes a ground select switch and a memory cell string select switch, and the controller is further configured to: Raise a first control signal and a second control signal during the first data read time period to respectively turn on the ground select switch and the memory cell string select switch of the at least one first memory cell string. The memory device of claim 8, wherein the at least one second memory cell string includes a ground select switch and a memory cell string select switch, and the controller is further configured to: Raise a first control signal and a second control signal during the second data read time period to respectively turn on the ground select switch and the memory cell string select switch of the at least one second memory cell string. The memory device of claim 8, wherein the controller is further configured to: apply the read voltage to a third read-selected word line of a third memory cell block during a third time period, wherein the second time period and the third time period partially overlap; and enable at least a third memory cell string in the third memory cell block during a third data read time period within the third time period, wherein the first read time period, the second data read time period, and the third data read time period do not overlap. The memory device of claim 8, wherein the at least one first memory cell string and the at least one second memory cell string are coupled to at least one first bit line and at least one second bit line, respectively. The memory device of claim 8, wherein the at least one first memory cell string and the corresponding at least one second memory cell string share the same common bit line. The memory device of claim 16 further comprises: At least one page buffer coupled to the common bit line A data access method for a memory device comprises: dividing a plurality of memory cell blocks into a plurality of word lines corresponding to the memory device; setting a first memory cell block and a second memory cell block in the memory cell blocks according to a read order; performing a preset operation on the word lines of the second memory cell block when at least one first memory cell string in the first memory cell block is enabled for a read operation; enabling at least one second memory cell string in the second memory cell block after the read operation on the at least one first memory cell string in the first memory cell block is completed; splitting requested data into a plurality of data pages; and The data pages are sequentially stored in the memory cell blocks in the memory device. The data access method of claim 18, wherein the step of performing a preset action on the word lines of the second memory cell block comprises: applying a read voltage to a read-selected word line in the second memory cell block; and applying a pass voltage to a plurality of unselected word lines in the second memory cell block.