TWI894759B - Display device and method for manufacturing the same - Google Patents

Abstract

A display device and a method for manufacturing the same. The display device may include: a substrate having: first and second subpixels each including a respective emitting area; and a non-emitting area surrounding the emitting areas; a respective first electrode in each of the first and second subpixels; a bank, the bank having a respective bank hole in each of the emitting areas and a bank trench in the non-emitting area; a first spacer on the bank; a second spacer in the bank trench; an emitting layer on the first electrodes and the bank trench and including a plurality of stacks and at least one charge generating layer between the plurality of stacks; and a second electrode on the emitting layer.

Description

Display device and manufacturing method thereof

The present invention relates to a display device, such as a light-emitting diode display device, and a method for manufacturing the same. In particular, the present invention relates to a display device (such as a light-emitting diode display device) having a structure for reducing or preventing leakage current between adjacent sub-pixels and a method for manufacturing the same.

Recent display devices that display information and interact with users viewing the information are required to come in a variety of sizes, shapes, and functions.

Display devices may include liquid crystal display (LCD) devices, electrophoretic display (EPD) devices, and light emitting diode (LED) display devices.

LED displays are emissive and, unlike LCDs, do not require an additional light source, allowing them to be lightweight and thin. Furthermore, due to their low-voltage drive, LED displays offer advantages in power consumption and superior color display, response speed, viewing angle, and contrast. Therefore, LED displays are being researched as next-generation displays.

Although the organic light-emitting diode (OLED) display device can be exemplarily described as an LED display device, the material of the light-emitting layer is not limited thereto.

LED displays display information by lighting up multiple pixels with a light-emitting layer. LED displays can be categorized into active matrix and passive matrix types based on the method used to drive the pixels.

Active matrix LED displays display images by controlling the current flowing through light-emitting diodes using thin-film transistors (TFTs).

An LED display device has an anode, a light-emitting layer, and a cathode. When voltage is applied to the anode and cathode, holes in the anode and electrons in the cathode migrate to the light-emitting layer. The holes and electrons combine in the light-emitting layer to form excitons, and when the excitons transition from their excited state to the ground state, light is emitted.

To provide high-quality image information, the resolution of LED display devices has gradually increased. As the resolution increases, the gap distance between adjacent sub-pixels decreases. As a result, image information is distorted due to leakage current in the lateral direction between adjacent sub-pixels.

Although various methods for preventing side leakage current have been proposed to achieve high-resolution LED display devices, they are still insufficient and need to be developed.

Therefore, embodiments of the present invention are directed to a light-emitting diode display device that substantially eliminates one or more problems due to limitations and disadvantages of the prior art.

An object of the present invention is to provide a light-emitting display device having a bank trench including at least one second spacer between adjacent sub-pixels. This device reduces or prevents an increase in side leakage current when the gap distance between adjacent sub-pixels decreases.

Additional features and advantages will be set forth in the description that follows, and in part will be apparent to those skilled in the art or may be learned by practice of the present invention. These and other advantages of the present invention may be realized or obtained by the structures particularly pointed out in the description, or by structures derived therefrom, in the claims, and in the accompanying drawings.

To achieve these and other advantages embodied and broadly described herein and consistent with the objectives of the present invention, a display device may include: a substrate having a first subpixel and a second subpixel, each including a light-emitting region, and a non-light-emitting region surrounding the light-emitting region; a first electrode located in each of the first subpixel and the second subpixel; a bank having a bank hole located in each of a plurality of light-emitting regions and a bank trench located in the non-light-emitting region; a first spacer located on the bank; a second spacer located in the bank trench; a light-emitting layer located on the first electrode and the bank trench and including a plurality of stacks and at least one charge generation layer between the plurality of stacks; and a second electrode located on the light-emitting layer.

In another aspect of the present invention, a display device may include: a substrate including a display area having a plurality of sub-pixels, a non-luminescent area between the plurality of sub-pixels, and a non-luminescent area adjacent to the display area; a first electrode located at each of the plurality of sub-pixels; a bank that divides the plurality of sub-pixels; a luminescent layer located on the first electrode; a second electrode located on the luminescent layer; and a cutout in the luminescent layer between two adjacent sub-pixels.

According to yet another embodiment of the present invention, a method for manufacturing a display device may include: forming a plurality of first electrodes separated from each other on a substrate; forming a bank on the substrate on which the plurality of first electrodes are formed; forming a bank hole in the bank to expose a portion of each of the plurality of first electrodes, and forming a bank trench between adjacent first electrodes in the bank; forming a second spacer in the bank trench; forming a light-emitting layer in the second spacer and the bank trench, the light-emitting layer including a plurality of stacks and at least one charge generation layer between the plurality of stacks; and forming a second electrode on the light-emitting layer.

It should be understood that the foregoing general description and the following detailed description are merely illustrative and exemplary and are intended to provide further explanation of the invention as claimed without limiting the scope of the claims.

100:LED display device

110:Substrate

112: Gate drive unit

114: Pad

120: Buffer layer

130: First insulating layer

140: Second insulating layer

150: Passivation layer

160: Planarization layer

161: First planarization layer

162: Second planarization layer

170: Connecting electrodes

200: Thin Film Transistor

210: Semiconductor pattern

230: Gate electrode

250: Source electrode

270: Drain electrode

310: First electrode

320: Embankment

330: First partition

340: Second partition

340a: First partition

340b: Second spacer

340c: Third partition

350: Luminous layer

351: First Stack

351B: First blue luminescent material layer

351G: First green luminescent material layer

351R: First red luminescent material layer

351-A: Hole injection layer

351-B: First hole transport layer

351-C: First luminescent material layer

351-D: First electron transport layer

352: Charge Generation Layer

352-n: N-type charge generation layer

352-p: P-type charge generation layer

353: Second stack

353B: Second blue luminescent material layer

353G: Second green luminescent material layer

353R: Second red luminescent material layer

353-A: Second hole transport layer

353-B: Second luminescent material layer

353-C: Second electron transport layer

353-D: Electron injection layer

360: Second electrode

400: Packaging layer

410: First packaging layer

420: Second packaging layer

430: Third packaging layer

500: Touch sensor layer

510: Touch buffer layer

520: First touch connection electrode

530: Touch insulation layer

540_C: Second touch connection electrode

540_R: First contact electrode

550: Touch planarization layer

AA: Display Area

BA: Bend Area

BH: Bank Hole

BT: Bank trench

DAM: Dam

EA: Luminous Area

ESD: Electrostatic Discharge Circuit

H1, H2, H3, H4: Height

MUX: Multiplexer

NA: Non-display area

NEA: Non-Emitting Area

P: Pixels

PCD: Crack Detection Circuit

PH: Spacer pattern hole

RL: Residual layer

SP_1: First subpixel

SP_2: Second sub-pixel

SP_3: Third sub-pixel

VDD: high voltage line

VSS: Low voltage line

II ' : line

The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this document. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings: FIG1 is a plan view of a LED display device according to an embodiment of the present invention; FIG2 is a plan view of a sub-pixel and a bank trench with a second spacer of the LED display device according to an embodiment of the present invention; FIG3 is a schematic cross-sectional view of the LED display device according to an embodiment of the present invention; FIG4A to FIG4D are schematic cross-sectional views of a manufacturing process of the LED display device according to an embodiment of the present invention; and FIG5 is a schematic view of a light-emitting layer of the LED display device according to an embodiment of the present invention.

The advantages, features, and implementations of the present invention are illustrated by the following embodiments with reference to the accompanying drawings. However, the present invention may be embodied in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make this invention thorough and complete, to assist those skilled in the art in fully understanding the scope of the invention. Furthermore, the scope of protection of the present invention is defined by the claims and their equivalents.

The shapes, sizes, proportions, angles, and quantities disclosed in the drawings used to describe the embodiments of the present invention are merely examples. Therefore, the present invention is not limited to the descriptions in the drawings. Unless otherwise specified, similar reference numerals generally refer to similar elements throughout the text.

In the following description, detailed descriptions of related known functions or configurations may unnecessarily obscure the features or aspects of the present invention, and the detailed descriptions of such known functions or configurations may be omitted or may be briefly described.

Unless terms such as "only" are used, when "include," "have," "comprises," etc. are used in this description, one or more other elements may be added. Unless otherwise specified, elements described in the singular may include plural elements, and vice versa.

When explaining a component, even if the error or tolerance is not explicitly described, the component is interpreted as including the error or tolerance.

When describing positional relationships, for example, when a positional relationship is described between two components using terms such as "on," "above," "below," "above," "below," "next to," or "next to," one or more other components may be positioned between the two components, unless further qualifying terms such as "immediately," "directly," or "proximally" are used. For example, when an element or layer is described as being "on" another element or layer, a third layer or element may be interposed therebetween.

Although terms such as "first," "second," "A," "B," "(a)," and "(b)" may be used when describing elements of the present invention, these elements should not be limited by these terms, as they are not intended to define a particular order or precedence. These terms may be used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element without departing from the scope of the present invention.

The features of the various embodiments of the present invention may be coupled or combined with each other in part or in whole. They can be connected and technically operated in various ways as fully understood by those skilled in the art. These embodiments can be implemented independently or in conjunction with each other in various combinations.

Herein, LED display devices according to various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Figure 1 shows a plan view of a light-emitting diode display device according to an embodiment of the present invention.

In FIG1 , a light-emitting diode (LED) display device 100 according to an embodiment of the present invention may include various components for generating signals or driving multiple sub-pixels SP_1, SP_2, and SP_3 in a display area AA. For example, the LED display device 100 may include at least one driver circuit for controlling the display panel. The driver circuit for controlling or driving the sub-pixels SP_1, SP_2, and SP_3 may include a gate driver unit 112, a data signal line, a multiplexer MUX, an electrostatic discharge (ESD) circuit, a high-voltage line VDD, a low-voltage line VSS, and a frequency conversion circuit. The LED display device 100 may further include components beyond those used to drive the sub-pixels SP_1, SP_2, and SP_3. For example, the LED display device 100 may include components that provide touch sensing, user authentication (e.g., fingerprint recognition), multi-level pressure sensing, and tactile feedback. These components may be located in the non-display area NA or in external circuitry connected to the interface.

The substrate 110 may include a display area AA and a non-display area NA. In the display area AA of the substrate 110, multiple pixels P are disposed and an image is displayed. In the non-display area NA of the substrate 110, no image is displayed. For example, the non-display area NA may be considered a border area, but this is not limited to such a border area. The non-display area NA may be disposed adjacent to the display area AA and may be disposed outside the display area AA. Alternatively, the non-display area NA may be disposed to surround all or a portion of the display area AA. The non-display area NA may be an area where the multiple sub-pixels SP_1, SP_2, and SP_3 are not disposed, but this is not limited to such a border area.

Each pixel P in the display area AA may include multiple sub-pixels SP_1, SP_2, and SP_3. Each sub-pixel SP_1, SP_2, and SP_3 is an independent light-emitting unit. The multiple sub-pixels SP_1, SP_2, and SP_3 may include, but are not limited to, red sub-pixels SP_R, green sub-pixels SP_G, blue sub-pixels SP_B, and/or white sub-pixels.

Sub-pixels SP_1, SP_2, and SP_3 each include a light-emitting diode and a sub-pixel circuit. For example, sub-pixels SP_1, SP_2, and SP_3 may each include a light-emitting diode for displaying an image and a sub-pixel circuit for driving or controlling the light-emitting diode.

Each subpixel SP may include multiple transistors, one or more capacitors, and multiple wires. For example, each subpixel SP may have a 2T1C structure including two transistors and one capacitor. Alternatively, each subpixel SP may have one of a 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, and 8T2C structure.

The non-display area NA is where multiple lines and multiple driver circuits for driving the multiple sub-pixels SP_1, SP_2, and SP_3 in the display area AA are located. For example, multiple integrated circuits (ICs) and driver circuits such as gate driver unit 112 and data driver unit can be located in the non-display area NA.

In Figure 1, while the non-display area NA surrounds the display area AA in a rectangular shape, the shapes and configurations of the adjacent display area AA and non-display area NA are not limited thereto. The display area AA and non-display area NA may have shapes corresponding to the design of an electronic device incorporating the LED display device 100. The display area AA and non-display area NA may have a circular shape corresponding to a watch used in a wearable device, or may have a free-form form suitable for a dashboard. For example, the display area AA may have one of the following shapes: a pentagon, a hexagon, an octagon, a circle, and an ellipse, but is not limited thereto.

The non-display area NA may include a curved area BA. The curved area BA may be disposed between the display area AA and the pad 114 of the non-display area NA. The curved area BA may be an area where a connecting line portion is disposed.

The bending area BA may be a portion of the substrate 110 that is bent to provide the pad 114 and an external module bonded to the pad 114 beyond the rear surface of the substrate 110. For example, because the bending area BA bends toward the rear surface of the substrate 110, the external module bonded to the pad 114 of the substrate 110 moves toward the rear surface of the substrate 110 and is not discernible in a plan view of the substrate 110. Although FIG. 1 may depict the display device 100 in a plan view before the bending area BA is bent, such that the pad 114 is visible in FIG. However, after the bending area BA is bent, the pad 114 may be disposed on the rear side of the display device 100, such that it is no longer visible from the front side of the display device 100. Furthermore, because the curved area BA is curved, the size of the non-display area NA is reduced in a plan view of the substrate 110, resulting in a narrow bezel. While the curved area BA is located within the non-display area NA of the LED display device 100, this is not limiting. For example, the curved area BA can be located within the display area AA, and the display area AA can be curved in various directions, allowing the curved area BA within the display area AA to have similar functionality to the curved area BA within the non-display area NA.

The pad 114 is disposed on one side of the non-display area NA. The pad 114 is a metal pattern bonded to an external module, such as a flexible printed circuit board (FPCB) or a chip-on-film (COF). Although the pad 114 is disposed adjacent to the substrate 110, the shape and configuration of the pad 114 are not limited thereto.

A gate driver unit 112 that provides a gate signal to a thin film transistor (TFT) may be disposed on the other side of the non-display area NA. The gate driver unit 112 may include multiple gate driver circuits, and the multiple gate driver circuits may be formed directly on the substrate 110. For example, the gate driver unit 112 formed directly on the substrate 110 may have a gate-in-panel (GIP) type.

The gate driver unit 112 can be disposed between the dam DAM of the display area AA and the non-display area NA.

The high-voltage line VDD, the low-voltage line VSS, the multiplexer MUX, the electrostatic discharge circuit ESD, and a plurality of connection lines can be disposed between the pad 114 of the display area AA and the non-display area NA.

The high-voltage line VDD, the low-voltage line VSS, the multiplexer MUX, and the electrostatic discharge circuit ESD can be located between the display area AA and the bending area BA.

Multiple connection lines may be provided in the non-display area NA. For example, the connection lines may be provided in the curved area BA of the non-display area NA, where the substrate 110 is curved. The connection lines may be used to transmit signals (voltages) from an external module bonded to the pad 114 to the display area AA or circuit cells such as the gate driver unit 112. For example, multiple signals such as a signal for driving the gate driver unit 112, a data signal, a high-level voltage, and a low-level voltage may be transmitted via the connection lines.

The dam is placed in the non-display area NA to surround all or part of the display area AA. The dam can be placed adjacent to the display area AA or outside of it.

Dams can be placed around the display area AA to regulate the flow of organic materials used in the second encapsulation layer located above the LED. One or more dams can be provided.

The dam DAM can be set in the display area AA, the high-voltage line VDD, the low-voltage line VSS, the multiplexer MUX, and the electrostatic discharge circuit ESD.

The crack detection circuit PCD can be disposed in the non-display area NA of the substrate 110.

The crack detection circuit PCD may be disposed between the end portion of the substrate 110 and the dam DAM. Alternatively, the crack detection circuit PCD may be disposed below the dam DAM to partially overlap with the dam DAM.

FIG2 is a plan view showing a sub-pixel of a light-emitting diode display device and a bank trench with a second spacer according to an embodiment of the present invention.

In Figure 2, substrate 110 may include a light-emitting area EA and a non-light-emitting area NEA surrounding the light-emitting area EA. Multiple light-emitting areas EA may be provided, separated from each other. The non-light-emitting area NEA may be provided to surround the light-emitting area EA.

The light-emitting area EA is an area from which light is emitted to the outside. As shown in FIG3 , the light-emitting area EA may be an area without the bank 320.

The non-light-emitting area NEA is a region where light is not emitted to the outside. As shown in FIG3 , the non-light-emitting area NEA may be a region where a bank 320 is provided.

Each of the multiple pixels P in the display area AA may include a first sub-pixel SP_1, a second sub-pixel SP_2, and a third sub-pixel SP_3.

Each of the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 may include a light-emitting area EA.

Each pixel P may include a sub-pixel that emits light corresponding to a different color. For example, each pixel P may include a first sub-pixel SP_1, a second sub-pixel SP_2, and a third sub-pixel SP_3 corresponding to different colors.

Alternatively, each pixel P may include multiple sub-pixels that emit light corresponding to different colors. For example, each pixel P may include a first sub-pixel SP_1, two second sub-pixels SP_2, and a third sub-pixel SP_3 corresponding to different colors.

The first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 may have one of the following shapes: rectangle, pentagon, hexagon, octagon, circle, and ellipse, but are not limited thereto.

The first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 can emit light corresponding to different colors. For example, the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 can emit light corresponding to at least one of red, green, and blue.

The third subpixel SP_3 may be larger than the first subpixel SP_1 and the second subpixel SP_2. As shown in FIG2 , the third subpixel SP_3 may be larger than the first subpixel SP_1 and larger than the second subpixel SP_2.

In a LED display device, as the resolution increases, the spacing between the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 decreases.

The LED display device 100 may include a light-emitting layer comprising multiple stacks (light-emitting units) and a charge generation layer between the stacks. The charge generation layer may adjust the charge balance between the stacks.

The charge generation layer may include multiple layers, including a first charge generation layer and a second charge generation layer. Each of the first and second charge generation layers may include a negative charge generation layer and a positive charge generation layer. The first charge generation layer may include an alkali metal such as lithium (Li), sodium (Na), potassium (K), and cesium (Cs), or an organic layer doped with one of magnesium (Mg), strontium (Sr), barium (Ba), and radium (Ra).

Metal in the charge generation layer can cause side leakage current (LLC). For example, when a sub-pixel is driven, adjacent sub-pixels may emit weak light due to leakage current in the lateral direction between adjacent sub-pixels, and image information may be distorted.

The first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3 may have different driving voltages for emitting light.

For example, the driving voltage for emitting blue light may be greater than the driving voltage for emitting red light or for emitting green light.

When the third subpixel SP_3 is driven, adjacent subpixels may be driven to emit weak light. Electrons from the third subpixel SP_3 are transferred to the adjacent subpixels via the charge generation layer continuously disposed between adjacent subpixels. As a result, the third subpixel SP_3 may have a state similar to that of its off-state adjacent subpixels and may emit weak light. This reduces color purity and color reproducibility. Specifically, weak light may be generated in relatively low grayscale.

Side leakage current can be reduced or minimized by forming a bank trench BT in the non-light emitting area NEA with a second spacer 340 disposed between adjacent sub-pixels.

Although the second spacer 340 is positioned to surround each of the first, second, and third sub-pixels SP_1, SP_2, and SP_3 in FIG2 , in another embodiment, the second spacer 340 may be positioned to surround some of the first, second, and third sub-pixels SP_1, SP_2, and SP_3. In some examples, the second spacer 340 may be positioned to surround the third sub-pixel SP_3, which emits only blue light. Because these sub-pixels have the highest driving voltage, there is a greater risk of leakage current from these sub-pixels to adjacent sub-pixels.

The light-emitting layer 350 is disposed on the first electrode 310 and the bank trench BT having the second spacer 340. In some embodiments, because the light-emitting layer 350 between adjacent sub-pixels is cut by the bank trench BT having the second spacer 340, the transmission of electrons in the light-emitting layer 350 of a sub-pixel to the adjacent sub-pixel is minimized.

Since side leakage current is reduced or minimized between adjacent sub-pixels, degradation in discrimination between adjacent sub-pixels in relatively low grayscale is reduced, and color reproduction is improved.

Although the second spacer 340 and the bank trench BT are disposed within the first, second, and third sub-pixels SP_1, SP_2, and SP_3 in FIG2 , the second spacer 340 and the bank trench BT may be omitted between adjacent sub-pixels in another embodiment. In other words, each instance of the second spacer 340 and the bank trench BT may be disposed between a pair of adjacent sub-pixels, between multiple pairs of adjacent sub-pixels, or between all pairs of adjacent sub-pixels.

The first spacer 330 can be configured to have a predetermined gap distance between the plurality of sub-pixels SP_1, SP_2, and SP_3. For example, the first spacer 330 can have a predetermined gap distance between the plurality of sub-pixels SP_1, SP_2, and SP_3 and can be surrounded by the plurality of sub-pixels SP_1, SP_2, and SP_3. In FIG2 , although one first spacer 330 is surrounded by four sub-pixels SP_1, SP_2, and SP_3, this is not a limitation. The first spacer 330 can provide gaps between the plurality of sub-pixels SP_1, SP_2, and SP_3 and can be separated from the plurality of sub-pixels SP_1, SP_2, and SP_3 by their respective gaps. Herein, the first spacer 330 may be referred to as an on-bank spacer, and the second spacer 340 may be referred to as an intra-bank spacer. It should be understood that "first" and "second" are merely used as labels to indicate the spacers and should not be considered limiting.

Sub-pixels emitting light of the same color can be arranged symmetrically with respect to the first spacer 330. For example, the second sub-pixel SP_2 can be arranged to face the first spacer 330. The first spacer 330 can be arranged in the central area of the sub-pixels emitting light of the same color.

The first spacer 330 can reduce the space between the substrate 110 having the light-emitting layer 350 and the upper substrate (encapsulation layer 400) to minimize cracking of the LED display device 100 caused by external impact.

Furthermore, the first spacers 330 can protect the light-emitting layer 350. For example, the light-emitting layer 350 can be formed using a fine metal mask (FMM), which can bend under weight. Since the fine metal mask contacts the first spacers 330, deterioration or distortion of the bank 320 caused by the contact between the fine metal mask and the bank 320 is prevented.

FIG3 is a schematic cross-sectional view of a light-emitting diode display device according to an embodiment of the present invention, and FIG4A to FIG4D are schematic cross-sectional views of a manufacturing process of the light-emitting diode display device according to an embodiment of the present invention. FIG3 is taken along line II ′ in FIG2.

In FIG3 , substrate 110 supports various components of LED display device 100. Substrate 110 may include flexible glass or plastic materials.

For example, substrate 110 may include one of polyimide (PI), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyethersulfone, and polycarbonate, but is not limited thereto.

When the substrate 110 includes polyimide (PI), the substrate 110 may include two PI layers or two PI layers and an inorganic layer located between the two PI layers.

The buffer layer 120 is disposed on the entire substrate 110.

The buffer layer 120 may include an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx). The buffer layer 120 may also include an organic insulating material, but is not limited thereto.

The buffer layer 120 may include a single layer or multiple layers of silicon nitride (SiNx) and silicon oxide (SiOx). When the buffer layer 120 includes multiple layers, the silicon oxide (SiOx) layers and the silicon nitride (SiNx) layers may be alternately arranged.

The buffer layer 120 may be omitted depending on the type and material of the substrate 110 and the structure and type of the thin film transistor.

The thin film transistor 200 may be disposed on the buffer layer 120. The thin film transistor 200 may include a semiconductor pattern, a gate electrode, a source electrode, and a drain electrode.

Although the driving thin-film transistor is depicted as thin-film transistor 200 in FIG3 and FIG4A through FIG4D , the LED display device 100 may further include another thin-film transistor, such as a switching thin-film transistor. Although thin-film transistor 200 has a top-gate structure in FIG3 and FIG4A through FIG4D , the thin-film transistor may have another structure, such as a bottom-gate structure.

The semiconductor pattern 210 of the thin film transistor 200 is disposed on the buffer layer 120.

The semiconductor pattern 210 may include a polycrystalline semiconductor material. For example, the polycrystalline semiconductor material may include, but is not limited to, low-temperature polysilicon. When the semiconductor pattern 210 includes a polycrystalline semiconductor material, power consumption is reduced and reliability is improved.

The semiconductor pattern 210 may include an oxide semiconductor material. For example, the oxide semiconductor material may include, but is not limited to, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium zinc tin oxide (IGTO), and indium gallium oxide (IGO). When the semiconductor pattern 210 includes an oxide semiconductor material, leakage current blocking efficiency is improved during low-frequency driving, and sub-pixel brightness variation is minimized.

When the semiconductor pattern 210 includes a polycrystalline semiconductor material or an oxide semiconductor material, a portion of the semiconductor pattern 210 may include a conductive region.

The semiconductor pattern 210 may include amorphous silicon (a-Si) or an organic semiconductor material such as fused pentacene, but is not limited thereto.

The first insulating layer 130 is disposed on the semiconductor pattern 210.

The first insulating layer 130 may be disposed between the semiconductor pattern 210 and the gate electrode 230 to insulate the semiconductor pattern 210 and the gate electrode 230.

The first insulating layer 130 may include an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx). The first insulating layer 130 may also include an organic insulating material, but is not limited thereto.

The first insulating layer 130 may have contact holes to electrically connect the source electrode 250, the drain electrode 270, and the semiconductor pattern 210.

The gate electrode 230 of the thin film transistor 200 is disposed on the first insulating layer 130 to overlap with the semiconductor pattern 210.

The gate electrode 230 may include one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and a transparent conductive oxide (TCO), or an alloy thereof, and may have a single layer or multiple layers thereof. However, the present invention is not limited thereto.

The second insulating layer 140 is disposed on the gate electrode 230.

The second insulating layer 140 is disposed between the gate electrode 230 and the source electrode 250 and between the gate electrode 230 and the drain electrode 270 to insulate the gate electrode 230 from the source electrode 250 and the drain electrode 270.

The second insulating layer 140 may include an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx). The second insulating layer 140 may also include an organic insulating material, but is not limited thereto.

The second insulating layer 140 may have contact holes to electrically connect the source electrode 250 and the drain electrode 270 to the semiconductor pattern 210.

The source electrode 250 and the drain electrode 270 are disposed on the second insulating layer 140.

The source electrode 250 and the drain electrode 270 can be connected to the semiconductor pattern 210 through contact holes in the first insulating layer 130 and the second insulating layer 140.

The source electrode 250 and the drain electrode 270 may include one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and transparent conductive oxide (TCO), or alloys thereof, and may have a single layer or multiple layers thereof. However, the present invention is not limited thereto.

For example, the source electrode 250 and the drain electrode 270 may have a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti), but are not limited thereto.

The passivation layer 150 is disposed on the source electrode 250 and the drain electrode 270.

The passivation layer 150 protects the thin film transistor 200. The passivation layer 150 may include an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx). The passivation layer 150 may also include an organic insulating material, but is not limited thereto.

The passivation layer 150 may have contact holes to electrically connect the thin film transistor 200 and the connection electrode 170.

The passivation layer 150 may be omitted depending on the structure and type of the thin film transistor 200.

The planarization layer 160 can be disposed on the passivation layer 150 or the thin film transistor 200.

The planarization layer 160 can protect the thin film transistor 200 and reduce or flatten the steps based on various patterns.

The planarization layer 160 may include an organic insulating material such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, but is not limited thereto.

The planarization layer 160 may have a single layer or multiple layers depending on the configuration of the electrodes.

In LED display device 100, as the number of signal lines increases with resolution, signal lines can be formed in more than a single layer with a predetermined spacing. Therefore, the signal lines can be formed in multiple layers to provide a sufficient number of signal lines. Furthermore, when planarization layer 160 includes multiple layers of dielectric material, planarization layer 160 can be used as a capacitor between metal layers.

The planarization layer 160 may include a first planarization layer 161 and a second planarization layer 162.

For example, a contact hole may be formed in the first planarization layer 161, and the connecting electrode 170 may be disposed in the contact hole of the first planarization layer 161. A second planarization layer 162 having a contact hole may be disposed on the first planarization layer 161 and the connecting electrode 170. A first electrode (e.g., an anode) 310 may be disposed in the contact hole of the second planarization layer 162. Thus, the thin film transistor 200 and the first electrode 310 may be electrically connected to each other through the connecting electrode 170.

One end portion of the connecting electrode 170 may be connected to the thin film transistor, and the other end portion of the connecting electrode 170 may be connected to the first electrode 310.

The connection electrode 170 may include one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and a transparent conductive oxide (TCO), or an alloy thereof, and may have a single layer or multiple layers thereof. However, the present invention is not limited thereto.

The connecting electrode 170 may be omitted based on the structure and type of the LED display device 100.

The first electrode 310 may be disposed on the planarization layer 160. The first electrode 310 may be disposed in the luminous area EA and a portion of the non-luminous area NEA.

When the LED display device 100 is a top-emitting type, the first electrode 310 can function as a reflective electrode comprising an opaque conductive material. The first electrode 310 can comprise one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), and chromium (Cr), or alloys thereof. For example, the first electrode 310 can comprise a three-layer structure of silver (Ag), lead (Pb), and copper (Cu), but is not limited thereto. Alternatively, the first electrode 310 can comprise a transparent conductive material with a relatively high work function, such as indium tin oxide (ITO).

When the LED display device 100 is a bottom-emission type, the first electrode 310 may function as a transparent electrode made of a transparent conductive material. The first electrode 310 may include one of indium tin oxide (ITO) and indium zinc oxide (IZO).

The bank 320 may be disposed on the first electrode 310 and the planarization layer 160.

The bank 320 can divide the plurality of sub-pixels SP to minimize the light blurring effect or light blurring problem and prevent color mixing at various viewing angles.

The bank 320 can define the light-emitting area EA and the non-light-emitting area NEA, and can be disposed in the non-light-emitting area NEA.

The bank 320 may have a bank hole BH exposing the first electrode 310, and may have a bank trench BT in the non-light emitting area NEA between adjacent sub-pixels.

The bank 320 may include, but is not limited to, at least one of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx), an organic insulating material such as benzocyclobutene (BCB), an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin, and a photoresist including a black pigment.

The bank 320 may be transparent or may have a black or colored color. The bank 320 may be provided to cover the end portion of the first electrode 310.

The bank trench BT can be formed by partially removing the bank 320. When the bank 320 is completely removed in the area designated for the bank trench BT, the bank trench BT can expose the planarization layer 160. In FIG3 , while the bank 320 is completely removed in the area designated for the bank trench BT, the bank 320 may be partially removed in another embodiment. The bank 320 in the area designated for the bank trench BT may have a thickness of one-half to one-third of the bank 320 in the remaining area.

The bank trench BT may overlap with the first touch electrode 540_R, the first touch connection electrode 520, the second touch electrode, and the second touch connection electrode 540_C.

The manufacturing process of the bank trench BT will be described with reference to Figures 4A to 4D.

At least one first spacer 330 may be disposed on the bank 320. The first spacer 330 may comprise the same material as the bank 320. The first spacer 330 may be formed simultaneously with the bank 320 or may be formed through a different process than the bank 320.

The thickness of the first spacer 330 may be greater than the thickness of the bank 320. For example, the thickness of the first spacer 330 may be in the range of 1 μm to 2 μm.

The second spacer 340 may be disposed on the bank 320 and the planarization layer 160.

In some embodiments, since the light-emitting layer 350 or the second electrode 360 is separated by the second spacer 340, electrons in the light-emitting layer 350 can be prevented from migrating to adjacent sub-pixels. Therefore, even if the gap distance between adjacent sub-pixels decreases, side leakage current can be minimized due to the second spacer 340.

The second spacer 340 may be disposed in the bank trench BT or may cover a portion of the sidewall of the bank trench BT.

The second spacer 340 may have a reverse tapered shape. For example, the second spacer 340 may have a bottom surface and a top surface, and the size of the top surface of the second spacer 340 may be larger than the size of the bottom surface of the second spacer 340.

The second spacer 340 may include the same material as the bank 320 or the first spacer 330. The manufacturing process of the second spacer 340 will be described with reference to Figures 4A to 4D.

The thickness of the second spacer 340 may be greater than the thickness of the bank 320.

The second height or vertical distance H2 from the substrate 110 to the top of the second spacer 340 may be smaller than the first height or vertical distance H1 from the substrate 110 to the top of the first spacer 330. Because the second spacer 340 is disposed in the bank trench BT formed by partially removing the bank 320, the height or vertical distance from the top of the second spacer 340 on the substrate 110 may be smaller than the height or vertical distance from the top of the first spacer 330 on the bank 320 on the substrate 110. The height and vertical distance herein refer to a direction/orientation perpendicular to the display surface of the display device, that is, perpendicular to the substrate 110. Alternatively, or in addition, as shown in FIG. 3 , the fourth height H4 of the second spacer 340 may be smaller than the third height H3 of the first spacer 330.

When the second height or vertical distance H2 of the top of the second spacer 340 from the substrate 110 is the same as or similar to the first height or vertical distance of the top of the first spacer 330 from the substrate 110, the second spacer 340 may contact the fine metal mask (FMM) used to form the light-emitting layer 350, thereby causing distortion or damage. In an embodiment of the present invention, since the second spacer 340 is disposed in the bank trench BT, the first spacer 330, rather than the second spacer 340, contacts the fine metal mask, and distortion or damage of the second spacer 340 is prevented.

The second spacer 340 may include at least three spacer patterns. For example, the second spacer may include a first spacer pattern 340a, a second spacer pattern 340b, and a third spacer pattern 340c.

The first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c may be separated from each other. The spacer pattern holes PH may be provided between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c. In other words, the first spacer pattern holes PH may be provided between the first spacer pattern 340a and the second spacer pattern 340b, and the second spacer pattern holes PH may be provided between the second spacer pattern 340b and the third spacer pattern 340c. In some examples, the second spacer 340 may include a first spacer pattern, a second spacer pattern, and a third spacer pattern, with the first spacer pattern hole PH located between the first and second spacer patterns, and the second spacer pattern hole PH located between the second and third spacer patterns. The second spacer may include at least the first and second spacer patterns, with the spacer pattern hole located therebetween. Increasing the number of spacer patterns and spacer pattern holes can further reduce leakage current between multiple sub-pixels. The second spacer including the spacer pattern can prevent the light-emitting layer 350 (second electrode 360) from being formed or positioned on the side slopes of the second spacer. This is because the spacer pattern forms an overhang, meaning that these side slopes are obscured by deposits thereon. This enables the formation of discontinuities/cutouts/gaps in the light-emitting layer 350, thereby reducing leakage current between multiple sub-pixels.

At least one of the spacer patterns may be configured to be separated from the bank 320. For example, the second spacer pattern 340b of the second spacer 340 may be configured to be separated from the bank 320. The second spacer pattern 340b may be wider than the first spacer pattern 340a and wider than the third spacer pattern 340c.

At least one of the spacer patterns may be configured to cover a portion of the bank 320. For example, the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 may be configured to cover a portion of the bank 320 or respective portions of the bank 320.

In FIG3 , although the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 cover a portion of the bank 320, in another embodiment, the second spacer 340 may include a plurality of second spacer patterns 340b separated from the bank 320 in the bank trench BT.

In FIG3 , although the second spacer 340 includes three spacer patterns, the number of spacer patterns can be varied according to the design and is not limited thereto.

The light-emitting layer 350 may be disposed on the first electrode 310, the bank 320, the first spacer 330, the second spacer 340, and the planarization layer 160.

In some embodiments, the light-emitting layer 350 is cut in the non-light-emitting area NEA by the second spacers 340 and the spacer pattern holes PH, preventing electrons in the light-emitting layer 350 from migrating to adjacent sub-pixels. Consequently, side leakage current can be minimized even when the gap distance between adjacent sub-pixels decreases. The light-emitting layer 350 may not form a continuous layer but may include cutouts, gaps, or discontinuous portions separating various portions of the light-emitting layer 350. This may be caused by the second spacers 340 in the bank trenches BT. In particular, the light-emitting layer 350 may include a discontinuous portion between a portion thereof disposed on the bank 320 and a portion thereof disposed on the first spacer pattern 340a, may include a discontinuous portion between a portion thereof disposed on the first spacer pattern 340a and a portion thereof disposed on the second spacer pattern 340b (i.e., due to the first spacer pattern hole PH), may include a discontinuous portion between a portion thereof disposed on the second spacer pattern 340b and a portion thereof disposed on the third spacer pattern 340c (i.e., due to the second spacer pattern hole PH), and/or may include a discontinuous portion between a portion thereof disposed on the third spacer pattern 340c and a portion thereof disposed on the bank 320. Herein, a cut in a layer can refer to a cut through the layer, i.e., a complete cut through the layer, or a surface cut in the layer, i.e., a cut partially through the layer (i.e., a reduction in thickness). In some examples, the thickness of the light-emitting layer 350 can be reduced in the region of the second spacer 340. For example, the second spacer 340 can include one or more side slopes where the light-emitting layer 350 is thinner, scattered, or discontinuous. This can reduce the transmission of leakage current through the light-emitting region in this region. In other words, the deposition of the light-emitting layer 350 can be reduced in the region of the second spacer 340, thereby reducing the transmission of leakage current in this region during use. In the area of the second spacer 340, the light-emitting layer 350 may not be continuous or uniform.

A portion of the light-emitting layer 350 may be disposed on the planarization layer 160, and another portion may be disposed in the bank trench BT. A portion of the light-emitting layer 350 may be disposed between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c of the second spacer 340, that is, disposed in the spacer pattern hole PH.

The light-emitting layer 350 may include multiple stacks (light-emitting units). For example, the light-emitting layer 350 may include a first stack 351 (shown in FIG. 5 ), a second stack 353 , and a charge generation layer 352 (shown in FIG. 5 ). The structure of the light-emitting layer 350 will be described with reference to FIG. 5 .

The second electrode (e.g., cathode) 360 may be disposed on the light-emitting layer 350.

The second electrode 360 may be cut in the non-light-emitting area NEA by the second spacer 340. The second electrode 360 may not form a continuous layer, but may include some cuts, gaps, or discontinuous portions that separate the respective portions of the second electrode 360 and correspond to the cuts/gaps/discontinuous portions of the light-emitting layer 350.

A portion of the second electrode 360 may be disposed in the bank trench BT, and a portion of the second electrode 360 may be disposed between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c of the second spacer 340, that is, disposed in the spacer pattern hole PH.

For example, each of the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c has a reverse tapered shape, wherein side surfaces of each of the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c form a sharp angle with the top surface of the second planarization layer 162. Therefore, the light-emitting layer 350 and the second electrode 360 may be cut between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c, and the residual layer RL having the light-emitting layer 350 and the second electrode 360 may be disposed on the second planarization layer 162 between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c. In other words, the term "residual layer RL" may be used to refer to the light-emitting layer 350 and the second electrode 360 disposed in the spacer pattern holes PH of the second spacer 340. A portion of the light-emitting layer 350 included in the residual layer RL may be separated from the portions of the light-emitting layer 350 disposed on the first, second, and third spacer patterns 340a, 340b, and 340c. A portion of the second electrode 360 included in the residual layer RL may be separated from the portions of the second electrode 360 disposed on the first, second, and third spacer patterns 340a, 340b, and 340c. Portions of the light-emitting layer 350 disposed on one or more of the first, second, and third spacer patterns 340a, 340b, and 340c may be separated from the portions of the light-emitting layer 350 disposed on the adjacent banks 320. Portions of the second electrode 360 disposed on one or more of the first spacer patterns 340a, the second spacer patterns 340b, and the third spacer patterns 340c may be separated from portions of the second electrode 360 disposed on adjacent banks 320.

The second electrode 360 can provide electrons to the light-emitting layer 350 and may include a conductive material with a relatively low work function.

When the LED display device 100 is a top-emitting type, the second electrode 360 may function as a transparent electrode comprising a transparent conductive material. The second electrode 360 may comprise one of indium tin oxide (ITO) and indium zinc oxide (IZO).

Alternatively, the second electrode 360 may include a translucent conductive material. For example, the second electrode 360 may include at least one of an alloy of lithium fluoride/aluminum (LiF/Al), csium fluoride/aluminum (CsF/Al), magnesium:silver (Mg:Ag), calcium/silver (Ca/Ag), lithium fluoride/magnesium:silver (LiF/Mg:Ag), lithium fluoride/calcium/silver (LiF/Ca/Ag), and lithium fluoride/calcium:silver (LiF/Ca:Ag).

When the LED display device 100 is a bottom-emitting type, the second electrode 360 may function as a reflective electrode comprising an opaque conductive material. For example, the second electrode 360 may comprise silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof.

Although not shown, a capping layer (CPL) may be disposed on the second electrode 360.

The capping layer can protect the second electrode 360 and improve the light extraction effect of the light-emitting layer 350. The capping layer can have a single layer or multiple layers, and is not limited thereto.

Depending on the structure and type of LED display device 100, the capping layer may be omitted.

The encapsulation layer 400 can be disposed on the second electrode 360 or the capping layer. The encapsulation layer 400 protects the first electrode 310, the light-emitting layer 350, and the second electrode 360 from moisture, oxygen, or external particles. For example, the encapsulation layer 400 blocks the penetration of oxygen and moisture from the outside, thereby preventing oxidation of the materials of the first and second electrodes 310, 360, and the light-emitting layer 350.

The encapsulation layer 400 may include a transparent material so that light emitted from the light-emitting layer 350 can pass through the encapsulation layer 400.

The packaging layer 400 may include a first packaging layer 410, a second packaging layer 420, and a third packaging layer 430 for preventing the permeation of moisture or oxygen. The first packaging layer 410, the second packaging layer 420, and the third packaging layer 430 may have a sequentially stacked structure.

The first encapsulation layer 410 and the third encapsulation layer 430 may include, but are not limited to, inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and aluminum oxide (AlOz). The first encapsulation layer 410 and the third encapsulation layer 430 may be formed using, but are not limited to, vacuum deposition methods such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).

Each of the first packaging layer 410 and the third packaging layer 430 may have a multi-layer structure including at least two layers. For example, the first packaging layer 410 may have a three-layer structure of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxide (SiOx), but is not limited thereto. Alternatively, the first packaging layer 410 may have a four-layer structure of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxide (SiOx), but is not limited thereto.

The second packaging layer 420 can cover particles generated during the manufacturing process. The second packaging layer 420 can also planarize the surface of the first packaging layer 410. For example, the second packaging layer 420 can be considered a particle covering layer.

The second encapsulation layer 420 may include an organic material such as silicon oxycarbide (SiOCz), epoxy, polyimide, polyethylene, and acrylic polymer, but is not limited thereto.

The second packaging layer 420 may include a heat-curable material that can be thermally cured or a light-curable material that can be light-cured.

The touch sensing layer 500 can be disposed on the packaging layer 400.

The touch sensing layer 500 may include a first touch electrode 540_R, a first touch connecting electrode 520, a second touch electrode, and a second touch connecting electrode 540_C.

A portion of the first touch electrode 540_R, the first touch link electrode 520, the second touch electrode, and the second touch link electrode 540_C may be disposed to overlap with the second spacer 340 and the bank trench BT.

First touch electrode 540_R, first touch connection electrode 520, second touch electrode 540_C may have a grid pattern in which metal lines, each having a relatively narrow width, intersect with each other. The grid pattern may have a diamond shape. Alternatively, the grid pattern may have one of the following shapes: rectangular, pentagonal, hexagonal, circular, and elliptical, but is not limited thereto.

First touch electrode 540_R, first touch connection electrode 520, second touch electrode 540_C, and second touch connection electrode 540_C may comprise an opaque conductive material with relatively low resistance. For example, first touch electrode 540_R, first touch connection electrode 520, second touch connection electrode 540_C may comprise one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and a transparent conductive oxide (TCO), or alloys thereof, and may comprise a single layer or multiple layers thereof. However, the present invention is not limited thereto.

For example, first touch electrode 540_R, first touch connection electrode 520, second touch electrode 540_C may have a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti), but the present invention is not limited thereto.

The first touch electrode 540_R, the first touch connection electrode 520, the second touch electrode, and the second touch connection electrode 540_C may include the same material as the source electrode 250 and the drain electrode 270.

The touch buffer layer 510 can be disposed on the packaging layer 400. The touch buffer layer 510 blocks the penetration of solutions (developers or etchants) used in the manufacturing process of the touch sensing layer 500, or moisture from the outside, into the luminescent layer 350. Furthermore, the touch buffer layer 510 prevents the various touch sensing metals on the touch buffer layer 510 from being cut by external impacts, and blocks interference signals generated when the touch sensing layer 500 is driven.

The touch buffer layer 510 may include at least one of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx), and an organic insulating material such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, but is not limited thereto.

The first touch connection electrode 520 can be disposed on the touch buffer layer 510.

For example, the first touch connection electrode 520 may be disposed between adjacent first touch electrodes 540_R along the first direction (X direction). The first touch connection electrode 520 may electrically connect multiple first touch electrodes 540_R that are separated from each other and adjacent to each other along the first direction (X direction), but is not limited thereto.

The first touch connection electrode 520 can be arranged along the second direction (Y direction) to overlap with the second touch connection electrode 540_C that connects to an adjacent second touch electrode. Because the first touch connection electrode 520 and the second touch connection electrode 540_C are arranged on different layers, the first touch connection electrode 520 and the second touch connection electrode 540_C can be electrically isolated.

The touch insulation layer 530 can be disposed on the touch buffer layer 510 and the first touch connection electrode 520.

The touch insulating layer 530 may have a contact hole for electrically connecting the first touch electrode 540_R and the first touch connection electrode 520.

The touch insulating layer 530 can electrically insulate the first touch connecting electrode 520 from the second touch connecting electrode 540_C.

The touch insulating layer 530 may include a single layer or multiple layers of silicon nitride (SiNx) and silicon oxide (SiOx), but is not limited thereto.

The first touch electrode 540_R, the second touch electrode, and the second touch connection electrode 540_C may be disposed on the touch insulating layer 530.

The first touch electrode 540_R and the second touch electrode can be separated from each other. The plurality of first touch electrodes 540_R can be separated from each other along a first direction (X direction). Adjacent first touch electrodes 540_R can be connected to the first touch connection electrode 520 located between the first touch electrodes 540_R along the first direction (X direction). For example, the adjacent first touch electrodes 540_R can be connected to the first touch connection electrode 520 through contact holes in the touch insulation layer 530.

Adjacent second touch electrodes can be connected to each other along the second direction (Y direction) via second touch connection electrode 540_C. The second touch electrodes and second touch connection electrode 540_C can be formed on the same layer. For example, second touch connection electrode 540_C can be disposed in the same layer as the second touch electrodes and can be disposed between the second touch electrodes. Second touch connection electrode 540_C can be formed to extend from the second touch electrodes.

The first touch electrode 540_R, the second touch electrode, and the second touch connection electrode 540_C can be formed through the same process.

The touch planarization layer 550 may be disposed on the first touch electrode 540_R, the second touch electrode, and the second touch connection electrode 540_C.

The touch driver circuit receives a touch sensing signal from the first touch electrode 540_R and transmits a touch driver signal to the second touch electrode. The touch driver circuit detects a user touch using the mutual capacitance between the first touch electrode 540_R and the second touch electrode. For example, when a touch occurs on the LED display device 100, the capacitance between the first touch electrode 540_R and the second touch electrode may change. The touch driver circuit detects this capacitance change to calculate the touch coordinates.

The manufacturing process of the bank trench BT and the second spacer 340 will be described herein.

In FIG4A , the first electrode 310 is formed in the light emitting area EA located on the substrate 110 having the thin film transistor 200.

In FIG4B , the bank 320 and the first spacer 330 are formed in the non-light emitting area NEA of the substrate 110 having the first electrode 310.

The bank 320 may include a bank hole BH that exposes the first electrode 310 in the light-emitting area EA. The bank hole BH may be formed by a portion of the bank 320.

At least one first spacer 330 may be disposed on the bank 320.

In FIG. 4B , although the bank 320 and the first spacer 330 are formed through the same process using a half-tone mask, in another embodiment, the bank 320 and the first spacer 330 may be formed through different processes.

In FIG4C , a bank trench BT is formed between adjacent sub-pixels. The bank trench BT can be formed by etching a portion of the bank 320. The planarization layer 160 can be exposed through the bank trench BT.

In FIG. 4C , although the entire bank 320 is removed in the region where the bank trench BT is provided, in another embodiment, a portion of the bank 320 may be removed. For example, a portion of the bank 320 may be removed, rather than the entire bank 320, to leave the planarization layer 160 in the region where the bank trench BT is provided.

In FIG4D , a second spacer 340 may be formed in the bank trench BT.

The second spacer 340 may include a first spacer pattern 340a, a second spacer pattern 340b, and a third spacer pattern 340c. The first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c may be separated from each other. The spacer pattern hole PH may be provided between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c.

At least one of the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c of the second spacer 340 may cover a portion of the bank 320. For example, the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 may be disposed so as to be separated from the bank 320.

In Figures 4A to 4D , although the bank hole BH, bank trench BT, first spacer 330, and second spacer 340 are formed through different processes, in another embodiment, the bank hole BH and bank trench BT may be formed simultaneously, and the first spacer 330 and second spacer 340 may be formed simultaneously.

FIG5 is a schematic diagram illustrating a light-emitting layer of a light-emitting diode display device according to an embodiment of the present invention.

In Figure 5, although the light-emitting layer includes two stacks (light-emitting units) and one charge-generating layer, in another embodiment, the light-emitting layer may include three or more stacks and two or more charge-generating layers.

In Figure 5 , the light-emitting layer 350 may include multiple stacks (light-emitting units). For example, the light-emitting layer 350 may include a first stack 351, a second stack 353, and a charge generation layer 352 between the first stack 351 and the second stack 353.

The first electrode (e.g., anode) 310, the first stack 351, the charge generation layer 352, the second stack 353, and the second electrode (e.g., cathode) 360 can be sequentially disposed on the substrate 110 having the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3.

The first stack 351 may include a hole injection layer 351-A, a first hole transport layer 351-B, a first light-emitting material layer 351-C, and a first electron transport layer 351-D.

The second stack 353 may include a second hole transport layer 353-A, a second light-emitting material layer 353-B, a second electron transport layer 353-C, and an electron injection layer 353-D.

The charge generation layer 352 may include a negative (N) type charge generation layer n-CGL (352-n) that assists in injecting electrons into the first stack 351 and a positive (P) type charge generation layer p-CGL (352-p) that assists in injecting holes into the second stack 353.

Although not shown, an electron blocking layer may be disposed between the first hole injection layer 351-A and the first light-emitting material layer 351-C, and between the first light-emitting material layer 351-C and the charge generation layer 352. Furthermore, an electron blocking layer may be disposed between the charge generation layer 352 and the second light-emitting material layer 353-B, and between the second light-emitting material layer 353-B and the electron injection layer 353-D.

A portion of the light-emitting layer 350 can be cut between adjacent sub-pixels by a bank trench BT formed by the second spacer 340 beneath the light-emitting layer 350. This prevents electrons in the light-emitting layer 350 from migrating to adjacent sub-pixels. Specifically, the degradation in visibility between adjacent sub-pixels in relatively low grayscale is reduced, and color reproducibility is improved.

The first light-emitting material layer 351-C and the second light-emitting material layer 353-B can be arranged to correspond to each sub-pixel and separated from each other. For example, the first light-emitting material layer 351-C and the second light-emitting material layer 353-B can be arranged to overlap with the bank hole BH and the end portion of the bank 320.

The hole injection layer 351-A can assist in the injection of holes. The hole injection layer 351-A can include at least one of HATCN (1,4,5,8,9,11-hexazotriphenylacetonitrile), CuPc (copper phthalocyanine), PEDOT (poly(3,4-ethylenedioxythiophene)), PANI (polyaniline), and NPD (N, N' -dinaphthyl-N, N' -diphenylbenzidine), but is not limited thereto.

The first hole transport layer 351-B and the second hole transport layer 353-A can assist in the transport of holes. The first hole transport layer 351-B and the second hole transport layer 353-A can include at least one of NPD (N, N' -dinaphthyl-N, N' -diphenylbenzidine), TPD (N, N' -bis-(3-methylphenyl)-N, N' -bis(phenyl)-benzidine), s-TAD, and MTDATA ( 4,4'4 " -tris(3-methylphenylamino)triphenylamine), but are not limited thereto.

The first electron transport layer 351-D and the second electron transport layer 353-C can assist in the transport of electrons. The first electron transport layer 351-D and the second electron transport layer 353-C can include Alq3 (tris (8-hydroxyquinoline) aluminum), PBD (2- (4-biphenyl) -5- (4-tert-butylphenyl) -1,3,4- At least one of oxadiazole), TAZ, spiro-PBD, BAlq and SAlq, but not limited thereto.

The electron injection layer 353-D assists in the injection of electrons. The electron injection layer 353-D may include Alq3 (tris(8-hydroxyquinoline)aluminum), PBD (2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4- At least one of oxadiazole), TAZ, spiro-PBD, BAlq and SAlq, but not limited thereto.

The first luminescent material layer 351-C and the second luminescent material layer 353-B can be disposed within the bank hole BH to overlap a portion of the bank 320 and be separated from each other between adjacent sub-pixels. For example, the first luminescent material layer 351-C and the second luminescent material layer 353-B can be deposited on each sub-pixel using a fine metal mask (FMM).

The first light-emitting material layer 351-C and the second light-emitting material layer 353-B may overlap each other and may emit light corresponding to the same color. The first light-emitting material layer 351-C and the second light-emitting material layer 353-B may emit light of the same wavelength, but are not limited thereto.

The first light-emitting material layer 351-C and the second light-emitting material layer 353-B may include light-emitting materials that emit red, green, and blue light, and the light-emitting materials may be formed using phosphorescent materials or fluorescent materials.

For example, the first red luminescent material layer 351R and the second red luminescent material layer 353R in the first subpixel SP_1 can be made of a phosphorescent material including a main material of CBP (carbazole biphenyl) or mCP (1,3-bis(carbazol-9-yl)benzene) and a doped material selected from PIQIr(acac) (bis(1-phenylisoquinolinato) iridium acetylacetonate), PQIr(acac) (bis(1-phenylquinolinato) iridium acetylacetonate), PQIr(tris(1-phenylquinolinato)iridium), and PtOEP (platinum octaethylporphyrin). Alternatively, the phosphorescent material can be made of PBD:Eu(DBM)3(Phen) or perylene. However, the present invention is not limited thereto.

For example, the first green light-emitting material layer 351G and the second green light-emitting material layer 353G in the second sub-pixel SP_2 can be composed of a phosphorescent material including a host material of CBP or mCP and a doping material including an iridium complex of Ir(ppy)3 (facial tris(2-phenylpyridinium) iridium), or a fluorescent material including Alq3 (tris(8-hydroxyquinoline)aluminum). However, this is not limiting.

For example, the first blue light-emitting material layer 351B and the second blue light-emitting material layer 353B in the third subpixel SP_3 can be composed of a phosphorescent material including a host material of CBP or mCP and a dopant material of (4,6-F2ppy)2Irpic, or a phosphorescent material including spiro-DPVBi, spiro-6P, distyrylbenzene (DSB), distyrylarylene (DSA), PFO polymer, and PPV polymer. However, the present invention is not limited thereto.

The first luminescent material layer 351-C and the second luminescent material layer 353-B may include an auxiliary luminescent material layer. For example, the auxiliary luminescent material layer may be disposed above or below the first luminescent material layer 351-C and the second luminescent material layer 353-B. The auxiliary luminescent material layer may emit light of the same color as the first luminescent material layer 351-C and the second luminescent material layer 353-B, or a different color.

The N-type charge generation layer n-CGL (352-n) can be composed of an alkali metal, an alkali metal compound, an organic material for injecting electrons, or an alloy thereof. For example, the N-type charge generation layer n-CGL (352-n) can include a mixed layer of an N-type material such as an anthracene derivative doped with lithium (Li) or cesium (Cs), but is not limited thereto.

The p-type charge generation layer (p-CGL) (352-p) may be formed of an organic material used for a hole injection layer. For example, the p-type charge generation layer (p-CGL) (352-p) may include a single layer of a p-type material such as HATCN or F4-TCNQ, but is not limited thereto.

Each layer of the first stack 351, the second stack 353, and the charge generation layer 352 may have multiple layers or may be omitted.

Therefore, in the LED display device according to the embodiment of the present invention, since the bank trench having at least one second spacer is disposed between adjacent sub-pixels, when the gap distance between adjacent sub-pixels is reduced or blocked, the side leakage current increases.

In some embodiments, since the light-emitting layer is cut by a trench having at least one second spacer bank between adjacent sub-pixels, electrons in the light-emitting layer can be prevented from moving to adjacent sub-pixels.

Since side leakage current is reduced or blocked between adjacent sub-pixels, the degradation in discrimination between adjacent sub-pixels in relatively low grayscale is reduced, and color reproduction is improved.

The embodiments of the present invention can also be described as follows.

According to one embodiment of the present invention, a display device may include: a substrate having a first sub-pixel and a second sub-pixel, each including a light-emitting region, and a non-light-emitting region surrounding the light-emitting region; a first electrode located in each of the first and second sub-pixels; a bank having a bank hole located in each of a plurality of light-emitting regions and a bank trench located in the non-light-emitting region; a first spacer located on the bank; a second spacer located in the bank trench; a light-emitting layer located on the first electrode and the bank trench and including a plurality of stacks and at least one charge generation layer between the plurality of stacks; and a second electrode located on the light-emitting layer.

In some embodiments, the second spacer may have a reverse tapered shape.

In some embodiments, the height of the top of the second spacer from the substrate may be different from the height of the top of the first spacer from the substrate.

In some embodiments, the height of the top of the second spacer from the substrate may be smaller than the height of the top of the first spacer from the substrate.

In some embodiments, the thickness of the second spacer may be greater than the thickness of the bank.

In some exemplary embodiments, the second spacer may include at least a first spacer pattern and a second spacer pattern, with the spacer pattern hole located therebetween.

In some embodiments, the second spacer may include at least a first spacer pattern, a second spacer pattern, and a third spacer pattern, wherein the first spacer pattern hole is located between the first spacer pattern and the second spacer pattern, and the second spacer pattern hole is located between the second spacer pattern and the third spacer pattern.

In some embodiments, at least one of the first spacer pattern, the second spacer pattern, and the third spacer pattern covers a portion of the bank.

In some embodiments, the display device may further include: a thin film transistor located on a substrate; and a planarization layer located on the thin film transistor.

In some embodiments, the bank trench may expose the planarization layer.

In some embodiments, the second spacer may be disposed on the planarization layer.

In some embodiments, the light-emitting layer may be disposed on the planarization layer.

In some embodiments, the light-emitting layer may include cutouts in the non-light-emitting region formed by the second spacers.

In some embodiments, the at least one charge generation layer may include a first charge generation layer and a second charge generation layer.

In some embodiments, each of the plurality of stacks may include a layer of light-emitting material.

In some embodiments, the display device may further include: a packaging layer located on the second electrode; and a touch sensing layer located on the packaging layer.

In some embodiments, the touch sensing layer may include a first touch electrode and a second touch electrode overlapping a second spacer.

In some example embodiments, the height of the second spacer may be smaller than the height of the first spacer.

According to another embodiment of the present invention, a display device may include: a substrate including a display area having a plurality of sub-pixels, a non-luminescent area between the plurality of sub-pixels, and a non-luminescent area adjacent to the display area; a first electrode located at each of the plurality of sub-pixels; a bank that divides the plurality of sub-pixels; a luminescent layer located on the first electrode; a second electrode located on the luminescent layer; and a cutout located in the luminescent layer between two adjacent sub-pixels or in the luminescent layer between two adjacent sub-pixels.

In some embodiments, the bank may include a plurality of bank holes corresponding to a plurality of sub-pixels, and a bank trench corresponding to a non-light-emitting area.

In some embodiments, the display device may further include a first spacer located on the bank.

In some embodiments, the cutouts may be formed by second spacers in the bank trenches.

In some embodiments, the second spacer may comprise the same material as the bank.

In some example embodiments, the height of the second spacer may be smaller than the height of the first spacer.

According to yet another embodiment of the present invention, a method for manufacturing a display device may include: forming a plurality of first electrodes separated from each other on a substrate; forming a bank on the substrate on which the plurality of first electrodes are formed; forming a bank hole in the bank to expose a portion of each of the plurality of first electrodes, and forming a bank trench between adjacent first electrodes in the bank; forming a second spacer in the bank trench; forming a light-emitting layer between the second spacer and the bank trench, the light-emitting layer including a plurality of stacks and at least one charge generation layer between the plurality of stacks; and forming a second electrode on the light-emitting layer.

In some embodiments, the method further includes simultaneously forming a first spacer and a second spacer on the bank.

Although the cutting portion described herein mainly refers to an embodiment in which the cutting portion includes a second spacer located in the bank groove, the cutting portion may have another form according to actual needs.

It is apparent to those skilled in the art that various modifications and variations can be made to the display device of this disclosure without departing from the technical spirit or scope of this disclosure. Therefore, as long as such modifications and variations fall within the scope of the appended patent applications and their equivalents, the embodiments of this disclosure are intended to cover such modifications and variations.

330: First spacer 340: Second spacer BT: Bank trench EA: Emitting area NEA: Non-emitting area P: Pixel SP_1: First subpixel SP_2: Second subpixel SP_3: Third subpixel I-I′: Line

Claims (21)

A display device includes: a substrate having a first sub-pixel, a second sub-pixel, and a non-luminescent region, wherein the first sub-pixel and the second sub-pixel each include a luminescent region, and the non-luminescent region surrounds the luminescent region; a first electrode located in each of the first sub-pixel and the second sub-pixel; a bank having a bank hole located in each of the luminescent regions and a bank hole located in the bank; A bank trench in a non-light-emitting area; a first spacer located on the bank; a second spacer located in the bank trench to be separated from the bank; a light-emitting layer located on the first electrode and the bank trench and comprising a plurality of stacks and at least one charge generation layer between the stacks; and a second electrode located on the light-emitting layer, wherein the light-emitting layer is cut by the second spacer in the non-light-emitting area. The display device of claim 1, wherein the second spacer has a reverse tapered shape. The display device of claim 1, wherein a height of a top of the second spacer from the substrate is different from a height of a top of the first spacer from the substrate. The display device of claim 1, wherein a height of a top of the second spacer from the substrate is smaller than a height of a top of the first spacer from the substrate. The display device of claim 1, wherein a thickness of the second spacer is greater than a thickness of the bank. The display device as described in claim 1, wherein the second spacer includes at least a first spacer pattern and a second spacer pattern, and a spacer pattern hole is located between the first spacer pattern and the second spacer pattern. A display device as described in claim 1, wherein the second spacer includes at least a first spacer pattern, a second spacer pattern, and a third spacer pattern, and a first spacer pattern hole is located between the first spacer pattern and the second spacer pattern, and a second spacer pattern hole is located between the second spacer pattern and the third spacer pattern. The display device of claim 7, wherein at least one of the first spacer pattern, the second spacer pattern, and the third spacer pattern covers a portion of the bank. The display device as described in claim 1 further includes: a thin film transistor located on the substrate; and a planarization layer located on the thin film transistor. The display device of claim 9, wherein the bank trench exposes the planarization layer. The display device of claim 9, wherein the second spacer is disposed on the planarization layer. The display device as described in claim 9, wherein the light-emitting layer is disposed on the planarization layer. The display device of claim 1, wherein at least one of the charge generation layers includes a first charge generation layer and a second charge generation layer. The display device of claim 1, wherein each of the stacks comprises a layer of luminescent material. The display device of claim 1 further comprises: a packaging layer located on the second electrode; and a touch sensing layer located on the packaging layer. The display device of claim 15, wherein the touch sensing layer includes a first touch electrode and a second touch electrode overlapping the second spacer. The display device of any one of claims 1 to 16, wherein a height of the second spacer is smaller than a height of the first spacer. A display device comprises: a substrate comprising a display area having a plurality of sub-pixels, a non-luminescent area located between the plurality of sub-pixels, and a non-display area adjacent to the display area; a respective first electrode located in each of the sub-pixels; a levee dividing the sub-pixels; a luminescent layer located on the first electrodes; a second electrode located on the luminescent layer; and a cutout located in the luminescent layer between two adjacent sub-pixels, wherein the levee comprises a plurality of levee holes corresponding to the sub-pixels respectively and a levee trench corresponding to the non-luminescent area, wherein the cutout is formed by a second spacer in the levee trench. The display device as described in claim 18 further includes a first spacer located on the bank. The display device of claim 18, wherein the second spacer comprises the same material as the bank. The display device of claim 19, wherein a height of the second spacer is smaller than a height of the first spacer.