TWI894636B - Chip package manufacturing method - Google Patents

Abstract

A method for manufacturing a chip package, comprising at least one chip, an insulating layer, at least one first metal layer, and at least one second metal layer; wherein each second metal layer is filled in at least one opening of the insulating layer and at least one opening of each first metal layer, and covers the back of each chip, and the first surface level of each second metal layer is at the same level as that of each first metal layer. The first surface of each second metal layer is at the same level; each second metal layer is formed by filling each opening of the insulating layer and each opening of the first metal layer with at least one conductive glue; and the first surface of each second metal layer is a flat surface formed by a grinding operation to avoid affecting the product yield and effectively solve the problem of the relatively complex chip packaging process.

Description

Chip package manufacturing method

The present invention is a method for manufacturing a chip package that can achieve electromagnetic shielding and chip heat dissipation, particularly a method for manufacturing a chip package that can solve the problems of reduced chip packaging yield and relatively complex manufacturing processes.

To achieve electromagnetic shielding and chip heat dissipation, existing chip packages typically incorporate an electromagnetic shielding layer on top of the chip package. A hole is drilled through the top of the chip package to expose the backside of the chip inside. A layer of copper is then electroplated on the backside to serve as a heatsink to aid in chip heat dissipation.

However, copper heat sinks formed through electroplating are prone to surface pitting (i.e., unevenness) or incomplete surface formation, which reduces chip packaging yield and compromises product market competitiveness. Furthermore, the typical copper electroplating process is relatively complex, which can increase manufacturing costs.

Therefore, a chip package that can solve the problems of reduced chip packaging yield and relatively complex manufacturing processes is currently eagerly awaited by the relevant industries.

The primary purpose of the present invention is to provide a method for manufacturing a chip package, comprising at least one chip, an insulating layer, at least one first metal layer, and at least one second metal layer; wherein each second metal layer is disposed so as to fill at least one opening of the insulating layer and at least one opening of each first metal layer, and covers the backside of each chip, and wherein the first surface of each second metal layer is at a level with the first metal layer. The first surfaces of each first metal layer are at the same level. Each second metal layer is formed by filling each opening in the insulating layer and each opening in the first metal layer with at least one conductive paste. The first surface of each second metal layer is flattened by a polishing process to avoid affecting product yield and effectively address the relatively complex chip packaging process.

To achieve the above-mentioned object, the present invention provides a chip package, which includes a substrate, at least one first circuit layer, at least one second circuit layer, at least one chip, an insulating layer, at least one first metal layer and at least one second metal layer; wherein the substrate has a first surface and an opposite second surface; wherein each of the first circuit layers is disposed on the first surface of the substrate, and each of the first circuit layers has a first surface; wherein each of the second circuit layers is disposed on the second surface of the substrate, and wherein each of the first circuit layers has a first surface; wherein each of the second circuit layers is disposed on the second surface of the substrate, and wherein each of the first circuit layers has a first surface; wherein each of the second circuit layers has a second surface; wherein each of the first circuit layers has a second ... The second circuit layer is electrically connected to each of the first circuit layers through the substrate; wherein each of the chips is electrically connected and disposed on the first surface of each of the first circuit layers, each of the chips having a backside and an opposite connection surface, each of the chips having at least two crystal pads on the connection surface, each of the chips being electrically connected to each of the first circuit layers through the crystal pads, wherein each of the chips is first electrically connected to the first surface of each of the first circuit layers, and then electrically connected to each of the second circuit layers through each of the first circuit layers. The circuit layer is electrically connected to each other so that each chip can be electrically connected to the outside through each second circuit layer; wherein the insulating layer is provided on the substrate and covers each chip, and the insulating layer has a first surface and at least one opening, wherein each opening of the insulating layer can allow the back of each chip to be exposed to the outside; wherein each first metal layer is fully covered on the first surface of the insulating layer, and each first metal layer has a first surface and at least one opening, wherein each opening of the first metal layer is connected to the insulating layer. The openings are interconnected, wherein the openings of the first metal layers allow the backside of the chips to be exposed. The second metal layers are filled in the openings of the insulating layer and the openings of the first metal layers, covering the backside of the chips. The first surface of the second metal layers is at the same level as the first surface of the first metal layers. The second metal layers are formed by filling the openings of the insulating layer and the first metal layers with at least one conductive adhesive. The first surface of each second metal layer is a flat surface formed by a grinding operation; each second metal layer is connected to each first metal layer to form a comprehensive protective metal layer structure for preventing each first circuit layer, each second circuit layer and each chip from being subjected to electromagnetic interference, and directly generating a heat dissipation effect on the back of each chip; wherein the manufacturing method of the chip package includes the following steps: Step S1: providing a substrate, wherein the substrate has The substrate has a first surface and an opposite second surface, wherein at least one first circuit layer is provided on the first surface of the substrate, and each first circuit layer has a first surface, wherein at least one second circuit layer is provided on the second surface of the substrate; step S2: at least one chip is provided on the first surface of each first circuit layer, wherein each chip has a back surface and an opposite connection surface, and each chip has at least two crystal pads on the connection surface; step S3: an insulating layer is provided on the substrate and the insulating layer is provided The insulating layer covers each chip, wherein the insulating layer has a first surface; step S4: at least one first metal layer is provided on the first surface of the insulating layer to fully cover the entire surface, wherein each first metal layer has a first surface; step S5: drilling holes in the insulating layer and each first metal layer simultaneously, so that the insulating layer and each first metal layer are respectively formed with at least one opening, wherein each opening of the insulating layer exposes the back of each chip to the outside, wherein each opening of the first metal layer is adjacent to the insulating layer. The openings of the insulating layer and the first metal layer are connected; step S6: each opening of the insulating layer and each opening of the first metal layer is filled with at least one conductive paste, and each conductive paste covers the backside of each chip; step S7: each conductive paste is polished to a surface level that is the same as the level of the first surface of each first metal layer. After the polishing operation is completed, each conductive paste located in each opening of the insulating layer and each opening of the first metal layer is formed into at least one second metal layer.

In a preferred embodiment of the present invention, each of the conductive adhesives formed into each of the second metal layers is silver adhesive.

In a preferred embodiment of the present invention, each second circuit layer further has a first surface; the chip package further has at least one first outer protective layer and at least one second outer protective layer; each first outer protective layer is disposed on the first surface of each first metal layer and the first surface of each second metal layer; each second outer protective layer is disposed on the first surface of each second circuit layer, and each second outer protective layer has at least one opening, each opening allowing the first surface of each second circuit layer to be exposed to the outside.

In a preferred embodiment of the present invention, the substrate further has at least one blind hole, each of which has a conductive line disposed therein, and each of the first circuit layers is electrically connected to each of the second circuit layers via the conductive line in each of the blind holes.

In a preferred embodiment of the present invention, each blind via of the substrate is further filled with at least one third metal layer to serve as a conductive trace within the blind via, and a first surface of each third metal layer is at the same level as the first surface of each first circuit layer. Furthermore, each second circuit layer is electrically connected to each first circuit layer via each third metal layer.

In a preferred embodiment of the present invention, each of the third metal layers is silver.

1: Chip packaging

10:Substrate

11: First Surface

12: Second Surface

13: Blind hole

20: First circuit layer

21: First Surface

30: Second circuit layer

31: First Surface

40: Chip

41: Crystal Back

42: Connecting surface

43: Crystal pad

50: Insulating layer

51: First Surface

52: Opening

60: First metal layer

61: First Surface

62: Opening

70: Second metal layer

70a: Conductive glue

71: First Surface

80: First outer protective layer

90: Second outer protective layer

91: Opening

100: Third metal layer

101: First Surface

Figure 1 is a schematic side cross-sectional plan view of an embodiment of the present invention.

Figure 2 is a schematic plan view of a side cross-section of the substrate of the present invention.

FIG3 is a schematic diagram of placing a chip on the first surface of the first circuit layer in FIG2.

Figure 4 is a schematic diagram of providing an insulating layer on the substrate in Figure 3.

FIG5 is a schematic diagram showing a first metal layer disposed on the first surface of the insulating layer in FIG4 to fully cover the entire surface.

Figure 6 is a schematic diagram of simultaneously drilling holes in the insulating layer and the first metal layer in Figure 5.

Figure 7 is a schematic diagram showing the openings in the insulating layer and the first metal layer in Figure 6 being filled with conductive glue.

Figure 8 is a schematic side cross-sectional plan view of another embodiment of the present invention (further comprising a first outer protective layer and a second outer protective layer).

The structure and technical features of the present invention are described in detail below with the help of illustrations. The illustrations are only used to illustrate the structural relationships and related functions of the present invention. Therefore, the dimensions of the components in the illustrations are not drawn to scale and are not intended to limit the present invention.

Referring to FIG. 1 , the present invention provides a chip package 1 comprising a substrate 10, at least a first circuit layer 20, at least a second circuit layer 30, at least a chip 40, an insulating layer 50, at least a first metal layer 60, and at least a second metal layer 70.

The substrate 10 has a first surface 11 and an opposite second surface 12 as shown in Figures 1 and 8.

Each of the first circuit layers 20 is disposed on the first surface 11 of the substrate 10. Each of the first circuit layers 20 has a first surface 21 as shown in Figures 1 and 8.

Each second circuit layer 30 is disposed on the second surface 12 of the substrate 10 as shown in Figures 1 and 8 ; each second circuit layer 30 is electrically connected to each first circuit layer 20 through the substrate 10 as shown in Figures 1 and 8 .

Each chip 40 is electrically connected to the first surface 21 of each first circuit layer 20. Each chip 40 has a backside 41 and an opposing connection surface 42. Each chip 40 has at least two pads 43 on the connection surface 42. Each chip 40 is electrically connected to the first circuit layer 20 via the pads 43, as shown in Figures 1 and 8. In the present invention, In a preferred embodiment of the chip package 1, the number of the die pads 43 on the chip package 1 is two, but not limited to, as shown in FIG1 . Each die 40 is first electrically connected to the first surface 21 of each first circuit layer 20 , and then electrically connected to each second circuit layer 30 through each first circuit layer 20 , so that each die 40 can be electrically connected to the outside through each second circuit layer 30 , as shown in FIG1 and FIG8 .

The insulating layer 50 is disposed on the substrate 10 and covers each of the chips 40. The insulating layer 50 has a first surface 51 and at least one opening 52. Each opening 52 of the insulating layer 50 allows the backside 41 of each chip 40 to be exposed, as shown in Figures 1 and 8.

Each first metal layer 60 is disposed on the first surface 51 of the insulating layer 50 to fully cover the entire surface. Each first metal layer 60 has a first surface 61 and at least one opening 62. Each opening 62 of each first metal layer 60 communicates with each opening 52 of the insulating layer 50, as shown in Figures 1 and 8 . Each opening 62 of each first metal layer 60 allows the backside 41 of each chip 40 to be exposed externally, as shown in Figures 1 and 8 .

Each second metal layer 70 is formed by filling each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60, and covering the backside 41 of each chip 40. A first surface 71 of each second metal layer 70 is at the same level as the first surface 61 of each first metal layer 60, as shown in Figures 1 and 8. Each second metal layer 70 is formed by filling each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60 with at least one conductive paste 70a, as shown in Figure 1. The first surface 71 of each second metal layer 70 is flattened by a polishing process, as shown in Figures 1 and 8.

Each second metal layer 70 is integrally bonded to each first metal layer 60 to form a fully protective metal layer structure that protects each first circuit layer 20, each second circuit layer 30, and each chip 40 from electromagnetic interference and directly dissipates heat from the backside 41 of each chip 40, as shown in Figures 1 and 8.

The manufacturing method of the chip package 1 includes the following steps:

Step S1: Providing a substrate 10 as shown in FIG2 ; wherein the substrate 10 has a first surface 11 and an opposite second surface 12 ; at least one first circuit layer 20 is disposed on the first surface 11 ; each first circuit layer 20 has a first surface 21 as shown in FIG2 ; wherein at least one second circuit layer 30 is disposed on the second surface 12 as shown in FIG2 .

Step S2: Place at least one chip 40 on the first surface 21 of each first circuit layer 20, as shown in FIG3 . Each chip 40 has a backside 41 and an opposing connection surface 42 , with at least two pads 43 on the connection surface 42 , as shown in FIG3 .

Step S3: An insulating layer 50 is provided on the substrate 10 so as to cover each of the chips 40 as shown in FIG4 ; wherein the insulating layer 50 has a first surface 51 as shown in FIG4 .

Step S4: At least one first metal layer 60 is disposed on the first surface 51 of the insulating layer 50 to fully cover the first surface 51, as shown in FIG5 . Each first metal layer 60 has a first surface 61, as shown in FIG5 .

Step S5: Drilling is performed simultaneously on the insulating layer 50 and each of the first metal layers 60 to form at least one opening 52 and 62 in the insulating layer 50 and each of the first metal layers 60, respectively, as shown in FIG6 . Each of the openings 52 in the insulating layer 50 exposes the backside 41 of each chip 40, as shown in FIG6 . Each of the openings 62 in the first metal layers 60 communicates with each of the openings 52 in the insulating layer 50, as shown in FIG6 .

Step S6: Fill each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60 with at least one conductive adhesive 70a, and each conductive adhesive 70a covers the backside 41 of each chip 40, as shown in FIG7 .

Step S7: Each conductive paste 70a is polished to the same level as the first surface 61 of each first metal layer 60 by a polishing process, as shown in FIG1 . After the polishing process is completed, each conductive paste 70a located within each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60 is formed into at least one second metal layer 70, as shown in FIG1 .

Referring to FIG. 1 , each of the conductive adhesives 70 a formed into each of the second metal layers 70 is silver adhesive but is not limited thereto.

Referring to Figure 8 , each second circuit layer 30 further has a first surface 31, but is not limited thereto. The chip package 1 further has at least one first outer protective layer 80 and at least one second outer protective layer 90, but is not limited thereto, to enhance structural strength. Each first outer protective layer 80 is disposed on the first surface 61 of each first metal layer 60 and the first surface 71 of each second metal layer 70. Each second outer protective layer 90 is disposed on the first surface 31 of each second circuit layer 30 and has at least one opening 91 therein. Each opening 91 exposes the first surface 31 of each second circuit layer 30 to the outside, thereby enabling electrical connection to each chip 40.

Referring to FIG1 , the substrate 10 further has at least one blind hole 13 but is not limited thereto. Each blind hole 13 is provided with a conductive line. Each first circuit layer 20 is electrically connected to each second circuit layer 30 via the conductive line in each blind hole 13. In a preferred embodiment of the chip package 1 of the present invention, the number of the blind holes 13 on the chip package 1 is two but is not limited thereto as shown in FIG1 . Each blind hole 13 of the substrate 10 is further provided with at least one third metal layer 100 filling the blind hole 13 to serve as a conductive layer for each blind hole 13. The conductive lines within the chip package are not limited to those shown in FIG1 , thereby increasing the conduction efficiency when electrically connecting the circuit layers within the chip package. The first surface 101 of each third metal layer 100 is at the same level as the first surface 21 of each first circuit layer 20 , thereby improving the yield rate. Each second circuit layer 30 is further electrically connected to each first circuit layer 20 via each third metal layer 100 , but is not limited to that shown in FIG1 . Each third metal layer 100 is made of silver, but is not limited to that.

In summary, the conductive glue 70a of the present invention is first filled in the openings 52 of the insulating layer 50 and the openings 62 of the first metal layer 60 and covered on the back surface 41 of the chip 40 as shown in FIG7 , and then the conductive glue 70a is polished to the same level as the first surface 61 of the first metal layer 60 by a polishing operation. As shown in Figure 1 , after the polishing process is completed, each second metal layer 70 is formed within each opening 52 of the insulating layer 50 and each opening 62 of the first metal layer 60. Furthermore, the first surface 71 of each second metal layer 70 is a flat surface, as shown in Figures 1 and 8 . This allows the chip package 1 of the present invention to have the following advantages over existing chip packages:

(1) The second metal layer 70 of the present invention is at the same level as the first surface 61 of the first metal layer 60, as shown in FIG1 . Furthermore, the first surface 71 of the second metal layer 70 is a flat surface, as shown in FIG1 and FIG8 . This effectively solves the problem of surface pits (i.e., unevenness) or incomplete surface of the copper heat dissipation metal layer of the existing chip, thereby improving chip packaging and enhancing the market competitiveness of the product.

(2) The second metal layers 70 of the present invention are formed in the openings 52 of the insulating layer 50 and the openings 62 of the first metal layers 60 by a grinding process, rather than forming a copper heat dissipation metal layer by a relatively complex electroplating process as in existing chip packaging, which helps to reduce manufacturing costs.

The above are merely preferred embodiments of the present invention and are illustrative rather than restrictive. Persons skilled in the art will appreciate that numerous changes, modifications, and even equivalent variations may be made within the spirit and scope of the present invention, all of which will fall within the scope of protection of the present invention.

1: Chip package 10: Substrate 11: First surface 12: Second surface 13: Blind via 20: First circuit layer 21: First surface 30: Second circuit layer 40: Chip 41: Back surface 42: Connection surface 43: Chip pad 50: Insulation layer 51: First surface 52: Opening 60: First metal layer 61: First surface 62: Opening 70: Second metal layer 70a: Conductive adhesive 71: First surface 100: Third metal layer 101: First surface

Claims (6)

A method for manufacturing a chip package comprises: step S1: providing a substrate; wherein the substrate has a first surface and an opposite second surface; wherein at least one first circuit layer is disposed on the first surface of the substrate, each of the first circuit layers having a first surface; wherein at least one second circuit layer is disposed on the second surface of the substrate; step S2: disposing at least one chip on the first surface of each of the first circuit layers; wherein each of the chips has a backside and an opposite bonding surface, and each of the chips has at least two chip pads on the bonding surface; step S3: disposing an insulating layer on the substrate so that the insulating layer covers each of the chips; wherein the insulating layer has a first surface; Step S4: Disposing at least one first metal layer on the first surface of the insulating layer to fully cover the entire surface; wherein each first metal layer has a first surface; Step S5: Simultaneously drilling holes in the insulating layer and each first metal layer to form at least one opening in each of the insulating layer and each first metal layer; wherein each opening in the insulating layer exposes the back of each chip; wherein each opening in each first metal layer is in communication with each opening in the insulating layer; Step S6: Filling each of the openings in the insulating layer and each of the openings in the first metal layer with at least one conductive paste, and each of the conductive pastes covers the backside of each of the chips; and Step S7: Polishing each of the conductive pastes until the surface level is the same as the level of the first surface of each of the first metal layers. After the polishing operation is completed, each of the conductive pastes located in each of the openings in the insulating layer and each of the openings in the first metal layer is formed into at least one second metal layer. The manufacturing method of the chip package as described in claim 1, wherein in the step S7, each of the conductive adhesives formed into each of the second metal layers is silver adhesive. A method for manufacturing a chip package as described in claim 1, wherein after step S7, each second circuit layer further has a first surface; wherein the chip package further has at least one first outer protective layer and at least one second outer protective layer; wherein each first outer protective layer is disposed on the first surface of each first metal layer and the first surface of each second metal layer; wherein each second outer protective layer is disposed on the first surface of each second circuit layer, and each second outer protective layer has at least one opening, each opening being capable of exposing the first surface of each second circuit layer to the outside. The manufacturing method of the chip package as described in claim 1, wherein in step S1, the substrate further has at least one blind hole, each blind hole has a conductive line, and each first circuit layer is electrically connected to each second circuit layer through the conductive line in each blind hole. A method for manufacturing a chip package as described in claim 4, wherein each blind hole of the substrate is further provided with at least one third metal layer filling the blind hole to serve as a conductive line in each blind hole, and the horizontal height of a first surface of each third metal layer is the same as the horizontal height of the first surface of each first circuit layer; wherein each second circuit layer is further electrically connected to each first circuit layer through each third metal layer. The method for manufacturing a chip package as described in claim 5, wherein each of the third metal layers is silver metal.