TWI894040B - Antenna - Google Patents

Abstract

An antenna device includes a transparent substrate, a thin film circuit structure, a redistribution structure, chips and antenna electrodes. The thin film circuit structure is located above a first surface of the transparent substrate and includes a first thin film conductive layer. The redistribution structure is located on the thin film circuit structure and includes a first redistribution layer. The thickness of the first thin film conductive layer is less than the thickness of the first redistribution layer. The chips are bonded to the redistribution structure. The antenna electrodes are located above the second surface of the transparent substrate opposite to the first surface. Each antenna electrode overlaps a corresponding one of the chips.

Description

Antenna device

The present invention relates to an antenna device.

Wireless communication technology is ubiquitous in modern life. Providing wireless local area networks (LANs) has become a necessity in major cities and public spaces, and many people even set up their own wireless networks at home. With advancements in wireless communication technology, many manufacturers are committed to developing higher-performance antennas. Currently, antennas contain complex circuit designs, handling a wide variety of signals. If signal lines are too close together, signals can easily interfere with each other, impacting antenna performance.

At least one embodiment of the present invention provides an antenna device comprising a transparent substrate, a thin-film circuit structure, a redistribution structure, a plurality of chips, and a plurality of antenna electrodes. The thin-film circuit structure is located on a first surface of the transparent substrate and includes a first thin-film conductive layer. The redistribution structure is located on the thin-film circuit structure and includes a first redistribution wiring layer. The thickness of the first thin-film conductive layer is less than the thickness of the first redistribution wiring layer. The plurality of chips are bonded to the redistribution wiring structure. The plurality of antenna electrodes are located on a second surface of the transparent substrate, opposite the first surface. Each antenna electrode overlaps a corresponding one of the chips.

Figure 1 is a schematic top view of an antenna device 1A according to an embodiment of the present invention. Referring to Figure 1 , antenna device 1A includes a transparent substrate 100 and a plurality of antenna units 10A disposed on transparent substrate 100. Antenna units 10A are arranged, for example, in an array. In this embodiment, at least one printed circuit board 510, 520 is electrically connected to the array of antenna units 10A via at least one flexible circuit board 610, 620, 630. Each antenna unit 10A includes an antenna electrode 110 and a chip 410A electrically connected to the antenna electrode 110.

In this embodiment, antenna device 1A includes printed circuit boards 510, 520 and flexible circuit boards 610, 620, and 630. Printed circuit boards 510, 520 are electrically connected to a redistribution structure (not shown in FIG1 ) on transparent substrate 100 via flexible circuit boards 610, 620, and 630, and further electrically connected to the array of antenna units 10A. In this embodiment, each printed circuit board 510, 520 is provided with multiple chips. In some embodiments, printed circuit boards 510 and 520 include a modulator/demodulator (MODEM), a field-programmable gate array (FPGA), a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a power module, a global positioning system (GPS), a gravity sensor, and the like. These components may be integrated into one or more chips.

In some embodiments, a modulator/demodulator is a device that encodes a digital signal (encoder) and modulates it onto an analog signal for transmission, and demodulates the received analog signal (decoder) and then decodes it back into a digital signal.

The printed circuit boards 510 and 520 are electrically connected to the array of antenna units 10A through flexible circuit boards 610, 620, and 630.

Chip 410A includes a beamformer integrated circuit (BFIC) or other active/passive components. Chip 410A can perform transmit beamforming processing (TX) and/or receive beamforming processing (RX).

In this embodiment, the antenna device 1A further includes an up/down converter (UDC) 430. The UDC 430 can be a chip connected to a redistribution structure on the transparent substrate 100 or a circuit fabricated directly on the transparent substrate 100. The printed circuit board 510 is electrically connected to the UDC 430 via a flexible circuit board 620 and the redistribution structure on the transparent substrate 100. The UDC 430 is also electrically connected to the chip 410A of the antenna unit 10A via the redistribution structure on the transparent substrate 100. For example, a relatively low-frequency signal (e.g., an intermediate frequency (IF) or low-frequency signal below 10 GHz (e.g., below 2 GHz)) provided by printed circuit board 510 is transmitted via flexible circuit board 620 to up/down converter 430, which then up/down converter 430 upconverts the signal to a high-frequency radio frequency (RF) signal (e.g., between 10 and 300 GHz). In this embodiment, because up/down converter 430 is disposed on transparent substrate 100 rather than printed circuit board 510, an SMA high-frequency cable connector (SMA connector) for transmitting RF signals is not required on transparent substrate 100.

Antenna device 1A includes a transparent region TR and a non-transparent region NTR. In some embodiments, printed circuit boards 510 and 520 are located in the non-transparent region NTR, while antenna electrode 110 and chip 410A of antenna unit 10A are located in the transparent region TR. In some embodiments, up/down converter 430 is also located in the transparent region TR. In some embodiments, antenna device 1A can be used in vehicle windows (e.g., car sunroofs) or building windows.

Figure 2 is a schematic cross-sectional view of an antenna device 1A according to an embodiment of the present invention. A transparent substrate 100 has a first surface S1 and a second surface S2 opposite to first surface S1. In some embodiments, the transparent substrate 100 is made of glass, quartz, an organic polymer, or other suitable materials. In some embodiments, the transparent substrate 100 has a thickness of 0.15 mm to 1.1 mm. For example, the transparent substrate 100 has a thickness of 0.5 mm, 0.7 mm, or 1.1 mm.

The antenna electrode 110 is disposed on the first surface S1 of the transparent substrate 100 .

A ground electrode 132 is disposed on the second surface S2 of the transparent substrate 110. In this embodiment, the ground electrode 132 has at least one opening 132h, and each opening 132h contains a bonding structure 134. The bonding structure 134 is electrically connected to the antenna electrode 110 via the substrate conductive via 120. Therefore, antenna signals from the antenna electrode 110 can be transmitted through the bonding structure 134 and the substrate conductive via 120. In other embodiments, the substrate conductive via 120 can be omitted, and the antenna signals from the antenna electrode 110 can be transmitted by radiation between the antenna electrode 110 and a driving electrode (not shown) overlapping the opening 132h.

In some embodiments, the width of the ground electrode 132 is greater than or equal to the width of the antenna electrode 110 .

In some embodiments, the materials of the antenna electrode 110 , the ground electrode 132 , the bonding structure 134 , and the substrate conductive via 120 include copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (e.g., indium tin oxide, indium zinc oxide, etc.), or other suitable materials or combinations thereof.

In some embodiments, the substrate conductive via 120 is formed by a glass modification process and a conductive material filling process. For example, the glass modification process involves first forming a through-hole in the transparent substrate 100 using a laser. This through-hole is then enlarged using a wet etching process to form a via extending from the first surface S1 to the second surface S2. Finally, the conductive material is filled into the through-hole to form the substrate conductive via 120.

In some embodiments, the method for forming the antenna electrode 110, the ground electrode 132, the bonding structure 134, and the substrate conductive via 120 includes first forming a seed layer on the first and second surfaces S1, S2, and in the vias of the transparent substrate 100 via sputtering, chemical plating, or other suitable processes. Subsequently, a metal layer is formed on the seed layer via electroplating. The resulting seed layer and metal layer can be patterned via lithography and etching processes to obtain the antenna electrode 110, the ground electrode 132, and the bonding structure 134. In other embodiments, the seed layer can be omitted.

The buffer layer 140 is disposed on the transparent substrate 100, the ground electrode 132, and the bonding structure 134. In some embodiments, the buffer layer 140 comprises a transparent material, such as an organic material (e.g., polyimide, polyethylene terephthalate, epoxy resin, etc.), an inorganic material (e.g., silicon nitride, silicon oxide, etc.), or a combination thereof. In some embodiments, since the thickness of the antenna electrode 110, the ground electrode 132, and the bonding structure 134 is 2 to 10 microns, the thickness of the buffer layer 140 is preferably 2 to 15 microns to achieve a planarization effect, and the thickness of the buffer layer 140 is not less than the thickness of the ground electrode 132. For example, the thickness of the buffer layer 140 is 1.3 times the thickness of the ground electrode 132. In order to achieve this thickness and obtain a planarization effect, the buffer layer 140 is preferably made of an organic material.

The thin film circuit structure 200 is located on the ground electrode 132 and the bonding structure 134. In this embodiment, the thin film circuit structure 200 is located on the buffer layer 140. In some embodiments, the entire thin film circuit structure 200 has a thickness of less than 10 microns.

The thin-film circuit structure 200 includes a first thin-film conductive layer 210, a first dielectric layer 220, a second thin-film conductive layer 230, and a second dielectric layer 240, which are deposited in sequence. In some embodiments, at least one contact portion PH1 of the second thin-film conductive layer 230 passes through the first dielectric layer 220 and is electrically connected to the first thin-film conductive layer 210. In some embodiments, the thin-film circuit structure 200 may include more conductive layers and dielectric layers, and the present invention is not limited to the number of conductive layers and dielectric layers in the thin-film circuit structure 200.

In some embodiments, the materials of the first thin-film conductive layer 210 and the second thin-film conductive layer 230 include copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.), or other suitable materials or combinations thereof. The first thin-film conductive layer 210 and the second thin-film conductive layer 230 each have a single-layer structure or a multi-layer structure. For example, the first thin-film conductive layer 210 and the second thin-film conductive layer 230 each have a molybdenum/aluminum/molybdenum stacked structure, a titanium/aluminum/titanium stacked structure, or a stacked structure composed of other conductive materials.

In some embodiments, the material of the first dielectric layer 220 and the second dielectric layer 240 includes an organic polymer (such as polyimide, polyethylene terephthalate, etc.) or an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, einsteinium oxide or other suitable materials or combinations thereof).

In some embodiments, before forming the second thin-film conductive layer 230, a lithography process and an etching process are used to form an opening in the first dielectric layer 220 to expose the first thin-film conductive layer 210. Then, the second thin-film conductive layer 230 is deposited in the opening to form a contact portion PH1 of the second thin-film conductive layer 230 so that the second thin-film conductive layer 230 contacts the first thin-film conductive layer 210.

The redistribution structure 300 is located on the thin film circuit structure 200. In this embodiment, the redistribution structure 300 is located on the second dielectric layer 240. In some embodiments, the overall thickness of the redistribution structure 300 is 14 microns to 150 microns.

The redistribution structure 300 includes a first redistribution layer 310, an insulating layer 320, and a second redistribution layer 330, which are deposited in sequence. In some embodiments, at least one contact portion PH2 of the first redistribution layer 310 passes through the second dielectric layer 240 and is electrically connected to the second thin-film conductive layer 230. In some embodiments, the first redistribution layer 310 and/or the second redistribution layer 330 are electrically connected to the ground electrode 132 and the bonding structure 134 via a conductive via LH1. The conductive via LH1 passes through the thin-film circuit structure 200 and the buffer layer 140, and optionally through the insulating layer 320. In some embodiments, the second redistribution layer 330 is electrically connected to the first redistribution layer 310 through at least one conductive via LH2 in the insulating layer 320. The redistribution structure 300 may further include more conductive layers and insulating layers, and the present invention does not limit the number of conductive layers and insulating layers in the redistribution structure 300.

In some embodiments, the materials of the first and second redistribution wiring layers 310 and 330 include copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (e.g., indium tin oxide, indium zinc oxide, etc.), or other suitable materials or combinations thereof. In some embodiments, the first and second redistribution wiring layers 310 and 330 each include a seed layer and a metal layer formed thereon. The seed layer is formed, for example, by sputtering, chemical plating, or other suitable methods, while the metal layer is formed by electroplating. In some embodiments, the seed layer may be omitted.

In some embodiments, the insulating layer 320 is made of an organic material (e.g., polyimide, polyethylene terephthalate, epoxy resin, etc.), an inorganic material (e.g., silicon nitride, silicon oxide, etc.), or a combination thereof. In some embodiments, the insulating layer 320 is formed by applying a dry film to the first RDL 310 or applying a liquid organic material (e.g., liquid polyimide (PI)) to the first RDL 310.

In some embodiments, the insulating layer 320 has high transmittance and low dissipation factor (Df). For example, the transmittance of the insulating layer 320 for light with a wavelength of 400 nm to 800 nm is greater than or equal to 90%. In some embodiments, the insulating layer 320 has a dielectric constant (Dk) less than 4 and a dissipation factor less than 0.004.

In some embodiments, the first RRI layer 310 of the RRI structure 300 is configured to transmit a ground signal, while the second RRI layer 330 is configured to transmit chip power signals and radio frequency (RF) signals (e.g., RF input signal (RF_in)). In some embodiments, the first and second thin film conductive layers 210 and 230 of the thin film circuit structure 200 include digital signal lines and analog signal lines, respectively, configured to transmit digital signals and analog signals used to control the chip 410A or circuits within the thin film circuit structure 200. Because the operating frequency of the digital and analog signals transmitted in the thin-film circuit structure 200 is relatively low, even if the film thicknesses of the first thin-film conductive layer 210, the first dielectric layer 220, the second thin-film conductive layer 230, and the second dielectric layer 240 in the thin-film circuit structure 200 are relatively thin, there will be no significant signal loss. In contrast, because the redistribution structure 300 is used to transmit high-frequency RF signals, the insulating layer 320 in the redistribution structure 300 needs to be thicker. Therefore, the thickness of the insulating layer 320 is greater than the thickness of the first dielectric layer 220 and the second dielectric layer 240. In some embodiments, the thickness of the insulating layer 320 is 10 microns to 60 microns. In some embodiments, the thickness of each of the first dielectric layer 220 and the second dielectric layer 240 is 0.03 microns to 1 micron, for example, 0.5 microns to 1 micron or 0.7 microns to 1 micron. In some embodiments, the thickness of each of the first thin-film conductive layer 210 and the second thin-film conductive layer 230 is less than the thickness of each of the first redistribution wiring layer 310 and the second redistribution wiring layer 330. In some embodiments, the thickness of each of the first thin-film conductive layer 210 and the second thin-film conductive layer 230 is 0.01 microns to 0.7 microns, for example, 0.01 microns to 0.3 microns or 0.01 microns to 0.05 microns. In some embodiments, the thickness of each of the first redistribution wiring layer 310 and the second redistribution wiring layer 330 is 2 microns to 10 microns.

In some embodiments, before forming the first redistribution wiring layer 310, an opening exposing the second thin-film conductive layer 230 is formed in the second dielectric layer 240 using a lithography process and an etching process. Then, the first redistribution wiring layer 310 is deposited in the opening to form a contact portion PH2 of the first redistribution wiring layer 310 so that the first redistribution wiring layer 310 contacts the second thin-film conductive layer 230.

In some embodiments, a laser drilling process is performed before forming the first redistribution wiring layer 310 and/or before forming the second redistribution wiring layer 330. For example, a laser drilling process is performed to form a laser hole, which is then filled with the first redistribution wiring layer 310 or the second redistribution wiring layer 330 to form a conductive via LH1 or a conductive via LH2. In this embodiment, the conductive via LH2 passes through the insulating layer 320, and the second redistribution wiring layer 330 contacts the first redistribution wiring layer 310 through the conductive via LH2. Conductive via LH1 passes through the insulating layer 320, the second dielectric layer 240, the first dielectric layer 220, and the buffer layer 140. The second redistribution layer 330 contacts the ground electrode 132 and the bonding structure 134 through the conductive via LH1. In this embodiment, due to the different formation methods of the contacts PH1 and PH2, the conductive vias LH1 and LH2, and the sidewalls of the substrate conductive via 120, the three have different sidewall tilt angles.

Chip 410A and up/down converter 430 are bonded to second redistribution layer 330. Each antenna electrode 110 overlaps a corresponding one of the chips 410A. In some embodiments, the width of antenna electrode 110 is greater than or equal to the width of chip 410A.

In some embodiments, the chip 410A and the up/down converter 430 are bonded to the second redistribution layer 330 via conductive connection structures 412 and 432, respectively. The conductive connection structures 412 and 432 may be, for example, solder, conductive adhesive, or other suitable structures. In some embodiments, the surface of the second redistribution layer 330 may be treated with processes such as electroless nickel immersion gold (ENIG) or immersion silver plating to improve the yield of the chip bonding process. In some embodiments, before the chip bonding process, an organic material such as an organic solderability preservative (OSP) can be formed on the second redistribution layer 330 to protect the metal pads from rusting (e.g., sulfurization or oxidation) due to contact with air, thereby improving the yield of the chip bonding process.

An underfill material 420 is formed between the chip 410A and the second redistribution layer 330, and between the up/down converter 430 and the second redistribution layer 330. In some embodiments, the underfill material 420 may include a thermal interface material (TIM) to facilitate heat dissipation from the chip 410A and the up/down converter 430. For example, the thermal conductivity of the underfill material 420 is greater than 0.3 W/mK.

In this embodiment, compared to a single chip corresponding to multiple antenna units, each chip 410A corresponds to one antenna unit 10A, distributing heat and thereby reducing the temperature of the antenna device 1A. Therefore, there is no need to install a separate heat sink on the chip 410A. In some embodiments, when the output power of the chip 410A is 60 mW and 70 mW, the surface temperature of the chip 410A is below 82 degrees Celsius and below 85.5 degrees Celsius, respectively.

By omitting the heat dissipation structure, the weight and thickness of the antenna device 1A can be significantly reduced while maintaining light transmittance, making it easier for the antenna device 1A to be integrated into a vehicle sunroof.

In some embodiments, chip 410A includes a beamformer integrated circuit (BFIC) or other active/passive components. In some embodiments, the beamformer integrated circuit includes a variable gain amplifier (VGA), a phase shifter (PS), signal control and memory circuits, a power amplifier (PA), and/or a low noise amplifier (LNA). In some embodiments, the circuits containing the active components can be located within the thin-film circuit structure 200, thereby reducing the circuitry required within chip 410A and, therefore, the size of chip 410A. For example, the signal control and memory circuits within the beamformer integrated circuit can be located within the thin-film circuit structure 200. In some embodiments, by having each antenna unit 10A include a BFIC, the signal path between the BFIC and the antenna electrode 110 can be shortened. If a single BFIC provided signals to multiple antenna electrodes 110, a longer signal path would be required, which would reduce the light-transmitting area of the antenna device. In other words, by having each antenna unit 10A include a chip 410A, the light-transmitting area LT of the antenna device 1A can be increased.

The printed circuit board 510 is electrically connected to the redistribution structure 300 via a flexible circuit board 620. For example, the flexible circuit board 620 is bonded to pads P of the second redistribution layer 330 using solder, conductive adhesive, or other suitable structures. The up/down converter 430 is electrically connected to the printed circuit board 510 and the chip 410A. The up/down converter 430 is used to convert the relatively low-frequency signal from the printed circuit board 510 into a high-frequency radio frequency (RF) signal. The high-frequency RF signal is then transmitted to the chip 410A for processing.

In some embodiments, the thin-film circuit structure 200 and the redistribution structure 300 are configured to transmit various signals. For example, ground signals (e.g., AGND, DGND, RF_GND), power signals (e.g., AVDD, DVDD), radio frequency signals (RF), radio frequency enable signals (RF_en), reference voltage signals (Vref), bias adjustment signals (Rbias), circuit control signals (e.g., CS, CLK, SDI, SDO, PDI), and antenna signals (e.g., horizontal polarization electric field antenna signal (RF_out_H), vertical polarization electric field antenna signal (RF_out_V)). In some embodiments, at least a portion of the power and circuit control signals are provided by the printed circuit board 510.

In some embodiments, the usage descriptions of various signals and the main transmission layers are shown in Table 1. Table 1 signal Description of use Main transport layer Power signal AVDD The power module provides system analog power signals to the UDC and BFIC (such as the PS, PA and/or LNA in the BFIC). Second redistribution layer Ground signal AGND Provides system analog ground signal to UDC and BFIC First redistribution layer Power signal DVDD The power module provides system digital power signals to the UDC and BFIC First and/or second thin film conductive layer Ground signal DGND Connect to the ground signal DGND to provide the system digital ground signal to the thin film circuit structure; or connect to the ground signal AGND to provide the system analog ground signal to the thin film circuit structure First and/or second thin film conductive layer RF signal Transmission between UDC and BFIC can be used to send or receive signals Second redistribution layer Ground signal RF_GND Provide RF analog ground signal to UDC and BFIC First redistribution layer and/or second redistribution layer Reference voltage signal Vref The reference voltage provided by the power module to the BFIC (such as the PS in the BFIC) First and/or second thin film conductive layer Bias adjustment signal Rbias Adjust the bias voltage of the PA and/or LNA in the BFIC Second redistribution layer Antenna signal RF_out Transmission between BFIC and antenna electrodes First and/or second redistribution layer RF enable signal RF_en Control the start and stop of the RF circuit or module to enable the antenna electrode to send or receive signals First and/or second thin film conductive layer Circuit control signal CS Provides chip select signal to BFIC to enable read/write operation First and/or second thin film conductive layer Circuit control signal CLK Provides clock signal to BFIC First and/or second thin film conductive layer Circuit control signal SDI BFIC serial data input signal First and/or second thin film conductive layer Circuit control signal SDO BFIC serial data output signal First and/or second thin film conductive layer Circuit control signal PDI BFIC parallel data input signal First and/or second thin film conductive layer

In some embodiments, at least one of the first and second RRL layers 310 and 330 includes one or more RF signal lines 334 configured to transmit RF signals to the chips 410A. For example, each RF signal line 334 is configured to transmit RF signals to the plurality of chips 410A arranged in a row via serial feed (as shown in FIG. 4 ); alternatively, the RF signal lines 334 are configured to transmit RF signals to the plurality of chips 410A arranged in a row via daisy chaining (as shown in FIG. 5 ).

In some embodiments, at least one of the first thin-film conductive layer 210 and the second thin-film conductive layer 230 includes one or more signal lines 211, 221 for transmitting low-frequency signals. Low-frequency signals can be analog or digital, and include power signals (e.g., DVDD), RF enable signals (RF_en), reference voltage signals (Vref), bias adjustment signals (Rbias), and circuit control signals (e.g., CS, CLK, SDI, SDO, PDI, etc.). In some embodiments, signal lines 211, 221 can also be referred to as analog signal lines and/or digital signal lines. The thickness of the RF signal line 334 is greater than that of the signal lines 211, 221.

Herein, low-frequency signals refer to signals operating at frequencies below 500 MHz, while high-frequency signals refer to signals operating at frequencies above 500 MHz (e.g., 10 GHz to 300 GHz or 10 GHz to 500 GHz). High-frequency signals include, for example, radio frequency (RF) signals and antenna signals (RF_out).

Figure 3 is a top view schematically illustrating an antenna device 1B according to an embodiment of the present invention. In this embodiment, antenna device 1B includes multiple antenna units 10A arrayed on a transparent substrate 100. Figure 3 illustrates chip 410A within antenna unit 10A, omitting other structures within antenna unit 10A. Note that in Figure 3, a line segment can represent a single signal line or multiple closely spaced signal lines.

In some embodiments, wavelength λ ₀ is the wavelength of the wireless signal in air that antenna unit 10A intends to receive or transmit. The pitch d between antenna units 10A is approximately half of λ _0. The range of the array of antenna units 10A can be defined by two parallel lines V1 and V2 and two other parallel lines H1 and H2. Lines H1 and H2 are perpendicular to lines V1 and V2.

Referring to Figure 3 , flexible circuit boards 610, 620, and 630 are each bonded to corresponding pads P and are used to transmit signals from one or more printed circuit boards (not shown) to thin-film circuit structures and/or redistribution structures located on transparent substrate 100. In this embodiment, flexible circuit boards 610 and 620 are located on one side of transparent substrate 100, while flexible circuit board 630 is located on the other side of transparent substrate 100, but the present invention is not limited to this. In other embodiments, flexible circuit boards 610, 620, and 630 are located on the same side of transparent substrate 100.

In some embodiments, flexible circuit board 610 is used to transmit digital signals and/or power signals provided by the printed circuit board to chip 410A of antenna unit 10A. The digital signals and/or power signals are transmitted, for example, via thin film circuit structure 200 (e.g., digital signal lines and/or power signal lines within thin film circuit structure 200).

The flexible circuit board 620 is used to transmit intermediate frequency (IF) or low frequency (LF) signals provided by the printed circuit board to the redistribution structure and up/down converter 430. After being processed by the up/down converter 430, the signals are converted into RF signals and transmitted through the redistribution structure to the chip 410A of the antenna unit 10A. The RF signals are transmitted, for example, via the second redistribution layer 330 of the redistribution structure 300 (e.g., the RF signal lines within the second redistribution layer 330).

In some embodiments, flexible circuit boards 610 and 620 are positioned between lines V1 and V2, and line H1 defines the side of the antenna element 10A array proximal to the flexible circuit boards 610 and 620. In some embodiments, the RF signal line from the up/down converter 430 to line H1 is designed with equal impedance (i.e., the impedance from the up/down converter 430 to every point on line H1 is equal). In some embodiments, the RF signal line from the up/down converter 430 is optionally distributed to different antenna elements 10A via one or more power dividers (not shown).

The flexible circuit board 630 is used to transmit power signals (e.g., AVDD) and ground signals (e.g., AGND) provided by the printed circuit board to the chip 410A of the antenna unit 10A. For example, the power signal AVDD is transmitted via the second redistribution layer 330 of the redistribution structure 300 (e.g., the power signal lines within the second redistribution layer 330). The ground signal AGND is transmitted via the first redistribution layer 310 of the redistribution structure 300 (e.g., the ground signal lines within the second redistribution layer 330).

In some embodiments, within the array of antenna units 10A (i.e., within the range between line H1 and line H2), the power signal lines, digital signal lines, and RF signal lines extend horizontally.

Figure 4 illustrates an RF signal transmission method for an antenna device according to some embodiments of the present invention. Figure 5 illustrates another RF signal transmission method for an antenna device according to some embodiments of the present invention. In the embodiment of Figure 4 , each RF signal line 334 is configured to transmit an RF signal to multiple chips 410A arranged in a row via serial feed. In the embodiment of Figure 5 , each RF signal line 334 is configured to transmit an RF signal to multiple chips 410A arranged in a row via daisy chaining.

4 and 5 , the chip 410A adopts, for example, time division duplex (TDD) technology or frequency division duplex (FDD) technology.

When chip 410A employs FDD technology, transmit beamforming processing (TX) and receive beamforming processing (RX) are performed, for example, by different antenna arrays. Chip 410A in one antenna array performs transmit beamforming processing (TX) for radio frequency signals, while chip 410A in another antenna array performs receive beamforming processing (RX).

When chip 410A utilizes TDD technology, when performing transmit beamforming (TX), RF signal line 334 provides an RF signal to chip 410A. When performing receive beamforming (RX), chip 410A provides an RF signal to RF signal line 334. In TDD technology, chips 410A in the same antenna element array perform transmit beamforming (TX) and receive beamforming (RX) at different times.

6 is a schematic diagram illustrating data writing/selection of an antenna device 1A according to some embodiments of the present invention. The antenna units 10A are arranged in an array consisting of N columns and M rows.

Signal lines Data_1 through Data_N are electrically connected to antenna units 10A in the first through Nth columns, respectively (e.g., chip 410A in antenna units 10A). Signal lines CLK_1 through CLK_N are electrically connected to antenna units 10A in the first through Nth columns, respectively (e.g., chip 410A in antenna units 10A). Signal lines CS_1 through CS_N are electrically connected to antenna units 10A in the first through Nth columns, respectively (e.g., chip 410A in antenna units 10A).

In some embodiments, signal lines Data_1 to Data_N are used to transmit at least one of circuit control signals SDI and SDO, signal lines CLK_1 to CLK_N are used to transmit circuit control signal CLK, and signal lines CS_1 to CS_N are used to transmit circuit control signal CS.

In this embodiment, data is sequentially written/selected to M rows of antenna units 10A, following steps 1, 2, 3, ..., through M. This is achieved via the circuit control signal CLK (a real-time clock signal) transmitted via signal lines CLK_1 through CLK_N. For example, signal lines CLK_1 through CLK_N simultaneously activate the first row of antenna units 10A, causing signal lines Data_1 through Data_N to transmit signals to the first row of antenna units 10A. Signal lines CLK_1 through CLK_N then transmit signals to the second row of antenna units 10A, activating the second row of antenna units 10A so that signal lines Data_1 through Data_N transmit signals to the second row of antenna units 10A.

After executing step M, the antenna array is activated using a clock signal provided by another signal line CLK_M+1 (not shown) and an RF enable signal RF_en provided by an RF enable signal line (not shown) to generate radiation.

In some embodiments, circuit control signals are transmitted to all chips 410A in a serial feed manner. The circuit control signals transmitted to chip 410A include, for example, SDI, SDO, CLK, CS, etc.

In some embodiments, the circuit control signal PDI, the RF input signal RF_in, the RF enable signal RF_en, the power signal AVDD, the power signal DVDD, the ground signal AGND, and the ground signal RF_GND are input to all chips 410A in parallel.

Figure 7 is a functional block diagram of an antenna device 1A according to an embodiment of the present invention. In this embodiment, each antenna unit 10A includes a chip 410A, which includes a BFIC.

In this embodiment, ground signals (e.g., AGND, RF_GND, etc.), power signals (e.g., AVDD, DVDD, etc.), RF signals (RF signal), RF enable signal (RF_en), reference voltage signal (Vref), and various circuit control signals (e.g., CS, CLK, SDI, SDO, PDI, etc.) are connected to chip 410A.

In this embodiment, circuit control signals are provided to the signal control circuit module SCC and the memory circuit module MC in the chip 410A. The signal control circuit module SCC provides signals to the variable gain amplifier and phase shifter module VGPS.

In this embodiment, the RF signal is processed by a power divider and then provided to a variable gain amplifier and phase shifter module VGPS. The variable gain amplifier and phase shifter module VGPS provides a signal to a power amplifier and/or a low loss amplifier module PALNA.

The power amplifier and/or low-loss amplifier module PALNA provides a first antenna signal (eg, a horizontally polarized electric field antenna signal (RF_out_H)) and a second antenna signal (eg, a vertically polarized electric field antenna signal (RF_out_V)) to the antenna electrode 110 .

In some embodiments, other passive devices PD, such as inductors, capacitors, and/or resistors, may be additionally provided in the antenna unit 10A. The passive device PD is connected to the power amplifier and/or the low-loss amplifier module PALNA of the chip 410A.

Figure 8 is a top view schematic diagram of an antenna device 1C according to an embodiment of the present invention. It should be noted that the embodiment of Figure 8 retains the same component numbers and some details as the embodiment of Figure 1 , with identical or similar components being designated by the same or similar reference numbers, and descriptions of identical technical details being omitted. For descriptions of omitted sections, please refer to the aforementioned embodiments and will not be repeated here.

Referring to FIG. 8 , an antenna device 1C includes a transparent substrate 100 and a plurality of antenna units 10C disposed on the transparent substrate 100. The antenna units 10C are arranged, for example, in an array. In this embodiment, at least one printed circuit board 510, 520 is electrically connected to the array of antenna units 10C via at least one flexible circuit board 610, 620, 630. Each antenna unit 10C includes an antenna electrode 110 and a chip 410C electrically connected to the antenna electrode 110. In this embodiment, a gate drive circuit DR connects the plurality of antenna units 10C in series. For example, the gate drive circuit DR provides a gate signal to the signal control and memory circuit in the antenna unit 10C, and the signal control and memory circuit provides a signal to the chip 410C.

FIG9 is a top view of an antenna device 1C according to an embodiment of the present invention. Referring to FIG9 , the antenna device 1C includes a transparent substrate 100 and a plurality of antenna units 10C disposed on the transparent substrate 100. The antenna units 10C are arranged in an array, for example, with light-transmitting regions LT defined between the antenna units 10C.

The thin film circuit structure 200C includes a plurality of thin film transistors T. For example, in this embodiment, a gate dielectric layer 250 is further included between the first dielectric layer 220 and the buffer layer 140. A plurality of semiconductor layers SM are further included between the gate dielectric layer 250 and the buffer layer 140.

The first thin-film conductive layer 210 is located on the gate dielectric layer 250 and includes a gate G overlapping the semiconductor layer SM. The first dielectric layer 220 covers the gate G. The second thin-film conductive layer 230 is located on the first dielectric layer 220 and includes a plurality of source/drain electrodes SD. In this embodiment, each thin-film transistor T includes a corresponding semiconductor layer SM, a corresponding gate G, and a corresponding source/drain electrode SD. In this embodiment, the thin-film transistor T is a top-gate thin-film transistor, but the present invention is not limited thereto. In other embodiments, the thin-film transistor T is a bottom-gate thin-film transistor, a double-gate thin-film transistor, or another type of thin-film transistor.

The thin film transistor T is electrically connected to the chip 410C and the signal line 221 (e.g., a digital signal line) in the thin film circuit structure 200C. The thickness of the signal line 221 is less than the thickness of the RF signal line 334. The signal line 221 is used to transmit any of the digital signals described in the previous embodiments.

Figure 10 is a top view schematic diagram of an antenna device 1D according to an embodiment of the present invention. It should be noted that the embodiment of Figure 10 uses the same component numbers and some details as the embodiment of Figure 3 , with identical or similar reference numbers used to represent identical or similar components, and descriptions of identical technical details omitted. For descriptions of omitted parts, please refer to the aforementioned embodiments and will not be repeated here.

In this embodiment, antenna device 1D includes a plurality of antenna units 10C arrayed on a transparent substrate 100. FIG10 illustrates chip 410C within antenna unit 10C, while omitting other structures within antenna unit 10C. Note that in FIG10 , a line segment can represent a single signal line or multiple closely spaced signal lines.

In some embodiments, the flexible circuit board 610 is used to transmit digital signals and/or power signals provided by the printed circuit board to the chip 410C of the antenna unit 10C. These digital signals and/or power signals are transmitted, for example, via the thin-film circuit structure 200 (e.g., digital signal lines and/or power signal lines within the thin-film circuit structure 200). Furthermore, the flexible circuit board 610 is electrically connected to the gate driver circuit DR and provides a clock signal (or gate signal) to the antenna unit 10C via the gate driver circuit DR and a plurality of signal lines CLK' (or clock signal lines or gate signal lines).

In some embodiments, the RF signal line is optionally distributed to different columns of antenna units 10C via one or more power dividers SW from the up/down converter 430. The RF signal line is designed to have equal impedance from the power divider SW to line H1 (i.e., the impedance from the power divider SW to each point on line H1 is equal).

FIG11 is a schematic diagram of data writing/selection of an antenna device 10C according to some embodiments of the present invention. The antenna units 10C are arranged in an array consisting of N columns and M rows.

The signal lines Data_1 to Data_N are electrically connected to the first to Nth row antenna units 10C, respectively (eg, signal control and memory circuits of the antenna unit 10C).

In some embodiments, the signal lines Data_1 to Data_N are used to transmit at least one of the circuit control signals SDI and SDO.

The signal lines CLK_1 to CLK_M are electrically connected to the first to Mth rows of antenna units 10C, respectively (eg, signal control and memory circuits of the antenna unit 10C).

In this embodiment, data is written/selected sequentially to M rows of antenna units 10C in accordance with steps 1, 2, 3, ..., through M. This is achieved via clock signals (which, in some embodiments, can be gate signals used to control transistors) transmitted via signal lines CLK_1 through CLK_M. Signal lines CLK_1 through CLK_M are electrically connected to a gate driver circuit DR (see FIG. 10 ).

After executing step M, the antenna array is activated using a clock signal provided by another signal line CLK_M+1 (not shown) and an RF enable signal RF_en provided by an RF enable signal line (not shown) to generate radiation.

In some embodiments, circuit control signals are transmitted horizontally to antenna units 10C in the same row. The aforementioned circuit control signals include, for example, SDI, SDO, CLK, and CS.

The clock signal (which may be referred to as a gate signal in some embodiments) is input vertically to the antenna units 10C in the same row (eg, the signal control and memory circuit or chip 410C of the antenna unit 10C).

In some embodiments, the circuit control signal PDI, the RF enable signal RF_en, the RF input signal RF_in, the power signal AVDD, the power signal DVDD, the ground signal AGND, and the ground signal RF_GND are input to all chips 410C in parallel.

Figure 12 is a functional block diagram of an antenna device 1C according to an embodiment of the present invention. In this embodiment, each antenna unit 10C includes a chip 410C and a phase control module PC (which, for example, includes signal control and memory circuits). Chip 410C includes a BFIC. Phase control module PC is implemented within a thin-film circuit structure 200C (see Figure 9) and includes multiple thin-film transistors T (or switching elements).

In this embodiment, ground signals (e.g., AGND, RF_GND), power signals (e.g., AVDD), RF signals (e.g., AVDD), and a reference voltage signal (Vref) are connected to chip 410C. Various circuit control signals (e.g., SDI, SDO, PDI), an RF enable signal (RF_en), and power signals (e.g., DVDD) are connected to the phase control module PC. Signal line CLK' is connected to the phase control modules PC of antenna units 10C in different rows.

In this embodiment, the circuit control signal is provided to the phase control module PC. The phase control module PC provides a signal to the chip 410C, such as the variable gain amplifier and phase shifter module VGPS in the chip 410C.

In this embodiment, the RF signal is processed by a divider and then provided to a variable gain amplifier and phase shifter module VGPS. The variable gain amplifier and phase shifter module VGPS provides a signal to a power amplifier and/or a low loss amplifier module PALNA.

The power amplifier and/or low-loss amplifier module PALNA provides a first antenna signal (eg, a horizontally polarized electric field antenna signal (RF_out_H)) and a second antenna signal (eg, a vertically polarized electric field antenna signal (RF_out_V)) to the antenna electrode 110 .

In some embodiments, other passive components PD, such as inductors, capacitors, and/or resistors, may be additionally provided in the antenna unit 10C. The passive components are connected to the power amplifier and/or low-loss amplifier module PALNA of the chip 410C.

Figure 13 is a schematic circuit diagram of an antenna unit according to an embodiment of the present invention. It should be noted that the embodiment of Figure 13 uses the same component numbers and some content as the embodiment of Figure 12 , with identical or similar components being designated by the same or similar reference numbers, and descriptions of identical technical content being omitted. For explanations of omitted portions, please refer to the aforementioned embodiments and will not be repeated here.

Referring to Figure 13 , in this embodiment, the signal control and memory circuit TC (i.e., the phase control module PC in Figure 12 ) includes multiple first switching elements T1, multiple first memory circuits MC1, multiple second switching elements T2, and multiple second memory circuits MC2. The first switching elements T1 are each electrically connected to the first memory circuits MC1. Each second switching element T2 is electrically connected to a corresponding one of the first memory circuits MC1 and a corresponding one of the second memory circuits MC2. The second memory circuits MC2 of the signal control and memory circuit TC are electrically connected to chip 410C.

Signal lines D1 to D5 are connected to a plurality of first switching elements T1. In some embodiments, each signal line D1 to D5 is connected to two corresponding first switching elements T1. A horizontal polarization/vertical polarization select line HVS is electrically connected to the gates of the first switching elements T1 and provides a gate signal to the gates of the first switching elements T1 to control the switching of the first switching elements T1. In some embodiments, among the ten first switching elements T1 shown in FIG13 , the top five first switching elements T1 correspond to the first memory circuit MC1 associated with the horizontally polarized electric field antenna signal (RF_out_H), while the bottom five first switching elements T1 correspond to the first memory circuit MC1 associated with the vertically polarized electric field antenna signal (RF_out_V). By making the top five first switching elements T1 and the bottom five first switching elements T1 include different types of transistors, for example, the top five first switching elements T1 may be one of an n-type transistor and a p-type transistor, while the bottom five first switching elements T1 may be the other of an n-type transistor and a p-type transistor, such that the top five first switching elements T1 and the bottom five first switching elements T1 have different on-voltages. In some embodiments, the number of first switching elements T1 can be adjusted according to needs.

The RF enable signal line is electrically connected to the gate of the second switching element T2 and provides an RF enable signal RF_en to the gate of the second switching element T2 to control the switching of the second switching element T2.

In some embodiments, the horizontal/vertical polarization select line HVS, the RF enable signal line, the signal lines D1 to D5, the first switching device T1, the first memory circuit MC1, the second switching device T2, and the second memory circuit M1 are disposed in a thin-film circuit structure 200C (see FIG. 9 ). For example, at least one of the first thin-film conductive layer 210 and the second thin-film conductive layer 220 includes the horizontal/vertical polarization select line HVS and the RF enable signal line.

In some embodiments, the circuit control signal CLK (a real-time pulse signal) provided by signal line CLK' is used to control the writing of data to the first memory circuit MC1, and the first memory circuit MC1 can be used to preload the data to be written next. The radio frequency enable signal RF_en is used to control the second memory circuit MC2, and the second memory circuit is used to maintain the current radiation state. For example, signal line CLK' in Figure 13 corresponds to signal lines CLK_1 to CLK_M in Figure 11. The gate driver circuit is electrically connected to the first memory circuit MC1 and the second memory circuit MC2 via signal line CLK'.

In some embodiments, the circuit layout of each of the first memory circuit MC1 and the second memory circuit MC2 is shown in FIG14 . Each memory circuit includes thin-film transistors M1, M2, M3, M4, M5, and M6. Thin-film transistors M1, M2, M3, M4, M5, and M6 are disposed in a thin-film circuit structure 200C (see FIG9 ). In some embodiments, a power signal DVDD is provided to thin-film transistors M2 and M4 in the memory circuits, and a circuit control signal CLK (a clock signal) is provided to thin-film transistors M5 and M6 in the memory circuits. In some embodiments, thin-film transistors M1 and M3 are connected to a ground signal.

FIG15 is a functional block diagram of an antenna device according to an embodiment of the present invention. The non-transparent region (NTR) of the antenna device includes a GPS/gravimeter module 710, a field-programmable logic gate array (FPGA) module 720, a modulator/demodulator module 730, a digital-to-analog converter (DAC) 740, an analog-to-digital converter (ADC) 750, and a power supply module 760. The GPS/gravimeter module 710, the FPGA module 720, the modulator/demodulator module 730, the DAC 740, the ADC 750, and the power supply module 760 are, for example, mounted on a printed circuit board (such as the PCBs 510 and 520 shown in FIG1 ).

In this embodiment, since the antenna device is installed on a vehicle, the vehicle computer system can provide a signal to the modulator/demodulator module 730, and the vehicle power system can provide a DC power to the power module 760.

Data/circuit control signals are transmitted between the GPS/gravimeter module 710 and the field-programmable logic gate array module 720, between the GPS/gravimeter module 710 and the modulator/demodulator module 730, between the field-programmable logic gate array module 720 and the digital-to-analog converter 740, and between the field-programmable logic gate array module 720 and the analog-to-digital converter 750.

In some embodiments, the FPLGAM module 720 can perform digital signal processing and timing management. The FPLGAM module 720 can transmit data as digital signals to the DAC 740 or receive data as digital signals from the ADC 750.

The power module 760 provides DC signals to the field-programmable logic gate array module 720, the modulator/demodulator module 730, the digital-to-analog converter 740, and the analog-to-digital converter 750. Furthermore, the power module 760 provides DC signals to the up/down converter 430 and the antenna unit 10C disposed in the transparent region TR. Examples of DC signals include ground signals (e.g., AGND, DGND, RF_GND), power signals (e.g., AVDD, DVDD), reference voltage signals (Vref), and similar signals.

The transparent region TR of the antenna device includes a gate driver circuit DR, an up/down converter 430, a power splitter SW1, and an antenna unit 10C. In this embodiment, the antenna unit 10C includes a chip 410C, a phase control module PC (e.g., including the signal control and memory circuit TC shown in FIG. 13 ), a power splitter SW2, and an antenna electrode 110.

Up/down converter 430 receives an intermediate frequency (IF) signal from digital-to-analog converter 740 or transmits an IF signal to analog-to-digital converter 750. In some embodiments, the IF signal has a frequency less than 10 GHz. Up/down converter 430 can convert the IF signal into a high-frequency RF signal, or vice versa. In some embodiments, the RF signal has a frequency greater than or equal to 10 GHz.

The RF signal is transmitted via power divider SW1 to chip 410C, where it is processed. It should be noted that chip 410C in Figure 15 utilizes TDD technology, enabling both transmit beamforming (TX) and receive beamforming (RX).

The gate driver circuit DR provides a circuit control signal (e.g., a gate signal or a clock signal) to the phase control module PC. The field-programmable logic gate array module 720 provides a circuit control signal (e.g., a clock signal) to the phase control module PC. The phase control module PC outputs the circuit control signal to the chip 410C to perform transmit beamforming processing (TX) and receive beamforming processing (RX). In some embodiments, the gate driver circuit DR and the phase control module PC may be incorporated into a thin-film circuit structure 200C (see FIG. 9 ). In some embodiments, the phase control module PC may be integrated into the chip 410C. In some embodiments, the gate driver circuit DR may be disposed in another chip and bonded to the redistribution structure 300 (see FIG. 9 ).

The power divider SW2 distributes the radio frequency signal between the chip 410C and the antenna electrode 110. In some embodiments, the power divider SW2 can be integrated into the chip 410C or disposed in the thin film circuit structure 200C (see FIG. 9 ).

In this embodiment, the GPS/gravimeter module 710, the FPLG module 720, the modulator/demodulator module 730, the DAC 740, the ADC 750, and the power module 760 are disposed in the non-transparent region NTR, but the present invention is not limited thereto. In other embodiments, one or more of the GPS/gravimeter module 710, the FPLG module 720, the modulator/demodulator module 730, the DAC 740, the ADC 750, and the power module 760 are disposed in the transparent region TR, that is, disposed on the transparent substrate 100, as shown in FIG16 .

Figure 17 is a functional block diagram of yet another antenna device according to an embodiment of the present invention. It should be noted that the embodiment of Figure 17 retains the same component numbers and some details as the embodiment of Figure 15 , with identical or similar reference numbers used to represent identical or similar components, and descriptions of identical technical details omitted. For explanations of omitted sections, please refer to the aforementioned embodiments and will not be repeated here.

The difference between the antenna device in Figure 17 and the antenna device in Figure 15 is that the chip in the antenna device in Figure 17 adopts FDD technology and uses different antenna unit arrays for transmit beamforming processing (TX) and receive beamforming processing (RX).

In the array formed by antenna unit 10C-1, up/down converter 430-1 provides an RF signal to chip 410C-1, which performs transmit beamforming processing (TX). Antenna 110-1 outputs a corresponding radiated signal. In some embodiments, gate driver circuit DR1 provides a circuit control signal (e.g., a gate signal or a clock signal) to phase control module PC1, and field programmable logic gate array module 720 provides a circuit control signal (e.g., a clock signal) to phase control module PC1. Phase control module PC1 outputs the circuit control signal to chip 410C-1, which performs transmit beamforming processing (TX).

In the array formed by antenna units 10C-2, antenna 110-2 receives the corresponding radiated signal. Chip 410C-2 performs receive beamforming (RX). Up/down converter 430-2 receives the RF signal from chip 410C-2. In some embodiments, gate driver circuit DR2 provides a circuit control signal (e.g., a gate signal or a clock signal) to phase control module PC2, and field programmable logic gate array module 720 provides a circuit control signal (e.g., a clock signal) to phase control module PC2. Phase control module PC2 outputs the circuit control signal to chip 410C-2, which performs receive beamforming (RX).

In some embodiments, the array formed by the antenna units 10C- 1 and the array formed by the antenna units 10C- 2 may be disposed in different regions on the same transparent substrate 100 , or may be disposed on two transparent substrates 100 , respectively.

In summary, the antenna device of the present invention includes a thin-film circuit structure, wherein a thin-film conductive layer is used to transmit circuit control signals. Due to the thinness of the thin-film conductive layer, the overall thickness of the antenna device can be reduced. Furthermore, since each antenna unit contains its own chip, heat sources within the antenna device can be dispersed.

1A, 1B, 1C, 1D: Antenna device 10A, 10C, 10C-1, 10C-2: Antenna unit 100: Transparent substrate 110, 110-1, 110-2: Antenna electrodes 120: Substrate conductive via 132: Ground electrode 132h: Opening 134: Bonding structure 140: Buffer layer 200, 200C: Thin-film circuit structure 210: First thin-film conductive layer 211, 221, D1, D2, D3, D4, D5, CLK’, CLK_1, CLK_N, CLK_M, CS_1, CS_N, Data_1, Data_N: Signal lines 220: First dielectric layer 230: Second thin-film conductive layer 240: Second dielectric layer 250: Gate dielectric layer 300: Redistribution structure 310: First redistribution layer 320: Insulation layer 330: Second redistribution layer 334: RF signal line 410A, 410C, 410C-1, 410C-2: Chip 412, 432: Conductive connection structure 420: Underfill material 430, 430-1, 430-2: Up/down converter 510, 520: Printed circuit board 610, 620, 630: Flexible circuit board 710: GPS/gravity meter module 720: Field-programmable logic gate array module 730: Modulator/demodulator module 740: Digital-to-analog converter 750: Analog-to-digital converter 760: Power supply module DR, DR1, DR2: Gate driver circuit G: Gate HVS: Horizontal polarization/vertical polarization select line H1, H2, V1, V2: Lines LH1, LH2: Conductive vias LT: Light-transmitting region M1, M2, M3, M4, M5, M6, T: Thin-film transistors MC: Memory circuit module MC1: First memory circuit MC2: Second memory circuit NTR: Non-transparent region P: Pad PALNA: Power amplifier and/or low-loss amplifier module PC, PC1, PC2: Phase control module PD: Passive device PH1, PH2: Contacts RX: Receive beamforming processing S1: Side 1 S2: Side 2 SCC: Signal control circuit module SD: Source/Drain SM: Semiconductor layer SW, SW1, SW2: Power divider T1: First switching element T2: Second switching element TC: Signal control and memory circuit TR: Transparent region TX: Transmit beamforming processing VGPS: Variable gain amplifier and phase shifter module

Figure 1 is a schematic top view of an antenna device according to an embodiment of the present invention. Figure 2 is a schematic cross-sectional view of an antenna device according to an embodiment of the present invention. Figure 3 is a schematic top view of an antenna device according to an embodiment of the present invention. Figure 4 illustrates radio frequency signal transmission methods of some antenna devices according to some embodiments of the present invention. Figure 5 illustrates radio frequency signal transmission methods of other antenna devices according to some embodiments of the present invention. Figure 6 is a schematic diagram of data writing/selection of an antenna device according to some embodiments of the present invention. Figure 7 is a functional block diagram of an antenna device according to an embodiment of the present invention. Figure 8 is a schematic top view of an antenna device according to an embodiment of the present invention. Figure 9 is a schematic cross-sectional view of an antenna device according to an embodiment of the present invention. Figure 10 is a schematic top view of an antenna device according to an embodiment of the present invention. Figure 11 is a schematic diagram of data writing/selection in an antenna device according to some embodiments of the present invention. Figure 12 is a functional block diagram of an antenna device according to an embodiment of the present invention. Figure 13 is a schematic circuit diagram of an antenna unit according to an embodiment of the present invention. Figure 14 is a schematic circuit diagram of a memory circuit of an antenna unit according to an embodiment of the present invention. Figure 15 is a functional block diagram of an antenna device according to an embodiment of the present invention. Figure 16 is a functional block diagram of another antenna device according to an embodiment of the present invention. Figure 17 is a functional block diagram of yet another antenna device according to an embodiment of the present invention.

1A: Antenna device

10A: Antenna unit

100:Transparent substrate

110: Antenna Electrode

410A: Chip

430: Up/Down Converter

510,520: Printed circuit board

610, 620, 630: Flexible circuit boards

NTR: Non-transparent region

TR: Transparent Zone

Claims (14)

An antenna device includes: a transparent substrate; a thin-film circuit structure disposed on a first surface of the transparent substrate and including a first thin-film conductive layer; a redistribution wiring structure disposed on the thin-film circuit structure and including a first redistribution wiring layer, wherein the thickness of the first thin-film conductive layer is less than the thickness of the first redistribution wiring layer; a plurality of chips bonded to the redistribution wiring structure; and a plurality of antenna electrodes disposed on a second surface of the transparent substrate opposite the first surface, with each antenna electrode overlapping a corresponding one of the chips. The antenna device of claim 1, wherein the thin film circuit structure includes a signal control and memory circuit, wherein the signal control and memory circuit is electrically connected to one of the chips. The antenna device as described in claim 2, wherein the signal control and memory circuit includes a plurality of first switch elements and a plurality of first memory circuits, and the first switch elements are electrically connected to the first memory circuits respectively. In the antenna device of claim 3, a gate drive circuit is electrically connected to the first memory circuits. The antenna device as described in claim 3, wherein the signal control and memory circuit further includes a plurality of second switching elements and a plurality of second memory circuits, each of the second switching elements being electrically connected to a corresponding one of the first memory circuits and a corresponding one of the second memory circuits. The antenna device as described in claim 5, wherein the thin film circuit structure further includes a second thin film conductive layer, wherein one of the first thin film conductive layer and the second thin film conductive layer includes an RF enable signal line, and the RF enable signal line is electrically connected to the gates of the second switch elements. The antenna device of claim 1 further comprises: At least one printed circuit board and at least one flexible circuit board, the at least one printed circuit board being electrically connected to the redistribution structure via the at least one flexible circuit board, wherein the at least one printed circuit board is disposed in a non-transparent region of the antenna device, and the antenna electrodes and the chips are disposed in a transparent region of the antenna device. The antenna device of claim 7, wherein the at least one printed circuit board comprises a field programmable logic gate array module. The antenna device of claim 7 further comprises: An up/down converter electrically connected to the at least one printed circuit board and the chips, and the up/down converter is disposed in the transparent region. The antenna device as described in claim 1, wherein the redistribution structure further includes a second redistribution layer, wherein at least one of the first redistribution layer and the second redistribution layer includes one or more RF signal lines, wherein the one or more RF signal lines are configured to transmit RF signals to multiple of the chips in a daisy-chain manner. The antenna device as described in claim 1, wherein the redistribution structure further includes a second redistribution layer, wherein at least one of the first redistribution layer and the second redistribution layer includes one or more RF signal lines, wherein the one or more RF signal lines are configured to transmit RF signals to multiple of the chips via serial feeding. The antenna device as described in claim 1 further includes a field programmable logic gate array module disposed on the transparent substrate. An antenna device as described in claim 1, wherein the thin film circuit structure includes a second thin film conductive layer, wherein at least one of the first thin film conductive layer and the second thin film conductive layer includes one or more digital signal lines, and the redistribution structure further includes a second redistribution layer, wherein at least one of the first redistribution layer and the second redistribution layer includes one or more radio frequency signal lines, wherein the thickness of the one or more radio frequency signal lines is greater than the thickness of the one or more digital signal lines, and wherein the one or more radio frequency signal lines are configured to transmit radio frequency signals to multiple of the chips. The antenna device of claim 13, wherein the one or more digital signal lines are configured to transmit digital signals to the plurality of chips.