TWI893884B - Voltage and frequency control system, method, computer-readable storage medium - Google Patents

Abstract

The disclosure relates to a voltage and frequency control system, method, computer-readable storage medium, the system comprises a delay detection module used for detecting the circuit delay of the calculation module in real-time; the frequency control module is used for controlling the frequency of the clock signal output to the calculation module according to the current power supply voltage and the circuit delay; the performance statistics module is used for periodically detecting the performance of the calculation module and obtaining the actual performance; the performance and power consumption level control module is used for controlling the power supply voltage output to the frequency control module and the calculation module according to the performance target and the actual performance.

Description

Voltage and frequency control system, method, and computer-readable storage medium

The present disclosure relates to the field of chips, and more particularly to a voltage and frequency control system, method, and computer-readable storage medium.

Data centers, workstations, high-performance computers, and mobile devices often utilize system-on-chips (SoCs). Therefore, SoC power management has always been a matter of great concern. Enabling SoCs to deliver the highest computing performance within a given power budget, or minimizing power consumption while meeting certain computing requirements, is a key goal in optimizing device performance.

The performance and power consumption of an SoC are directly related to the supply voltage and operating frequency of its primary functional components (i.e., the computing module). Traditional power control solutions require a significant amount of time to determine the optimal supply voltage and operating frequency, resulting in long control cycles, low efficiency, and poor accuracy, hindering the full performance of the chip.

In view of this, the present disclosure proposes a voltage and frequency control system, method, and computer-readable storage medium. According to the voltage and frequency control system of the embodiments of the present disclosure, real-time frequency control in the inner loop is used to reduce circuit timing redundancy, maximize performance, and optimize control efficiency. Periodic voltage control and periodic frequency control in the outer loop are used to improve control accuracy, thereby achieving better performance improvement or power consumption reduction.

According to one aspect of the present disclosure, a voltage and frequency control system is provided, the system comprising a delay detection module, a frequency control module, a performance statistics module, and a performance and power consumption level control module. The system is used to control the clock frequency and power supply voltage of a computing module. The delay detection module is used to detect the circuit delay of the computing module in real time and output the circuit delay to the frequency control module. The frequency control module is used to adjust the circuit delay according to the current power supply voltage and the circuit. The module controls the frequency of the clock signal output to the computing module, and the current power supply voltage is provided by the performance and power consumption level control module. The performance statistics module is used to periodically detect the performance of the computing module, obtain the actual performance and output it to the performance and power consumption level control module. The performance and power consumption level control module is used to control the power supply voltage output to the frequency control module and the computing module according to a preset performance target and the actual performance.

In one possible implementation, the delay detection module and the computing module physically maintain the same operating conditions of process characteristics, power supply voltage, and device temperature. The real-time detection of the circuit delay of the computing module includes: real-time detection of its own circuit delay under the current working conditions of process characteristics, current power supply voltage, and current device temperature as the circuit delay of the computing module.

In one possible implementation, controlling the frequency of the clock signal output to the computing module based on the current power supply voltage and the circuit delay includes: determining a maximum frequency under the current power supply voltage and the circuit delay, and controlling the frequency of the clock signal output to the computing module to be equal to the maximum frequency.

In one possible implementation, when the difference between the performance target and the actual performance is greater than a first threshold, the performance and power consumption level control module is further used to output a first clock control instruction to the frequency control module; the frequency control module is further used to control the frequency value of the clock signal to increase by a second threshold according to the first clock control instruction; when the difference between the actual performance and the performance target is greater than the first threshold, the performance and power consumption level control module is further used to output a second clock control instruction to the frequency control module; the frequency control module is further used to control the frequency value of the clock signal of the computing module to decrease by a third threshold according to the second clock control instruction.

In one possible implementation, the performance and power consumption level control module is pre-set with multiple levels of voltage values, and the higher the voltage level, the larger the voltage value. The power supply voltage output to the frequency control module and the calculation module is controlled according to the preset performance target and the actual performance, including: when the performance target is greater than the actual performance, the voltage value level of the output power supply voltage is controlled to increase; when the performance target is less than the actual performance, the voltage value level of the output power supply voltage is controlled to decrease.

In one possible implementation, the system further includes a power consumption statistics module, which is used to periodically detect the power consumption of the computing module, obtain actual power consumption and output it to the frequency control module and the performance and power consumption level control module; the frequency control module is also used to control the frequency of the clock signal output to the computing module based on a preset power consumption benchmark and the actual power consumption, so that the first power consumption estimate of the computing module when operating at the frequency does not exceed the power consumption benchmark; the performance and power consumption level control module is also used to control the power supply voltage output to the frequency control module and the computing module based on the preset power consumption benchmark and the actual power consumption.

In one possible implementation, controlling the frequency of the clock signal output to the computing module based on a preset power consumption benchmark and the actual power consumption includes: when the difference between the actual power consumption and the power consumption benchmark is greater than a fourth threshold, controlling the frequency of the output clock signal to be equal to the product of the maximum frequency and a preset coefficient, where the value of the preset coefficient is less than 1.

In one possible implementation, the performance and power consumption level control module is pre-set with multiple levels of voltage values, and the higher the voltage level, the greater the voltage value. The control of the power supply voltage output to the frequency control module and the calculation module based on the preset performance target and the actual performance includes: when the performance target is greater than the actual performance, determining the voltage value level of the first target power supply voltage, so that the voltage value level of the first target power supply voltage is higher than the voltage value level of the current power supply voltage; when the performance target is less than the actual performance, determining the first target power supply voltage voltage level of the first target power supply voltage so that the voltage level of the first target power supply voltage is lower than the voltage level of the current power supply voltage; determining a first power consumption estimate when the calculation module operates under the first target power supply voltage; when the first power consumption estimate is less than the power consumption baseline, controlling the power supply voltage output to the frequency control module and the calculation module to be equal to the first target power supply voltage; when the first power consumption estimate is greater than the power consumption baseline, controlling the power supply voltage output to the frequency control module and the calculation module according to a preset power consumption baseline and the actual power consumption.

In one possible implementation, controlling the power supply voltage output to the frequency control module and the computing module based on a preset power consumption benchmark and the actual power consumption includes: when the difference between the actual power consumption and the power consumption benchmark is greater than a fifth threshold, determining a voltage value level of a second target power supply voltage so that a second power consumption estimate of the computing module when operating at the second target power supply voltage is less than the power consumption benchmark and the difference between the second power consumption estimate and the power consumption benchmark is minimized; and controlling the power supply voltage output to the frequency control module and the computing module to be equal to the second target power supply voltage.

In one possible implementation, the performance and power consumption level control module is further used to obtain an analysis report at the end of the current cycle based on one or more of the actual performance, actual power consumption, changes in the output power supply voltage, and output instructions obtained in the current cycle. The analysis report is used to adjust the performance target and the power consumption benchmark used in the next cycle.

According to another aspect of the present disclosure, a voltage and frequency control method is provided. The method is applied to a voltage and frequency control system. The system includes a delay detection module, a frequency control module, a performance statistics module, and a performance and power consumption level control module. The system is used to control the clock frequency and power supply voltage of a computing module. The method includes: the delay detection module detects the circuit delay of the computing module in real time and outputs the circuit delay to the frequency control module; the frequency control module The frequency of the clock signal output to the computing module is controlled based on the current power supply voltage and the circuit delay, wherein the current power supply voltage is provided by the performance and power consumption level control module. The performance statistics module periodically detects the performance of the computing module, obtains the actual performance and outputs it to the performance and power consumption level control module. The performance and power consumption level control module controls the power supply voltage output to the frequency control module and the computing module based on a preset performance target and the actual performance.

In one possible implementation, the delay detection module and the computing module physically maintain the same operating conditions of process characteristics, power supply voltage, and device temperature. The real-time detection of the circuit delay of the computing module includes: real-time detection of its own circuit delay under the current working conditions of process characteristics, current power supply voltage, and current device temperature as the circuit delay of the computing module.

In one possible implementation, controlling the frequency of the clock signal output to the computing module based on the current power supply voltage and the circuit delay includes: determining a maximum frequency under the current power supply voltage and the circuit delay, and controlling the frequency of the clock signal output to the computing module to be equal to the maximum frequency.

In one possible implementation, the method further includes: when the difference between the performance target and the actual performance is greater than a first threshold, the performance and power consumption level control module outputs a first clock control instruction to the frequency control module; the frequency control module controls the frequency value of the clock signal to increase by a second threshold based on the first clock control instruction; when the difference between the actual performance and the performance target is greater than the first threshold, the performance and power consumption level control module outputs a second clock control instruction to the frequency control module; the frequency control module controls the frequency value of the clock signal of the computing module to decrease by a third threshold based on the second clock control instruction.

In one possible implementation, the performance and power consumption level control module is pre-set with multiple levels of voltage values, and the higher the voltage level, the larger the voltage value. The power supply voltage output to the frequency control module and the calculation module is controlled according to the preset performance target and the actual performance, including: when the performance target is greater than the actual performance, the voltage value level of the output power supply voltage is controlled to increase; when the performance target is less than the actual performance, the voltage value level of the output power supply voltage is controlled to decrease.

In one possible implementation, the system further includes a power consumption statistics module, and the method further includes: the power consumption statistics module periodically detects the power consumption of the computing module, obtains actual power consumption and outputs it to the frequency control module and the performance and power consumption level control module; the frequency control module controls the frequency of the clock signal output to the computing module based on a preset power consumption benchmark and the actual power consumption, so that a first power consumption estimate of the computing module when operating at the frequency does not exceed the power consumption benchmark; the performance and power consumption level control module controls the power supply voltage output to the frequency control module and the computing module based on the preset power consumption benchmark and the actual power consumption.

In one possible implementation, controlling the frequency of the clock signal output to the computing module based on a preset power consumption benchmark and the actual power consumption includes: when the difference between the actual power consumption and the power consumption benchmark is greater than a fourth threshold, controlling the frequency of the output clock signal to be equal to the product of the maximum frequency and a preset coefficient, where the value of the preset coefficient is less than 1.

In one possible implementation, the performance and power consumption level control module is pre-set with multiple levels of voltage values, and the higher the voltage level, the greater the voltage value. The control of the power supply voltage output to the frequency control module and the calculation module based on the preset performance target and the actual performance includes: when the performance target is greater than the actual performance, determining the voltage value level of the first target power supply voltage, so that the voltage value level of the first target power supply voltage is higher than the voltage value level of the current power supply voltage; when the performance target is less than the actual performance, determining the first target power supply voltage voltage level of the first target power supply voltage so that the voltage level of the first target power supply voltage is lower than the voltage level of the current power supply voltage; determining a first power consumption estimate when the calculation module operates under the first target power supply voltage; when the first power consumption estimate is less than the power consumption baseline, controlling the power supply voltage output to the frequency control module and the calculation module to be equal to the first target power supply voltage; when the first power consumption estimate is greater than the power consumption baseline, controlling the power supply voltage output to the frequency control module and the calculation module according to a preset power consumption baseline and the actual power consumption.

In one possible implementation, controlling the power supply voltage output to the frequency control module and the computing module based on a preset power consumption benchmark and the actual power consumption includes: when the difference between the actual power consumption and the power consumption benchmark is greater than a fifth threshold, determining a voltage value level of a second target power supply voltage so that a second power consumption estimate of the computing module when operating at the second target power supply voltage is less than the power consumption benchmark and the difference between the second power consumption estimate and the power consumption benchmark is minimized; and controlling the power supply voltage output to the frequency control module and the computing module to be equal to the second target power supply voltage.

In one possible implementation, the method further includes: at the end of the current cycle, the performance and power consumption level control module obtains an analysis report based on one or more of the actual performance, actual power consumption, changes in the output power supply voltage, and output instructions obtained in the current cycle, and the analysis report is used to adjust the performance target and the power consumption benchmark used in the next cycle.

According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

According to another aspect of the present disclosure, a computer program product is provided, comprising a computer-readable code, or a computer-readable storage medium carrying the computer-readable code. When the computer-readable code is executed in a processor of an electronic device, the processor in the electronic device executes the above method.

According to the voltage and frequency control system of the disclosed embodiment, the time required to detect circuit delay is greatly reduced compared to detecting process, power supply voltage, and temperature, thereby improving detection efficiency. The circuit delay characteristics determine the maximum operating clock frequency of the calculation module under a certain power supply voltage. Therefore, the frequency control module uses the power supply voltage and delay to control the frequency of the clock signal, and can achieve the same accuracy as using the process, power supply voltage, and temperature to determine the frequency of the clock signal. The real-time acquisition of circuit delay enables the frequency control module to also achieve real-time frequency control, thereby improving frequency control efficiency while ensuring accuracy. The performance statistics module periodically monitors the performance of the compute module, obtains actual performance, and outputs this information to the performance and power level control module. Based on preset performance targets and actual performance, the performance and power level control module controls the supply voltage output to the frequency control module and the compute module, achieving periodic supply voltage control and forming a closed control loop. Because control is based on preset performance targets and actual performance, supply voltage control is more accurate. Since supply voltage has a direct impact on the frequency of the clock signal, this allows for more precise regulation of both the supply voltage and the clock signal frequency. The voltage and frequency control system of the disclosed embodiment reduces circuit timing redundancy, maximizes performance, and optimizes control efficiency through real-time frequency control by the inner-loop delay detection module and frequency control module. Cyclic voltage control and cyclic frequency control by the outer-loop performance statistics module and performance and power consumption level control module improve control accuracy, thereby achieving both performance and control efficiency improvements. Therefore, the combination of the inner and outer loops achieves both efficiency and accuracy, resulting in even greater performance improvements.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Various exemplary embodiments, features, and aspects of the present disclosure are described in detail below with reference to the accompanying drawings. Like reference numerals in the drawings indicate elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, to better illustrate this disclosure, numerous specific details are provided in the specific embodiments below. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of this disclosure.

Several traditional power consumption control solutions are introduced below.

The earliest power consumption control solution was dynamic voltage and frequency scaling (DVFS). Its basic idea is to dynamically adjust the chip's supply voltage and operating clock frequency based on the application's computing power requirements. When the computing load is heavy and high performance is required, the supply voltage and operating clock frequency are increased to ensure performance is met. When the computing load is light and high performance is not required, the supply voltage and operating clock frequency are minimized to reduce power consumption, achieving the goal of ensuring system performance while minimizing power consumption.

The supply voltage and operating clock frequency of DVFS are typically pre-set, but their alignment with actual application scenarios is poor. Building on dynamic voltage and frequency scaling (DVFS), existing technologies have proposed adaptive voltage and frequency scaling (AVFS). This solution controls the optimal supply voltage and operating clock frequency for each chip based on its process characteristics, operating temperature fluctuations, power supply fluctuations, and power supply noise. This maximizes the operating clock frequency to deliver the highest computing performance. While meeting performance requirements, it minimizes product power consumption, or provides higher computing performance within a given power budget.

The following introduces two control systems that use AVFS in existing technologies.

The control system of prior art 1 determines the operating clock frequency of the computing module based on performance targets and outputs this operating clock frequency information to the AVFS controller via instructions. Based on the instructions, the AVFS controller controls sensors to sample the chip's process temperature (P), temperature (T), and voltage (V) in real time, and obtains the sampled process temperature (P), temperature (T), and voltage (V). The AVFS controller is pre-configured with a frequency-voltage configuration table simulated based on measured data. This frequency-voltage configuration table indicates the optimal operating clock frequency and supply voltage for various combinations of process temperature (P), temperature (T), and voltage (V). Therefore, by combining the currently sampled process P, temperature T, voltage V, and the preset frequency-voltage configuration table, it is possible to determine the value to which the supply voltage needs to be controlled. This supply voltage and the operating clock frequency determined according to the performance target are then applied to the computing module.

Existing technology solutions rely on sensors to separately detect chip process, voltage, temperature, and other information. This detection process takes time, which limits the speed of voltage and frequency control. This results in a long overall control cycle (typically on the order of several milliseconds or tens of milliseconds), preventing timely optimization of power consumption and performance. On the other hand, the statistical process for frequency-voltage configuration tables is very complex, requiring fitting based on a large amount of measured data. This measured data is typically collected from multiple different chips under different combinations of process P, temperature T, and voltage V. The fitting method simply uses a single rule to provide a global approximation for all data samples (such as meeting the minimum mean square error). As a result, the fitting result may not be optimal for a specific chip, and sometimes the deviation is quite large, resulting in the inability to guarantee the accuracy of voltage and frequency control. Therefore, there may be performance headroom of varying degrees for the characteristics of a particular chip.

Based on the control system of the existing technology one, the control system of the existing technology two adds registers that can cache process P, temperature T, and voltage V, and enables the sensor to periodically collect process P, temperature T, and voltage V and cache them in the register. Each time the AVFS controller receives a frequency modulation instruction, it can directly obtain the process P, temperature T, and voltage V stored in the register and perform subsequent processing. For the entire workflow, the control cycle of a single voltage and frequency can be reduced, but the degree of reduction is very limited, still in the millisecond level. The pre-cached process P, temperature T, and voltage V are not necessarily consistent with the actual process P, temperature T, and voltage V when the instruction is received, which may make the accuracy of voltage and frequency control worse.

In summary, traditional power consumption control schemes consume considerable time to determine the optimal supply voltage and operating clock frequency, resulting in long control cycles, low control efficiency, and poor accuracy, which in turn prevents the chip from fully utilizing its performance.

In light of this, the present disclosure proposes a voltage and frequency control system, method, and computer-readable storage medium. According to the voltage and frequency control system of the disclosed embodiments, real-time frequency control in the inner loop is used to reduce circuit timing redundancy, maximize performance, and optimize control efficiency. Cyclic voltage and frequency control in the outer loop is used to improve control accuracy, thereby achieving both performance and control efficiency improvements.

Furthermore, when additional power consumption requirements are met, the outer loop's cyclic voltage control and cyclic frequency control can be combined with power consumption requirements to control voltage, further reducing power consumption and improving the system's performance-to-power ratio.

Figure 1 shows a schematic diagram of the structure of a voltage and frequency control system according to an embodiment of the present disclosure. Below, an exemplary application scenario of the voltage and frequency control system is introduced in conjunction with Figure 1.

As shown in Figure 1, the voltage and frequency control system may include a delay detection module 10, a frequency control module 20, a performance statistics module 30, and a performance and power consumption level control module 40. These modules can be implemented using either software or hardware, and this disclosure does not limit this.

This application scenario also includes a hardware computing module 50, which can be a functional module within a system-on-a-chip (SoC) that provides computing power, such as a processor core. The performance of the computing module 50 depends on its operating clock frequency; higher clock frequencies result in higher performance. The power consumption of the computing module 50 is affected by the supply voltage and operating clock frequency, with higher supply voltages and higher clock frequencies resulting in higher power consumption. The voltage and frequency control system is used to control the clock frequency and supply voltage of the computing module 50 to ensure that its power consumption or performance meets requirements.

The computing module 50 typically operates under certain process, power supply voltage, and device temperature conditions. These conditions vary between different chips. Even on the same chip, even with the same process, the power supply voltage and device temperature conditions can vary at different times. These conditions directly affect the circuit delay of the computing module 50, which in turn determines the maximum operating clock frequency of the computing module 50.

In the disclosed embodiment, the delay detection module 10 and the computing module 50 operate under the same process, power supply voltage, and device temperature conditions. That is, if the delay detection module 10 itself is a hardware module, it can be located in the same silicon region or electronic device as the computing module 50. To ensure that the delay detection module 10 and the computing module 50 maintain the same temperature, the delay detection module 10 (or the processor implementing the delay detection module 10) and the computing module 50 can be physically located in close proximity. In the example of FIG1 , the delay detection module 10 can be a hardware module, and both the computing module 50 and the delay detection module 10 can be located on the electronic device 1.

When the frequency control module 20, performance statistics module 30, and performance and power consumption level control module 40 are hardware modules, they can be located in the silicon region or electronic device where the computing module 50 is located, or they can be located on another electronic device that can communicate with the electronic device where the computing module 50 is located. In the example of Figure 1, the frequency control module 20, performance statistics module 30, and performance and power consumption level control module 40 can be located together on electronic device 2, which can communicate with electronic device 1. The frequency control module 20 and performance statistics module 30 can be hardware modules, while the performance and power consumption level control module 40 can be a software module. The performance and power consumption level control module 40 can be implemented by a processor (not shown) on electronic device 2.

The delay detection module 10 can communicate with the frequency control module 20 and the computing module 50. The frequency control module 20 can communicate with the delay detection module 10 and the performance and power level control module 40. The performance statistics module 30 can communicate with the performance and power level control module 40 and the computing module 50. The performance and power level control module 40 can communicate with the frequency control module 20 and the performance statistics module 30. The computing module 50 can communicate with the delay detection module 10, the frequency control module 20, and the performance statistics module 30. For details on these communications, please refer to the description of FIG. 2 below.

The following describes an exemplary operation of the voltage and frequency control system according to an embodiment of the present disclosure. FIG2 shows an exemplary operation of the voltage and frequency control system according to an embodiment of the present disclosure.

As shown in FIG2 , in one possible implementation, the delay detection module 10 is used to detect the circuit delay of the computing module 50 in real time and output the circuit delay to the frequency control module 20; the frequency control module 20 is used to control the frequency of the clock signal output to the computing module 50 based on the current supply voltage and circuit delay, where the current supply voltage is provided by the performance and power consumption level control module 40; the performance statistics module 30 is used to periodically detect the performance of the computing module 50, obtain the actual performance, and output it to the performance and power consumption level control module 40; the performance and power consumption level control module 40 is used to control the supply voltage output to the frequency control module 20 and the computing module 50 based on a preset performance target and actual performance, so that the final actual performance approaches the performance target.

For example, in the disclosed embodiment, the delay detection module 10 and the frequency control module 20 jointly implement real-time inner-loop control of the frequency of the clock signal of the computing module 50, and the frequency control module 20, the performance statistics module 30, and the performance and power consumption level control module 40 jointly implement periodic outer-loop control of the power supply voltage and the frequency of the clock signal of the computing module 50.

The following describes an exemplary method of inner-loop control of the frequency of the clock signal of the computing module 50 according to the disclosed embodiment in conjunction with FIG2 .

In one possible implementation, the delay detection module 10 and the computing module 50 physically maintain the same operating conditions of process characteristics, power supply voltage, and device temperature, and detect the circuit delay of the computing module in real time, including: real-time detection of its own circuit delay under the current process characteristics, current power supply voltage, and current device temperature operating conditions as the circuit delay of the computing module 50.

For example, because delay detection module 10 and calculation module 50 are subject to the same process, power supply voltage, and device temperature, the circuit delay of delay detection module 10 and calculation module 50 at the same moment are consistent. In this case, delay detection module 10 can instantly detect its own circuit delay under the current process, power supply voltage, and temperature conditions and output the detected circuit delay to frequency control module 20. Circuit delay detection can be implemented based on existing technologies. For example, conventional key timing path analogy methods can be used. This involves analogizing the key timing path in calculation module 50 and using a delay detection chain composed of minimum delay units to detect changes in the path timing, thereby determining the circuit delay based on the timing changes. Alternatively, a fixed-frequency clock signal can be used, and a delay detection chain composed of minimum delay units can be used to detect changes in the rising or falling edges of the clock signal, thereby determining the circuit delay based on the changes in the rising or falling edges of the clock signal. Circuit delay can be represented by a multi-bit binary code (the larger the circuit delay, the larger the decimal value corresponding to the binary code) and provided to frequency control module 20. The detection time cost of circuit delay is very low, usually in the nanosecond level.

Because the delay detection module and the calculation module use the same process, power supply voltage, and device temperature, the circuit delay of the delay detection module itself and the circuit delay of the calculation module can be consistent. By detecting the circuit delay of the delay detection module itself, the circuit delay of the calculation module can be detected, which can further reduce time costs and improve control efficiency.

Those skilled in the art should understand that there are many ways to implement circuit delay detection. As long as the circuit delay can promptly reflect changes in process, power supply voltage, and device temperature conditions, and can promptly reflect the circuit delay of the calculation module 50, this disclosure does not limit the specific detection method adopted by the delay detection module 10.

The frequency control module 20 and the computing module 50 are powered by the same voltage, both supplied by the performance and power consumption level control module 40. Therefore, the current power supply voltage of the frequency control module 20 is also the current power supply voltage of the computing module 50. The frequency control module 20 can control the frequency of the clock signal output to the computing module 50 based on the current power supply voltage and circuit delay. An exemplary control method is described below. Because the delay detection module 10 detects circuit delay in real time, the circuit delay is also transmitted to the frequency control module 20 in real time. The frequency control module 20 then determines the frequency of the clock signal in real time, resulting in a more efficient inner-loop control.

The following describes an exemplary method of outer loop control of the power supply voltage and the frequency of the clock signal of the computing module 50 in accordance with an embodiment of the present disclosure in conjunction with FIG2 .

The performance statistics module 30 can periodically detect the performance (referring to computing performance) of the computing module 50, obtain actual performance (referring to actual computing performance) and output it to the performance and power consumption level control module 40. Among them, performance can refer to computing efficiency, memory utilization, and other computing performance of the computing module 50. For example, the computing module 50 is usually equipped with at least one performance counter. Each performance counter is used to detect the performance of a part of the circuit of the computing module 50. The performance detection standard of each performance counter may be the same or different. The counting result of the performance counter directly indicates the quality of performance. The performance statistics module 30 can periodically obtain the counting result of each performance counter according to the preset performance statistics cycle (which may be around tens of microseconds (us) or hundreds of microseconds (us)). Based on these counting results, the performance statistics module 30 can determine the actual performance of the calculation module 50 through weighted averaging. The weight of each performance counter's counting result can be determined based on parameters such as the performance test standard of the performance counter and/or the area of the circuit portion corresponding to the performance counter.

The user can preset a performance target for the computing module 50. The performance target indicates that the user hopes that the actual performance of the computing module will reach or exceed the performance target. The performance and power consumption level control module 40 can control the power supply voltage output to the frequency control module 20 and the computing module 50 based on the preset performance target and actual performance. Its exemplary control method can be found in the relevant description below. Since the performance statistics module 30 periodically detects the performance of the computing module 50, the actual performance it obtains is also periodically transmitted to the performance and power consumption level control module 40. The performance and power consumption level control module 40 periodically controls the output power supply voltage, and the control period and the actual performance acquisition period can be similar, for example, it may be on the order of tens of microseconds (us) or hundreds of microseconds (us). The supply voltage has a direct impact on the frequency of the clock signal, thus also achieving control of the frequency of the clock signal.

According to the voltage and frequency control system of the disclosed embodiment, the time required to detect circuit delay is greatly reduced compared to detecting process, power supply voltage, and temperature, thereby improving detection efficiency. The circuit delay characteristics determine the maximum operating clock frequency of the calculation module under a certain power supply voltage. Therefore, the frequency control module uses the power supply voltage and delay to control the frequency of the clock signal, and can achieve the same accuracy as using the process, power supply voltage, and temperature to determine the frequency of the clock signal. The real-time acquisition of circuit delay enables the frequency control module to also achieve real-time frequency control, thereby improving frequency control efficiency while ensuring accuracy. The performance statistics module periodically monitors the performance of the compute module, obtains actual performance, and outputs this information to the performance and power level control module. Based on preset performance targets and actual performance, the performance and power level control module controls the supply voltage output to the frequency control module and the compute module, achieving periodic supply voltage control and forming a closed control loop. Because control is based on preset performance targets and actual performance, supply voltage control is more accurate. Since supply voltage directly affects the frequency of the clock signal, this allows for more precise regulation of both the supply voltage and the clock signal frequency. The voltage and frequency control system of the disclosed embodiment reduces circuit timing redundancy, maximizes performance, and optimizes control efficiency through real-time frequency control by the inner-loop delay detection module and frequency control module. Cyclic voltage control and cyclic frequency control by the outer-loop performance statistics module and performance and power consumption level control module improve control accuracy, thereby achieving both performance and control efficiency improvements. Therefore, the combination of the inner and outer loops achieves both efficiency and accuracy, resulting in even greater performance improvements.

Compared to the millisecond-level process, temperature, and voltage detection of the prior art, the disclosed embodiment only requires a few nanoseconds to complete the delayed detection, greatly reducing the detection time.

Compared to the second prior art, the voltage control cycle of the disclosed embodiment is limited only by the cycle setting of the performance statistics module and the time required for the performance statistics module to complete the acquisition of actual performance. Therefore, the voltage control cycle can be as low as tens or hundreds of microseconds, which is much shorter than the millisecond-level voltage control cycle of the second prior art.

Compared to existing technologies 1 and 2, the disclosed embodiment does not require a pre-prepared frequency-voltage configuration table, thereby reducing data processing costs and avoiding the reduced accuracy associated with using a frequency-voltage configuration table. This significantly improves performance and power consumption control accuracy.

The following describes an exemplary method for controlling the frequency of the clock signal in inner-loop control.

In one possible implementation, controlling the frequency of the clock signal output to the computing module based on the current power supply voltage and circuit delay includes: determining the maximum frequency under the current power supply voltage and circuit delay, and controlling the frequency of the clock signal output to the computing module to be equal to the maximum frequency.

For example, without considering performance targets and power consumption requirements, the purpose of inner-loop control is to control the frequency of the clock signal so that the computing module can achieve maximum performance under current operating conditions (supply voltage, device temperature, and process characteristics). The higher the clock signal frequency, the greater the performance of the computing module. Therefore, the frequency control module 20 controls the frequency of the clock signal output to the computing module 50 based on the current supply voltage and delay. This can be done by determining the maximum frequency under the current supply voltage and circuit delay. Circuit delay is inherently related to current operating conditions. Therefore, the maximum frequency under the current supply voltage and circuit delay is also the maximum frequency under the current operating conditions. The frequency of the clock signal output to the computing module 50 is then controlled to be equal to the maximum frequency. Under a certain power supply voltage, the relationship between circuit delay and maximum frequency is known: the smaller the circuit delay, the greater the maximum frequency. Therefore, based on this known relationship, the maximum frequency can be uniquely determined using the power supply voltage and circuit delay.

For example, the frequency control module 20 may be internally provided with a conventional clock frequency generation circuit (not shown) to generate and output a clock signal. The time required to generate and output the clock signal may be in the nanosecond (ns) level.

In this way, the performance potential of the computing module under a certain power supply voltage can be fully utilized.

The following describes an exemplary control method for the power supply voltage in outer loop control.

In one possible implementation, the performance and power consumption level control module is pre-set with multiple levels of voltage values, with higher voltage levels increasing the voltage value. The power supply voltage output to the frequency control module and the computing module is controlled based on the preset performance target and actual performance, including: when the performance target is greater than the actual performance, the voltage level of the output power supply voltage is increased; when the performance target is less than the actual performance, the voltage level of the output power supply voltage is decreased.

For example, without considering power consumption requirements, the purpose of outer-loop control is to adjust the supply voltage based on the current actual performance feedback, so that the actual performance of the computing module 50 under the adjusted supply voltage more closely approaches the set performance target. The control cycle of outer-loop control depends on the performance statistics cycle and the time required for supply voltage control. The control cycle of outer-loop control can be as low as tens to hundreds of microseconds, significantly shorter than the traditional AVFS control cycle. To achieve this, the performance and power consumption level control module 40 can be pre-set with multiple voltage levels, with higher voltage levels set to increase the voltage value, to implement hierarchical voltage control. As the supply voltage increases, the performance of the computing module 50 also increases. Therefore, the supply voltage output to the frequency control module and computing module is controlled based on a preset performance target and actual performance. When the performance target exceeds the actual performance, the output supply voltage is controlled to increase in level; when the performance target is less than the actual performance, the output supply voltage is controlled to decrease in level. For example, a proportional-integral-derivative control algorithm similar to conventional techniques can be employed to maintain the supply voltage at a certain level.

The power supply voltage is output to both the frequency control module 20 and the computing module 50. When the power supply voltage is higher, the maximum frequency determined by the frequency control module 20 is also higher, thereby increasing the frequency of the clock signal output to the computing module 50. This improves the performance of the computing module 50.

This approach allows the preset performance target to be achieved at the lowest supply voltage, reducing power consumption. Combined with inner-loop control, the computing module can more quickly approach performance targets at lower supply voltage levels and power consumption, significantly improving the computing module's computing power-to-power ratio.

In one possible implementation, when the difference between the performance target and the actual performance is greater than a first threshold, the performance and power consumption level control module is further configured to output a first clock control instruction to the frequency control module; the frequency control module is further configured to control the frequency of the clock signal to increase by a second threshold based on the first clock control instruction; when the difference between the actual performance and the performance target is greater than the first threshold, the performance and power consumption level control module is further configured to output a second clock control instruction to the frequency control module; the frequency control module is further configured to control the frequency of the clock signal of the computing module to decrease by a third threshold based on the second clock control instruction.

For example, since the supply voltage is output to the frequency control module 20, and the frequency control module 20 has the ability to directly control the frequency of the clock signal, when the gap between the performance target and the actual performance is too large, the frequency control capability of the frequency control module 20 can be used to control the supply voltage of the computing module 50 while also controlling the frequency of the clock signal of the computing module 50, thereby improving control efficiency.

For example, a first threshold can be pre-set. When the difference between the performance target and the actual performance is greater than the first threshold, it indicates that the performance of the computing module 50 is lower than the performance requirement. To improve the performance of the computing module 50, the performance and power consumption level control module 40 can also output a first clock control instruction to the frequency control module 20. The frequency control module 20 controls the clock frequency to increase by a second threshold based on the first clock control instruction. The second threshold can be pre-set, that is, the first clock control instruction can force the frequency of the clock signal to increase by a certain value.

Similarly, when the difference between actual performance and the performance target is greater than the first threshold, it indicates that the performance of computing module 50 exceeds the performance requirement. Higher performance may result in higher power consumption. To reduce the performance of computing module 50, and therefore reduce power consumption, performance and power level control module 40 can also output a second clock control instruction to frequency control module 20. Based on the second clock control instruction, frequency control module 20 controls the clock frequency to decrease by a third threshold. The third threshold can be pre-set; that is, the second clock control instruction can forcibly reduce the frequency of the clock signal by a certain value.

The first threshold, the second threshold, and the third threshold can be set according to the application scenario requirements. The present disclosed embodiment does not limit the specific values of the first threshold, the second threshold, and the third threshold.

For the frequency control module 20, the frequency control method for controlling the clock signal based on the power supply voltage and circuit delay (achieving the maximum frequency) is different from the frequency control method for controlling the clock signal based on performance targets and actual performance (increasing the second threshold or lowering the third threshold). Therefore, although both control the frequency of the clock signal, there is no conflict between the two.

In this way, the computational module can reach its performance goals faster.

In some application scenarios, users may wish to ensure that the power consumption of the computing module does not exceed a preset power consumption baseline. To meet this user need, the voltage and frequency control system of the disclosed embodiment also features accurate power consumption control. Figure 3 shows a schematic diagram of the structure of the voltage and frequency control system according to the disclosed embodiment.

In one possible implementation, the system further includes a power consumption statistics module 60, which is used to periodically detect the power consumption of the computing module 50, obtain the actual power consumption and output it to the frequency control module 20 and the performance and power consumption level control module 40; the frequency control module 20 is also used to control the frequency of the clock signal output to the computing module 50 based on a preset power consumption benchmark and actual power consumption, so that the first power consumption estimate of the computing module 50 when operating at the frequency does not exceed the power consumption benchmark; the performance and power consumption level control module 40 is also used to control the power supply voltage output to the frequency control module 20 and the computing module 50 based on the preset power consumption benchmark and actual power consumption.

As shown in Figure 3, the power consumption statistics module 60 can periodically detect the power consumption of the computing module 50, obtain the actual power consumption, and output it to the frequency control module 20 and the performance and power consumption level control module 40. For example, the computing module 50 is typically equipped with at least one power consumption counter. Each power consumption counter is used to detect the power consumption of a portion of the computing module 50 circuit. The power consumption detection standards of each power consumption counter may be the same or different. The counting results of the power consumption counters directly indicate the amount of power consumption. The power consumption statistics module 60 can periodically obtain the counting results of each power consumption counter according to a preset power consumption statistics period (which may be around tens or hundreds of microseconds (us)). Based on these counting results, the power consumption statistics module 60 can determine the actual power consumption of the calculation module 50 through weighted averaging and certain calculations. The weight of each power consumption counter's counting result can be determined based on parameters such as the power consumption detection standard of the power consumption counter and/or the area of the circuit portion corresponding to the power consumption counter.

The power consumption statistics cycle of the power consumption statistics module 60 and the performance statistics cycle of the performance statistics module 30 may be the same as or different from each other, and this disclosure does not impose any limitation on this.

The user can preset a power consumption baseline for the computing module 50. This baseline represents the user's expectation that the actual power consumption of the computing module 50 will not exceed this baseline. Based on the preset power consumption baseline and actual power consumption, the frequency control module 20 can periodically control the frequency of the clock signal output to the computing module 50, ensuring that the first power consumption estimate of the computing module 50 when operating at this frequency does not exceed the power consumption baseline. An exemplary control method is described below. Real-time frequency control based on the power consumption baseline and actual power consumption is equivalent to real-time power consumption control, which can ensure that actual power consumption is lower than the power consumption baseline, meeting system power consumption requirements and enhancing system stability and reliability.

The performance and power consumption level control module 40 can periodically control the power supply voltage output to the frequency control module 20 and the computing module 50 based on a preset power consumption baseline and actual power consumption to prevent the computing module's actual power consumption from exceeding the power consumption baseline. Furthermore, if performance targets are not considered, the power supply voltage can be controlled to a maximum power supply voltage that ensures the computing module's actual power consumption does not exceed the power consumption baseline. As described above, the performance and power consumption level control module 40 can also control the power supply voltage based on performance targets and actual performance. Therefore, when the voltage and frequency control system includes the power consumption statistics module 60, the performance and power consumption level control module 40 has two power supply voltage control methods. Examples of these two control methods are described further below.

In this way, power consumption benchmarks are further considered based on performance targets, making power consumption control more precise.

The following describes an exemplary method by which the frequency control module controls the frequency of the clock signal output to the computing module based on a preset power consumption baseline and actual power consumption.

In one possible implementation, controlling the frequency of a clock signal output to a computing module based on a preset power consumption baseline and actual power consumption includes controlling the frequency of the output clock signal to be equal to the product of a maximum frequency and a preset coefficient when the difference between the actual power consumption and the power consumption baseline is greater than a fourth threshold, where the value of the preset coefficient is less than 1.

For example, although the clock signal frequency and supply voltage are controlled based on the power consumption benchmark and actual power consumption, theoretically, the actual power consumption of computing module 50 at this frequency and supply voltage will not exceed the power consumption benchmark. However, the actual operating conditions of computing module 50 are constantly changing, which may result in the actual power consumption of computing module 50 still exceeding the power consumption benchmark. To address this, a fourth threshold can be pre-set. When the difference between the actual power consumption and the power consumption benchmark is less than or equal to the fourth threshold, the actual power consumption is considered to be within a relatively safe range, and the efficiency of controlling the clock signal frequency and supply voltage based on the power consumption benchmark and actual power consumption is still acceptable. However, if the difference between the actual power consumption and the power consumption baseline exceeds the fourth threshold, the actual power consumption is excessive, posing a risk of damage to computing module 50 and placing significant pressure on the computing module's power supply and heat dissipation. In this case, controlling the clock signal frequency and supply voltage based on the power consumption baseline and actual power consumption may be slow, requiring the clock signal frequency to be reduced as quickly as possible.

To accelerate the reduction rate of the clock signal frequency, the frequency control module 20 can be configured to control the frequency of the output clock signal to be equal to the product of the maximum frequency and a preset coefficient when the difference between the actual power consumption and the power consumption baseline is greater than a fourth threshold. The preset coefficient is less than 1. The product of the maximum frequency and the preset coefficient indicates a low-frequency clock signal. The preset coefficient can be set to a smaller value so that the frequency of the low-frequency clock signal is lower than the current clock signal frequency. When the calculation module 50 operates under the low-frequency clock signal, its actual power consumption does not exceed the power consumption baseline.

For the frequency control module 20, the two methods of controlling the clock signal frequency based on power consumption benchmarks and actual power consumption (reducing the frequency to the product of the maximum frequency and a preset coefficient) and the method of controlling the clock signal frequency based on supply voltage and circuit delay (achieving the maximum frequency) both aim to achieve specific frequency values, and therefore may conflict. In the event of a conflict, meeting the power consumption benchmark takes precedence, i.e., reducing the clock signal frequency to the product of the maximum frequency and a preset coefficient.

In this way, when the power consumption of the computing module is high, power consumption can be reduced more quickly.

As can be seen from the above description, when the voltage and frequency control system includes the power consumption statistics module 60, there are two ways to control the supply voltage. One can be regarded as a response to the received actual performance, and the other can be regarded as a response to the received actual power consumption.

The following describes an exemplary method in which a frequency performance and power consumption level control module controls the power supply voltage output to the frequency control module and the computing module based on preset performance targets and actual performance when the voltage and frequency control system includes a power consumption statistics module.

In one possible implementation, the performance and power consumption level control module 40 is pre-set with multiple levels of voltage values, and the higher the voltage level, the greater the voltage value.

According to the preset performance target and actual performance, the power supply voltage output to the frequency control module 20 and the calculation module 50 is controlled, including: when the performance target is greater than the actual performance, the voltage value level of the first target power supply voltage is determined so that the voltage value level of the first target power supply voltage is higher than the voltage value level of the current power supply voltage; when the performance target is less than the actual performance, the voltage value level of the first target power supply voltage is determined so that the voltage value level of the first target power supply voltage is lower than the current power supply voltage. The voltage value level of the current power supply voltage; determining a first power consumption estimate when the computing module 50 operates at the first target power supply voltage; when the first power consumption estimate is less than the power consumption baseline, controlling the power supply voltage output to the frequency control module 20 and the computing module 50 to be equal to the first target power supply voltage; when the first power consumption estimate is greater than the power consumption baseline, controlling the power supply voltage output to the frequency control module 20 and the computing module 50 based on a preset power consumption baseline and actual power consumption.

For example, the power supply voltage of the computing module 50 has a significant impact on the power consumption of the computing module 50. The relationship between the two is shown in formulas (1)-(3): P _total =P _dynamic +P _static (1) P _dynamic =α∙C _load ∙F _clk ∙V ² (2) P _static =β∙V∙e ^-Vth/(γ∙V _T ⁾ (3)

Where F _clk represents the frequency of the clock signal, V represents the supply voltage, C _load represents the equivalent load capacitance of computing module 50, α represents the circuit flip-flop factor, V _th represents the threshold voltage of computing module 50, _VT represents the thermoelectric voltage of computing module 50, i.e., the potential difference caused by temperature difference, and β and γ represent the process parameters of computing module 50. P _dynamic represents the power consumption of computing module 50 operating at the supply voltage and clock signal frequency, P _static represents the additional power consumption caused by process and temperature, and P _total represents the total power consumption of computing module 50.

Under the premise of considering the power consumption benchmark, the purpose of the outer loop control is to ensure that the actual performance of the computing module 50 is closer to the set performance target under the premise that the power consumption of the controlled power supply voltage does not exceed the power consumption benchmark.

To this end, the performance and power consumption level control module 40 can pre-set multiple voltage levels, with higher voltage levels increasing the value, to implement voltage level control. The number of levels can be set based on actual needs, and the voltage difference between adjacent levels can be set to 10mV, 5mV, or other values. The present embodiment does not limit the specific number of levels or the voltage difference between adjacent levels.

The higher the supply voltage, the greater the performance of the computing module 50. Therefore, the supply voltage output to the frequency control module 20 and computing module 50 is controlled based on the preset performance target and actual performance. A target voltage level is first determined based on the performance target and actual performance, and then a determination is made as to whether the estimated power consumption of the computing module at that voltage level would exceed a power consumption baseline. If the power consumption baseline is not exceeded, the supply voltage is controlled to be equal to the voltage value of that voltage level. If the power consumption baseline is exceeded, the supply voltage control method is further determined based on the power consumption baseline and actual power consumption (see the relevant description below for an example).

For example, when the performance target is greater than the actual performance, the voltage value level of the first target power supply voltage (i.e., the target voltage value level) can be determined so that the voltage value level of the first target power supply voltage is higher than the voltage value level of the current power supply voltage; when the performance target is less than the actual performance, the voltage value level of the first target power supply voltage (i.e., the target voltage value level) can be determined so that the voltage value level of the first target power supply voltage is lower than the voltage value level of the current power supply voltage.

Next, a first estimated power consumption value of the computing module when operating at the first target power supply voltage is determined. When the first estimated power consumption value is less than a power consumption baseline, the power supply voltage output to the frequency control module 20 and the computing module 50 is controlled to be equal to the first target power supply voltage. For example, a proportional integral derivative control algorithm similar to conventional techniques can be employed to ensure that the power supply voltage reaches a certain voltage value. When the first estimated power consumption value is greater than the power consumption baseline, the power supply voltage output to the frequency control module 20 and the computing module 50 is controlled based on a preset power consumption baseline and actual power consumption (an example of which is described below).

This ensures that the computing module's power consumption under the supply voltage does not exceed the power consumption benchmark, providing stronger protection for the computing module.

Those skilled in the art will understand that when the voltage and frequency control system does not include the power consumption statistics module 60, as long as a power consumption benchmark is preset, the performance and power consumption level control module 40 can still complete the determination of the voltage value level of the first target power supply voltage and the determination of the first power consumption estimate value when the calculation module 50 operates under the first target power supply voltage. When the first power consumption estimate is less than the power consumption baseline, the power supply voltage output to the frequency control module 20 and the calculation module 50 can still be controlled to be equal to the first target power supply voltage. When the first power consumption estimate is greater than the power consumption baseline, the output power supply voltage can be directly controlled to decrease in voltage level. Optionally, a third clock control instruction can be given, and the frequency control module 20 can also control the frequency of the clock signal to decrease by a certain value (such as a preset sixth threshold, etc.) according to the third clock control instruction.

The following describes an exemplary method for controlling the power supply voltage output to the frequency control module and the computing module based on preset actual power consumption and power consumption benchmarks when the voltage and frequency control system includes a power consumption statistics module.

In one possible implementation, controlling the power supply voltage output to the frequency control module 20 and the computing module 50 based on a preset power consumption baseline and actual power consumption includes: when the difference between the actual power consumption and the power consumption baseline is greater than a fifth threshold, determining a voltage value level of a second target power supply voltage so that a second power consumption estimate of the computing module when operating at the second target power supply voltage is less than the power consumption baseline and the difference between the second power consumption estimate and the power consumption baseline is minimized; and controlling the power supply voltage output to the frequency control module 20 and the computing module 50 to be equal to the second target power supply voltage.

For example, when the performance of the computing module 50 meets the performance target, the power consumption of the computing module 50 may not meet the power consumption benchmark; however, when the power consumption of the computing module 50 meets the power consumption benchmark, regardless of whether the performance of the computing module 50 meets the performance target, it is considered that the user can accept the current performance. Therefore, when the difference between the actual power consumption and the power consumption baseline is greater than the fifth threshold, the voltage value level of the second target power supply voltage can be determined, and the second power consumption estimate value of the calculation module 50 when operating under the second target power supply voltage can be judged. The voltage value level of the second target power supply voltage when the second power consumption estimate value is less than the power consumption baseline and the difference between the second power consumption estimate value and the power consumption baseline is minimized is selected as the determined voltage value level of the second target power supply voltage, and the power supply voltage output to the frequency control module 20 and the calculation module 50 is controlled to be equal to the second target power supply voltage. At this time, the performance of the calculation module 50 under the second target power supply voltage has reached the maximum performance under the power consumption baseline. Therefore, there is no need to further judge whether the performance at this time has reached the performance target.

In this way, while ensuring that the power consumption of the computing module under the supply voltage does not exceed the power consumption benchmark, the supply voltage can be maximized, allowing the computing module to achieve optimal performance.

Those skilled in the art should understand that when the voltage and frequency control system includes the power consumption statistics module 60, the performance and power consumption level control module 40 can also output the first clock control instruction and the second clock control instruction when the conditions described above are met to make the control more efficient.

In one possible implementation, the performance and power consumption level control module 40 is also used to obtain an analysis report at the end of the current cycle based on one or more of the actual performance, actual power consumption, changes in the output power supply voltage, and output instructions obtained in the current cycle. The analysis report is used to adjust the performance target and power consumption benchmark used in the next cycle.

For example, the current cycle may refer to the performance statistics cycle of the performance statistics module 30, and an analysis report may be obtained based on one or more of the actual performance obtained in the current cycle, the change in the output power supply voltage, and the output instructions; the current cycle may also refer to the power consumption statistics cycle of the power consumption statistics module 60, and an analysis report may be obtained based on one or more of the actual power consumption obtained in the current cycle, the change in the output power supply voltage, and the output instructions.

If the default performance target and power consumption benchmark are output to the performance and power consumption level control module 40 by a device (e.g., a user device), the performance and power consumption level control module 40 can feed back the analysis report to the device. Based on the analysis report and the default performance target and power consumption benchmark for the current cycle, the device adjusts the performance target and power consumption benchmark for the next cycle and outputs the results to the performance and power consumption level control module 40. If the default performance target and power consumption benchmark are determined by the performance and power consumption level control module 40 itself, the performance and power consumption level control module 40 can directly adjust the performance target and power consumption benchmark for the next cycle based on the analysis report and the default performance target and power consumption benchmark for the current cycle. The disclosed embodiment does not limit the execution object of the step of using the analysis report to adjust the performance target and power consumption baseline for the next cycle.

In this way, performance targets and power consumption baselines can be updated in a timely manner.

The disclosed embodiment also provides a voltage and frequency control method. FIG4 is a schematic diagram showing the process of the voltage and frequency control method according to the disclosed embodiment.

As shown in FIG4 , the method is applied to a voltage and frequency control system, which includes a delay detection module, a frequency control module, a performance statistics module, and a performance and power consumption level control module. The system is used to control the clock frequency and power supply voltage of the computing module. The method includes steps S41 to S44: Step S41, the delay detection module detects the circuit delay of the computing module in real time and outputs the circuit delay to the frequency control module; Step S42, the frequency control module adjusts the circuit delay according to the current power supply voltage. The current power supply voltage and the circuit delay are used to control the frequency of the clock signal output to the computing module, and the current power supply voltage is provided by the performance and power consumption level control module; in step S43, the performance statistics module periodically detects the performance of the computing module, obtains the actual performance and outputs it to the performance and power consumption level control module; in step S44, the performance and power consumption level control module controls the power supply voltage output to the frequency control module and the computing module according to a preset performance target and the actual performance.

In one possible implementation, the delay detection module and the computing module physically maintain the same operating conditions of process characteristics, power supply voltage, and device temperature. The real-time detection of the circuit delay of the computing module includes: real-time detection of its own circuit delay under the current working conditions of process characteristics, current power supply voltage, and current device temperature as the circuit delay of the computing module.

In one possible implementation, controlling the frequency of the clock signal output to the computing module based on the current power supply voltage and the circuit delay includes: determining a maximum frequency under the current power supply voltage and the circuit delay, and controlling the frequency of the clock signal output to the computing module to be equal to the maximum frequency.

In one possible implementation, the method further includes: when the difference between the performance target and the actual performance is greater than a first threshold, the performance and power consumption level control module outputs a first clock control instruction to the frequency control module; the frequency control module controls the frequency value of the clock signal to increase by a second threshold based on the first clock control instruction; when the difference between the actual performance and the performance target is greater than the first threshold, the performance and power consumption level control module outputs a second clock control instruction to the frequency control module; the frequency control module controls the frequency value of the clock signal of the computing module to decrease by a third threshold based on the second clock control instruction.

In one possible implementation, the performance and power consumption level control module is pre-set with multiple levels of voltage values, and the higher the voltage level, the larger the voltage value. The power supply voltage output to the frequency control module and the calculation module is controlled according to the preset performance target and the actual performance, including: when the performance target is greater than the actual performance, the voltage value level of the output power supply voltage is controlled to increase; when the performance target is less than the actual performance, the voltage value level of the output power supply voltage is controlled to decrease.

In one possible implementation, the system further includes a power consumption statistics module, and the method further includes: the power consumption statistics module periodically detects the power consumption of the computing module, obtains actual power consumption and outputs it to the frequency control module and the performance and power consumption level control module; the frequency control module controls the frequency of the clock signal output to the computing module based on a preset power consumption benchmark and the actual power consumption, so that a first power consumption estimate of the computing module when operating at the frequency does not exceed the power consumption benchmark; the performance and power consumption level control module controls the power supply voltage output to the frequency control module and the computing module based on the preset power consumption benchmark and the actual power consumption.

In one possible implementation, controlling the frequency of the clock signal output to the computing module based on a preset power consumption benchmark and the actual power consumption includes: when the difference between the actual power consumption and the power consumption benchmark is greater than a fourth threshold, controlling the frequency of the output clock signal to be equal to the product of the maximum frequency and a preset coefficient, where the value of the preset coefficient is less than 1.

In one possible implementation, the performance and power consumption level control module is pre-set with multiple levels of voltage values, and the higher the voltage level, the greater the voltage value. The control of the power supply voltage output to the frequency control module and the calculation module based on the preset performance target and the actual performance includes: when the performance target is greater than the actual performance, determining the voltage value level of the first target power supply voltage, so that the voltage value level of the first target power supply voltage is higher than the voltage value level of the current power supply voltage; when the performance target is less than the actual performance, determining the first target power supply voltage voltage level of the first target power supply voltage so that the voltage level of the first target power supply voltage is lower than the voltage level of the current power supply voltage; determining a first power consumption estimate when the calculation module operates under the first target power supply voltage; when the first power consumption estimate is less than the power consumption baseline, controlling the power supply voltage output to the frequency control module and the calculation module to be equal to the first target power supply voltage; when the first power consumption estimate is greater than the power consumption baseline, controlling the power supply voltage output to the frequency control module and the calculation module according to a preset power consumption baseline and the actual power consumption.

In one possible implementation, controlling the power supply voltage output to the frequency control module and the computing module based on a preset power consumption benchmark and the actual power consumption includes: when the difference between the actual power consumption and the power consumption benchmark is greater than a fifth threshold, determining a voltage value level of a second target power supply voltage so that a second power consumption estimate of the computing module when operating at the second target power supply voltage is less than the power consumption benchmark and the difference between the second power consumption estimate and the power consumption benchmark is minimized; and controlling the power supply voltage output to the frequency control module and the computing module to be equal to the second target power supply voltage.

In one possible implementation, the method further includes: at the end of the current cycle, the performance and power consumption level control module obtains an analysis report based on one or more of the actual performance, actual power consumption, changes in the output power supply voltage, and output instructions obtained in the current cycle, and the analysis report is used to adjust the performance target and the power consumption benchmark used in the next cycle.

In some embodiments, the method provided by the disclosed embodiments may be executed by the modules included in the above system embodiments. The specific implementation thereof may refer to the description of the above system embodiments and will not be described again here for the sake of brevity.

The disclosed embodiment also provides a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the above method is implemented. The computer-readable storage medium can be a volatile or computer-readable storage medium.

The disclosed embodiment also provides a computer program product, including a computer-readable code, or a computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

FIG5 shows a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, electronic device 1900 can be provided as a server or a terminal device. Referring to FIG5 , electronic device 1900 includes a processing element 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as applications, that can be executed by processing element 1922. The application stored in memory 1932 can include one or more modules, each corresponding to a set of instructions. Furthermore, processing element 1922 is configured to execute the instructions to perform the above-described method.

Electronic device 1900 may also include a power supply 1926 configured to perform power management for electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input/output interface 1958 (I/O interface). Electronic device 1900 may operate based on an operating system stored in memory 1932, such as Windows Server ^™ , Mac OS X ^™ , Unix ^™ , Linux ^™ , FreeBSD ^™ , or the like.

In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing element 1922 of the electronic device 1900 to perform the above-described method.

The present disclosure may be a system, method and/or computer program product. The computer program product may include a computer-readable storage medium that carries computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. More specific examples of computer-readable storage media (a non-exhaustive list) include: portable computer disks, hard drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanical encoding devices such as punched cards or raised-in-recess structures on which instructions are stored, and any suitable combination of the foregoing. As used herein, computer-readable storage medium is not to be construed as a transient signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or electrical signals transmitted through wires.

The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing/processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and/or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers. A network interface card or network interface in each computing/processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to the computer-readable storage medium in each computing/processing device for storage.

The computer program instructions for performing the operations disclosed herein may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, and conventional procedural programming languages such as "C" or similar programming languages. The computer-readable program instructions may be executed entirely on the user computer, partially on the user computer, as a stand-alone packaged software, partially on the user computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer can be connected to the user computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by utilizing state information of computer-readable program instructions to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), which can execute computer-readable program instructions.

Various aspects of the present disclosure are described herein with reference to flowcharts and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and/or block diagrams, as well as combinations of blocks in the flowcharts and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine such that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions/actions specified in one or more blocks in the flowchart and/or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and/or other equipment to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions/actions specified in one or more blocks in the flowchart and/or block diagram.

Computer-readable program instructions may also be loaded onto a computer, other programmable data processing device, or other apparatus to cause a series of operating steps to be performed on the computer, other programmable data processing device, or other apparatus to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing device, or other apparatus to implement the functions/actions specified in one or more blocks in the flowchart and/or block diagram.

The flowcharts and block diagrams in the accompanying figures illustrate possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each box in a flowchart or block diagram may represent a module, program segment, or portion of an instruction that contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the boxes may occur in an order different from that marked in the accompanying figures. For example, two consecutive boxes may actually be executed substantially in parallel, or they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagrams and/or flowcharts, and combinations of boxes in the block diagrams and/or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

While various embodiments of the present disclosure have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein is selected to best explain the principles, practical applications, or market-leading technological advancements of the embodiments, or to facilitate understanding of the embodiments by others skilled in the art.

Although specific embodiments of the present disclosure have been described with reference to the above-described embodiments, these embodiments are not intended to limit the present disclosure. Various substitutions and modifications may be made by those skilled in the relevant art without departing from the principles and spirit of the present disclosure. Therefore, the scope of protection of the present disclosure is determined by the appended patent applications.

1: Electronic Device 2: Electronic Device 10: Delay Detection Module 20: Frequency Control Module 30: Performance Statistics Module 40: Performance and Power Level Control Module 50: Computing Module 60: Power Statistics Module 1900: Electronic Device 1922: Processing Component 1926: Power Component 1932: Memory 1950: Network Interface 1958: Input/Output Interface S41-S44: Steps

To more clearly illustrate the technical solutions of this application or the prior art, the following briefly describes the figures required for use in the embodiments or prior art descriptions. It should be understood that the figures described below represent some embodiments of this application. A person skilled in the art can derive other figures based on these figures without inventive effort. Figure 1 is a schematic diagram of the structure of a voltage and frequency control system according to an embodiment of the present disclosure. Figure 2 is an exemplary workflow of a voltage and frequency control system according to an embodiment of the present disclosure. Figure 3 is a schematic diagram of the structure of a voltage and frequency control system according to an embodiment of the present disclosure. Figure 4 is a schematic diagram of the flow of a voltage and frequency control method according to an embodiment of the present disclosure. Figure 5 shows a block diagram of an electronic device according to an embodiment of the present disclosure.

10: Delay Detection Module 20: Frequency Control Module 30: Performance Statistics Module 40: Performance and Power Level Control Module 50: Computation Module

Claims (11)

A voltage and frequency control system includes a delay detection module, a frequency control module, a performance statistics module, and a performance and power consumption level control module. The system is used to control the clock frequency and power supply voltage of a computing module. The delay detection module and the computing module physically maintain the same operating conditions of process characteristics, power supply voltage, and device temperature. The delay detection module is used to instantly detect its own circuit delay under the current operating conditions of process characteristics, current power supply voltage, and current device temperature, and use it as the circuit delay of the computing module, and output the circuit delay. to the frequency control module; the frequency control module is used to control the frequency of the clock signal output to the computing module according to the current power supply voltage and the circuit delay, and the current power supply voltage is provided by the performance and power consumption level control module; the performance statistics module is used to periodically detect the performance of the computing module, obtain the actual performance and output it to the performance and power consumption level control module; and the performance and power consumption level control module is used to control the power supply voltage output to the frequency control module and the computing module according to a preset performance target and the actual performance. A voltage and frequency control system as described in claim 1, wherein the frequency of the clock signal output to the computing module is controlled based on the current power supply voltage and the circuit delay, including: determining the maximum frequency under the current power supply voltage and the circuit delay, and controlling the frequency of the clock signal output to the computing module to be equal to the maximum frequency. A voltage and frequency control system as described in claim 1, wherein when the difference between the performance target and the actual performance is greater than a first threshold, the performance and power consumption level control module is further used to output a first clock control instruction to the frequency control module; the frequency control module is further used to control the frequency value of the clock signal to increase by a second threshold according to the first clock control instruction; when the difference between the actual performance and the performance target is greater than the first threshold, the performance and power consumption level control module is further used to output a second clock control instruction to the frequency control module; and the frequency control module is further used to control the frequency value of the clock signal of the computing module to decrease by a third threshold according to the second clock control instruction. A voltage and frequency control system as described in claim 1, wherein the performance and power consumption level control module is pre-set with multiple levels of voltage values, and the higher the voltage value level, the larger the voltage value, and the power supply voltage output to the frequency control module and the calculation module is controlled according to the preset performance target and the actual performance, including: when the performance target is greater than the actual performance, the voltage value level of the power supply voltage output is controlled to increase; and when the performance target is less than the actual performance, the voltage value level of the power supply voltage output is controlled to decrease. A voltage and frequency control system as described in claim 1, wherein the system further includes a power consumption statistics module, which is used to periodically detect the power consumption of the computing module, obtain actual power consumption and output it to the frequency control module and the performance and power consumption level control module; the frequency control module is also used to control the frequency of the clock signal output to the computing module based on a preset power consumption benchmark and the actual power consumption, so that the first power consumption estimate of the computing module when operating at the frequency does not exceed the power consumption benchmark; and the performance and power consumption level control module is also used to control the power supply voltage output to the frequency control module and the computing module based on the preset power consumption benchmark and the actual power consumption. The voltage and frequency control system of claim 5, wherein the frequency of the clock signal output to the computing module is controlled based on a preset power consumption baseline and the actual power consumption, including: when the difference between the actual power consumption and the power consumption baseline is greater than a fourth threshold, the frequency of the clock signal output is controlled to be equal to the product of the maximum frequency and a preset coefficient, the value of the preset coefficient being less than 1. As described in claim 6, the voltage and frequency control system, wherein the performance and power consumption level control module is pre-set with multiple levels of voltage values, and the higher the voltage value level, the greater the voltage value, and the power supply voltage output to the frequency control module and the calculation module is controlled according to the preset performance target and the actual performance, including: when the performance target is greater than the actual performance, determining the voltage value level of the first target power supply voltage, so that the voltage value level of the first target power supply voltage is higher than the voltage value level of the current power supply voltage; when the performance target is less than the actual performance, determining the first target power supply voltage level. The present invention relates to a method for controlling the power supply voltage of the frequency control module and the computing module to adjust the voltage value level of the first target power supply voltage so that the voltage value level of the first target power supply voltage is lower than the voltage value level of the current power supply voltage; determining a first power consumption estimate value of the computing module when operating under the first target power supply voltage; when the first power consumption estimate value is less than the power consumption baseline, controlling the power supply voltage output to the frequency control module and the computing module to be equal to the first target power supply voltage; and when the first power consumption estimate value is greater than the power consumption baseline, controlling the power supply voltage output to the frequency control module and the computing module according to a preset power consumption baseline and the actual power consumption. A voltage and frequency control system as described in claim 7, wherein the power supply voltage output to the frequency control module and the computing module is controlled based on a preset power consumption baseline and the actual power consumption, including: when the difference between the actual power consumption and the power consumption baseline is greater than a fifth threshold, determining the voltage value level of a second target power supply voltage so that a second power consumption estimate of the computing module when operating at the second target power supply voltage is less than the power consumption baseline and the difference between the second power consumption estimate and the power consumption baseline is minimized; and controlling the power supply voltage output to the frequency control module and the computing module to be equal to the second target power supply voltage. A voltage and frequency control system as described in any one of claims 5-8, wherein the performance and power consumption level control module is further used to obtain an analysis report at the end of the current cycle based on one or more of the actual performance, actual power consumption, changes in the output power supply voltage, and output instructions obtained in the current cycle, and the analysis report is used to adjust the performance target and the power consumption benchmark used in the next cycle. A voltage and frequency control method, wherein the method is applied to a voltage and frequency control system, the system including a delay detection module, a frequency control module, a performance statistics module, and a performance and power consumption level control module, the system being used to control the clock frequency and power supply voltage of a computing module, wherein the delay detection module and the computing module physically maintain the same working conditions of process characteristics, power supply voltage, and device temperature, the method comprising: the delay detection module instantly detecting its own circuit delay under the working conditions of current process characteristics, current power supply voltage, and current device temperature, as the computing module circuit delay and outputs the circuit delay to the frequency control module; the frequency control module controls the frequency of the clock signal output to the computing module according to the current power supply voltage and the circuit delay, wherein the current power supply voltage is provided by the performance and power consumption level control module; the performance statistics module periodically detects the performance of the computing module, obtains the actual performance and outputs it to the performance and power consumption level control module; and the performance and power consumption level control module controls the power supply voltage output to the frequency control module and the computing module according to a preset performance target and the actual performance. A computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions implement the method described in claim 10 when executed by a processor.