TWI893863B - Nvm memory structure and method of manufacturing the same - Google Patents

Abstract

A non-volatile memory （NVM） structure includes a substrate, a device isolation structure, a floating gate, a select gate, an interlayer dielectric （ILD） layer, a conductive structure, and at least one dielectric layer. The device isolation structure defines an active region in the substrate. The select gate and the floating gate are disposed on the substrate and across over the active region. The floating gate further has an extension part away from the active region. The ILD layer is disposed on the floating gate and the select gate, and it has contact openings and an extension opening. The contact openings respectively expose the select gate and the active region. The extension opening is over the extension part of the floating gate. The conductive structure is formed in the extension opening and the contact openings. The at least one dielectric layer is disposed between the conductive structure and the extension part of the floating gate, and the one in direct contact with the conductive structure in the at least one dielectric layer is a silicon nitride layer or a high-k dielectric layer.

Description

Non-volatile memory structure and manufacturing method thereof

The present invention relates to a non-volatile memory (NVM) technology, and more particularly to a non-volatile memory structure and a method for manufacturing the same.

Non-volatile memory (NVRAM) has the advantage of being able to store, read, and erase data multiple times, and the stored data persists even after a power outage. Therefore, NVRAM has become a widely used memory component in personal computers and electronic devices. Therefore, further improving the electrical performance of memory components is a current goal of the industry.

The present invention provides a method for manufacturing a non-volatile memory structure, capable of forming a non-volatile memory with a high coupling ratio.

The present invention also provides a non-volatile memory structure that can effectively improve the coupling rate, thereby increasing the operating speed.

The present invention provides a method for fabricating a non-volatile memory structure, comprising the following steps: forming a device isolation structure within a substrate to define an active region; forming a select gate across the active region on the substrate; forming a floating gate on the substrate, the floating gate comprising a main portion and an extension portion, the main portion being located on one side of the select gate and spanning the active region; and the extension portion being located on the device isolation structure and connected to one end of the main portion. forming a conformal dielectric structure on the floating gate, the dielectric structure including a stop layer; and forming an interlayer dielectric layer on the substrate to cover the floating gate and the select gate. An extension opening is formed in the interlayer dielectric layer, wherein the stop layer of the dielectric structure above the extension is exposed through the extension opening. A plurality of contact window openings are formed in the interlayer dielectric layer to expose the select gate and the active region, respectively. Conductive structures are formed within the extension opening and the contact window openings.

In one embodiment of the present invention, the dielectric structure includes an ONO structure or an ONONO structure.

In one embodiment of the present invention, the stop layer is a silicon nitride layer or a high-k dielectric layer.

In one embodiment of the present invention, the extension opening further extends above the main body of the floating gate.

Another method for fabricating a non-volatile memory structure according to the present invention includes the following steps: forming a device isolation structure within a substrate to define an active region and a coupling region; forming a well region and a doped region within the coupling region, with the doped region formed within the well region; forming a select gate on the substrate to span the active region; forming a floating gate on the substrate, the floating gate comprising a main portion and an extension portion, the main portion being located on one side of the select gate and spanning the active region, and the extension portion being located above the well region and connected to one end of the main portion; forming an interlayer dielectric layer on the substrate to cover the floating gate and the select gate; forming an extension opening in the interlayer dielectric layer, wherein the extension portion is exposed through the extension opening. A conformal high-k dielectric layer is formed on the sidewalls of the extension opening and on the extension. Several contact window openings are formed in the interlayer dielectric layer, with the first portion of each contact window opening exposing the select gate and active region, respectively, and the second portion of each contact window opening exposing the doped region within the coupling region. Conductive structures are formed within the extension opening and the contact window openings.

In other embodiments of the present invention, after forming the above-mentioned conductive structure, a metal layer may be formed above the extension portion to connect the conductive structure in the extension opening with the conductive structure in the second portion.

In the above embodiments of the present invention, the extension opening and the contact window opening are formed using different manufacturing processes.

The non-volatile memory structure of the present invention includes at least a substrate, an element isolation structure, a selection gate, a floating gate, an interlayer dielectric layer, a conductive structure and at least one dielectric layer. The element isolation structure is arranged in the substrate to define an active region. The selection gate is arranged on the substrate and spans the active region. The floating gate is arranged on the substrate. The floating gate includes a main body and an extension. The main body is located on one side of the selection gate and spans the active region. The extension is connected to one end of the main body and is away from the active region. The interlayer dielectric layer is arranged above the main body and the selection gate of the floating gate and has a plurality of contact window openings and an extension opening. The contact window opening exposes the select gate and active region, respectively. The extension opening is located above the floating gate extension and extends above the main body of the floating gate. A conductive structure is formed within the extension opening and the contact window opening. A dielectric layer is located between the conductive structure and the floating gate extension, and the portion of the dielectric layer that directly contacts the conductive structure is a silicon nitride layer or a high-k dielectric layer.

In another embodiment of the present invention, the at least one dielectric layer is a stacked layer of an oxide layer and the silicon nitride layer.

In another embodiment of the present invention, the at least one dielectric layer is a single high-k dielectric layer.

In another embodiment of the present invention, the extension opening further extends above the main body of the floating gate.

In another embodiment of the present invention, the at least one dielectric layer may further extend to the sidewall of the extension opening and be located between the conductive structure and the interlayer dielectric layer.

In another embodiment of the present invention, in a top view, the extension portion is a comb-like structure or a grid-like structure.

In another embodiment of the present invention, the extension portion of the floating gate is disposed on the device isolation structure.

In another embodiment of the present invention, the device isolation structure may further define a coupling region within the substrate below the extension. The coupling region includes a well region and a doped region. The doped region is formed within the well region and is located outside the extension.

In another embodiment of the present invention, the conductive structure formed in the extension opening is electrically connected to the doped region.

To make the above features of the present invention more clearly understood, the following examples are given and described in detail with reference to the accompanying drawings.

100: Base

102: Component Isolation Structure

104: Source Region

106: Drain area

108: Middle Area

110: Spacer

112: Silicon nitride liner

114: Oxide layer

116, 118, 120, 202, 204: Patterned mask

122:Conductive structure

124, 210: Barrier Layer

126: Conductor layer

200: Patterned photoresist layer

206: Intermetallic dielectric layer

208:Interface Window

300: Coupling zone

302: Well Area

304: Mixed Area

306: High-k dielectric layer

AA: Active Area

CO1: Contact window opening

CO21: Part 1

CO22: Part 2

DS: Dielectric Structure

EO1, EO2, EO3: Extension opening

EO2s: Sidewall

FG: Floating Gate

FG1: Main body

FG2, FG3, FG4, FG5: Extensions

GO: Gate Oxide

ILD: Interlayer Dielectric

M1, 212: Metal layer

O1, O2: Oxide layer

VO: Interlayer window opening

SG: Select Gate

SL: Stop layer

Figure 1 is a top view of an intermediate process of a non-volatile memory structure according to the first embodiment of the present invention.

Figures 2A and 2B are cross-sectional views of the non-volatile memory structure in Figure 1 taken along lines A-A’ and B-B’, respectively.

Figures 3A and 3B are cross-sectional views of the subsequent manufacturing processes of the structures shown in Figures 2A and 2B, respectively.

Figures 4A and 4B are cross-sectional views of the subsequent manufacturing processes of the structures shown in Figures 3A and 3B, respectively.

Figures 5A and 5B are cross-sectional views of the subsequent manufacturing processes of the structures shown in Figures 4A and 4B, respectively.

Figure 6 is a top view of the structure shown in Figures 5A and 5B undergoing subsequent manufacturing processes.

Figures 7A and 7B are cross-sectional views of the non-volatile memory structure in Figure 6 taken along lines A-A’ and B-B’, respectively.

Figures 8A and 8B are cross-sectional views of the subsequent manufacturing processes of the structures of Figures 7A and 7B, respectively.

Figures 9A and 9B are cross-sectional views of the subsequent manufacturing processes of the structures shown in Figures 8A and 8B, respectively.

FIG10 is a top view of an intermediate process of a non-volatile memory structure according to the second embodiment of the present invention.

Figures 11A and 11B are cross-sectional views of the non-volatile memory structure shown in Figure 10 taken along lines A-A’ and B-B’, respectively.

Figures 12A and 12B are cross-sectional views of the subsequent manufacturing processes of the structures shown in Figures 11A and 11B, respectively.

Figures 13A and 13B are cross-sectional views of the subsequent manufacturing processes of the structures shown in Figures 12A and 12B, respectively.

Figures 14A and 14B are cross-sectional views of the subsequent manufacturing processes of the structures shown in Figures 13A and 13B, respectively.

Figure 15 is a top view of the structure shown in Figures 14A and 14B undergoing subsequent manufacturing processes.

Figures 16A and 16B are cross-sectional views of the non-volatile memory structure shown in Figure 15 taken along lines A-A’ and B-B’, respectively.

Figures 17A and 17B are cross-sectional views of the subsequent manufacturing processes of the structures of Figures 16A and 16B, respectively.

Figures 18A and 18B are cross-sectional views of the subsequent manufacturing processes of the structures of Figures 17A and 17B, respectively.

Figures 19A and 19B are cross-sectional views of the subsequent manufacturing processes of the structures of Figures 18A and 18B, respectively.

Figures 20A and 20B are cross-sectional views of the subsequent manufacturing processes of the structures of Figures 19A and 19B, respectively.

FIG21 is a top view of another example of the non-volatile memory structure of the second embodiment.

Figure 22 is a top view of an intermediate process of a non-volatile memory structure according to the third embodiment of the present invention.

Figures 23A and 23B are cross-sectional views of the non-volatile memory structure in Figure 22 taken along lines A-A’ and B-B’, respectively.

Figures 24A and 24B are cross-sectional views of the subsequent manufacturing processes of the structures of Figures 23A and 23B, respectively.

Figures 25A and 25B are cross-sectional views of the subsequent manufacturing processes of the structures of Figures 24A and 24B, respectively.

Figure 26 is a top view of the structure shown in Figures 25A and 25B undergoing subsequent manufacturing processes.

Figures 27A and 27B are cross-sectional views of the non-volatile memory structure in Figure 26 taken along lines A-A' and B-B', respectively.

Figures 28A and 28B are cross-sectional views of the subsequent manufacturing processes of the structures of Figures 27A and 27B, respectively.

The present invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. Furthermore, the dimensions of the various regions in the drawings are for illustration only and are not intended to limit the scope of the present invention.

Figures 1 through 9B illustrate a manufacturing process flow diagram for a non-volatile memory structure according to the first embodiment of the present invention. Figures 1 and 6 are top views, and for clarity, most components are omitted. Figures 2A through 5A and 7A through 9A are cross-sectional views of the manufacturing process taken along line A-A' in the top views; Figures 2B through 5B and 7B through 9B are cross-sectional views of the manufacturing process taken along line B-B' in the top views.

Please first refer to Figures 1, 2A, and 2B. An element isolation structure 102 is formed in a substrate 100 to define an active area AA. A select gate SG is formed on the substrate 100 across the active area AA; and a floating gate FG is formed on the substrate 100. In some embodiments, the select gate SG and the floating gate FG can be formed by the same process. In addition, before forming the select gate SG and the floating gate FG, a gate oxide layer GO can be formed on the surface of the substrate 100, wherein the method for forming the gate oxide layer GO is, for example, but not limited to, a deposition process such as thermal oxidation or CVD. In some embodiments, a gate oxide layer GO is not formed on the surface of the element isolation structure 102. The floating gate FG comprises a main portion FG1 and an extension FG2. The main portion FG1 is located on one side of the select gate SG and spans the active area AA. The extension FG2 is located on the device isolation structure 102 and connected to one end of the main portion FG1. In the top view (Figure 1), the extension FG2 has a comb-like structure, resulting in a side surface area several times larger than that of a single-layer structure. Furthermore, an ion implantation process can be used to form a source region 104, a drain region 106, and an intermediate region 108 between the select gate SG and the main body FG1 in the active area AA. If the source region 104, the drain region 106, and the intermediate region 108 are N+ regions, a P-type well can be formed in the active area AA, and so on. In some embodiments, spacers 110 can be formed on the sidewalls of the select gate SG and the floating gate FG. The spacers 110 may include a structure consisting of a silicon nitride liner 112 and an oxide layer 114 formed on the silicon nitride liner 112, but this is not limited to this.

Referring to Figures 3A and 3B , a conformal dielectric structure DS is formed over the main portion FG1 and the extension portion FG2. The dielectric structure DS includes a stop layer SL. In one embodiment, the dielectric structure DS is, for example, an ONO structure. Therefore, the stop layer SL may be a silicon nitride layer interposed between the oxide layers O1 and O2. In other embodiments, the dielectric structure DS is, for example, an ONONO structure. Therefore, the stop layer SL may be the topmost silicon nitride layer in the ONONO structure, and so on. In other embodiments, the dielectric structure DS may also be a high-k dielectric layer. In addition to covering the main portion FG1 and the extension portion FG2, the dielectric structure DS also covers the select gate SG.

Referring to Figures 4A and 4B , since the select gate SG needs to be electrically connected to the outside, a patterned mask 116 is first used to cover the main portion FG1 and the extension portion FG2 and then etched to remove the dielectric structure DS above the select gate SG while retaining the dielectric structure DS above the main portion FG1 and the extension portion FG2.

Referring to Figures 5A and 5B , after removing the patterned mask 116 shown in Figures 4A and 4B , an interlayer dielectric (ILD) layer is formed on the substrate 100, covering the main portion FG1, the extension portion FG2, and the select gate SG. Then, for subsequent processing, another patterned mask 118 may be formed on the ILD layer to expose a portion of the ILD layer.

Referring to Figures 6, 7A, and 7B, an extension opening EO1 is formed in the interlayer dielectric layer ILD. The extension opening EO1 is formed, for example, by using a patterned mask 118 as an etch mask to remove the exposed interlayer dielectric layer ILD. Due to the etch selectivity, the oxide layer O2 overlying the dielectric structure DS is also removed, allowing the extension opening EO1 to expose the stop layer SL above the extension FG2. Consequently, a stack of the oxide layer O1 and the stop layer SL remains above the extension FG2. The extension opening EO1 may also extend above the main body FG1 of the floating gate FG.

Referring to Figures 8A and 8B , after removing the patterned mask 118 in Figures 7A and 7B , several contact openings CO1 are formed in the interlayer dielectric layer ILD to expose the select gate SG and the active area AA, respectively, such as the source region 104 and the drain region 106 in the active area AA. The contact openings CO1 can be formed by, for example, first forming a patterned mask 120 to cover the area outside the active area AA and expose a portion of the interlayer dielectric layer ILD. The patterned mask 120 is then used as an etching mask to remove the exposed interlayer dielectric layer ILD. This process can also be integrated with the fabrication of a MOSFET (not shown) in the logic area.

Referring to Figures 9A and 9B , after removing the patterned mask 120 shown in Figures 8A and 8B , a conductive structure 122 is formed within the extension opening EO1 and the contact window opening CO1. The conductive structure 122 within the extension opening EO1 covers the top and sides of the extension FG2, forming a capacitor therebetween. In some embodiments, the method for forming the conductive structure 122 includes first forming a conformal barrier layer 124 within the extension opening EO1 and the contact window opening CO1, and then filling the extension opening EO1 and the contact window opening CO1 with a conductive layer 126. The barrier layer 124 may be made of, for example, Ti/TiN or other suitable materials, and the conductive layer 126 may be made of, for example, a metal such as tungsten or other suitable conductive materials. Therefore, a barrier layer 124 is formed on the sidewalls of the extension opening EO1, the sidewalls of the contact window opening CO1, and the surface of the structure at the bottom of the aforementioned opening (such as the stop layer SL of the dielectric structure DS).

The non-volatile memory structure of the first embodiment includes at least a substrate 100, a device isolation structure 102, a select gate SG, a body portion FG1 and an extension portion FG2 (of a floating gate), an interlayer dielectric layer ILD, a conductive structure 122, and a dielectric structure DS. The device isolation structure 102 is disposed within the substrate 100 to define an active area AA. The select gate SG is disposed on the substrate 100 and spans the active area AA. The body portion FG1 is located on one side of the select gate SG and spans the active area AA. The extension portion FG2 is located on the device isolation structure 102. An interlayer dielectric layer (ILD) is disposed above the select gate SG and the main body portion FG1 and has a contact opening CO1 and an extension opening EO1. The contact opening CO1 exposes the select gate SG and the active area AA, respectively. The extension opening EO1 is above the extension portion FG2 and further extends above the main body portion FG1. A conductive structure 122 is formed within the extension opening EO1 and the contact opening CO1 and serves as the control gate of the non-volatile memory structure. The dielectric structure DS is located between the conductive structure 122 and the extension FG2. Directly contacting the conductive structure 122 is the stop layer SL (i.e., a silicon nitride layer). This layer is thinner than the dielectric structure DS, thereby increasing the coupling ratio between the conductive structure 122 and the extension FG2.

Figures 10 to 20B are flowcharts illustrating the fabrication of a non-volatile memory structure according to a second embodiment of the present invention. The same reference numerals as in the first embodiment are used to represent identical or similar parts and components. For details regarding identical or similar parts and components, reference can be made to the first embodiment and will not be repeated here. Figures 10 and 15 are top views, and for clarity, most components are omitted. Figures 11A to 14A and 16A to 20A are cross-sectional views of the fabrication process taken along line A-A' in the top views; Figures 11B to 14B and 16B to 20B are cross-sectional views of the fabrication process taken along line B-B' in the top views.

Referring to Figures 10, 11A, and 11B, the fabrication process of the second embodiment is similar to that of the first embodiment, including first forming a device isolation structure 102 within a substrate 100 to define an active area AA; then forming a select gate SG across the active area AA on the substrate 100; and finally forming a floating gate FG on the substrate 100. The second embodiment differs from the first embodiment in that the extension FG3 of the floating gate FG is a monolithic structure. Therefore, from a top view (Figure 10), the extension FG3 appears square, but this is not limiting. The main body FG1 is located on one side of the select gate SG and across the active area AA. The extension FG3 is located on the device isolation structure 102 and connected to one end of the main body FG1. In this embodiment, a source region 104, a drain region 106, and an intermediate region 108 are formed in the active area AA. A spacer 110 comprising a silicon nitride liner 112 and an oxide layer 114 is formed on the sidewalls of the select gate SG and the floating gate FG. A gate oxide layer GO is also formed on the surface of the substrate 100.

Referring to Figures 12A and 12B , a conformal dielectric structure DS is formed on the main portion FG1 and the extension portion FG3 , and the dielectric structure DS includes a stop layer SL. The dielectric structure DS may be, for example, an ONO structure or an ONONO structure, and the stop layer SL may be a silicon nitride layer.

Referring to Figures 13A and 13B , since the select gate SG needs to be electrically connected to the outside, a patterned photoresist layer 200 is first used to cover the entire extension FG3 and then etched to remove the dielectric structure DS above the entire active area AA, exposing the main body FG1 and the select gate SG.

Referring to Figures 14A and 14B , after removing the patterned photoresist layer 200 shown in Figures 13A and 13B , an interlayer dielectric (ILD) layer is formed on the substrate 100, covering the main portion FG1, the extension portion FG3, and the select gate SG. Then, for subsequent processing, another patterned mask 202 may be formed on the ILD layer to expose a portion of the ILD layer.

Referring to Figures 15, 16A, and 16B, an extension opening EO2 is formed in the interlayer dielectric layer ILD. The extension opening EO2 is formed, for example, by using a patterned mask 202 as an etching mask to remove the exposed interlayer dielectric layer ILD. Portions of the dielectric structure DS can also be removed simultaneously to expose the stop layer SL above the extension FG3.

Referring to Figures 17A and 17B , after removing the patterned mask 202 in Figures 16A and 16B , several contact openings CO1 are formed in the interlayer dielectric layer ILD to expose the select gate SG and the active area AA, respectively. The contact openings CO1 can be formed by, for example, first forming a patterned mask 204 to cover the area outside the active area AA and expose a portion of the interlayer dielectric layer ILD. The patterned mask 204 is then used as an etching mask to remove the exposed interlayer dielectric layer ILD.

Referring to Figures 18A and 18B , after removing the patterned mask 204 shown in Figures 17A and 17B , a conductive structure 122 is formed within the extension opening EO2 and the contact window opening CO1, serving as the control gate of the non-volatile memory structure. Conductive structure 122 includes a barrier layer 124 and a conductive layer 126. Barrier layer 124 is made of, for example, Ti/TiN or other suitable materials, and conductive layer 126 is made of, for example, a metal such as tungsten or other suitable conductive materials. Due to the large area of extension opening EO2, the top of conductive layer 126 formed within extension opening EO2 forms a recessed portion.

Referring to Figures 19A and 19B , a metal layer M1 is formed over the conductive structure 122. The metal layer M1 is, for example, an aluminum layer or other suitable metal layer. The metal layer M1 is electrically connected to the source region 104, the drain region 106, and the select gate SG of the active area AA. The metal layer M1 also directly contacts the conductive structure 122 above the extension FG3 to enhance coupling between the extension FG3 and the conductive structure 122.

The non-volatile memory structure of the second embodiment includes at least a substrate 100, a device isolation structure 102, a select gate SG, a body portion FG1 and an extension portion FG3 (of a floating gate), an interlayer dielectric layer ILD, a conductive structure 122, and a dielectric structure DS. The device isolation structure 102 is disposed within the substrate 100 to define an active area AA. The select gate SG is disposed on the substrate 100 and spans the active area AA. The body portion FG1 is located on one side of the select gate SG and spans the active area AA. The extension portion FG3 is located on the device isolation structure 102. The interlayer dielectric layer (ILD) is disposed above the select gate SG and the main portion FG1 and has a contact opening CO1 and an extension opening EO2. The contact opening CO1 exposes the select gate SG and the active area AA, respectively. The extension opening EO2 is above the extension FG3. The dielectric structure DS is located between the conductive structure 122 and the extension FG3. The stop layer SL (i.e., a silicon nitride layer) is in direct contact with the conductive structure 122.

Referring to Figures 20A and 20B , an intermetallic dielectric layer 206 and a via 208 may be formed on the metal layer M1 for external connection. The formation method may include, but is not limited to, first coating the intermetallic dielectric layer 206 on the interlayer dielectric layer ILD, then forming a via opening VO therein, forming a conformal barrier layer 210 therein, and finally filling the via opening VO with a metal layer 212.

Figure 21 is a top view of another example of the non-volatile memory structure of the second embodiment. The floating gate FG extension FG4 has a grid-like structure, allowing for the formation of similarly grid-shaped extension openings EO3. The remaining structure and manufacturing process remain the same as above and will not be further described.

Figures 22 to 28B are flowcharts illustrating the fabrication of a non-volatile memory structure according to the third embodiment of the present invention. The same reference numerals as in the second embodiment are used to represent identical or similar parts and components. For details regarding identical or similar parts and components, reference can be made to the second embodiment and will not be repeated here. Figures 22 and 26 are top views, and for clarity, most components are omitted. Figures 23A to 25A and 27A to 28A are cross-sectional views of the fabrication process taken along line A-A' in the top views; Figures 23B to 25B and 27B to 28B are cross-sectional views of the fabrication process taken along line B-B' in the top views.

Referring to Figures 22, 23A, and 23B, the manufacturing process of the third embodiment is similar to that of the second embodiment. A device isolation structure 102 is formed within a substrate 100; a select gate SG is formed on the substrate 100, spanning the active area AA; and a floating gate FG is formed on the substrate 100. The floating gate FG includes a main portion FG1 and an extension FG5. The main portion FG1 is located on one side of the select gate SG and spans the active area AA. The extension FG5 is located on the well area 302 and connected to one end of the main portion FG1. From a top view (Figure 22), the extension FG5 has a square structure, but this is not limited to this. In some embodiments, the extension FG5 may also have a comb-like or grid-like structure. The third embodiment differs from the second embodiment in that, in addition to defining the active area AA, the device isolation structure 102 further defines a coupling region 300 adjacent to the active area AA. A well region 302 is then formed within the coupling region 300, followed by a doped region 304 within the well region 302. The doped region 304 can be formed together with the source region 104, drain region 106, and intermediate region 108 of the active area AA, but is not limited thereto. In one embodiment, the well region 302 and the doped region 304 have the same conductivity type; in other embodiments, the well region 302 and the doped region 304 have different conductivity types. Therefore, the well region 302 and the doped region 304 can be N-type well/N+ region, P-type well/P+ region, N-type well/P+ region, or P-type well/N+ region. Furthermore, the third embodiment differs from the second embodiment in that, after forming the floating gate FG and the select gate SG, an interlayer dielectric layer ILD covering the floating gate FG and the select gate SG is formed on the substrate 100. A patterned mask 202 may then be formed on the interlayer dielectric layer ILD to expose a portion of the interlayer dielectric layer ILD. An etching process is then performed to form an extension opening EO2 in the interlayer dielectric layer ILD, wherein the extension opening EO2 exposes the extension FG5, and the interlayer dielectric layer ILD is located above the doped region 304 but does not overlap with the extension opening EO2 (as viewed from a top view). In this embodiment, spacers 110 comprising a silicon nitride liner 112 and an oxide layer 114 are formed on the sidewalls of the select gate SG and the floating gate FG. A gate oxide layer GO is formed on the surface of both the active area AA and the coupling region 300. Therefore, the extended opening EO2 also partially exposes the gate oxide layer GO.

Referring to Figures 24A and 24B , after removing the patterned mask 202 in Figures 23A and 23B , a conformal high-k dielectric layer 306 is formed on the sidewalls EO2s of the extension opening EO2 and the extension FG5 . The high-k dielectric layer 306 is also formed on the top surface of the interlayer dielectric layer ILD. However, the present invention is not limited to this, and the high-k dielectric layer 306 may also be replaced by an ONO structure or an ONONO structure.

Referring to Figures 25A and 25B , several contact openings are formed in the interlayer dielectric (ILD) layer. A first portion CO21 of the contact opening exposes the select gate SG and the active area AA, respectively, while a second portion CO22 of the contact opening exposes the doped region 304 within the coupling region 300. The first and second portions CO21 and CO22 can be formed by, for example, first forming a patterned mask 204 and then using the patterned mask 204 as an etching mask to remove the exposed ILD layer.

Referring to Figures 26, 27A, and 27B, a conductive structure 122 is formed within the first portion CO21 and the second portion CO22 of the extension opening EO2 and the contact window opening, serving as the control gate of the non-volatile memory structure. Conductive structure 122 includes a barrier layer 124 and a conductive layer 126. Barrier layer 124 may be made of, for example, Ti/TiN or other suitable materials, and conductive layer 126 may be made of, for example, a metal such as tungsten or other suitable conductive materials. Conductive structure 122 within extension opening EO2 covers the top and sides of extension FG5. Conductive structure 122 within first portion CO21 connects select gate SG to source region 104 and drain region 106 of active area AA, respectively. The conductive structure 122 in the second portion CO22 is connected to the doped region 304 and is electrically connected to the well region 302 through the doped region 304.

Referring to Figures 28A and 28B , a metal layer M1 is formed over the extension FG5 to connect the conductive structure 122 within the extension opening EO2 with the conductive structure 122 within the second portion CO22 of the contact opening. The metal layer M1 over the active area AA is electrically connected to the source region 104, drain region 106, and select gate SG of the active area AA. When a positive voltage is applied to the metal layer M1 over the coupling region 300, the extension FG5 not only couples with the conductive structure 122 on its top and sides, but also with the well region 302 beneath it, creating an all-around coupling structure, further improving the coupling efficiency.

The non-volatile memory structure of the third embodiment includes at least a substrate 100, an element isolation structure 102, a select gate SG, a main body portion FG1 (of a floating gate) and an extension portion FG5, an interlayer dielectric layer ILD, a conductive structure 122, and a single high-k dielectric layer 306. The element isolation structure 102 is disposed within the substrate 100 to define an active region AA and a coupling region 300. The coupling region 300 is located within the substrate 100 below the extension portion FG5. The coupling region 300 includes a well region 302 and a doped region 304, such as an N-type well and an N+ region. The doped region 304 is located outside the extension portion FG5. The select gate SG and the main body FG1 are both disposed on the substrate 100 and straddle the active area AA. The extension FG5 is disposed on the coupling region 300 and is separated from the substrate 100 by a gate oxide layer GO. An interlayer dielectric layer ILD is disposed above the select gate SG and the main body FG1 and has contact openings (a first portion CO21 and a second portion CO22) and an extension opening EO2. The first portion CO21 exposes the select gate SG and the active area AA, respectively, while the second portion CO22 exposes the doped region 304. The extension opening EO2 is located above the extension FG5. The conductive structure 122 is formed within the aforementioned opening and is electrically connected to the doped region 304, the source region 104, the drain region 106, and the select gate SG. A high-k dielectric layer 306 is interposed between the conductive structure 122 and the extension FG5 and directly contacts the conductive structure 122. The high-k dielectric layer 306 further extends to the sidewalls EO2s of the extension opening EO2 and is interposed between the conductive structure 122 and the interlayer dielectric layer ILD.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the art may make minor modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Base

102: Component Isolation Structure

110: Spacer

112: Silicon nitride liner

114: Oxide layer

122:Conductive structure

124: Barrier Layer

126: Conductor layer

FG2: Extension

ILD: Interlayer Dielectric

O1: Oxide layer

SL: Stop layer

Claims (18)

A method for fabricating a non-volatile memory structure comprises: forming a device isolation structure within a substrate to define an active region; forming a select gate on the substrate to span the active region; forming a floating gate on the substrate, the floating gate comprising a main portion and an extension, the main portion being located on one side of the select gate and spanning the active region, and the extension being located on the device isolation structure and connected to one end of the main portion; forming a conformal dielectric structure on the floating gate, the dielectric structure including a stop layer; forming an interlayer dielectric layer on the substrate to cover the floating gate and the select gate; An extension opening is formed in the interlayer dielectric layer, wherein the stop layer of the dielectric structure above the extension is exposed through the extension opening; a plurality of contact window openings are formed in the interlayer dielectric layer to expose the select gate and the active region, respectively; and a conductive structure is formed in the extension opening and the plurality of contact window openings. The method for manufacturing a non-volatile memory structure as described in claim 1, wherein the dielectric structure includes an ONO structure or an ONONO structure. The method for manufacturing a non-volatile memory structure as described in claim 1, wherein the stop layer is a silicon nitride layer or a high-k dielectric layer. The method for manufacturing a non-volatile memory structure as described in claim 1, wherein the extension opening and the plurality of contact window openings are formed using different processes. The method for manufacturing a non-volatile memory structure as described in claim 1, wherein the extension opening also extends above the main portion of the floating gate. A method for fabricating a non-volatile memory structure comprises: forming a device isolation structure within a substrate to define an active region and a coupling region; forming a well region and a doped region within the coupling region, the doped region being formed within the well region; forming a select gate on the substrate, extending across the active region; forming a floating gate on the substrate, the floating gate comprising a main portion and an extension portion, the main portion being located on one side of the select gate and extending across the active region, the extension portion being located on the well region and connected to one end of the main portion; forming an interlayer dielectric layer on the substrate, covering the floating gate and the select gate; An extension opening is formed in the interlayer dielectric layer, wherein the extension is exposed from the extension opening; A conformal high-k dielectric layer is formed on the sidewalls of the extension opening and on the extension; A plurality of contact window openings are formed in the interlayer dielectric layer, wherein a first portion of the plurality of contact window openings exposes the select gate and the active region, respectively, and a second portion of the plurality of contact window openings exposes the doped region in the coupling region; and A conductive structure is formed in the extension opening and the plurality of contact window openings. The method for manufacturing a non-volatile memory structure as described in claim 6, wherein the extension opening and the plurality of contact window openings are formed using different processes. The method for manufacturing a non-volatile memory structure as described in claim 6, wherein the extension opening also extends above the main portion of the floating gate. The method for manufacturing a non-volatile memory structure as described in claim 6 further comprises, after forming the conductive structure, forming a metal layer above the extension portion to connect the extension portion opening and the conductive structure in the second portion. A non-volatile memory structure comprises: a substrate; a device isolation structure disposed within the substrate to define an active region; a select gate disposed on the substrate and spanning the active region; a floating gate disposed on the substrate, the floating gate comprising a main portion and an extension portion, the main portion being located on one side of the select gate and spanning the active region, and the extension portion being connected to one end of the main portion and distal from the active region; An interlayer dielectric layer is disposed over the main portion of the floating gate and the select gate and has a plurality of contact window openings and an extension opening, wherein the plurality of contact window openings expose the select gate and the active region, respectively, and the extension opening is above the extension of the floating gate; A conductive structure is formed within the extension opening and the plurality of contact window openings; and At least one dielectric layer is disposed between the conductive structure and the extension of the floating gate, and the at least one dielectric layer directly contacting the conductive structure is a silicon nitride layer or a high-k dielectric layer. The non-volatile memory structure of claim 10, wherein the at least one dielectric layer is a stacked layer of an oxide layer and the silicon nitride layer. The non-volatile memory structure as described in claim 10, wherein the at least one dielectric layer is a single layer of the high-k dielectric layer. The non-volatile memory structure as described in claim 10, wherein the extension opening also extends above the main portion of the floating gate. The non-volatile memory structure as described in claim 10, wherein the at least one dielectric layer further extends to the sidewall of the extension opening and is between the conductive structure and the interlayer dielectric layer. The non-volatile memory structure as described in claim 10, wherein the extension portion is a comb-like structure or a grid-like structure in a top view. The non-volatile memory structure as described in claim 10, wherein the extension of the floating gate is disposed on the device isolation structure. The non-volatile memory structure as described in claim 10, wherein the device isolation structure further defines a coupling region in the substrate below the extension, and the coupling region includes a well region and a doped region, the doped region is formed in the well region and is located outside the extension. The non-volatile memory structure of claim 17, wherein the conductive structure formed in the extension opening is electrically connected to the doped region.