TWI893623B - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device is provided in the present invention, including a memory device on a semiconductor substrate, a first CESL and a second CESL conformally and sequentially on the surface of memory device, an ILD layer covering the second CESL, and a bit line contact extending vertically through the ILD layer, the second CESL and the first CESL to the semiconductor substrate, wherein an outwardly and horizontally extending protruding part is provided at the bottom of bit line contact and.

Description

Semiconductor device and manufacturing method thereof

The present invention generally relates to a semiconductor device and a method for manufacturing the same. More specifically, it relates to a semiconductor device having a flash memory and a larger bit line contact area and a method for manufacturing the same.

Flash memory (FLASH) has become a widely used non-volatile memory component in personal computers and electronic devices due to its ability to store, read, and erase data multiple times, and its stored data persists even after a power outage.

However, as the density of flash memory devices continues to increase, parasitic capacitance can easily affect the critical voltage (V _T ) of memory devices. For example, in NOR FLASH devices, crosstalk between the floating gate (FG) and the bit line (BL) can seriously interfere with the erase operation of Fowler-Nordheim (FN) tunneling, causing the critical voltage distribution to widen.

On the other hand, when depositing the interlayer dielectric (ILD), air gaps are created between adjacent bit lines. This can easily cause piping when depositing the conductive material to form the bit lines, leading to short circuits between the bit lines. Furthermore, the contact resistance between the bit lines and the substrate is likely to increase significantly with shrinking fabrication technology, impacting the performance of subsequent semiconductor devices.

Therefore, those skilled in the art must improve existing semiconductor device structures and processes in order to resolve the aforementioned known issues.

To address the aforementioned known problems, the present invention proposes a novel semiconductor device and its manufacturing method. Its features include a double-layer contact etch stop layer (CESL) design that creates a horizontally extending protrusion at the bottom of the bitline contact, thereby reducing contact resistance. Furthermore, the bitline contact is surrounded by a liner during formation, thus preventing piping. Furthermore, an air gap is formed between the bitline contact and the memory device to prevent crosstalk, which is the efficiency and advantage of the present invention.

One aspect of the present invention is to provide a semiconductor device having a structure comprising a semiconductor substrate, a memory device located on the semiconductor substrate, a first contact etch stop layer conformally located on a surface of the memory device, a second contact etch stop layer conformally located on a surface of the first contact etch stop layer, an interlayer dielectric layer covering the second contact etch stop layer, The semiconductor substrate includes a first contact etch stop layer and a second contact etch stop layer, and a bit line contact vertically extending through the interlayer dielectric layer, the second contact etch stop layer, and the first contact etch stop layer to electrically connect to the source/drain in the semiconductor substrate. The bottom of the bit line contact has a protrusion extending horizontally outward, and the protrusion is vertically located between the second contact etch stop layer and the semiconductor substrate.

Another aspect of the present invention is to provide a method for manufacturing a semiconductor device, the steps of which include providing a semiconductor substrate, forming a semiconductor device on the semiconductor substrate, sequentially forming a conformal first contact etch stop layer and a second contact etch stop layer on the surfaces of the semiconductor device and the semiconductor substrate, covering the second contact etch stop layer with a sacrificial polysilicon layer, performing a photolithography process to form a vertical A contact hole is formed by extending through the sacrificial polysilicon layer, the second contact etch stop layer, and the first contact etch stop layer to the semiconductor substrate. A wet etching process is performed to remove the exposed portion of the first contact etch stop layer at the bottom of the contact hole, thereby forming a protruding space extending horizontally outward from the contact hole. A conductive metal is then filled into the contact hole to form a contact having a protruding portion.

Another aspect of the present invention is to provide a method for manufacturing a semiconductor device, the steps of which include providing a semiconductor substrate, forming a semiconductor device on the semiconductor substrate, sequentially forming a conformal first contact etch stop layer and a second contact etch stop layer on the surfaces of the semiconductor device and the semiconductor substrate, covering the second contact etch stop layer with a sacrificial polysilicon layer, performing a photolithography process to pattern the sacrificial polysilicon layer to form vertical sacrificial polysilicon pillars, forming a conformal liner on the surfaces of the sacrificial polysilicon pillars and the second contact etch stop layer, and forming a conformal liner. An interlayer dielectric layer is formed to cover the liner, exposing the top surface of the sacrificial polysilicon pillar from the interlayer dielectric layer. The exposed sacrificial polysilicon pillar is removed to form a contact hole extending vertically through the interlayer dielectric layer and the second contact etch stop layer. A wet etching process is performed to remove the exposed first contact etch stop layer at the bottom of the contact hole, thereby extending the contact hole through the first contact etch stop layer to the semiconductor substrate and forming a protruding space extending horizontally outward from the contact hole. A conductive metal is then filled into the contact hole to form a contact having a protruding portion.

These and other objects of the present invention will become more apparent after the reader has read the following detailed description of the preferred embodiment described with reference to various figures and drawings.

100:Semiconductor substrate

102: Memory device

104: Tunneling oxide layer

106: Gate dielectric layer

110: Next door

112: First contact etch stop layer

114: Second contact etch stop layer

116: Sacrificial polysilicon layer

118: Contact hole

118a: Highlight Space

120: Bit line contacts

120a: protrusion

122: Interlayer dielectric layer

124: Air Gap

126: Sacrificial polycrystalline silicon pillars

128: Lining

130: Conductive metal

132: Metal wiring

Figure 1 is a schematic cross-sectional view of a semiconductor device having a flash memory and a larger bitline contact area according to an embodiment of the present invention; Figures 2 to 8 are schematic cross-sectional views of the fabrication process of a semiconductor device having a flash memory and a larger bitline contact area according to an embodiment of the present invention; and Figures 9 to 16 are schematic cross-sectional views of the fabrication process of a semiconductor device having a flash memory and a larger bitline contact area according to another embodiment of the present invention.

Please note that all illustrations in this manual are for illustrative purposes only. For the sake of clarity and ease of illustration, the sizes and proportions of the components in the illustrations may be exaggerated or reduced. Generally speaking, the same reference symbols in the drawings will be used to indicate corresponding or similar components and features in modified or different embodiments.

The following describes in detail exemplary embodiments of the present invention, with reference to the accompanying figures illustrating the described features to facilitate understanding and implementation of the technical effects. The reader should understand that the description herein is by way of example only and is not intended to limit the present invention. The various embodiments of the present invention and non-conflicting features within the embodiments may be combined or rearranged in various ways. Modifications, equivalents, or improvements to the present invention will be apparent to those skilled in the art and are intended to be within the scope of the present invention.

Readers should readily understand that the meanings of “on,” “over,” and “above” in this disclosure should be interpreted broadly, such that “on” means not only “directly on” something but also includes being “on” something with intervening features or layers, and “on” or “above” means not only “on” or “above” something but also includes being “on” or “above” something with no intervening features or layers (i.e., directly on something). In addition, for convenience of description, spatially relative terms such as “under,” “beneath,” “lower,” “over,” and “upper” may be used herein to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

As used herein, the term "layer" refers to a portion of a material comprising a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than that of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and/or along an inclined surface. A substrate may be a layer, which may include one or more layers, and/or may have one or more layers located thereon, above, and/or below. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which contacts, interconnects, and/or vias are formed) and one or more dielectric layers.

Readers can generally understand terms at least in part from their usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used in a singular sense to describe any feature, structure, or characteristic, or can be used in a plural sense to describe a combination of features, structures, or characteristics. Similarly, depending at least in part on the context, terms such as "a," "an," "the," or "said" can likewise be understood to convey either singular or plural usage. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors but can allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

Readers should further understand that when words such as "include" and/or "comprising" are used in this specification, they specify the presence of the described features, regions, entireties, steps, operations, elements, and/or components, but do not exclude the possibility of the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components, and/or combinations thereof.

The following embodiments will illustrate the semiconductor device and its manufacturing process of the present invention with reference to Figures 1 and 2-8. It should be noted that while the present embodiments utilize NOR flash memory devices as an example, the concepts of the present invention are not limited thereto. In other embodiments, the structure and manufacturing method of the present invention can also be applied to NAND flash memory devices or other semiconductor devices that address similar issues.

Referring now to FIG. 1 , which is a schematic cross-sectional view of a semiconductor device with flash memory and a large bitline contact area according to an embodiment of the present invention. As shown, the semiconductor device of the present invention includes a semiconductor substrate 100 as the foundation for the entire structure. Semiconductor substrate 100 can comprise any suitable substrate, such as a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. Semiconductor substrate 100 can include a silicon material such as silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbon (SiC), or a multilayer structure thereof. Although silicon is the most common semiconductor material used in wafer manufacturing, other semiconductor materials can also be used as additional layer structures in the present invention, including but not limited to germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), silicon germanium (SiGe), cadmium telluride (CdTe), zinc selenide (ZnSe), etc.

Refer again to FIG. 1 . A memory element 102 is formed on a semiconductor substrate 100. In the embodiment of the present invention, the memory element 102 is exemplified by a NOR FLASH, which may include a floating gate FG, a control gate CG, and an auxiliary gate AG. The floating gate FG is formed on the semiconductor substrate 100 with a tunnel oxide layer 104 between the floating gate FG and the semiconductor substrate 100. The control gate CG is formed on the floating gate FG with an intergate dielectric layer 106 between the floating gate FG and the control gate CG. On the other hand, an auxiliary gate AG may be formed on the semiconductor substrate 100 adjacent to the floating gate FG. The auxiliary gate AG does not contact the floating gate FG, and a control gate CG may also be provided thereon. A tunnel oxide layer 104 may also be provided between the auxiliary gate AG and the semiconductor substrate 100, and an intergate dielectric layer 106 may also be provided between the auxiliary gate AG and the control gate CG thereon. In an embodiment, the floating gate FG and the auxiliary gate AG may have the same height, and the two control gates CG may also have the same height. In an embodiment of the present invention, the floating gate FG, the control gate CG, and the auxiliary gate AG may be made of doped polysilicon, the tunnel oxide layer 104 may be made of silicon oxide, and the intergate dielectric layer 106 may be made of a multilayer structure consisting of silicon oxide/silicon nitride (ON) or silicon oxide/silicon nitride/silicon oxide (ONO). In this embodiment, a floating gate FG, an auxiliary gate AG, and two control gates CG constitute a memory device 102. The present invention uses two memory devices 102 as an example, which have identical and mirror-symmetrical structural configurations, but the present invention is not limited to this.

Refer again to Figure 1. Spacers 110 may be formed on the sidewalls of the floating gate FG, control gate CG, and auxiliary gate AG. These spacers separate the gates from surrounding components and define the source/drain regions in the semiconductor substrate 100. Furthermore, in this embodiment of the present invention, a first contact etch stop layer (CESL) 112 and a second contact etch stop layer 114 are sequentially formed on the memory device 102. The first and second contact etch stop layers 112, 114 are conformally formed on the surface of the memory device 102 and serve as etch stop layers in the subsequent contact formation process. An interlayer dielectric (ILD) 122, such as a pre-metal dielectric (PMD), is formed on the second contact etch stop layer 114, blanketing the memory device 102 and the semiconductor substrate 100. In one embodiment, the spacers 110 may be made of silicon oxide, the first contact etch stop layer 112 may be made of silicon oxide, the second contact etch stop layer 114 may be made of silicon nitride, and the interlayer dielectric 122 may be made of silicon oxide or a low-k dielectric material.

Refer again to FIG. 1 . In an embodiment of the present invention, a bit line contact 120 extends vertically through an interlayer dielectric layer 122, a second contact etch stop layer 114, and a first contact etch stop layer 112 to electrically connect to a source/drain (not shown) in the semiconductor substrate 100. It should be noted that in the present invention, the bottom of the bit line contact 120 has a protrusion 120 a extending horizontally outward. The protrusion 120 a is vertically located between the second contact etch stop layer 114 and the semiconductor substrate 100, and its top surface may be flush with the adjacent first contact etch stop layer 112. The material of the bit line contact 120 may be tungsten (W). Because the bitline contact 120 of the present invention has a horizontal protrusion 120a for contacting the semiconductor substrate 100, it can reduce contact resistance due to the increased contact area, solving the problem of the contact resistance between the bitline and the substrate increasing significantly due to device scaling in the prior art. Furthermore, in this embodiment of the present invention, an air gap 124 can be provided between the bitline contact 120 and the adjacent floating gate FG or auxiliary gate AG. Air gap 124 is located between the bit line contact 120, the second contact etch stop layer 114, the first contact etch stop layer 112, and the floating gate FG/auxiliary gate AG. Its ultra-low dielectric constant effectively solves the crosstalk problem between the floating gate and the bit line in conventional technology, preventing the critical voltage (V _T ) from being distributed over a wider range.

During the write/erase operation of the memory device 102, a bias voltage is applied from the control gate CG and the source/drain connected to the bit line contact 120, causing electrons to tunnel into or out of the floating gate FG. During the flash memory read operation, an operating voltage is applied from the control gate CG. The charge state of the floating gate FG affects the on/off state of the channel below it. The on/off state of this channel serves as the basis for determining whether the data value is "0" or "1". When no voltage is applied to auxiliary gate AG, no source region is formed in semiconductor substrate 100 below auxiliary gate AG, thereby preventing leakage current from the source region to the drain region of memory device 102. On the other hand, during operation of memory device 102, a voltage is applied through auxiliary gate AG, forming an inversion layer in semiconductor substrate 100 below it, which serves as a source region.

After describing the semiconductor device of the present invention, please refer to Figures 2 to 8, which are cross-sectional schematic diagrams illustrating the manufacturing process of a semiconductor device having a flash memory and a larger bit line contact area according to an embodiment of the present invention.

First, please refer to Figure 2. At the beginning of the process, a semiconductor substrate 100, such as a silicon substrate, is provided as the foundation for the entire structure. A memory element 102 is then formed on the semiconductor substrate 100. Taking NOR FLASH as an example, the present invention may include sequentially forming a tunnel oxide layer, a first doped polysilicon layer, an intergate dielectric layer, and a second doped polysilicon layer on the semiconductor substrate 100. The above-mentioned layer structure can be formed through a suitable deposition process, such as a chemical vapor deposition process (CVD) or an atomic layer deposition process (ALD). The tunnel oxide layer can also be formed through thermal oxidation. Subsequently, a photolithography process is performed to pattern the aforementioned layers, forming a gate stack structure comprising a tunneling oxide layer 104, a floating gate FG, an intergate dielectric layer 106, and a control gate CG, as shown in the figure; and a gate stack structure comprising a tunneling oxide layer 104, an auxiliary gate AG, an intergate dielectric layer 106, and a control gate CG. The two gate stack structures are adjacent to each other but do not directly contact each other. After the gate stack structure is formed, spacers 110 are formed on the sidewalls of the gate stack structure. These spacers can be formed through a deposition process and an etch-back process. After the spacers 110 are formed, source/drain electrodes and self-aligned silicide (such as CoSi ₂ ) structures may be formed on the semiconductor substrate 100. Since the source/drain electrodes and self-aligned silicide are not the focus of the present invention, they are not shown for the sake of simplicity.

Refer to Figure 3. After the memory device 102 is formed, a first contact etch stop layer 112 and a second contact etch stop layer 114 are sequentially formed on the memory device 102. The first contact etch stop layer 112 and the second contact etch stop layer 114 can be conformally formed on the memory device 102 and the semiconductor substrate 100 through an atomic layer deposition process. It should be noted that in this embodiment of the present invention, the first contact etch stop layer 112 and the second contact etch stop layer 114 are made of materials with different etch selectivities, such as silicon oxide and silicon nitride, to provide etch selectivity in subsequent processes.

See Figure 4. After the first contact etch stop layer 112 and the second contact etch stop layer 114 are formed, a sacrificial polysilicon layer 116 is formed on the second contact etch stop layer 114. The sacrificial polysilicon layer 116 can be formed using a CVD process. It blankets the memory device 102 and fills the spaces and gaps therebetween. In other embodiments, the sacrificial polysilicon layer 116 can be replaced with other materials, such as a material having a different etch selectivity than the first contact etch stop layer 112 and the second contact etch stop layer 114.

Please refer to Figure 5. After the sacrificial polysilicon layer 116 is formed, a photolithography process is performed to form a contact hole 118 that extends vertically through the sacrificial polysilicon layer 116, the second contact etch-stop layer 114, and the first contact etch-stop layer 112. The contact hole 118 connects to the source/drain or metal silicide on the surface of the semiconductor substrate 100, and allows portions of the second contact etch-stop layer 114 and the first contact etch-stop layer 112 to be exposed from the sidewalls of the contact hole 118.

Please refer to Figure 6. After the contact hole 118 is formed, a wet etching process is performed to remove the first contact etch stop layer 112 from the bottom of the contact hole 118, thereby forming a protruding space 118a extending horizontally outside the contact hole 118. In this embodiment of the present invention, the wet etching process may be an immersion etching process that uses buffered hydrofluoric acid (BHF) as an etchant to selectively etch the first contact etch stop layer 112 made of silicon oxide without removing the second contact etch stop layer 114 made of silicon nitride and the sacrificial polysilicon layer 116 made of polysilicon. This forms a protruding space 118a extending horizontally outward from the contact hole 118. The protruding space 118a is located vertically between the second contact etch stop layer 114 and the semiconductor substrate 100. The advantage of the double-layer contact etch stop layer design of the present invention is that the special contact hole 118 protruding space 118a can be formed through the above-mentioned process.

Refer to Figure 7. After the protruding space 118a is formed, the contact hole 118 is then filled with a conductive metal, such as tungsten (W), via a CVD process. This forms a bitline contact 120 having a protruding portion 120a, as shown. This protruding portion 120a is vertically positioned between the second contact etch-stop layer 114 and the semiconductor substrate 100, and its top surface is aligned with the adjacent first contact etch-stop layer 112. The sacrificial polysilicon layer 116 is removed after the bitline contact 120 is formed, for example, by selectively wet etching the sacrificial polysilicon layer 116 using an etchant containing a mixture of hydrofluoric acid, nitric acid, and acetic acid, or by dry etching using a chlorine-based etching gas. In the present invention, the bitline contact 120 has a horizontal protrusion 120a that contacts the semiconductor substrate 100. This increases the contact area and reduces contact resistance, resolving the conventional problem of significantly increasing contact resistance between the bitline and substrate as device dimensions are reduced.

See Figure 8. After the sacrificial polysilicon layer 116 is removed, an interlayer dielectric layer 122, such as a pre-metal deposition dielectric (PMD), is deposited over the second contact etch stop layer 114. The interlayer dielectric layer 122 can be formed using LPCVD or PECVD processes and can be made of silicon oxide-based phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or a low-k material. The interlayer dielectric layer 122 fills the gaps between the memory elements 102 and blankets the memory elements 102. A chemical mechanical planarization (CMP) process exposes and surrounds the previously formed bit line contacts 120. It should be noted that in this embodiment of the present invention, after the formation of the interlayer dielectric layer 122, an air gap 124 forms in the relatively narrow space between the bitline contact 120 and the adjacent floating gate FG or auxiliary gate AG due to uneven filling. The ultra-low dielectric constant of air gap 124 effectively solves the crosstalk problem between the floating gate and the bitline in conventional technology, preventing the critical voltage (V _T ) from being distributed over a wider range.

Next, please refer to Figures 9 through 16, which are cross-sectional schematic diagrams illustrating the fabrication process of a semiconductor device having flash memory and a larger bitline contact area according to another embodiment of the present invention. This embodiment differs from the previous embodiments in that sacrificial polysilicon pillars are formed first rather than a sacrificial polysilicon layer. This allows for an additional protective liner to be formed over the entire structure before the bitline contacts are formed, thus avoiding the conventional piping problem.

First, please refer to Figure 9. This figure continues the steps of Figure 4 in the aforementioned embodiment. After the sacrificial polysilicon layer 116 is formed, a photolithography process is performed to pattern the sacrificial polysilicon layer 116, forming vertical sacrificial polysilicon pillars 126 as shown. In this embodiment of the present invention, sacrificial polysilicon pillars 126 are located between the memory devices 102 and aligned with the source/drain electrodes (not shown) in the underlying semiconductor substrate 100. Their top surfaces are higher than the top surface of the second contact etch stop layer 114. The photolithography process may include first forming a patterned photoresist, and then using the photoresist as a mask to perform a dry etching process using chlorine as the main etching gas to etch the sacrificial polysilicon layer 116, thereby forming the sacrificial polysilicon pillars 126. This etching process stops after the second contact etch stop layer 114 of the silicon nitride material is exposed.

Refer to Figure 10. After the sacrificial polysilicon pillars 126 are formed, a conformal liner 128 is formed over the entire substrate surface. In this embodiment of the present invention, the liner 128 is located on the surfaces of the sacrificial polysilicon pillars 126 and the second contact etch stop layer 114. Its thickness is preferably less than the gap between the sacrificial polysilicon pillars 126 and the memory device 102. The material of the liner 128 can be silicon nitride, which can be formed using an atomic layer deposition process.

See Figure 11. After the liner layer 128 is formed, an interlayer dielectric layer 122 is blanketed on the liner layer 128. The interlayer dielectric layer 122 can be formed using LPCVD or PECVD processes and can be made of silicon oxide-based phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or a low-k material. The interlayer dielectric layer 122 fills the gaps between the memory elements 102 and covers the memory elements 102 and the sacrificial polysilicon pillars 126. It should be noted that in this embodiment of the present invention, after the formation of the interlayer dielectric layer 122, an air gap 124 is formed in the relatively narrow space between the sacrificial polysilicon pillar 126 and the adjacent floating gate FG or auxiliary gate AG due to uneven filling. The ultra-low dielectric constant of the air gap 124 effectively solves the crosstalk problem between the floating gate and the bit line in conventional technology, preventing the critical voltage (V _T ) from being distributed over a wider range.

Refer to Figure 12. After forming the interlayer dielectric layer 122, a CMP process is performed to remove the interlayer dielectric layer 122, liner layer 128, and sacrificial polysilicon pillars 126 above a certain height, exposing the sacrificial polysilicon pillars 126 from the liner layer 128. A dry etching process, such as an anisotropic dry etching process using chlorine as the primary etching gas, is then performed on the sacrificial polysilicon pillars 126, using the interlayer dielectric layer 122 as a mask. This removes the sacrificial polysilicon pillars 126 and forms contact holes 118 in the interlayer dielectric layer 122. In this embodiment of the present invention, the dry etching process also removes the second contact etch stop layer 114 exposed from the contact hole 118 and stops after the first contact etch stop layer 112 is exposed. Thus, the resulting contact hole 118 extends vertically through the interlayer dielectric layer 122, is surrounded by the liner layer 128, and has the first contact etch stop layer 112 at its bottom.

Please refer to Figure 13. After the contact hole 118 is formed, a wet etching process is then performed to remove the first contact etch stop layer 112 from the bottom of the contact hole 118. In this way, the contact hole 118 passes through the first contact etch stop layer 112 to the semiconductor substrate 100, and a protruding space 118a extending horizontally toward the outside of the contact hole 118 is formed. In this embodiment of the present invention, the wet etching process may be an immersion etching process, which uses buffered hydrofluoric acid as an etchant to selectively etch the first contact etch stop layer 112 made of silicon oxide without removing the second contact etch stop layer 114 and the liner 128 made of silicon nitride. This forms a protruding space 118a extending horizontally outward from the contact hole 118. The protruding space 118a is located vertically between the second contact etch stop layer 114 and the semiconductor substrate 100. The advantage of the double-layer contact etch stop layer design of the present invention is that the special contact hole 118 protruding space 118a can be formed through the above-mentioned process.

Refer to Figure 14. After the protruding space 118a of the contact hole 118 is formed, the contact hole 118 is then filled with a conductive metal 130, such as tungsten (W) through a CVD process. The conductive metal 130 also fills the previously formed protruding space 118a. A portion of the conductive metal 130 is located on the interlayer dielectric layer 122 outside the contact hole 118.

Refer to Figure 15 . After the conductive metal 130 is filled, a chemical mechanical planarization (CMP) process is performed to remove the conductive metal 130, the interlayer dielectric layer 122, and the liner 128 above a certain height. This results in a bitline contact 120 with a protruding portion 120a surrounded by the liner 128, as shown in the figure. In this embodiment, the bitline contact 120 after CMP is preferably taller than the interlayer dielectric layer 122. This allows a portion of the bitline contact 120 to protrude from the surface of the interlayer dielectric layer 122, facilitating subsequent circuit connection. The protrusion 120a of the bitline contact 120 is vertically positioned between the second contact etch-stop layer 114 and the semiconductor substrate 100, and its top surface is flush with the adjacent first contact etch-stop layer 112. In the present invention, the horizontal protrusion 120a of the bitline contact 120 in contact with the semiconductor substrate 100 increases the contact area and reduces contact resistance, resolving the conventional problem of significantly increasing contact resistance between the bitline and substrate due to device scaling.

Please refer to Figure 16. After the bitline contact 120 is formed, the semiconductor back-end-of-line (BEOL) process can be performed to form a metal line 132 on the interlayer dielectric layer 122. The metal line 132 will be electrically connected to the bitline contact 120 protruding from the surface of the interlayer dielectric layer 122. The material of the metal line 132 can be tungsten (W) or copper (Cu) and can be formed using a CVD process.

From the above-described embodiments, it can be understood that the present invention's unique feature lies in the double-layer contact etch-stop layer design, which creates a horizontally extending protrusion at the bottom of the bitline contact, thereby reducing contact resistance. Furthermore, the bitline contact is surrounded by a liner during formation, thus preventing the formation of a communication channel after the bitline contact is formed. Furthermore, an air gap is formed between the bitline contact and the memory device, preventing crosstalk between them. These are the key features and advantages of the present invention's structure.

The above description is merely a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention should fall within the scope of the present invention.

100: Semiconductor substrate 102: Memory device 104: Tunneling oxide layer 106: Intergate dielectric layer 110: Spacer 112: First contact etch-stop layer 114: Second contact etch-stop layer 120: Bit line contact 120a: Protrusion 122: Interlayer dielectric layer 124: Air gap

Claims (18)

A semiconductor device comprises: a semiconductor substrate; a memory device disposed on the semiconductor substrate; a first contact etch stop layer conformally disposed on a surface of the memory device; a second contact etch stop layer conformally disposed on a surface of the first contact etch stop layer; an interlayer dielectric layer covering the second contact etch stop layer; and A bit line contact extends vertically through the interlayer dielectric layer, the second contact etch stop layer, and the first contact etch stop layer to electrically connect to the source/drain in the semiconductor substrate. The bottom of the bit line contact has a protrusion extending horizontally outward, and the protrusion is vertically located between the second contact etch stop layer and the semiconductor substrate. The semiconductor device as described in claim 1, wherein the memory device includes a floating gate and a control gate located on the floating gate. The semiconductor device as described in claim 2, wherein the memory device further includes an auxiliary gate adjacent to the floating gate. The semiconductor device of claim 2 further comprises an air gap between the bit line contact and the second contact etch stop layer, the first contact etch stop layer, and the floating gate. The semiconductor device as described in claim 1 further comprises a liner conformally disposed on surfaces of the bit line contact and the second contact etch stop layer, wherein the interlayer dielectric layer is disposed on the liner. The semiconductor device as described in claim 5, wherein the material of the liner is silicon nitride. The semiconductor device as described in claim 1, wherein the material of the first contact etch stop layer is silicon oxide. The semiconductor device as described in claim 1, wherein the material of the second contact etch stop layer is silicon nitride. A method for manufacturing a semiconductor device comprises: providing a semiconductor substrate and forming a semiconductor device on the semiconductor substrate; sequentially forming a conformal first contact etch stop layer and a second contact etch stop layer on the surfaces of the semiconductor device and the semiconductor substrate; covering the second contact etch stop layer with a sacrificial polysilicon layer; performing a photolithography process to form a contact hole extending vertically through the sacrificial polysilicon layer, the second contact etch stop layer, and the first contact etch stop layer to the semiconductor substrate; A wet etching process is performed to remove the exposed portion of the first contact etch stop layer at the bottom of the contact hole from within the contact hole, thereby forming a protruding space extending horizontally outward from the contact hole; and a conductive metal is filled into the contact hole to form a contact having a protruding portion. The method for manufacturing a semiconductor device as described in claim 9 further comprises: Removing the sacrificial polysilicon layer after forming the contact; and Coating an interlayer dielectric layer on the second contact etch stop layer. The method for manufacturing a semiconductor device as described in claim 10, wherein the step of covering the second contact etch stop layer with an interlayer dielectric layer further includes: forming an air gap between the bit line contact and the second contact etch stop layer, the first contact etch stop layer, and the floating gate. A method for manufacturing a semiconductor device as described in claim 9, wherein the material of the first contact etch stop layer is silicon oxide, the material of the second contact etch stop layer is silicon nitride, and the wet etching process uses hydrofluoric acid to selectively etch the first contact etch stop layer. A method for manufacturing a semiconductor device comprises: providing a semiconductor substrate and forming a semiconductor device on the semiconductor substrate; sequentially forming a conformal first contact etch stop layer and a second contact etch stop layer on the surfaces of the semiconductor device and the semiconductor substrate; covering the second contact etch stop layer with a sacrificial polysilicon layer; performing a photolithography process to pattern the sacrificial polysilicon layer to form vertical sacrificial polysilicon pillars; forming a conformal liner layer on the surfaces of the sacrificial polysilicon pillars and the second contact etch stop layer; An interlayer dielectric layer is formed covering the liner, with the top surface of the sacrificial polysilicon pillar exposed from the interlayer dielectric layer; The exposed sacrificial polysilicon pillar is removed, thereby forming a contact hole extending vertically through the interlayer dielectric layer and the second contact etch stop layer; A wet etching process is performed to remove the exposed first contact etch stop layer at the bottom of the contact hole from within the contact hole, thereby extending the contact hole through the first contact etch stop layer to the semiconductor substrate and forming a protruding space extending horizontally outward from the contact hole; and The contact hole is filled with a conductive metal, thereby forming a contact having a protruding portion. The method for manufacturing a semiconductor device as described in claim 13, wherein the step of forming an interlayer dielectric layer covering the liner further includes: forming an air gap between the sacrificial polysilicon pillar and the second contact etch stop layer, the first contact etch stop layer, and the floating gate. A method for manufacturing a semiconductor device as described in claim 13, wherein the material of the first contact etch stop layer is silicon oxide, the material of the second contact etch stop layer is silicon nitride, the material of the liner is silicon nitride, and the wet etching process uses hydrofluoric acid to selectively etch the first contact etch stop layer. The method for manufacturing a semiconductor device as described in claim 13 further comprises: After forming the interlayer dielectric layer, performing a chemical mechanical planarization process to remove the interlayer dielectric layer and the sacrificial polysilicon pillars above a certain height, thereby exposing the sacrificial polysilicon pillars from the interlayer dielectric layer. The method for manufacturing a semiconductor device as described in claim 13, wherein the step of removing the exposed sacrificial polysilicon pillar further comprises: Performing an anisotropic dry etching process using the interlayer dielectric layer as a hard mask to remove the sacrificial polysilicon pillar and the first contact etch-stop layer directly beneath the sacrificial polysilicon pillar, thereby exposing the second contact etch-stop layer. The method for manufacturing a semiconductor device as described in claim 13, wherein the step of forming a contact having a protruding portion further comprises: After filling the conductive metal, performing a chemical mechanical planarization process to remove the conductive metal on the interlayer dielectric layer, thereby forming the contact having a protruding portion, wherein the contact protrudes from the surface of the interlayer dielectric layer.