TWI892421B - Pumping controller for a plurality of charge pump units - Google Patents

Abstract

In one example, a system comprises a plurality of charge pump units connected in parallel to receive an input voltage and to generate an output voltage greater than the input voltage and a pumping controller to provide a pumping signal to a first charge pump unit of the plurality of charge pump units and to provide sequentially delayed versions of the pumping signal to the other charge pump units of the plurality of charge pump units.

Description

Pumping controller for multiple charge pump units

[Priority Request]

This application claims priority to U.S. Provisional Patent Application No. 63/442,807, filed on February 2, 2023, entitled “CHARGE PUMP INCLUDING A SELF-OSCILLATING VOLTAGE REGULATOR BASED ON A LATTICE,” and U.S. Patent Application No. 18/135,395, filed on April 17, 2023, entitled “PUMPING CONTROLLER FOR A PLURALITY OF CHARGE PUMP UNITS.”

A pumping controller for providing a pumping signal to a plurality of charge pump units is disclosed.

Charge pumps are commonly used in semiconductor devices to generate voltages greater than the available supply voltage, which is typically denoted by VDD. For example, charge pumps are used in flash memory systems to generate voltages greater than VDD for programming, erasing, or reading operations.

Conventional designs include multiple charge pump units operating in parallel. One limitation of these conventional designs is that, because each charge pump unit simultaneously initiates its charge and discharge operations based on a common pumping signal, a power surge occurs at the beginning of each charge cycle, which can damage circuits sensitive to surges in current or voltage. Another drawback of conventional designs is that, if the charge pump reaches the desired voltage level, charging can sometimes continue for a period of time before stopping, causing its output to be higher than desired.

What is needed is an improved charge pump design and control system.

A pumping controller for a plurality of charge pumps is disclosed.

FIG1 illustrates a system including a voltage regulator 100. Voltage regulator 100 includes charge pump cells 102-1, 102-2, 102-3, and 102-4. Charge pump cells 102-1, 102-2, 102-3, and 102-4 are connected in parallel, and each receives an input voltage VDD and generates an output voltage VD25 that is greater than the input voltage. In this example, four charge pump cells are connected in parallel to provide an output voltage VD25 sufficient to power an attached load without voltage droop.

Voltage regulator 100 further includes a pumping controller 101. Pumping controller 101 includes a voltage divider having a first resistor 103 and a second resistor 104. This voltage divider generates a divided voltage _VS at node 113 that is proportional to output voltage VD25. Comparator 106 receives and compares the divided voltage _VS at its first non-inverting input and a reference voltage VREF at its second inverting input. When _VS > VREF, comparator 106 output VDET is high, and when _VS < VREF, comparator 106 output is low. Capacitor 105 converts ripple from VD25 to _VS , accelerating comparator 106.

The latch 107 is a gate-controlled D-type latch with a reset signal, which operates according to the following truth table: R D LAT Q 1 0/1 0/1 0 0 0/1 0 D 0 0/1 1 Q

The RESET signal is provided by other logic circuits or controllers (not shown) to the reset port R of the latch 107. The latch enable port LAT of the latch 107 receives the signal VDET from the comparator 106. The data port D of the latch 107 receives the signal from the inverter 112, as will be described in detail below. As shown in the aforementioned truth table, when the RESET signal at the reset port R is asserted, its output Q is 0 regardless of the values received by the data port D and the latch enable port LAT. When the RESET signal on the reset port R is not asserted, but the signal received by the latch enable port LAT is asserted (this occurs when _VS > VREF, indicating that VD25 has reached or exceeded the desired voltage), output Q maintains its level regardless of the value subsequently received by data port D. When the RESET signal on the reset port R is not asserted and the signal received by the latch enable port LAT is not asserted (this occurs when _VS < VREF, indicating that VD25 is less than the desired voltage and requires additional pumping), output Q will be whatever value is received by data port D at that time.

Output Q is signal PMP CLK, which is provided as a pumping signal to charge pump unit 102-1 and the input of delay circuit 108. Delay circuit 108 processes the received signal PMP CLK but adds a delay to generate signal PMP CLK′ at the output of delay circuit 108.

PMP CLK′ is provided as a pumping signal to the charge pump unit 102 - 2 and the input of the delay circuit 109 . The delay circuit 109 processes the received signal PMP CLK′ but adds a delay to generate the signal PMP CLK″ at the output of the delay circuit 109 .

PMP CLK″ is provided as a pumping signal to the charge pump unit 102 - 3 and the input of the delay circuit 110 . The delay circuit 110 processes the received signal PMP CLK″ but adds a delay to generate the signal PMP CLK″ at the output of the delay circuit 110 .

PMP CLK''' is provided as a pumping signal to the inputs of charge pump cell 102-4 and delay circuit 111. Delay circuit 111 processes the received signal PMP CLK''' but adds an additional delay to generate signal PMP CLK'''' at the output of delay circuit 111. In this example, charge pump cell 102-4 is the last of the plurality of (charge) pump cells 102.

The inverter 112 receives the signal PMP CLK'''' and generates an inverted version of PMP CLK'''', and then provides the inverted version as a data signal to the data port D of the latch 107.

The end result is that when RESET is low and VDET is low, the pumping controller generates an oscillating signal (PMP CLK) and generates multiple sequentially delayed versions of the oscillating signal (PMP CLK', PMP CLK'', PMP CLK''', and PMP CLK''''). When VDET goes high, PMP CLK remains stable at its current value, and the oscillation of the oscillating signal (PMP CLK) and the sequentially delayed versions of the oscillating signal (PMP CLK', PMP CLK'', PMP CLK''', and PMP CLK'''') ceases.

Therefore, it can be understood that the voltage regulator 100 includes: a plurality of charge pump cells 102 for receiving an input voltage (VDD) and generating an output voltage (VD25) greater than the input voltage; and a pumping controller 101 for providing a pumping signal (PMP CLK) to a first pump cell (e.g., charge pump cell 102-1) of the plurality of pump cells, and providing respective sequentially delayed variations of the pumping signal (PMP CLK′, PMP CLK″, and PMP CLK′″) to the other pump cells (e.g., charge pump cells 102-2, 102-3, and 102-4) of the plurality of pump cells.

Although the voltage regulator 100 in this example includes four pump units 102 , it should be understood that the voltage regulator 100 may alternatively include fewer than four pump units 102 or more than four pump units 102 .

FIG2 depicts a timing diagram 200 of the voltage regulator 100 and shows the signals PMP CLK, VD25, and VDET. Unlike some prior art systems, the output voltage VD25 does not experience additional charge cycles that would cause the output voltage to be higher than expected (in contrast to the dashed line shown for VD25, which illustrates how VD25 experiences voltage increases in some prior art systems). This is due to VDET being used as the LAT input to the latch 107. That is, when VDET goes high, the output PMP CLK of latch 107 will remain in its current state and will stop oscillating (in contrast to the dashed line shown for PMP CLK, which illustrates how PMP CLK may behave in some prior art systems).

FIG3 depicts a method 300 for operating the voltage regulator 100 of FIG1 and FIG2. The method 300 includes receiving an input voltage (301) through a plurality of charge pump cells connected in parallel; providing a pumping signal to a first charge pump cell of the plurality of charge pump cells (302); providing a plurality of sequentially delayed variations of the pumping signal to other charge pump cells of the plurality of charge pump cells (303); and generating an output voltage greater than the input voltage (304) through the plurality of charge pump cells.

FIG4 depicts method 400. Method 400 is an example of a method for performing the steps of providing a pumping signal to a first charge pump unit (302) of a plurality of charge pump units and providing a plurality of sequentially delayed variations of the pumping signal to other charge pump units (303) of the plurality of charge pump units in method 300. The method 400 includes comparing a voltage proportional to an output voltage with a reference voltage to generate a comparator output (401); receiving the comparator output as a latch start signal (402) by a gate-controlled D-type latch having a reset port; receiving a data signal on a data port and a reset signal on a reset port by the gate-controlled D-type latch (403); generating a pumping signal as an output by the gate-controlled D-type latch (404); generating a plurality of sequentially delayed variations of the pumping signal (405) through respective delay circuits; receiving an input (406) comprising a delayed variation of the pumping signal provided to the last charge pump unit in the plurality of charge pump units through an inverter; generating an output (407) through the inverter; and providing the output of the inverter as a data signal to a latch (408).

It should be noted that, as used herein, the terms "over" and "on" include both "directly on" (without intervening materials, elements, or spaces therebetween) and "indirectly on" (with intervening materials, elements, or spaces therebetween). For example, forming a component "over a substrate" may include forming the component directly on the substrate without intervening materials/elements, and forming the component indirectly on the substrate with one or more intervening materials/elements therebetween.

100: Voltage regulator 101: Pumping controller 102: Pump unit 102-1: Charge pump unit 102-2: Charge pump unit 102-3: Charge pump unit 102-4: Charge pump unit 103: First resistor 104: Second resistor 105: Capacitor 106: Comparator 107: Latch 108: Delay circuit 109: Delay circuit 1 10: Delay circuit 111: Delay circuit 112: Inverter 113: Node 200: Timing diagram 300: Methods 301, 302, 303, 304: (Method) Step 400: Methods 401, 402, 403, 404, 405, 406, 407, 408: (Method) Step D: Data port LAT: Latch enable port PMP CLK: (Pumping) signal PMP CLK': (Pumping signal) delay variation/signal PMP CLK'': (Pumping signal) delay variation/signal PMP CLK''': (Pumping signal) delay variation/signal PMP CLK'''': (Pumping signal) delay variation/signal Q: Output R: Reset port RESET: (Reset port) signal VD25: Output voltage VDD: Input voltage VDET: (Comparator) output/signal VREF: Reference voltage _VS : Divider voltage

Figure 1 depicts a schematic diagram of a voltage regulator including a pumping controller and a plurality of charge pump units.

Figure 2 depicts the timing diagram for the voltage regulator of Figure 1.

FIG3 and FIG4 illustrate the steps of operating the voltage regulator of FIG1.

100: Voltage regulator

101: Pumping Controller

102-1: Charge pump unit

102-2: Charge pump unit

102-3: Charge pump unit

102-4: Charge pump unit

103: First resistor

104: Second resistor

105:Capacitor

106: Comparator

107: Latch

108: Delay Circuit

109: Delay Circuit

110: Delay circuit

111: Delay Circuit

112: Inverter

113: Node

Claims (16)

A charge pumping system includes: a plurality of charge pump cells connected in parallel to receive an input voltage and generate an output voltage greater than the input voltage; and a pumping controller for providing a pumping signal to a first charge pump cell of the plurality of charge pump cells and providing a plurality of sequentially delayed variations of the pumping signal to other charge pump cells of the plurality of charge pump cells. The pumping controller includes: a voltage divider for receiving the output voltage and generating a lower voltage at a node, the voltage divider including a first resistor coupled to a second resistor at the node, wherein the first resistor receives the output voltage; and A capacitor coupled between the output voltage and the node. The system of claim 1, wherein the pumping controller comprises: a comparator comprising a first input coupled to the node, a second input coupled to a reference voltage, and an output. The system of claim 2, wherein the pumping controller comprises: a latch that generates a latch output in response to an output from the comparator received on a latch activation port, a data signal received on a data port, and a reset signal received on a reset port. The system of claim 3, wherein the latch output is provided as the pumping signal to the first charge pump unit of the plurality of charge pump units. The system of claim 4, wherein the pumping controller comprises: A plurality of delay circuits for generating sequentially delayed variations of the pumping signal. The system of claim 5, wherein the pumping controller comprises: an inverter configured to receive as an input a delayed variation of a pumping signal provided to a last one of the other charge pump units in the plurality of charge pump units and to generate an output, wherein the output of the inverter is provided as the data signal to the latch. A charge pumping method comprises: receiving an input voltage via a plurality of charge pump cells connected in parallel; providing a pumping signal to a first charge pump cell of the plurality of charge pump cells; providing a plurality of sequentially delayed variations of the pumping signal to other charge pump cells of the plurality of charge pump cells; generating an output voltage greater than the input voltage via the plurality of charge pump cells; comparing a voltage proportional to the output voltage with a reference voltage to generate a comparator output; receiving the comparator output at a latch enable port via a gate-controlled D-type latch having a reset port; The latch receives a data signal on a data port and a reset signal on a reset port; and the latch generates the pumping signal as an output. The method of claim 7, comprising: Producing the sequentially delayed variations of the pump signal by respective delay circuits. The method of claim 8, comprising: receiving, via an inverter, an input comprising a delayed variation of a pumping signal provided to a last charge pump unit among the other charge pump units in the plurality of charge pump units; and generating, via the inverter, an output. The method of claim 9, comprising: Providing the output of the inverter as the data signal to the latch. A charge pumping system includes: a voltage regulator that generates a pumping signal for a first pump unit of a plurality of pump units connected in parallel and generates a plurality of sequentially delayed variations of the pumping signal for the remaining pump units of the plurality of pump units; a voltage divider that receives an output voltage from the plurality of pump units and generates a voltage proportional to the output voltage at a node, the voltage divider including a first resistor coupled to a second resistor at the node, wherein the first resistor receives the output voltage; and a capacitor including a first plate that receives the output voltage and a second plate coupled to the node. The system of claim 11, comprising: A comparator comprising a first input coupled to the node, a second input coupled to a reference voltage, and an output. The system of claim 12, comprising: A latch that generates a latch output in response to an output from the comparator received on a latch enable port, a data signal received on a data port, and a reset signal received on a reset port. The system of claim 13, wherein the latch output is provided as the pumping signal. The system of claim 14, comprising: A plurality of delay circuits for generating sequentially delayed variations of the pumping signal. The system of claim 15, comprising: An inverter for receiving a last of the sequentially delayed variations of the pump signal as an input and generating an output provided to the latch as the data signal.