TWI892481B - Memory system and receiver - Google Patents

Abstract

A memory system includes a controller and a memory circuit. The controller is configured to output a first data strobe signal and a second data strobe signal. The memory circuit is coupled to controller, and is configured to receive first data strobe signal and second data strobe signal. The memory circuit includes a receiver. The receiver includes a logic conversion circuit. The logic conversion circuit is coupled to controller. When the first data strobe signal and the second data strobe signal are at the same voltage level, the logic conversion circuit is configured to convert the first data strobe signal and second data strobe signal into the third data strobe signal and the fourth data strobe signal. The third data strobe signal and the fourth data strobe signal converted by logic conversion circuit are at different voltage levels. When the first data strobe signal and the second data strobe signal are at different voltage levels, the logic conversion circuit is configured to pass the first data strobe signal and the second data strobe signal and as the third data strobe signal and the fourth data strobe signal.

Description

Memory systems and receivers

This case involves an electronic system and an electronic device. More specifically, it involves a memory system and a receiver.

Existing controllers are defined by different memory companies, and the data strobe signals output by these controllers during the standby phase (or undefined phase) violate the Joint Electron Device Engineering Council (JEDEC) memory standard. Incorrect data strobe signals can cause memory circuit failures.

Therefore, the above technology still has many defects, and it is necessary for practitioners in this field to develop other suitable memory systems and receivers.

One aspect of the present invention relates to a memory system. The memory system includes a controller and a memory circuit. The controller is used to output a first data selection signal and a second data selection signal. The memory circuit is coupled to the controller and is used to receive the first data selection signal and the second data selection signal. The memory circuit includes a receiver. The receiver includes a logic conversion circuit. When the first data selection signal and the second data selection signal are at the same voltage level, the logic conversion circuit is used to convert the first data selection signal and the second data selection signal into a third data selection signal and a fourth data selection signal. The third data selection signal and the fourth data selection signal converted by the logic conversion circuit include different voltage levels. When the first data strobe signal and the second data strobe signal are at different voltage levels, the logic conversion circuit is used to transmit the first data strobe signal as the third data strobe signal and to transmit the second data strobe signal as the fourth data strobe signal.

Another aspect of this invention relates to a receiver. The receiver includes an amplifier and a logic conversion circuit. The amplifier is used to receive and amplify a first data selection signal and a second data selection signal from a controller. The logic conversion circuit is coupled to the amplifier. When the first data selection signal and the second data selection signal are at the same voltage level, the logic conversion circuit is used to convert the first data selection signal and the second data selection signal into a third data selection signal and a fourth data selection signal. After conversion by the logic conversion circuit, the third data selection signal and the fourth data selection signal have different voltage levels. When the first data strobe signal and the second data strobe signal are at different voltage levels, the logic conversion circuit is used to transmit the first data strobe signal as the third data strobe signal and to transmit the second data strobe signal as the fourth data strobe signal.

In view of the aforementioned shortcomings and deficiencies of the prior art, this invention provides a memory system and receiver for converting data strobe signals of the same voltage level into data strobe signals of different voltage levels specified by JEDEC, so that the memory chip or memory circuit can operate normally.

The following diagrams and detailed descriptions clearly illustrate the spirit of this invention. After understanding the embodiments of this invention, anyone with ordinary skill in the art can make changes and modifications based on the techniques taught in this invention without departing from the spirit and scope of this invention.

The terms used herein are for describing specific embodiments only and are not intended to be limiting of the present invention. Singular forms such as "a," "the," "this," and "the" as used herein also include plural forms.

The terms "include", "including", "have", "contain", etc. used in this document are open terms, meaning including but not limited to.

Unless otherwise noted, the terms used in this document generally have the ordinary meanings they possess in the art, within the context of this application, and in the specific context. Certain terms used to describe this application are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art regarding the description of this application.

FIG1 is a circuit block diagram of a memory system 100 according to some embodiments of the present invention. Referring to FIG1 , in some embodiments, the memory system 100 includes a controller 110 and a memory circuit 120. The controller 110 is coupled to the memory circuit 120. The controller 110 is configured to transmit a plurality of signals CMD and a plurality of data via a plurality of data buses D1-D15. The memory circuit 120 includes a receiver 121 and a plurality of control circuits 122. The memory circuit 120 includes dynamic random-access memories (DRAM). In some embodiments, the plurality of signals CMD include a plurality of commands and a plurality of signals generated by the controller 110.

Controller 110 is used to generate data strobe signals DQS1 and DQS2 to receiver 121 before receiver 121 enters the preamble stage. Receiver 121 is used to accurately identify each transmission cycle within a clock cycle based on data strobe signals DQS1 and DQS2, allowing receiver 121 to receive multiple data from multiple data buses D1-D15.

In some embodiments, data strobe signals DQS1 and DQS2 represent data strobe signals DQS_c and DQS_t, respectively, as defined in the JEDEC memory standard. Controller 110 can adjust the relationship between data strobe signals DQS (DQS_c and DQS_t) and clock signals CK (CK_t and CK_c) by writing equalization characteristics and device feedback characteristics. Specifically, the controller samples the clock signals using the rising or falling edges of data strobe signals DQS1 and DQS2. The technical terms "_t" and "_c" are used to represent the true value and complement of a differential signal pair, respectively.

Then, Double Data Rate Synchronous Dynamic Random-access Memory (DDR SDRAM) stands for "Double Data Rate Synchronous Dynamic Random-access Memory." The technical term "double data rate" can be applied to any product that uses two edges (rising and falling) to periodically transition a signal from "1" to "0" (or vice versa), such as a clock or data strobe. DDR SDRAM uses a bidirectional data strobe (DQS) that moves in parallel with the DQ (input/output data) signal. This allows the DDR SDRAM to use the DQS signal as a reference signal to obtain the corresponding DQ signal. A single DQS signal can correspond to either a 4-bit or 8-bit DQ signal. The fundamental benefit of using a DQS signal is that it achieves a high data rate per pin by reducing both the access time of the double-data-rate synchronous dynamic random access memory (DDRM) and the propagation delay between the DDRM and the memory controller. Furthermore, the skew between the input clock signals of the DDRM and the memory controller can be ignored.

According to memory industry regulations, such as those from the Joint Electron Device Engineering Council (JEDEC), data strobe signals DQS1 and DQS2 are required to be high and low, respectively, during the standby phase preceding the preamble stage (i.e., data strobe signal DQS1 is high and data strobe signal DQS2 is low). The preamble stage provides a timing window for the receiving device to activate its capture circuitry when a known/valid level is present on the data strobe signal, thereby avoiding false triggering of the capture circuitry. During the preamble phase and the subsequent data input phase, the data strobe signals DQS1 and DQS2 vary between high and low levels. In actual applications, some manufacturers or product suppliers do not follow the Joint Electron Device Engineering Council (JEDEC) specifications. As a result, the data strobe signals DQS1 and DQS2 provided by these manufacturers are not at the correct levels during the standby phase (i.e., DQS1 is high and DQS2 is low).

Specifically, during the standby phase before the preamble phase, the data strobe signals DQS1 and DQS2 output by the controller 110 (which should be high and low, respectively, according to JEDEC regulations) are mistakenly considered to be at the same voltage level. This can cause memory cell failure. To prevent memory cell failure, the present embodiment generates data strobe signals DQS3 and DQS4 based on data strobe signals DQS1 and DQS2, respectively. Data strobe signals DQS3 and DQS4 follow JEDEC regulations during the standby phase (i.e., data strobe signal DQS3 is at a high level and data strobe signal DQS4 is at a low level).

FIG2 is a circuit block diagram of a receiver 121 of the memory circuit 120 of the memory system 100 of FIG1 according to some embodiments of the present invention. The receiver 121 includes an amplifier DA and a logic conversion circuit LC.

Amplifier DA is configured to receive and amplify data strobe signals DQS1 and DQS2. In some embodiments, amplifier DA comprises a differential amplifier. A logic conversion circuit LC is coupled to amplifier DA. In other words, logic conversion circuit LC is configured to convert data strobe signals DQS1 (e.g., 0 or 1) and data strobe signals DQS2 (e.g., 0 or 1) into data strobe signals DQS3 (e.g., 1) and data strobe signals DQS4 (e.g., 0).

FIG3 is a circuit block diagram of a logic conversion circuit LC1 corresponding to the logic conversion circuit LC of the receiver 121 in FIG2 according to some embodiments of the present invention.

Logic conversion circuit LC1 includes input terminal N1, input terminal N2, output terminal N3, and output terminal N4. Input terminal N1 is used to receive data strobe signal DQS1. Input terminal N2 is used to receive data strobe signal DQS2. Output terminal N3 is used to output data strobe signal DQS3. Output terminal N4 is used to output data strobe signal DQS4.

Logic conversion circuit LC1 further includes inverter I1, inverter I2, logic gate G1, and logic gate G2. The first terminal is counted from the top and right of the components in the figure. Inverter I1 and inverter I2 each include a first terminal and a second terminal. Logic gate G1 includes input terminal A, input terminal B, and output terminal X. Logic gate G2 includes input terminal C, input terminal D, and output terminal Y. In some embodiments, logic gate G1 includes an OR gate. Logic gate G2 includes an AND gate.

In some embodiments, input terminal A of logic gate G1 is coupled to input terminal N1 of logic conversion circuit LC1. Input terminal B of logic gate G1 is coupled to a first terminal of inverter I1. A second terminal of inverter I1 is coupled to input terminal N2 of logic conversion circuit LC1. Output terminal X of logic gate G1 is coupled to output terminal N3 of logic conversion circuit LC1.

Input terminal C of logic gate G2 is coupled to the first terminal of inverter I2. The second terminal of inverter I2 is coupled to input terminal N1 of logic conversion circuit LC1. Input terminal D of logic gate G2 is coupled to input terminal N2 of logic conversion circuit LC1. Output terminal Y of logic gate G2 is coupled to output terminal N4 of logic conversion circuit LC1. The truth table of logic conversion circuit LC1 is shown below.

Table 1. Data strobe signal DQS1 Data strobe signal DQS2 Data strobe signal DQS3 Data strobe signal DQS4 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0

FIG4 is a signal timing diagram of data strobe signals DQS1 to DQS4 according to some embodiments of the present invention. The signal timing diagram includes a standby phase T1, a preamble phase T2, and a data input phase T3.

Referring to Figures 3 and 4, the data strobe signal DQS1 and the data strobe signal DQS2 are erroneously at the same voltage level (e.g., low level L) during the standby phase T1.

During the standby phase T1, both data strobe signals DQS1 and DQS2 are at a low level, L. Logic conversion circuit LC1 is used to convert the first data strobe signal DQS1 (e.g., a low level, L) and the second data strobe signal DQS2 (e.g., a low level, L) into a third data strobe signal DQS3 (e.g., a high level, H) and a fourth data strobe signal DQS4 (e.g., a low level, L). During the standby phase T1, which precedes the preamble phase T2, the third data strobe signal DQS3 and the fourth data strobe signal DQS4 comply with JEDEC specifications.

During the preamble phase T2 and the data input phase T3, the first data strobe signal DQS1 and the second data strobe signal DQS2 both switch between a high level (H) and a low level (L). The logic conversion circuit LC1 is used to convert the first and second data strobe signals DQS1 and DQS2 into the third and fourth data strobe signals DQS3 and DQS4, respectively. This ensures that the logic conversion circuit LC1 does not affect the original operation of the preamble phase T2 and the data input phase T3.

However, in the embodiment of the present invention, the standby phase T1 before the leading phase T2 is not limited to the voltage level of each of the first data strobe signal DQS1 and the second data strobe signal DQS2 being at the low level L. The voltage level of the data strobe signal DQS1 and the data strobe signal DQS2 can be at the high level H, which will be discussed in the following paragraphs.

FIG5 is a signal timing diagram of data strobe signals DQS1 to DQS4 according to some embodiments of the present invention. The signal timing diagram includes a standby phase T1, a preamble phase T2, and a data input phase T3.

Referring to Figures 3 and 5, the data strobe signal DQS1 and the data strobe signal DQS2 are both erroneously at the same voltage level (e.g., high level H) during the standby phase T1.

During the standby phase T1, both data strobe signals DQS1 and DQS2 are at a high level (H). Logic conversion circuit LC1 is used to convert the first data strobe signal DQS1 (e.g., a high level (H)) and the second data strobe signal DQS2 (e.g., a high level (H)) into a third data strobe signal DQS3 (e.g., a high level (H)) and a fourth data strobe signal DQS4 (e.g., a low level (L)). During the standby phase T1, which precedes the preamble phase T2, the third data strobe signal DQS3 and the fourth data strobe signal DQS4 comply with JEDEC specifications.

During the preamble phase T2 and the data input phase T3, the first data strobe signal DQS1 and the second data strobe signal DQS2 both switch between a high level (H) and a low level (L). The logic conversion circuit LC1 is used to convert the first and second data strobe signals DQS1 and DQS2 into the third and fourth data strobe signals DQS3 and DQS4, respectively. This ensures that the logic conversion circuit LC1 does not affect the original operation of the preamble phase T2 and the data input phase T3.

FIG6 is a circuit block diagram of a logic conversion circuit LC2 corresponding to the logic conversion circuit LC of the receiver 121 in FIG2 according to some embodiments of the present invention.

Logic conversion circuit LC2 includes input terminal N1, input terminal N2, output terminal N3, and output terminal N4. Input terminal N1 is used to receive data strobe signal DQS1. Input terminal N2 is used to receive data strobe signal DQS2. Output terminal N3 is used to output data strobe signal DQS3. Output terminal N4 is used to output data strobe signal DQS4.

Logic conversion circuit LC2 further includes an inverter I3, an inverter I4, a logic gate G3, and a logic gate G4. Inverter I1 and inverter I2 each include a first terminal and a second terminal. Logic gate G3 includes an input terminal A, an input terminal B, and an output terminal X. Logic gate G4 includes an input terminal C, an input terminal D, and an output terminal Y. In some embodiments, logic gate G3 includes a NAND gate. Logic gate G4 includes a NOR gate.

In some embodiments, input terminal A of logic gate G3 is coupled to a first terminal of inverter I3. A second terminal of inverter I3 is coupled to input terminal N1 of logic conversion circuit LC2. Input terminal B of logic gate G3 is coupled to input terminal N2 of logic conversion circuit LC2. Output terminal X of logic gate G3 is coupled to output terminal N3 of logic conversion circuit LC2.

Input terminal C of logic gate G4 is coupled to input terminal N1 of logic conversion circuit LC2. Input terminal D of logic gate G4 is coupled to the first terminal of inverter I4. The second terminal of inverter I4 is coupled to input terminal N2 of logic conversion circuit LC2. Output terminal Y of logic gate G4 is coupled to output terminal N4 of logic conversion circuit LC2. The operation of logic conversion circuit LC2 is similar to that of logic conversion circuit LC1. The truth table of logic conversion circuit LC2 is similar to Table 1 of logic conversion circuit LC1.

FIG7 is a circuit block diagram of a logic conversion circuit LC3 corresponding to the logic conversion circuit LC of the receiver 121 in FIG2 according to some embodiments of the present invention. There are multiple differences between the logic conversion circuit LC3 in FIG7 and the logic conversion circuit LC1 in FIG3. The first difference is that the logic conversion circuit LC3 further includes an inverter I3. The second difference is that the logic gate G2 further includes an input terminal E. The third difference is that the inverter I3 is coupled to the input terminal E of the logic gate G2 and the output terminal X of the logic gate G1. The remaining circuit structure of the embodiment of FIG7 is similar to the circuit structure of FIG3 and is not described in detail here. The operation of logic conversion circuit LC3 is similar to that of logic conversion circuit LC1. The truth table of logic conversion circuit LC3 is similar to Table 1 of logic conversion circuit LC1.

FIG8 is a circuit block diagram of a logic conversion circuit LC4 corresponding to the logic conversion circuit LC of the receiver 121 in FIG2 according to some embodiments of the present invention.

There are several differences between the logic conversion circuit LC4 of Figure 8 and the logic conversion circuit LC2 of Figure 6. The first difference is that the logic gate G4 further includes an input terminal E. The second difference is that the input terminal E of the logic gate G4 is coupled to the output terminal X of the logic gate G3. The remaining circuit structure of the embodiment of Figure 8 is similar to the circuit structure of Figure 6 and is not described in detail here. The operation of the logic conversion circuit LC4 is similar to the operation of the logic conversion circuit LC1. The truth table of the logic conversion circuit LC4 is similar to Table 1 of the logic conversion circuit LC1.

In some embodiments, the Boolean algebra of each of the logic conversion circuits LC1 to LC4 is listed below according to Table 1. ...Formula 1

According to the aforementioned embodiments, the present invention provides a memory system and a receiver for converting data strobe signals of the same voltage level into data strobe signals of different voltage levels specified by JEDEC, so that the memory chip or memory circuit operates normally.

Although this invention is disclosed above with detailed embodiments, it does not exclude other feasible embodiments. Therefore, the scope of protection of this invention shall be determined by the scope of the attached patent application, and shall not be limited by the aforementioned embodiments.

It is clear to those skilled in the art that various modifications and improvements can be made to this application without departing from the spirit and scope of this application. Based on the aforementioned embodiments, all modifications and improvements made to this application are also covered by the scope of protection of this application.

100: Memory system 110: Controller 120: Memory circuit 121: Receiver 122: Control circuit CMD: Signal D1-D15: Data bus DA: Amplifier LC, LC1-LC4: Logic conversion circuit DQS1-DQS4: Data strobe signal N1, N2, A, B, C, D, E: Inputs N3, N4, X, Y: Outputs G1-G4: Logic gates I1-I4: Inverters H: High level L: Low level T1: Standby phase T2: Preamble phase T3: Data input phase

The present invention may be better understood by referring to the embodiments described in the following paragraphs and the following figures: Figure 1 is a schematic circuit block diagram of a memory system according to some embodiments of the present invention; Figure 2 is a schematic circuit block diagram of a receiver of a memory circuit of a memory system according to some embodiments of the present invention; Figure 3 is a schematic circuit block diagram of a logic conversion circuit of a receiver according to some embodiments of the present invention; Figure 4 is a schematic signal timing diagram of multiple data strobe signals according to some embodiments of the present invention; Figure 5 is a schematic signal timing diagram of multiple data strobe signals according to some embodiments of the present invention; Figure 6 is a schematic circuit block diagram of a logic conversion circuit of a receiver according to some embodiments of the present invention; Figure 7 is a schematic circuit block diagram of a logic conversion circuit of a receiver according to some embodiments of the present invention; and Figure 8 is a schematic circuit block diagram of a logic conversion circuit of a receiver according to some embodiments of the present invention.

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121: Receiver DA: Amplifier LC: Logic Converter DQS1-DQS4: Data Strobe Signals

Claims (15)

A memory system includes: A controller configured to output a first data strobe signal and a second data strobe signal; and A memory circuit coupled to the controller and configured to receive the first data strobe signal and the second data strobe signal, wherein the memory circuit includes a receiver, wherein the receiver includes: A logic conversion circuit is coupled to the controller. When the first data strobe signal and the second data strobe signal are at the same voltage level, the logic conversion circuit is configured to convert the first data strobe signal and the second data strobe signal into a third data strobe signal and a fourth data strobe signal. The third data strobe signal and the fourth data strobe signal converted by the logic conversion circuit have different voltage levels. When the first data strobe signal and the second data strobe signal are at different voltage levels, the logic conversion circuit is configured to transmit the first data strobe signal as the third data strobe signal and to transmit the second data strobe signal as the fourth data strobe signal. The memory system of claim 1, wherein the receiver further comprises: An amplifier coupled to the logic conversion circuit and configured to receive and amplify the first data strobe signal and the second data strobe signal. The memory system of claim 2, wherein the logic conversion circuit comprises: a first input terminal for receiving the first data strobe signal; a second input terminal for receiving the second data strobe signal; a first output terminal for outputting the third data strobe signal; a second output terminal for outputting the fourth data strobe signal; a first inverter comprising: a first terminal; and a second terminal coupled to the second input terminal of the logic conversion circuit; and a second inverter comprising: a first terminal; and a second terminal coupled to the first input terminal of the logic conversion circuit. The memory system of claim 3, wherein the logic conversion circuit further comprises: a first logic gate comprising: a first input terminal coupled to the first input terminal of the logic conversion circuit; a second input terminal coupled to the first terminal of the first inverter; and an output terminal coupled to the first output terminal of the logic conversion circuit; and a second logic gate comprising: a first input terminal coupled to the first terminal of the second inverter; a second input terminal coupled to the second input terminal of the logic conversion circuit; and an output terminal coupled to the second output terminal of the logic conversion circuit. The memory system of claim 4, wherein the second logic gate further includes a third input terminal, and wherein the logic conversion circuit further includes: a third inverter comprising: a first terminal coupled to the third input terminal; and a second terminal coupled to the output terminal of the first logic gate. The memory system of claim 2, wherein the logic conversion circuit comprises: a first input terminal for receiving the first data strobe signal; a second input terminal for receiving the second data strobe signal; a first output terminal for outputting the third data strobe signal; a second output terminal for outputting the fourth data strobe signal; a first inverter comprising: a first terminal; and a second terminal coupled to the first input terminal of the logic conversion circuit; and a second inverter comprising: a first terminal; and a second terminal coupled to the second input terminal of the logic conversion circuit. The memory system of claim 5, wherein the logic conversion circuit further comprises: a first logic gate comprising: a first input terminal coupled to the first terminal of the first inverter; a second input terminal coupled to the second input terminal of the logic conversion circuit; and an output terminal coupled to the first output terminal of the logic conversion circuit; and a second logic gate comprising: a first input terminal coupled to the first input terminal of the logic conversion circuit; a second input terminal coupled to the first terminal of the second inverter; and an output terminal coupled to the second output terminal of the logic conversion circuit. The memory system of claim 7, wherein the second logic gate further includes a third input terminal, wherein the third input terminal of the second logic gate is coupled to the output terminal of the first logic gate. A receiver includes: an amplifier for receiving and amplifying a first data strobe signal and a second data strobe signal from a controller; and A logic conversion circuit is coupled to the amplifier. When the first data strobe signal and the second data strobe signal are at the same voltage level, the logic conversion circuit is configured to convert the first data strobe signal and the second data strobe signal into a third data strobe signal and a fourth data strobe signal. The third data strobe signal and the fourth data strobe signal converted by the logic conversion circuit have different voltage levels. When the first data strobe signal and the second data strobe signal are at different voltage levels, the logic conversion circuit is configured to transmit the first data strobe signal as the third data strobe signal and to transmit the second data strobe signal as the fourth data strobe signal. The receiver of claim 9, wherein the logic conversion circuit comprises: a first input terminal for receiving the first data strobe signal; a second input terminal for receiving the second data strobe signal; a first output terminal for outputting the third data strobe signal; a second output terminal for outputting the fourth data strobe signal; a first inverter comprising: a first terminal; and a second terminal coupled to the second input terminal of the logic conversion circuit; and a second inverter comprising: a first terminal; and a second terminal coupled to the first input terminal of the logic conversion circuit. The receiver of claim 10, wherein the logic conversion circuit further comprises: a first logic gate comprising: a first input terminal coupled to the first input terminal of the logic conversion circuit; a second input terminal coupled to the first terminal of the first inverter; and an output terminal coupled to the first output terminal of the logic conversion circuit; and a second logic gate comprising: a first input terminal coupled to the first terminal of the second inverter; a second input terminal coupled to the second input terminal of the logic conversion circuit; and an output terminal coupled to the second output terminal of the logic conversion circuit. The receiver of claim 11, wherein the second logic gate further includes a third input terminal, and wherein the logic conversion circuit further includes: a third inverter comprising: a first terminal coupled to the third input terminal; and a second terminal coupled to the output terminal of the first logic gate. The receiver of claim 9, wherein the logic conversion circuit comprises: a first input terminal for receiving the first data strobe signal; a second input terminal for receiving the second data strobe signal; a first output terminal for outputting the third data strobe signal; a second output terminal for outputting the fourth data strobe signal; a first inverter comprising: a first terminal; and a second terminal coupled to the first input terminal of the logic conversion circuit; and a second inverter comprising: a first terminal; and a second terminal coupled to the second input terminal of the logic conversion circuit. The receiver of claim 13, wherein the logic conversion circuit further comprises: a first logic gate comprising: a first input terminal coupled to the first terminal of the first inverter; a second input terminal coupled to the second input terminal of the logic conversion circuit; and an output terminal coupled to the first output terminal of the logic conversion circuit; and a second logic gate comprising: a first input terminal coupled to the first input terminal of the logic conversion circuit; a second input terminal coupled to the first terminal of the second inverter; and an output terminal coupled to the second output terminal of the logic conversion circuit. The receiver of claim 14, wherein the second logic gate further comprises a third input terminal, wherein the third input terminal of the second logic gate is coupled to the output terminal of the first logic gate.