TWI892154B - Driving circuit - Google Patents

Abstract

A driving circuit providing power to an internal circuit and including a junction field effect transistor (JFET), a resistance, and an electrostatic discharge (ESD) protection circuit is provided. The source of the JFET is coupled to the internal circuit. The resistance is coupled between the gate of the JFET and a power terminal. The ESD protection circuit is coupled between the source and the power terminal. In a normal operation period, the internal circuit operates according to the voltage of the source. In a protection period, the ESD protection circuit is turned to release an ESD current to the power terminal.

Description

drive circuit

The present invention relates to a drive circuit, and in particular to a drive circuit with electrostatic discharge protection capability.

Component damage caused by electrostatic discharge (ESD) has become one of the most significant reliability issues for integrated circuit products. As device dimensions continue to shrink to sub-micron levels, the gate oxide layer of metal oxide semiconductors (MOS) becomes increasingly thinner, making integrated circuits more susceptible to damage from ESD.

According to general industry standards, the input and output pins (I/O) of integrated circuit products must be able to pass human body model ESD tests exceeding 2000 volts and mechanical model ESD tests exceeding 200 volts. Therefore, ESD protection devices must be installed near all I/O pads in integrated circuit products to protect the core circuits from ESD current.

One embodiment of the present invention provides a driver circuit for supplying power to an internal circuit. The driver circuit includes a junction field-effect transistor (JFET), an impedance element, and an electrostatic discharge (ESD) protection circuit. The JFET has a first gate, a first drain, and a first source. The first source is coupled to the internal circuit. The impedance element is coupled between the first gate and a first power supply terminal. The ESD protection circuit is coupled between the first source and the first power supply terminal. During normal operation, the internal circuit operates based on the voltage at the first source. During a protection period, the ESD protection circuit conducts to discharge an ESD current to the first power supply terminal.

In another embodiment, the first drain is coupled to a second power terminal. When the voltage of the second power terminal increases, the voltage of the first source increases.

In another embodiment, the impedance element is a resistor. The resistance of the resistor is greater than 5M ohms.

In another embodiment, the impedance element is a metal oxide semiconductor field effect transistor. The metal oxide semiconductor field effect transistor has a second gate, a second source, and a second drain. The second gate is coupled to the second source. The second drain is coupled to the first gate. The second source is coupled to the first power terminal.

In another embodiment, the impedance element is a metal oxide semiconductor field effect transistor. The metal oxide semiconductor field effect transistor has a second gate, a second source, and a second drain. The second gate is coupled to the second source. The second source is coupled to the first gate. The second drain is coupled to the first power terminal.

In another embodiment, the impedance element is a bipolar junction transistor (BJT). The BJT has a base, a collector, and an emitter. The base is coupled to the emitter. The collector is coupled to the first gate. The emitter is coupled to the first power terminal.

In another embodiment, the impedance element is a bipolar junction transistor. The bipolar junction transistor has a base, a collector, and an emitter. The base is coupled to the emitter. The emitter is coupled to the first gate. The collector is coupled to the first power terminal.

In another embodiment, when an electrostatic discharge event occurs, the voltage of the first gate is greater than the voltage of the first source.

100: Control chip

100: Control chip

110: Drive circuit

120: Internal circuit

130, 140: Power supply

111: Junction Field Effect Transistor

112: Impedance Element

113: Electrostatic discharge protection circuit

G_1, G_2, G_3: Gates

D_1, D_2, D_3: Drain

S_1, S_2, S_3: Source

Cgd: parasitic capacitance

210: N-type metal oxide semiconductor field effect transistor

220: P-type metal oxide semiconductor field effect transistor

230, 240: Bipolar junction transistor

B_1, B_2: Base

C_1, C_2: Collectors

E_1, E_2: emitter

Figure 1 is a schematic diagram of the control chip of the present invention.

Figure 2A is a schematic diagram of the impedance element of the present invention.

Figure 2B is another schematic diagram of the impedance element of the present invention.

Figure 2C is another schematic diagram of the impedance element of the present invention.

Figure 2D is another schematic diagram of the impedance element of the present invention.

To make the objects, features, and advantages of the present invention more clearly understood, the following examples are presented and illustrated in detail with accompanying figures. This specification provides various examples to illustrate the technical features of various embodiments of the present invention. The configuration of the various components in the examples is for illustrative purposes only and is not intended to limit the present invention. Furthermore, any repetition of figure numerals in the examples is for simplification and does not indicate a relationship between the different embodiments.

Figure 1 is a schematic diagram of the control chip of the present invention. As shown, the control chip 100 includes a driver circuit 110 and an internal circuit 120. The driver circuit 110 is coupled between a power supply terminal 130 and a power supply terminal 140. During normal operation, the driver circuit 110 supplies power to the internal circuit 120. During a protection period, the driver circuit 110 protects the internal circuit 120 from electrostatic discharge (ESD) current.

For example, when an electrostatic discharge event does not occur, the driver circuit 110 operates in a normal mode. In normal mode, the power supply terminal 130 receives a first operating voltage, and the power supply terminal 140 receives a second operating voltage. The second operating voltage may be a ground voltage. In this example, the first operating voltage is greater than the ground voltage. In normal mode, the driver circuit 110 may transmit the first operating voltage to the internal circuit 120, or provide a voltage slightly less than the first operating voltage to the internal circuit 120. When an electrostatic discharge event occurs at the power supply terminal 130 and the power supply terminal 140 receives a ground voltage, the driver circuit 110 operates in a protection mode. In the protection mode, the driver circuit 110 provides a discharge path for discharging an electrostatic discharge current from the power terminal 130 to the power terminal 140.

Driver circuit 110 includes a junction field effect transistor (JFET) 111, an impedance element 112, and an ESD protection circuit 113. In this embodiment, JFET 111 is an ultra-high voltage (UHV) device and an initial-on device. As shown, JFET 111 has a gate G_1, a drain D_1, and a source S_1. Gate G_1 is coupled to impedance element 112. Drain D_1 is coupled to power supply terminal 130. Source S_1 is coupled to internal circuit 120 and ESD protection circuit 113. In this embodiment, a parasitic capacitor Cgd exists between the drain D_1 and the gate G_1 of the junction field effect transistor 111.

When power terminal 130 receives a first operating voltage and power terminal 140 receives a second operating voltage, junction field-effect transistor 111 turns on. Consequently, the voltage at source S_1 gradually increases. After the voltage at source S_1 stabilizes (e.g., approaches the first operating voltage), internal circuit 120 operates based on the voltage at source S_1. In this example, the voltage at source S_1 serves as the operating voltage for internal circuit 120.

When an ESD event occurs at power terminal 130 and power terminal 140 receives a ground voltage, the voltage at gate G_1 rises due to capacitive coupling from parasitic capacitor Cgd. Because the voltage at gate G_1 is greater than the voltage at source S_1, junction field-effect transistor 111 remains in the on state. At this time, the voltage at source S_1 increases. When the voltage at source S_1 reaches a trigger voltage, ESD protection circuit 113 activates, providing a discharge path. This discharge path discharges an ESD current from power terminal 130 to power terminal 140.

Impedance element 112 is coupled between gate G_1 and power terminal 140 to prevent ESD current from flowing into gate G_1. Furthermore, when an ESD event occurs, impedance element 112 causes the voltage at gate G_1 of junction field effect transistor 111 to be greater than the voltage at source S_1. Therefore, impedance element 112 ensures that junction field effect transistor 111 remains conductive during an ESD event.

The present invention is not limited to the type of impedance element 112. In one possible embodiment, impedance element 112 is a resistor. In this example, the resistance of the resistor is greater than 5 MΩ. In some embodiments, the resistance of the resistor is greater than 10 MΩ. When an electrostatic discharge event occurs at power terminal 130 and power terminal 140 receives a ground voltage, the impedance element 112 coupled between gate G_1 and power terminal 140 prevents electrostatic discharge current from flowing into and damaging gate G_1. In some embodiments, by coupling impedance element 112 between gate G_1 of junction field effect transistor 111 and power terminal 140, junction field effect transistor 111 can withstand voltages exceeding 4.6 kV.

The ESD protection circuit 113 is coupled between the source S_1 of the junction field effect transistor 111 and the power terminal 140 to prevent ESD current from entering the internal circuit 120. For example, when an ESD event occurs at the power terminal 130 and the power terminal 140 receives a ground voltage, the voltage of the gate G_1 increases due to the capacitive coupling effect caused by the parasitic capacitance Cgd. Because the voltage of the gate G_1 of the junction field effect transistor 111 is greater than the voltage of the source S_1, the junction field effect transistor 111 turns on. As a result, the voltage of the source S_1 gradually increases. When the voltage at the source S_1 of the JFET 111 reaches a trigger voltage, the ESD protection circuit 113 is turned on to discharge an ESD current from the power terminal 130 to the power terminal 140.

When an ESD event does not occur, power terminal 130 receives a first operating voltage, and power terminal 140 receives a second operating voltage. At this time, JFET 111 is turned on. Consequently, the voltage at source S_1 of JFET 111 increases. However, since the voltage at source S_1 of JFET 111 is insufficient to trigger ESD protection circuit 113, ESD protection circuit 113 remains inactive. At this time, internal circuit 120 operates based on the voltage at source S_1.

FIG2A is a schematic diagram of an impedance element of the present invention. In this embodiment, the impedance element 112 is an N-type metal-oxide semiconductor field-effect transistor (NMOSFET) 210. The NMOSFET 210 has a gate G_2, a drain D_2, and a source S_2.

The gate G_2 of the N-type metal oxide semiconductor field effect transistor 210 is coupled to the source S_2 and the power terminal 140. The drain D_2 of the N-type metal oxide semiconductor field effect transistor 210 is coupled to the gate G_1 of the junction field effect transistor 111. In some embodiments, the gate G_2 is directly electrically connected to the source S_2 and the power terminal 140. In this example, the drain D_2 is directly electrically connected to the gate G_1 of the junction field effect transistor 111.

When the N-type metal oxide semiconductor field effect transistor 210 is turned on, it has an equivalent resistance. This equivalent resistance prevents electrostatic discharge current from the power terminal 130 from flowing into the gate G_1 of the junction field effect transistor 111. Therefore, the N-type metal oxide semiconductor field effect transistor 210 prevents the gate G_1 from being damaged by the electrostatic discharge current.

Figure 2B is another schematic diagram of an impedance element of the present invention. In this embodiment, the impedance element 112 is a P-type metal oxide semiconductor field effect transistor (PMOSFET) 220. The P-type metal oxide semiconductor field effect transistor 220 has a gate G_3, a drain D_3, and a source S_3.

The gate G_3 of the P-type metal oxide semiconductor field effect transistor 220 is electrically coupled to the source S_3 and the gate G_1 of the junction field effect transistor 111. The drain D_3 of the P-type metal oxide semiconductor field effect transistor 220 is electrically coupled to the power terminal 140. In some embodiments, the gate G_3 is directly electrically connected to the source S_3 and the gate G_1 of the junction field effect transistor 111. Alternatively, the drain D_3 may be directly electrically connected to the power terminal 140.

When the P-type metal oxide semiconductor field effect transistor 220 is turned on, it has an equivalent impedance. This equivalent impedance prevents the electrostatic discharge current from the power terminal 130 from directly flowing into the gate G_1 of the junction field effect transistor 111. Therefore, the P-type metal oxide semiconductor field effect transistor 220 protects the gate G_1 of the junction field effect transistor 111 from being damaged by the electrostatic discharge current.

Figure 2C is another schematic diagram of an impedance element of the present invention. In this embodiment, impedance element 112 is a bipolar junction transistor (BJT) 230. BJT 230 is an npn type transistor. BJT 230 has a base B_1, a collector C_1, and an emitter E_1.

The collector C_1 of the BJT 230 is coupled to the gate G_1 of the JFET 111. The base B_1 of the BJT 230 is coupled to the emitter E_1 and the power terminal 140. In some embodiments, the collector C_1 of the BJT 230 is directly electrically connected to the gate G_1 of the JFET 111. In this example, the base B_1 of the BJT 230 is directly electrically connected to the emitter E_1 and the power terminal 140.

When the BJT 230 is turned on, it has an equivalent impedance. This equivalent impedance prevents the ESD current from the power terminal 130 from directly flowing into the gate G_1 of the JFET 111. Therefore, the BJT 230 protects the gate G_1 of the JFET 111 from being damaged by the ESD current.

Figure 2D is another schematic diagram of the impedance element of the present invention. In this embodiment, the impedance element 112 is a bipolar junction transistor 240. The bipolar junction transistor 240 is a pnp type transistor. The bipolar junction transistor 240 has a base B_2, a collector C_2, and an emitter E_2.

The base B_2 of the BJT 240 is electrically coupled to the emitter E_2 and the gate G_1 of the JFET 111. The collector C_2 of the BJT 240 is electrically coupled to the power terminal 140. In some embodiments, the base B_2 of the BJT 230 is directly electrically connected to the emitter E_2 and the gate G_1 of the JFET 111. In this example, the collector C_2 of the BJT 240 is directly electrically connected to the power terminal 140.

When the BJT 240 is turned on, it has an equivalent impedance. This equivalent impedance prevents the ESD current from the power terminal 130 from flowing directly into the gate G_1 of the JFET 111. Therefore, the BJT 240 protects the gate G_1 of the JFET 111 from being damaged by the ESD current.

It should be understood that when an element or layer is referred to as being "coupled" to another element or layer, it can be directly coupled or connected to the other element or layer, or it can have other elements or layers intervening therebetween. Conversely, when an element or layer is "connected" to another element or layer, there are no intervening elements or layers.

Unless otherwise defined, all terms used herein (including technical and scientific terms) are generally understood by those skilled in the art to which this invention belongs. Furthermore, unless otherwise indicated, dictionary definitions of terms should be interpreted as consistent with their meanings in articles in the relevant technical field and should not be construed as ideal or overly formal. Although terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another.

Although the present invention has been disclosed above with reference to preferred embodiments, these are not intended to limit the present invention. Any person skilled in the art may make modifications and alterations without departing from the spirit and scope of the present invention. For example, the systems, devices, or methods described in the embodiments of the present invention may be implemented as hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Control chip

110: Drive circuit

120: Internal circuit

130, 140: Power supply

111: Junction Field Effect Transistor

112: Impedance Element

113: Electrostatic discharge protection circuit

G_1: Gate

D_1: Drain

S_1: source

Cgd: parasitic capacitance

Claims (7)

A driver circuit for supplying power to an internal circuit includes: a junction field effect transistor having a first gate, a first drain, and a first source, the first source being coupled to the internal circuit; a metal oxide semiconductor field effect transistor coupled between the first gate and a first power terminal, and having a second gate, a second source, and a second drain; and an electrostatic discharge protection circuit coupled between the first source and the first power terminal. , wherein: when the voltage of the first source does not reach a trigger voltage, the electrostatic discharge protection circuit is not conductive and the internal circuit operates according to the voltage of the first source. When the voltage of the first source reaches the trigger voltage, the electrostatic discharge protection circuit is conductive to release an electrostatic discharge current to the first power supply terminal. When a continuous electrostatic discharge event occurs, the voltage of the first gate is greater than the voltage of the first source, and the second gate is coupled to the second source. The driving circuit of claim 1, wherein the first drain is coupled to a second power terminal, and when the voltage of the second power terminal increases, the voltage of the first source increases. The driving circuit of claim 1, wherein the second drain is coupled to the first gate, and the second source is coupled to the first power terminal. The driving circuit of claim 1, wherein the second source is coupled to the first gate, and the second drain is coupled to the first power terminal. A driving circuit for supplying power to an internal circuit includes: a junction field effect transistor having a first gate, a first drain, and a first source, the first source being coupled to the internal circuit; a metal oxide semiconductor field effect transistor coupled between the first gate and a first power supply terminal; and an electrostatic discharge protection circuit coupled between the first source and the first power supply terminal, wherein: when the voltage of the first source does not reach a trigger voltage, the electrostatic discharge protection circuit The circuit is non-conductive and the internal circuit operates according to the voltage of the first source. When the voltage of the first source reaches the trigger voltage, the electrostatic discharge protection circuit is conductive to release an electrostatic discharge current to the first power supply terminal. When a continuous electrostatic discharge event occurs, the voltage of the first gate is greater than the voltage of the first source. The impedance element is a bipolar junction transistor having a base, a collector, and an emitter, with the base coupled to the emitter. The driving circuit of claim 5, wherein the collector is coupled to the first gate, and the emitter is coupled to the first power terminal. The driving circuit of claim 5, wherein the emitter is coupled to the first gate, and the collector is coupled to the first power terminal.