TWI891354B - Precharging method and programming method for 3d memory device - Google Patents

Abstract

A pre-charging and programming method for 3D memory device having top-deck WL group, middle dummy WL group, bottom-deck WL group and bottom dummy WL group is provided. The method includes: selected a word line to be programmed, determining the word line is in the top- or bottom-deck WL group; when the word line is in the top-deck WL group, applying a pre-charge on voltage to the middle dummy WL group to turn on the channel to pre-charge the channel; and when the word line is in the bottom-deck WL group, applying a pre-charge off voltage to the middle dummy WL group to turn off the channel to not pre-charge the channel. This method is suitable for 3D NAND flash memory having high capacity and high performance.

Description

Pre-charging method and programming method for 3D memory device

The present invention relates to an operating method of a memory device, and more particularly to a pre-charging method of a 3D memory device.

Before programming the memory, that is, before applying the programming pulse, a precharge is typically performed. Precharge is crucial for mitigating programming interference. Insufficient precharge capability exacerbates programming interference and raises the upper bound of the memory cell's erase state, resulting in a loss of read window.

Today, to achieve higher capacity, 3D NAND memory devices are increasing the number of stacked layers and adopting a multi-deck structure. As shown in the simplified structure in Figure 1, from top to bottom, the upper word line group (WL) 2, the middle dummy word line group (MDWL) 6, the lower word line group (WL) 4, and the bottom dummy word line group (BDWL) 8 are included. A precharge voltage is typically applied from the common source line (CSL) on the source side to further remove electrons from the channel 9. During the precharge operation, the bottom dummy word line (BDWL) 8 and the middle dummy word line (MDWL) 6 are turned on, allowing the precharge voltage to be fully applied to the channel 9.

Specifically, during the precharge operation, a voltage must be applied to the selected middle dummy word line group (MDWL) 6 in the joint layer to turn it on. This allows the precharge voltage to be applied to the channel 9 from the common source line (CSL). Therefore, the critical voltage of the selected middle dummy word line group (MDWL) 6 in the joint layer will impact the precharge capability.

In conventional methods, the middle dummy word line group (MDWL) 6 in the connection layer is always continuously turned on and off during the entire word line programming process, even if the upper word line 2 has been programmed and the lower word line (WL) 4 is being programmed. At this time, due to the down-coupling (A) effect, the excess precharge generated by turning the middle dummy word line group (MDWL) 6 on and off interferes with the boundary word line 2a adjacent to the middle dummy word line group (MDWL) 6. This increases the channel potential Pch, causing electrons to migrate to the memory cell on the adjacent boundary word line 2a. This raises the upper limit of the erase (ER) state of the memory cell.

Therefore, it is important to maintain the precharge capability of the upper word line and avoid interfering with the word line adjacent to the middle dummy word line.

As described above, according to one embodiment of the present invention, a precharging method for a 3D memory device is provided. The 3D memory device includes at least an upper word line group, a middle dummy word line group, a lower word line group, and a bottom dummy word line group arranged in sequence. The pre-charging method includes: selecting a word line from the upper word line group and the lower word line group for programming; determining whether the selected word line is located in the upper word line group or the lower word line group; when the word line is located in the upper word line group, applying a pre-charge on voltage to the middle dummy word line group so that the pre-charge voltage reaches the channel corresponding to the middle dummy word line group; and when the word line is located in the lower word line group, applying a pre-charge off voltage to the middle dummy word line group so that the pre-charge voltage does not reach the channel corresponding to the middle dummy word line group.

According to another embodiment of the present invention, a precharging method for a 3D memory device is provided. The 3D memory device includes at least: multiple word line groups, multiple middle dummy word line groups, and a bottom dummy word line group. The bottom dummy word line group is located below the lowest word line group of the multiple word line groups. Each of the multiple middle dummy word line groups is disposed between every two word line groups of the multiple word line groups. The pre-charge method includes: selecting a word line from a plurality of word line groups for programming; determining that the selected word line is a word line group in the plurality of word line groups; applying a pre-charge on voltage to each intermediate dummy word line group below the word line group so that the pre-charge voltage reaches the channels corresponding to the intermediate dummy word line groups below the word line group; and applying a pre-charge off voltage to each intermediate dummy word line group above the word line group so that the pre-charge voltage does not reach the channels corresponding to the intermediate dummy word line groups above the word line group.

According to another embodiment of the present invention, a programming method for a 3D memory device is provided. The 3D memory device includes at least an upper word line group, a middle dummy word line group, a lower word line group, and a bottom dummy word line group arranged in sequence. The programming method includes: selecting a word line from the upper word line group and the lower word line group for programming; determining whether the selected word line is located in the upper word line group or the lower word line group; when the word line is located in the upper word line group, applying a precharge on voltage to the middle dummy word line so that the precharge voltage reaches a channel corresponding to the middle dummy word line; when the word line is located in the lower word line group, applying a precharge off voltage to the middle dummy word line so that the precharge voltage does not reach the channel corresponding to the middle dummy word line; and after terminating the application of the precharge voltage, applying a programming voltage to the selected word line.

According to an embodiment of the present invention, in the above-mentioned pre-charge method or programming method, the 3D memory device further includes a common source line, and the pre-charge voltage is applied from the common source line.

According to an embodiment of the present invention, in the above-mentioned pre-charging method or programming method, the pre-charging on-voltage is much smaller than the voltage for programming the selected word line, and the pre-charging off-voltage is 0V.

According to an embodiment of the present invention, in the above-mentioned pre-charging method or programming method, the pre-charging further includes applying the pre-charging conduction voltage to the bottom dummy word line group.

According to an embodiment of the present invention, in the above-mentioned pre-charging method or programming method, the memory device comprises an array of multiple memory cells, wherein the multiple memory cells are single-level cells, dual-level cells, triple-level cells, or quad-level cells. According to an embodiment of the present invention, in the above-mentioned pre-charging method or programming method, the memory device is a 3D NAND memory device.

According to embodiments of the present invention, in a 3D memory device with a multi-segment word line group structure, during the precharge phase, the middle dummy word line layer is appropriately controlled to be turned on or off based on the position of the word line selected for programming, thereby controlling the precharge operation. This maintains the precharge capability of the upper segment word line and avoids interference with adjacent word lines.

The following description uses 3D NAND flash memory as an example, but the present invention is not limited to this and is applicable to any 3D memory structure. Furthermore, the present invention is also applicable to 2D memory.

Figure 2 illustrates a memory architecture used as an example of an embodiment of the present invention, illustrating a portion of the structure of a 3D NAND flash memory. Furthermore, while the present embodiment illustrates a multi-segment structure, Figure 2 illustrates only one segment. Therefore, a two-segment 3D NAND flash memory structure consists of two structures, as shown in Figure 1. Specifically, an upper segment word line structure is further configured above dummy word lines DWLT0-DWLT2 and between select line SSL0, thereby stacking a structure equivalent to word lines WL0-WL95 to form a two-segment 3D NAND flash memory. The layers of dummy word lines DWLT0-DWLT2 between the multiple word lines in the upper and lower segments can also be referred to as connection layers. Furthermore, if there are three or more segments, they are stacked continuously in this manner.

The following briefly describes the structure of a single segment. As shown in Figure 2, a schematic structure of a 3D NAND flash memory device has multiple word lines WL0 to WL95 (96 for illustration) formed in the vertical direction z. A vertical channel (VC) is also formed along the vertical direction z. Each word line extends in the xy plane. Furthermore, bottom dummy word lines DWLB1 and DWLB0 are arranged below word line WL0, and top dummy word lines DWLT1 and DWLT0 are arranged above word line WL95. While two bottom dummy word lines and two top dummy word lines are illustrated here, their number is not particularly limited and can be adjusted appropriately based on needs.

In addition, the 3D NAND flash memory device may also include a common source line (CSL) that connects the source lines together. The 3D NAND flash memory device may also include select lines SSL0, SSL1, SSL2, etc., which may be arranged above the top virtual word line DWLT2. The 3D NAND flash memory device may also form a global source line (GSL) below the bottom virtual word line and a global bit line (GBL) above the top virtual word line to connect the bit lines. The structure of the 3D NAND flash memory device shown in FIG. 2 is only for facilitating understanding of the relationship between a segment of word lines (data word lines) WL0-WL95 and virtual word lines, and is not intended to limit the scope of implementation of the present invention.

FIG3 shows a schematic diagram of the structure of each word line, which is an enlarged view of the word line portion of FIG2. As shown in FIG3, the 3D NAND flash memory device includes a plurality of word lines WL0~WL95, which are penetrated by a vertical channel VC. The vertical channel VC has a dielectric layer core 10, a channel layer 20 surrounding the dielectric layer core 10, and a charge trapping layer 30 between each word line WL0~WL95 and the channel layer 20. The channel layer 20 is formed of, for example, polysilicon, and the charge trapping layer is composed of, for example, an oxide-nitride-oxide (ONO) layer. The structure illustrated here is only an example of a 3D NAND flash memory device to which the programming method of the present invention can be applied, and the method of the present invention is not limited to any memory structure.

FIG4 is a schematic diagram illustrating an application state of an embodiment of the present invention. As shown in FIG4 , the 3D memory device 100 includes at least an upper word line group 110, a middle dummy word line group 114, a lower word line group 112, and a bottom dummy word line group 116, which are arranged in sequence. Each word line can include multiple word lines. In this example, the drain side is above the 3D memory device 100, and the source side is below the 3D memory device 100. In addition, the 3D memory device 100 only illustrates the required components, that is, a schematic positional relationship diagram of the word lines and the channel 120. Other components of the 3D memory device 100 that are not shown can refer to existing existing structures that will be developed in the future, and their description is omitted here.

In this example, the 3D memory device 100 is illustrated as a two-stage stacked 3D NAND flash memory device, formed by stacking two structures illustrated in Figures 2 and 3. Furthermore, the memory programming example involves programming each word line WL one by one, starting from the upper word line group 110 and moving downwards toward the lower word line group 112. Furthermore, during programming, an incremental step programming pulse (ISPP) method can be employed to program selected word lines.

Figures 5A and 5B are waveform diagrams illustrating a pre-charging method according to an embodiment of the present invention. To reduce the potential interference of the pre-charging operation on boundary word lines (e.g., 110A) adjacent to the middle dummy word line group 114, the on/off switching of the middle dummy word line group 114 is controlled during the pre-charging period.

As shown in Figures 4 and 5A , when programming each word line WL, the process is performed sequentially, from upper word line group 110 to lower word line group 112. Figure 5A illustrates only representative word lines and does not represent all word lines WL. Before programming, a precharge voltage VPRE is applied from the common source line CSL and input to the channel (vertical channel) 120.

First, a word line to be programmed is selected from the upper word line group 110 and the lower word line group 112. Next, it is determined whether the word line is located in the upper word line group 110 or the lower word line group 112. For example, if the selected word line 110A is located in the upper word line group 110, a precharge on-voltage Vpre_on is applied to the middle dummy word line group (MDWL) 114 during the precharge phase to turn on the corresponding channel 120A. Furthermore, for precharging purposes, the bottom dummy word line group (BDWL) 116 is also applied with the precharge on-voltage Vpre_on, turning it on. Furthermore, because the memory cells on the lower word line group 112 have not yet been programmed and are in the erased (ER) state, their corresponding channels are also on. Therefore, by turning on the middle dummy word line group (MDWL) 114, the precharge voltage VPRE applied from the common source line CSL can reach the channel 120A corresponding to the middle dummy word line group (MDWL) 114. Therefore, for example, before programming the selected word line 110A in the upper word line group 110, the dummy word line group (MDWL) 114 is turned on to perform precharge. In this way, the channel from the bottom dummy word line to the corresponding dummy word line group (MDWL) 114 can be fully boosted by the precharge voltage VPRE, further removing any remaining electrons in the channel to reduce programming interference. Furthermore, this also maintains the precharge capability of the upper word line group 110.

Furthermore, the pre-charge on-state voltage Vpre_on only needs to be high enough to turn on the memory cell coupled to the middle dummy word line (MDWL) 114, thereby opening its channel 120A. Furthermore, the pre-charge on-state voltage Vpre_on can be much lower than the programming voltage VPGM to avoid malfunctioning the middle dummy word line (MDWL) 114.

Furthermore, as shown in FIG5A , after the precharge phase ends, the programming phase begins. At this stage, a programming voltage, VPGM, is applied to the selected word line 110A for programming, and a pass voltage, VPASSP, is applied to the unselected word lines (including the programmed word lines in the upper word line group 110 and the unprogrammed word lines in the lower word line group 112). Furthermore, a pass voltage, VPASSP, is also applied to the middle dummy word line group (MDWL) 114 and even the bottom dummy word line group (BDWL) 116. The pass voltage VPASSP keeps the word lines in an unselected state.

Furthermore, as shown in FIG5B , when the selected word line 112A is in the lower word line group 112, a precharge off voltage Vpre_off is applied to the middle dummy word line group (MDWL) 114 during the precharge phase, turning off its channel 120A. Furthermore, to perform the precharge, the bottom dummy word line group (BDWL) 116 is also applied with a precharge on voltage Vpre_on, turning it on. Furthermore, in the lower word line group 112, the memory cells connected to the word lines below the selected word line 112A have not yet been programmed and are in the erase (ER) state, so their corresponding channels are also on. Therefore, the precharge voltage VPRE applied from the common source line CSL only reaches the channels corresponding to the word lines below the selected word line 112A.

Furthermore, because the precharge off voltage Vpre_off is applied to the middle dummy word line group (MDWL) 114, the corresponding channel is not turned on, and the precharge voltage VPRE cannot reach it. Consequently, the upper segment word line 110A adjacent to the middle dummy word line group (MDWL) 114 is prevented from interfering with the programmed state of the upper segment word line 110A due to downward coupling. This prevents interference with the word line 110A adjacent to the middle dummy word line group 114.

Similarly, as shown in FIG5B , after the precharge phase, the program phase begins. At this stage, a program voltage VPGM is applied to the selected lower word line 112A for programming, and a pass voltage VPASSP is applied to the unselected word lines (including the programmed word lines in the upper word line group 110 and the unprogrammed word lines in the lower word line group 112). Furthermore, a pass voltage VPASSP is also applied to the middle dummy word line group (MDWL) 114 and even the bottom dummy word line group (BDWL) 116. The pass voltage VPASSP keeps the word lines in an unselected state.

Figure 6 is a graph comparing experimental results using a known pre-charging method and the pre-charging method according to an embodiment of the present invention. In Figure 6, the vertical axis represents the bit count, and the horizontal axis represents the critical voltage Vt. In addition, Figure 6 shows the erased state (ER) and programmed state (A-G) of each word line on the memory cell. The upper portion of Figure 6 shows the experimental results using the known pre-charging method, while the lower portion of Figure 6 shows the experimental results using the pre-charging method according to an embodiment of the present invention.

As can be seen from the top of Figure 6, in a two-stage stacked structure, when programming the lower word line, the middle dummy word line remains conductive during the precharge phase. Therefore, the precharge voltage can interfere with the programmed upper word line adjacent to the middle dummy word line. As a result, the erased state ER and the programmed state A become too close, potentially causing the read boundary between them to overlap, leading to erroneous reads.

As can be seen in the lower portion of FIG6 , using the pre-charging method of this embodiment of the present invention, during the pre-charging phase, the pre-charge on voltage Vpre_on is applied to the middle dummy word line 114 to turn on its channel and pre-charge the channel only when programming the upper word line 110. However, when programming the lower word line 110, the pre-charge off voltage Vpre_off is applied to the middle dummy word line 114 to turn off its channel, without pre-charging the channel. Therefore, in this case, unnecessary pre-charging operations will not interfere with the programmed upper word line adjacent to the middle dummy word line.

FIG7 is a schematic diagram illustrating a variation of the precharging method of the present invention. In this example, a 3D memory device 200 includes multiple word line groups 210-1, 210-2, ..., 210-n (n-group). Furthermore, between each pair of word line groups 210-1, 210-2, ..., 210-n, multiple intermediate dummy word line groups 220-1, 220-2, ..., 220-m (m-group) are provided. For example, intermediate dummy word line group 220-2 is provided between a word line group 210-2 and a word line group 210-3. Furthermore, a bottom dummy word line group 230 is disposed below the lowest word line group 210-1 of the plurality of word line groups 210-1, 210-2, ..., 210-n. Furthermore, in one embodiment, a top dummy word line group 240 is disposed above the highest word line group 210-n of the plurality of word line groups 210-1, 210-2, ..., 210-n. Similarly, other components of the 3D memory device 200 not shown may refer to existing structures for future development, and their description is omitted here.

In this example, the vertical stacking structure is described in a horizontal manner. That is, word line group 210-n is located at the top segment of the entire stacking structure, while word line group 210-1 is located at the bottom segment of the entire stacking structure. Each of the multiple word line groups 210-1, 210-2, ..., 210-n can further include multiple word lines. Each of the middle dummy word line groups 220-1, 220-2, ..., 220-m can further include multiple middle dummy word lines. Bottom dummy word line group 230 can include multiple bottom dummy word lines. Top dummy word line group 240 can include multiple top dummy word lines.

In addition, in this embodiment, the voltage waveforms used in the pre-charge stage and the programming stage can refer to the examples of Figures 5A and 5B. Similar to the above embodiment, before programming, a pre-charge voltage VPRE is applied from the common source line CSL to pre-charge the channel 220. First, a word line is selected from the multi-segment word line group 210-1, 210-2, ..., 210-n for programming. For example, word lines are selected sequentially (from top to bottom) from the multi-segment word line group 210-n, 210-(n-1), ..., 210-2, 210-1, and word line 210-3A is selected. Next, it is determined that the selected word line 210-3a is a word line group among the multiple word line groups 210-n, 210-(n-1), ..., 210-2, and 210-1. In this example, it is word line group 210-3.

Next, a precharge on-voltage Vpre_on is applied to each of the intermediate dummy word line groups 220-2 and 220-1 and the bottom dummy word line 230 below the segment of word line group 210-3, ensuring that the precharge voltage VPRE reaches the corresponding channels of each of the intermediate dummy word lines 220-2 and 220-1 below the segment of word line group 210-3. This maintains the precharge capability of word line group 210-3. Furthermore, a precharge off-voltage Vpre_off is applied to each of the intermediate dummy word line groups 220-3, ..., 220-m above the segment of word line group 210-3 to turn off their channels. As a result, the precharge voltage VPRE does not reach the channels corresponding to the middle dummy word lines 220-3, ..., 220-m on the word line group 210-3, thereby preventing interference with the word lines adjacent to the middle dummy word line groups 220-3, ..., 220-m.

The above embodiments use 3D NAND flash memory devices as an example for illustration, but the present invention is not limited to NAND flash memory devices and is also applicable to other types of memory devices, such as 3D NOR flash memory devices.

Furthermore, in a memory device to which the pre-charging method of the present invention is applicable, the memory cells constituting the memory device may also have an architecture such as a single-level cell (SLC) storing 1 bit, a multiple-level cell (MLC) storing 2 bits, a triple-level cell (TLC) storing 3 bits, or a quad-level cell (QLC) storing 4 bits.

In summary, according to the embodiments of the present invention, in a 3D memory device with a multi-segment word line group structure, during the precharge phase, the middle dummy word line layer is appropriately controlled to be turned on or off based on the position of the word line selected for programming, thereby controlling the precharge operation. This maintains the precharge capability of the upper segment word line and avoids interference with adjacent word lines.

2. 110: Upper word line group 2a: Boundary word line 4. 112: Lower word line group 6. 114: Middle dummy word line group 8. 116: Bottom dummy word line group 9. 120, 120A, 220: Channel 10: Dielectric core 20: Channel layer 30: Charge trapping layer 100, 200: 3D memory device 110A, 112A, 210-3A: Selected word line 210-1, 210-2, 210-3, 210-4, ..., 210-n: Word line groups 220-1, 220-2, 220-3, ..., 220-m: Middle dummy word line group 230: Bottom dummy word line 240: Top dummy word line WL0-WL95: Word lines DWLB0-DWLB2: Bottom dummy word lines DWLT0-DWLT2: Top dummy word lines CSL: Common source line SSL, SSL0, SSL1, SSL2: Select lines GSL: Global source line GBL: Global bit line VC: Vertical channel A: Bottom coupling effect VPASSP: Pass voltage VPGM: Programming voltage Vpre_on: Precharge on-state voltage Vpre_off: Pre-charge shutdown voltage VPRE: Pre-charge voltage

Figure 1 is a diagram illustrating the effect of precharging on programming disturbance. Figure 2 is a schematic diagram illustrating the memory structure associated with each word line. Figure 3 is a schematic diagram illustrating the structure associated with each word line. Figure 4 is a schematic diagram illustrating an application of an embodiment of the present invention. Figures 5A and 5B are waveform diagrams illustrating a precharging method according to an embodiment of the present invention. Figure 6 is a diagram comparing experimental results of a conventional precharging method and the precharging method according to an embodiment of the present invention. Figure 7 is a schematic diagram illustrating a variation of the precharging method of the present invention.

110: Upper character line group

112: Lower character line group

VPASSP: Pass voltage

VPGM: Programmable Voltage

Vpre_off: Pre-charge shutdown voltage

VPRE: Precharge voltage

Claims (10)

A pre-charging method for a 3D memory device, wherein the 3D memory device includes at least an upper word line group, a middle dummy word line group, a lower word line group, and a bottom dummy word line group arranged in sequence, the pre-charging method comprising: selecting a word line from the upper word line group and the lower word line group for programming; determining whether the selected word line is located in the upper word line group or the lower word line group; word line group; when the word line is located in the upper word line group, a pre-charge on voltage is applied to the middle dummy word line group so that the pre-charge voltage reaches the channel corresponding to the middle dummy word line group; and when the word line is located in the lower word line group, a pre-charge off voltage is applied to the middle dummy word line group so that the pre-charge voltage does not reach the channel corresponding to the middle dummy word line group. The precharge method for a 3D memory device according to claim 1, wherein the 3D memory device further includes a common source line, and the precharge voltage is applied from the common source line. The pre-charging method for a 3D memory device as claimed in claim 1, wherein the pre-charging on voltage is much smaller than a voltage for programming the selected word line, and the pre-charging off voltage is 0V. The precharging method of a 3D memory device as claimed in claim 1 further comprises applying the precharge on voltage to the bottom dummy word line group during the precharging process. The pre-charging method for a 3D memory device as described in claim 1, wherein the 3D memory device has an array consisting of a plurality of memory cells, and the plurality of memory cells are single-level cells, dual-level cells, triple-level cells, or quadruple-level cells. The precharging method for a memory device as described in claim 1, wherein the 3D memory device is a 3D NAND memory device. A programming method for a 3D memory device, wherein the 3D memory device includes at least an upper word line group, a middle dummy word line group, a lower word line group, and a bottom dummy word line group arranged in sequence, the programming method comprising: selecting a word line from the upper word line group and the lower word line group for programming; determining whether the selected word line is located in the upper word line group or the lower word line group; and when the word line is located in the upper word line group, programming the word line. The word line group is a segment word line group, a pre-charge on voltage is applied to the middle dummy word line group so that the pre-charge voltage reaches the channel corresponding to the middle dummy word line group; when the word line is located in the lower segment word line group, a pre-charge off voltage is applied to the middle dummy word line group so that the pre-charge voltage does not reach the channel corresponding to the middle dummy word line group; and after the application of the pre-charge voltage is terminated, a programming voltage is applied to the selected word line. The programming method of a 3D memory device as claimed in claim 7, wherein the 3D memory device further includes a common source line, and the precharge voltage is applied from the common source line. The programming method of a 3D memory device as described in claim 7, wherein the precharge on voltage is much smaller than a voltage for programming the selected word line, and the precharge off voltage is 0V. The programming method of a 3D memory device as claimed in claim 7, further comprising applying the precharge on voltage to the bottom dummy word line group during precharging.