TWI890979B - Temperature sensor system in a chip and chip - Google Patents

Abstract

A temperature sensor system in a chip and chip. The temperature sensor system in the chip includes a first temperature sensing unit and a control unit. The first temperature sensing unit senses the temperature by using the back metal structure formed in the back end process of the chip to output a temperature sensing electrical signal. The control unit is coupled with the first temperature sensing unit and processes the temperature sensing electric signal output by the first temperature sensing unit to output a measurement result. The temperature sensor system can improve the temperature measurement accuracy.

Description

Temperature sensor system on chip and chip

Embodiments of the present disclosure relate to a temperature sensor system in a chip and a chip.

Chip temperature is typically acquired through an on-chip temperature sensor system. Currently, the most commonly used temperature sensor system in the industry consists of a temperature sensing unit composed of a bipolar junction transistor (BJT).

At least one embodiment of the present disclosure provides a temperature sensor system in a chip. The temperature sensor system includes: a first temperature sensing unit that senses temperature using a back-end metal structure formed in a back-end process of the chip to output a temperature sensing electrical signal; and a control unit coupled to the first temperature sensing unit and processing the temperature sensing electrical signal output by the first temperature sensing unit to output a measurement result.

For example, in a temperature sensor system provided in one embodiment of the present disclosure, a chip includes at least one die, and the first temperature sensing unit and the control unit are integrated into the same die of the at least one die; the first temperature sensing unit is integrated into one of the at least one die, and the control unit is independent of the at least one die.

For example, in a temperature sensor system provided in an embodiment of the present disclosure, the chip further includes a packaging portion, the first temperature sensing unit is integrated into one of the at least one die, and the control unit is independent of the at least one die. This includes: the first temperature sensing unit is integrated into one of the at least one die, and the control unit is disposed in the packaging portion outside the die; or, in the case where the chip includes multiple dies stacked via a bonding structure, the first temperature sensing unit is integrated into one of the at least one die, and the first temperature sensing unit is disposed in the bonding structure.

For example, in a temperature sensor system provided in an embodiment of the present disclosure, the temperature sensor system includes a plurality of temperature sensing units, including the first temperature sensing unit. The temperature sensor system further includes a multiplexer coupled to the control unit and the plurality of temperature sensing units and configured to select one of the plurality of temperature sensing units.

For example, in the temperature sensor system provided in one embodiment of the present disclosure, the chip includes multiple dies, and the multiplexer and the first temperature sensing unit are located in the same die or in different dies.

For example, in a temperature sensor system provided in an embodiment of the present disclosure, the at least one die includes a first die, the multiplexer is located in the first die, and when the first temperature sensing unit is integrated into one of the at least one die and the control unit is independent of the at least one die, the multiplexer is coupled to the control unit via the package circuit structure of the first die.

For example, in a temperature sensor system provided in an embodiment of the present disclosure, the first die includes a signal output port, the multiplexer is coupled to the signal output port, and the signal output port is coupled to the package circuit structure, so that the multiplexer is coupled to the control unit.

For example, in a temperature sensor system provided in an embodiment of the present disclosure, at least one die further includes a second die. The first die and the second die are stacked via a bonding structure and packaged by the package circuit structure. The second die includes a signal output port, while the first die does not. The multiplexer is coupled to the signal output port via the bonding structure, and is coupled to the control unit via the signal output port and the package circuit structure.

For example, in a temperature sensor system provided in an embodiment of the present disclosure, at least one die includes a first die and a second die. Where the first temperature sensing unit and the control unit are integrated into different dies of the at least one die, the first temperature sensing unit is located in the first die, the control unit is located in the second die, and the multiplexer in the first die is coupled to the control unit via an interconnect structure, wherein the interconnect structure is used to couple the first die and the second die; or the multiplexer in the first die is coupled to the control unit via a bonding structure, wherein the bonding structure is used to stack the first die and the second die.

For example, in a temperature sensor system provided in an embodiment of the present disclosure, a chip includes a first die and a second die. In the case where the first temperature sensing unit is disposed in the bonding structure, the control unit is disposed in the first die or the second die, and the multiplexer and the control unit are disposed in the same die. Alternatively, the control unit is independent of the first die and the second die, the second die includes a signal output port, the multiplexer is disposed in the second die, the signal output port is coupled to the package circuit structure, the multiplexer is coupled to the signal output port, and the signal output port is coupled to the package circuit structure, so that the multiplexer is coupled to the control unit via the package circuit structure.

For example, in a temperature sensor system provided in an embodiment of the present disclosure, the back-end metal structure includes at least one of the following: a back-end metal wiring, a metal structure consisting of a back-end metal via array and the back-end metal wiring, or a metal structure consisting of the back-end metal wiring and an array of vias passing through a silicon substrate.

For example, in the temperature sensor system provided in one embodiment of the present disclosure, the control unit and the first sensing unit form a 4-wire Kelvin circuit to process the temperature sensing electrical signal and output a measurement result.

At least one embodiment of the present disclosure provides a chip, which includes the temperature sensor system provided by any embodiment of the present disclosure.

To make the above features and advantages of the present disclosure more clearly understood, the following examples are given with reference to the accompanying drawings for detailed description.

100, 210, 220, 230, 300: Chips

101, 102, 103, 104, 105, 120, 130: Metal windings

110: Temperature sensor system

111, 2111, 2211, 2311, 301, 302, 303, 402, 412, 502, 512: Temperature sensing units

112: Control unit

140: Columnar Metal

150, 160, 170, 180: Passing through the silicon wafer channel

211, 221, 231, 232, 601, 602: Grains

2112, 2221, 2341, 305, 403, 413, 42, 43, 503, 513, 52, 53: ADC module

222, 233: Packaging

234, 604: Keying structure

304, 401, 411, 501, 511: Multiplexers

603: Silicon interposer, substrate, or base

611: Transistor layer

612: Back-end metal structure

6121: Back-end metal winding

6122: Metal structure formed by back-end metal via array and back-end metal routing

6123: A metal structure consisting of back-end metal routing and an array of vias passing through the silicon substrate.

613: Silicon substrate

VDD_MH, VDD_FH, VSS_ML, VSS_FL: Connectors

To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly introduced below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

FIG1A shows a schematic diagram of a temperature sensor system in a chip provided by at least one embodiment of the present disclosure.

Figure 1B shows a schematic diagram of a back-end metal structure provided by at least one embodiment of the present disclosure.

Figure 1C shows a schematic diagram of another back-end metal structure provided by at least one embodiment of the present disclosure.

Figure 1D shows a schematic diagram of another back-end metal structure provided by at least one embodiment of the present disclosure.

Figure 2A shows a schematic diagram of the relationship between the resistance and temperature of the back-end metal structure.

Figure 2B shows a schematic block diagram of a chip provided by at least one embodiment of the present disclosure.

Figure 2C shows a schematic block diagram of another chip provided by at least one embodiment of the present disclosure.

Figure 2D shows a schematic block diagram of another chip provided by at least one embodiment of the present disclosure.

Figure 3 shows a schematic diagram of the coupling relationship between the multiplexer and the temperature sensing unit provided in at least one embodiment of the present disclosure.

Figure 4 shows a schematic diagram of a temperature sensor system provided by at least one embodiment of the present disclosure.

FIG5 shows a schematic diagram of a temperature sensor system provided by at least one embodiment of the present disclosure.

Figure 6 shows a schematic structural diagram of a chip provided in at least one embodiment of the present disclosure.

To further clarify the purpose, technical solutions, and advantages of the disclosed embodiments, the following clearly and completely describes the technical solutions of the disclosed embodiments, in conjunction with the accompanying figures. Obviously, the described embodiments are only a portion of the disclosed embodiments, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the described embodiments without requiring any creative effort are also within the scope of protection of this disclosure.

Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. "First", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "one", "an" or "the" and other similar terms do not indicate quantity limitations, but rather indicate the presence of at least one. "Include" or "comprising" and other similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Coupled" or "connected" and other similar terms are not limited to physical or mechanical coupling, but may include electrical coupling, whether direct or indirect. "Up," "down," "left," "right," etc. are only used to express relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

A temperature sensor system uses a temperature sensing element to measure the temperature at its location. Therefore, the temperature measurement accuracy of a high-precision temperature sensor system is closely related to the measurement accuracy of the temperature sensing element. Temperature sensing elements composed of BJTs are affected by the chip manufacturing process. Their accuracy decreases, especially at advanced process nodes (e.g., FinFet 14nm and beyond), limiting the overall accuracy of the on-chip temperature sensor system.

At least one embodiment of the present disclosure provides a temperature sensor system within a chip and a chip. The temperature sensor system includes a first temperature sensing unit and a control unit. The first temperature sensing unit senses temperature using a back-end metal structure formed during the back-end process of the chip to output a temperature sensing electrical signal. The control unit is coupled to the first temperature sensing unit and processes the temperature sensing electrical signal output by the first temperature sensing unit to output a measurement result. By utilizing a back-end metal structure formed during the back-end process as the temperature sensing unit, the temperature sensor system avoids fluctuations in the BJT manufacturing process during the front-end process, thereby improving the temperature measurement accuracy of the temperature sensor system and enabling temperature measurement of back-end structures within the chip.

FIG1A shows a schematic diagram of a temperature sensor system in a chip provided by at least one embodiment of the present disclosure.

As shown in FIG1A , a chip 100 includes a temperature sensor system 110. The temperature sensor system 110 includes a temperature sensing unit 111 and a control unit 112. The temperature sensing unit 111 is an example of a first temperature sensing unit.

The temperature sensing unit 111 uses a back-end metal structure formed during the back-end process of the chip to sense temperature and output a temperature sensing electrical signal.

For example, the chip manufacturing process can be divided into front-end and back-end processes. For example, the process of implementing N-type and P-type field-effect transistors (FETs) on a silicon substrate is called the front-end of line (FEOL). For example, FEOL processes may include photolithography, etching machines, cleaning machines, ion implantation, and chemical mechanical planarization. The corresponding back-end of line (BEOL) processes, for example, create several layers of conductive metal wires, with metal pillars connecting different layers. BEOL processes, for example, are used for packaging and include wiring and via drilling. BEOL metal structures, for example, include BEOL metal formed during BEOL processes. For example, back-end metal structures include back-end metal routing, metal pillars (vias) used to couple metal lines between different layers, and through-silicon vias (TSVs). Through-silicon vias (TSVs) create vertical connections between chips or wafers. By filling the vias with conductive materials such as copper, tungsten, and polysilicon, vertical electrical connections are achieved, enabling interconnection between chips.

For example, the temperature sensing unit 111 may include a back-end metal wire formed in a back-end process to sense temperature using a conductive metal wire. For another example, the first temperature sensing unit 111 may include a back-end metal wire formed in a back-end process and an array of back-end metal vias formed of pillar metal for coupling metal wires on different layers. For another example, the first temperature sensing unit 111 may include a back-end metal wire formed in a back-end process and an array of vias that pass through silicon wafer channels.

The disclosed embodiments utilize a metal-based temperature sensor whose sensing unit can be constructed from any layer of back-end metal routing or metal via arrays, enabling temperature measurement at multiple physical layers within a chip, as well as temperature measurement within 3D chip stacking structures.

The disclosed embodiments utilize the metal properties of the metal routing and metal channels (e.g., pillar metal) coupled to the vias in the back-end process to accurately measure temperature.

Figure 1B shows a schematic diagram of a back-end metal structure provided in at least one embodiment of the present disclosure. Figure 1C shows a schematic diagram of another back-end metal structure provided in at least one embodiment of the present disclosure. Figure 1D shows a schematic diagram of another back-end metal structure provided in at least one embodiment of the present disclosure.

As shown in Figure 1B, in this example, the back-end metal structure is a metal routing within the wafer.

As shown in Figure 1C, in this example, the back-end metal structure includes metal routing wires and a back-end metal via array located on multiple layers. For example, metal routing wires 120 and 130 are located on different layers. Figure 1C shows the metal routing wires located on one layer as a parallelogram. A metal pillar 140 couples metal routing wires 130 and 120. Multiple metal pillars similar to metal pillar 140, used to couple metal routing wires on different layers, form a back-end metal via array.

As shown in FIG1D , the back-end metal structure includes a through-wafer via array formed by a plurality of through-wafer vias (e.g., through-wafer via 150 , through-wafer via 160 , through-wafer via 170 , and through-wafer via 180 ) and metal wires (e.g., metal wire 101 , metal wire 102 , metal wire 103 , metal wire 104 , and metal wire 105 ) coupling two through-wafer vias.

The control unit 112 is coupled to the temperature sensing unit 111 and processes the temperature sensing electrical signal output by the temperature sensing unit 111 to output the measurement result.

The control unit 112 may be, for example, an on-chip analog-to-digital converter (ADC) module. The ADC module performs analog-to-digital conversion of data to measure the resistance of the temperature sensor's sensing element.

For example, the ADC module receives a temperature sensing signal and outputs a temperature measurement result based on the temperature sensing signal. For example, the temperature sensing signal includes current and voltage. The ADC module receives the current and voltage, calculates the resistance value based on the current and voltage, and obtains the temperature measurement result based on the relationship between temperature and resistance shown in Figure 2A.

Figure 2A shows a schematic diagram of the relationship between the resistance and temperature of the back-end metal structure.

For example, Figure 2A shows how the resistance of back-end metal traces located at different thin film layers or substrate layers within a chip changes with temperature. For example, the back-end metal structure can be single-layer or multi-layer (composite). Using a multi-layer structure can satisfy the constraints imposed by back-end routing on the location of the metal temperature sensor. The following example illustrates a multi-layer back-end metal structure.

As shown in Figure 2A, the resistance of the back-end metal wiring on the ITO/Ag/PET layer varies nearly linearly with temperature. The resistance of the back-end metal wiring on the ITO/Cu/PET layer varies nearly linearly with temperature. The resistance of the back-end metal wiring on the ITO/ZnO/PET layer varies nearly linearly with temperature. The resistance of the back-end metal wiring on the ITO/PET layer varies nearly linearly with temperature. The resistance of the back-end metal wiring on the ITO/Al/PET layer varies nearly linearly with temperature.

As shown in Figure 2A, the resistance of the back-end metal structure changes nearly linearly with temperature.

This technique leverages the fact that the resistance of back-end metal structures changes nearly linearly with temperature to measure the chip's internal temperature. For example, by supplying power to the back-end metal structure and measuring the current and voltage across it, the resistance of the back-end metal structure can be calculated based on the current and voltage across the back-end metal.

In this embodiment, the temperature sensing electrical signal may include, for example, current and voltage.

In some embodiments of the present disclosure, the control unit and the first sensing unit form a 4-wire Kelvin circuit, processing multiple temperature sensing electrical signals to output measurement results.

A 4-wire Kelvin circuit consists of four signal lines: a high-voltage application line, a low-voltage application line, a high-voltage detection line, and a low-voltage detection line.

For example, for the back-end metal structure shown in Figures 1B, 1C, and 1D, the back-end metal routing includes four terminals: VDD_MH, VDD_FH, VSS_ML, and VSS_FL. For example, VDD_MH is used to couple to a high-voltage detection line to measure high voltages, VDD_FH is used to couple to a high-voltage application line to provide high voltage and low current, VSS_FL is used to couple to a low-voltage application line to provide low voltage and low current, and VSS_ML is used to couple to a low-voltage detection line to measure low voltages. The detailed operating principles of the 4-wire Kelvin circuit are described in relevant literature and will not be further elaborated in this disclosed embodiment.

As shown in Figures 1B, 1C, and 1D, the distance between terminals VDD_FL and VDD_FH is greater than or equal to the distance between terminals VSS_ML and VSS_MH to implement 4-wire Kelvin measurements. For example, terminals VSS_FL and VDD_FH are located at the farthest ends of the back-end metal structure to accurately measure the resistance of the back-end metal structure. The farthest ends of the back-end metal structure refer to the beginning and end of the metal connection formed by the back-end metal structure. This allows the resistance of all traces or pillars to be included in the metal connection structure, avoiding inaccurate resistance measurements caused by ignoring the resistance of some metal structures. As shown in Figure 1D, metal wire 101, through-wafer via 150, metal wire 102, through-wafer via 160, metal wire 103, through-wafer via 170, metal wire 104, through-wafer via 180, and metal wire 105 form a complete metal connection structure. The starting point of this metal connection structure is located at metal wire 101, and the tail end is located at metal wire 105. Therefore, connection terminals VDD_FH and VDD_MH are located on metal wire 105, and connection terminals VSS_ML and VSS_FL are located on metal wire 101.

The disclosed embodiments use a metal-type temperature sensor sensing unit to replace the BJT-type temperature sensor sensing unit. This utilizes the stable temperature offset characteristics of metal resistors in the back-end (BEOL) process to mitigate fluctuations in the BJT manufacturing process in the front-end (FoF) and improve the inherent accuracy of the temperature sensor sensing unit.

In some embodiments of the present disclosure, a wafer includes at least one die (DIE, or die, bare die), and the first temperature sensing unit and the control unit are integrated into the same die in the at least one die; or the first temperature sensing unit is integrated into one of the at least one die, and the control unit is independent of the at least one die.

Figure 2B shows a schematic block diagram of a chip provided by at least one embodiment of the present disclosure.

As shown in FIG2B , chip 210 includes a die (DIE) 211. Chip 210 includes a temperature sensor system, which includes a temperature sensing unit 2111 and an ADC module 2112 integrated into die (DIE) 211. Temperature sensing unit 2111 is an example of a first temperature sensing unit, and ADC module 2112 is an example of a control unit.

In some embodiments of the present disclosure, the chip further includes a packaging portion, wherein the first temperature sensing unit is integrated into at least one of the dies and the control unit is independent of the at least one of the dies, including: the packaging portion in which the first temperature sensing unit is integrated into at least one of the dies and the control unit is disposed outside the dies.

Figure 2C shows a schematic block diagram of another chip provided by at least one embodiment of the present disclosure.

As shown in Figure 2C, chip 220 includes a die 221 and a packaging portion 222. The packaging portion is used to package chip 220. A temperature sensing unit 2211 is integrated into die 221, and an ADC module 2221 is disposed within packaging portion 222 to be independent of die 221. Temperature sensing unit 2211 is an example of a first temperature sensing unit, and ADC module 2221 is an example of a control unit.

In some embodiments of the present disclosure, when a chip includes multiple dies stacked together via a bonding structure, a first temperature sensing unit is integrated into at least one of the dies and the first temperature sensing unit is disposed in the bonding structure.

Figure 2D shows a schematic block diagram of another chip provided by at least one embodiment of the present disclosure.

As shown in FIG2D , chip 230 includes die 231, die 232, and a packaging portion 233. Die 231 and die 232 are stacked together via a bonding structure 234. Bonding structure 234 is used to bond die 231 and die 232 together.

The temperature sensing unit 2311 is integrated into the die 231, and the ADC module 2341 is located in the bonding structure 234, independent of the die 231 and the die 232.

In some embodiments of the present disclosure, a temperature sensor system includes a plurality of temperature sensing units, including a first temperature sensing unit. The temperature sensor system further includes a multiplexer coupled to the control unit and the plurality of temperature sensing units and configured to select one of the plurality of temperature sensing units.

For example, a temperature sensor system includes back-end metal windings arranged at multiple locations, and these back-end metal windings at multiple locations serve as multiple temperature sensing units.

The multiplexer couples multiple temperature sensing units to realize power supply and switching for multiple temperature sensing units.

Figure 3 shows a schematic diagram of the coupling relationship between the multiplexer and the temperature sensing unit provided in at least one embodiment of the present disclosure.

As shown in Figure 3, chip 300 includes temperature sensing unit 301, temperature sensing unit 302, and temperature sensing unit 303. Temperature sensing unit 301, temperature sensing unit 302, and temperature sensing unit 303 are all coupled to multiplexer 304. The multiplexer is coupled to ADC module 305.

Multiplexer 304 is used to select one of temperature sensing units 301, 302, and 303 to connect to ADC module 305. As shown in Figure 3, for example, multiplexer 304 selects temperature sensing unit 303 to connect to ADC module 305. As shown in Figure 3, ADC module 305 forms a four-wire Kelvin circuit with temperature sensing unit 303 through multiplexer 304. ADC module 305 applies a high voltage and low current to temperature sensing unit 303 via a high voltage application line and a low voltage and low current via a low voltage application line, respectively. ADC module 305 then detects the voltage across the temperature sensing unit via a high voltage detection line and a low voltage detection line.

The 4-wire Kelvin circuit enables more accurate resistance measurements, thereby improving temperature measurement accuracy.

In some embodiments of the present disclosure, the chip includes multiple dies, and the multiplexer and the first temperature sensing unit are located in the same die or in different dies.

For example, in the example of FIG2D , the temperature sensing unit 2311 is located in the die 231 , the multiplexer can be located in the die 231 , or the multiplexer can be located in the bonding structure 234 .

In some embodiments of the present disclosure, for example, each die may include multiple temperature sensing units. Each die may then include a multiplexer to select one of the multiple temperature sensing units to connect to the ADC module.

Figure 4 shows a schematic diagram of a temperature sensor system provided by at least one embodiment of the present disclosure.

In the example of Figure 4, a chip includes multiple dies packaged in a 2.5D package. In embodiments of this disclosure, a package in which multiple dies are arranged side by side on a silicon interposer, substrate, or base is referred to as a 2.5D package. For example, in the embodiments of Figure 4, die A and die B are arranged side by side on a silicon interposer, substrate, or base. Figure 4 illustrates four embodiments of temperature sensor systems provided by this disclosure. These four temperature sensor systems are described using a chip including die A and die B as an example.

As shown in the example of Figure 4(a), in some embodiments of the present disclosure, die A and die B each have built-in multiplexed sensors and ADC modules. Die A's multiplexer 401 is coupled to at least one temperature-sensing unit 402, or at least one back-end metal structure, in die A, and is also coupled to an ADC module 403 built into die A. Similarly, die B's multiplexer 411 is coupled to at least one temperature-sensing unit 412, or at least one back-end metal structure, in die B, and is also coupled to an ADC module 413 built into die B.

In some embodiments of the present disclosure, when the first temperature sensing unit and the control unit are integrated into different dies within at least one die, the first temperature sensing unit is located in the first die, and the control unit is located in the second die. The multiplexer in the first die is coupled to the control unit via an interconnect structure that couples the first die and the second die.

For example, in the example of FIG4(b), the first temperature sensing unit is the temperature sensing unit in die A, i.e., die A is an example of the first die, and the control unit is located in die B, i.e., die B is an example of the second die.

Die A has a built-in multiplexer 401 but no built-in ADC module; Die B has a built-in multiplexer 411 and an ADC module 413. Die A's multiplexer 401 is coupled to at least one temperature sensing unit 402 in Die A and is also coupled to ADC module 413 in Die B. For example, Die A and Die B are coupled via an inter-chip interconnect circuit structure. Those skilled in the art can employ circuit structures known in the art to couple Die A and Die B to enable communication between them.

The multiplexer 411 of die B is coupled to at least one temperature sensing unit 412 in die B and is also coupled to the built-in ADC module 413 in die B.

In some embodiments of the present disclosure, when a temperature sensing unit (e.g., a first temperature sensing unit) is integrated into at least one die and a control unit is independent of the at least one die, the multiplexer is coupled to the control unit via the package circuit structure of the first die.

For example, in the example of FIG4(c), the ADC module 42 is independent of any die (die A and die B) in the chip. Die A integrates a temperature sensing unit 402 and a multiplexer 401, and die B integrates a temperature sensing unit 412 and a multiplexer 411. The multiplexer 401 of die A is coupled to the multiple temperature sensing units 402 in die A, and the multiplexer 411 in die B is coupled to the multiple temperature sensing units 412 in die B. The multiplexer 401 in die A and the multiplexer 411 in die B are respectively coupled to the packaged ADC module 42 via a packaged circuit structure. The packaged ADC module 42 refers to an ADC module that is packaged into the same chip as die A and die B. In this example, die A and die B are both examples of the first die. The first die is packaged by a package circuit structure. For example, the first die includes a signal output port, the multiplexer is coupled to the signal output port, and the signal output port is coupled to the package circuit structure so that the multiplexer is coupled to the control unit.

For example, in the example shown in Figure 4(d), the chip includes an ADC module 43 independent of any die in the chip. In addition to ADC module 43, the chip also includes another ADC module 403 integrated into die A. Specifically, die A has built-in ADC module 403 and multiplexer 401, which is coupled to multiple temperature sensing units 402. Die B has built-in multiplexer 411 but no built-in ADC module. Therefore, multiplexer 411 in die B can be coupled to the encapsulated ADC module 43 via the packaged circuit structure.

In the examples shown in Figure 4 (c) and (d), the ADC module is integrated into the chip package and connected to the on-die temperature sensing unit via a multiplexer. This reduces the ADC module's footprint within the die, improving the chip's performance, power consumption, and area (PPA). Furthermore, since the ADC module is integrated into the chip package and connected to the on-die temperature sensing unit via a multiplexer, the ADC module's measurement accuracy is not limited by the die's ADC module area, thus improving temperature measurement resolution.

Figure 5 shows a schematic diagram of a temperature sensor system provided by at least one embodiment of the present disclosure.

In the example of Figure 5 , a wafer includes multiple dies bonded together via a bonding structure. The stacked structure of multiple dies shown in Figure 5 is referred to as a 3D wafer in this disclosure. Figure 5 illustrates four embodiments of a temperature sensor system in a wafer provided in this disclosure that includes multiple dies bonded together via a bonding structure. As shown in Figure 5 , die A and die B are bonded together via a bonding structure.

As shown in the example of Figure 5(a), in some embodiments of the present disclosure, die A and die B each have built-in multiplexed sensors and ADC modules. Die A's multiplexer 501 is coupled to at least one temperature-sensing unit 502 in die A and also to an ADC module 503 built into die A. Similarly, die B's multiplexer 511 is coupled to at least one temperature-sensing unit 512 in die B and also to an ADC module 513 built into die B.

In some embodiments of the present disclosure, when the first temperature sensing unit and the control unit are integrated into different dies within at least one die, the first temperature sensing unit is located in the first die, and the control unit is located in the second die. The multiplexer in the first die is coupled to the control unit via a bonding structure.

For example, in the example of Figure 5(b), the second die is die A, which is adjacent to the underlying substrate, and the first die is die B, which is stacked on the side of the second die away from the underlying substrate. The first temperature sensing unit is, for example, temperature sensing unit 502 in die A, meaning die A is an example of the second die, and the control unit is located in die B, meaning die B is an example of the first die.

Die A has a built-in multiplexer 501 but no built-in ADC module; Die B has a built-in multiplexer 511 and an ADC module 513. Die A's multiplexer 501 is coupled to at least one temperature sensing unit 502 in Die A and is also coupled to the ADC module 513 in Die B. For example, the multiplexer 501 in Die A is coupled to the ADC module 513 in Die B via a bonding structure. For example, the multiplexer 501 in Die A and the ADC module 513 in Die B are coupled via a circuit structure in the bonding structure. This disclosure does not limit the circuit structure in the bonding structure; those skilled in the art can design the circuit structure in the bonding structure to couple the multiplexer 501 in Die A to the ADC module 513 in Die B.

The multiplexer in die B is coupled to at least one temperature sensing unit in die B and is also coupled to the ADC module built into die B.

In some embodiments of the present disclosure, a first die and a second die are stacked via a bonding structure and packaged by a packaging circuit structure. The second die includes a signal output port, while the first die does not. The multiplexer is coupled to the signal output port via the bonding structure and is coupled to a control unit via the signal output port and the packaging circuit structure.

In the example shown in Figure 5(b), by integrating the ADC module in die B within the 3D chip and connecting it to the temperature sensing unit in die A, the ADC module's footprint in die A can be reduced, improving die A's PPA performance, power consumption, and footprint. Furthermore, die A can provide a larger area for designing a higher-precision ADC module, thereby improving temperature measurement resolution.

For example, in the example shown in Figure 5(c), ADC module 52 is independent of either die (die A or die B) in the chip. Die A integrates a temperature sensing unit 502 and a multiplexer 501, while die B integrates a temperature sensing unit 512 and a multiplexer 511. Multiplexer 501 in die A is coupled to multiple temperature sensing units 502 in die A, while multiplexer 511 in die B is coupled to multiple temperature sensing units 512 in die B.

For example, die A includes a signal output port, while die B does not. In this example, die B is an example of the first die, and die A is an example of the second die. The multiplexer 511 in die B is coupled to the signal output port of die A via a bonding structure, then to the packaged circuit structure via die A's signal output port, and then to the packaged ADC module 52 via the packaged circuit structure. The multiplexer 501 in die A is coupled to the packaged circuit structure via its own signal output port, and then to the packaged ADC module 52 via the packaged circuit structure.

In this example, the first die (i.e., die B) and the second die (i.e., die A) are packaged by a packaged circuit structure, and the ADC module 52 is sealed with the packaged first and second dies.

In the example of Figure 5(c), ADC module 52 is independent of die A and die B, reducing the ADC area occupied by die A and die B, improving the performance, power consumption, and area of die A and die B. Furthermore, die A and die B can provide a larger area for designing higher-precision ADC modules, thereby improving temperature measurement resolution.

For example, in the example of (d) in Figure 5 , the chip includes an ADC module 53 that is independent of any die in the chip. In addition to the ADC module 53, the chip also includes another ADC module 503 integrated in die A. That is, die A has a built-in ADC module 503 and a multiplexer 501, and the multiplexer 501 is coupled to multiple temperature sensing units 502. Die B has a built-in multiplexer 511, but no built-in ADC module. Therefore, the multiplexer 511 in die B can be coupled to the signal output port of die A through a bonding circuit structure, and coupled to the control unit through the signal output port and the packaging circuit structure. The ADC module 503 is used to process the temperature sensing signal output by the temperature sensing unit 502 in die A to obtain a measurement result. The ADC module 53 is used to process the temperature sensing signal output by the temperature sensing unit 512 in die B to obtain a measurement result.

In the example shown in Figure 5(d), by integrating the ADC in die A within the 3D chip and connecting it to the temperature-sensing unit in die B, the ADC area within die B is reduced, improving the performance, power consumption, and area of die B. Furthermore, die B provides a larger area for designing a higher-precision ADC module, thereby enhancing temperature measurement resolution.

In some embodiments of the present disclosure, a temperature sensing unit is disposed within a keying structure. When the temperature sensing unit is disposed within the keying structure, the control unit (e.g., ADC module) can be disposed within a first die (e.g., die A) or a second die (e.g., die B), with the multiplexer and the control unit disposed within the same die. For example, the ADC module can be disposed within the first die, and the multiplexer can also be disposed within the first die.

In some other embodiments of the present disclosure, the control unit is independent of the first die and the second die. The second die includes a signal output port. The multiplexer is disposed in the second die. The signal output port is coupled to the package circuit structure. The multiplexer is coupled to the signal output port. The signal output port is coupled to the package circuit structure, so that the multiplexer is coupled to the control unit via the package circuit structure.

For example, in the structure shown in Figure 5(d), the bonding structure includes a temperature-sensing unit. The second die is die A, which is adjacent to the underlying substrate, and the first die is die B, which is stacked on the side of the second die away from the underlying substrate. Die A includes a signal output port, and a multiplexer is disposed within die A. The multiplexer is coupled to the temperature-sensing unit in the bonding structure. The signal output port is coupled to the package circuit structure, the multiplexer is coupled to the signal output port, and the signal output port is coupled to the package circuit structure, so that the multiplexer is coupled to the control unit via the package circuit structure.

In this embodiment, a temperature sensing unit is provided in the key structure, thereby being able to monitor the temperature in the key structure.

Another aspect of the present disclosure provides a chip including the temperature sensor system provided by any of the aforementioned embodiments. This chip has high temperature measurement accuracy.

Figure 6 shows a schematic structural diagram of a chip provided in at least one embodiment of the present disclosure.

As shown in Figure 6, the chip includes die 601 and 602 stacked by a bonding structure 604. Die 601 is formed on a silicon interposer, substrate, or base 603. Die 602 is located on a side of die 601 that is away from the silicon interposer or base.

As shown in Figure 6, die 601 includes a transistor layer 611 (also called the "lower layer") formed through front-end processes, a back-end metal structure 612 (also called the "upper layer") formed through back-end processes, and a silicon substrate layer 613. The silicon substrate layer is the non-circuit layer of the chip. Figure 6 shows the chip in an inverted position.

As shown in FIG6 , the back-end metal structure 612 in die 601 includes a back-end metal routing 6121, a metal structure 6122 formed by a back-end metal via array and the back-end metal routing, and a metal structure 6123 consisting of a back-end metal routing and an array of vias passing through the silicon substrate.

The back-end metal routing 6121, the metal structure 6122 formed by the back-end metal via array and the back-end metal routing, and the metal structure 6123 composed of the back-end metal routing and the via array passing through the silicon substrate are used to sense the temperature at different locations in the die 601.

The structure of die 602 is similar to that of die 601 and will not be further described.

There are a few points that need clarification:

(1) The figures in the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure. Other structures can refer to the general design.

(2) In the absence of conflict, the embodiments of this disclosure and the features of the embodiments can be combined with each other to obtain new embodiments.

The above description is only a specific implementation of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be based on the scope of protection of the aforementioned claims.

100: Chip

110: Temperature sensor system

111: Temperature sensing unit

112: Control unit

Claims (11)

A temperature sensor system in a chip comprises: a first temperature sensing unit that senses temperature using a back-end metal structure formed in a back-end process of the chip to output a temperature sensing electrical signal, wherein the first temperature sensing unit senses temperature using at least one of a back-end metal routing or a metal via array formed in any layer of the back-end process; and a control unit coupled to the first temperature sensing unit that processes the temperature sensing electrical signal output by the first temperature sensing unit to output a measurement result. The chip comprises at least one die; the first temperature sensing unit and the control unit are integrated into the same die of the at least one die, or the first temperature sensing unit is integrated into one of the at least one die and the control unit is independent of the at least one die. The chip further includes a packaging portion, the first temperature sensing unit is integrated into one of the at least one die, and the control unit is independent of the at least one die, including: The first temperature sensing unit is integrated into one of the at least one die, and the control unit is disposed in the packaging portion outside the die; or When the chip includes multiple dies stacked via a bonding structure, the first temperature sensing unit is integrated into one of the at least one die, and the control unit is disposed within the bonding structure. The temperature sensor system of claim 1, wherein the temperature sensor system includes a plurality of temperature sensing units, the plurality of temperature sensing units including the first temperature sensing unit; The temperature sensor system further includes: A multiplexer coupled to the control unit and the plurality of temperature sensing units and configured to select one of the plurality of temperature sensing units. The temperature sensor system of claim 2, wherein the chip includes multiple dies, and the multiplexer and the first temperature sensing unit are located in the same die or in different dies. The temperature sensor system of claim 2, wherein the at least one die includes a first die, the multiplexer is located in the first die, wherein the first temperature sensing unit is integrated into one of the at least one die and the control unit is independent of the at least one die, the multiplexer is coupled to the control unit via a package circuit structure of the first die. A temperature sensor system as described in claim 4, wherein the first die includes a signal output port, the multiplexer is coupled to the signal output port, and the signal output port is coupled to the package circuit structure so that the multiplexer is coupled to the control unit. The temperature sensor system of claim 4, wherein the at least one die further includes a second die, the first die and the second die are stacked via a bonding structure and packaged by the package circuit structure, the second die includes a signal output port, while the first die does not, the multiplexer is coupled to the signal output port via the bonding structure, and is coupled to the control unit via the signal output port and the package circuit structure. The temperature sensor system of claim 2, wherein the at least one die includes a first die and a second die, and in a case where the first temperature sensing unit and the control unit are integrated into different dies of the at least one die: the first temperature sensing unit is located in the first die, and the control unit is located in the second die; the multiplexer in the first die is coupled to the control unit via an interconnect structure, wherein the interconnect structure is used to couple the first die and the second die; or the multiplexer in the first die is coupled to the control unit via a bonding structure, wherein the bonding structure is used to stack the first die and the second die. The temperature sensor system of claim 2, wherein the chip includes a first die and a second die, and in the case where the first temperature sensing unit is disposed in the bonding structure, the control unit is disposed in the first die or the second die, and the multiplexer and the control unit are disposed in the same die; or the control unit is independent of the first die and the second die, the second die includes a signal output port, the multiplexer is disposed in the second die, the signal output port is coupled to a package circuit structure, the multiplexer is coupled to the signal output port, and the signal output port is coupled to the package circuit structure, such that the multiplexer is coupled to the control unit via the package circuit structure. The temperature sensor system of any one of claims 1-8, wherein the back-end metal structure comprises at least one of the following: A back-end metal routing wire, a metal structure consisting of a back-end metal via array and the back-end metal routing wire, or a metal structure consisting of the back-end metal routing wire and an array of vias passing through a silicon substrate. A temperature sensor system as described in any one of claims 1-8, wherein the control unit and the first sensing unit form a 4-wire Kelvin circuit to process the temperature sensing electrical signal to output a measurement result. A chip comprising: a temperature sensor system as described in any one of claims 1-10.