TWI890199B - Cooling device for semiconductor device - Google Patents

Abstract

A semiconductor device according to an embodiment includes: a chamber including an internal structure capable of holding a pressure in the chamber lower than atmospheric pressure; one or a plurality of cooling member provided inside of the internal structure of the chamber, the cooling member holding and cooling a semiconductor device; and a heat transfer part exchanging heat with a refrigerator cooling the cooling member.

Description

Semiconductor device cooling equipment

One embodiment of the present disclosure relates to a semiconductor device cooling apparatus including a mechanism for cooling the semiconductor device.

In recent years, semiconductor devices such as memory systems that include non-volatile memory (NVRAM) have become increasingly common. Solid-state drives (SSDs) that include NAND flash memory are well-known examples of such semiconductor devices.

It is known that when flash memory is operated at low temperatures, data retention improves and the characteristic variation of memory cell transistors is reduced, thereby improving memory performance. As a result, a single memory cell can retain multiple bits of information through low-temperature operation. It has been shown that, in addition to flash memory, the performance of memory devices such as static random access memory (SRAM), dynamic random access memory (DRAM), and magnetic random access memory (MRAM), or logic devices such as central processing units (CPUs) and graphics processing units (GPUs) can be improved by cooling them to low temperatures and operating them. [Prior Art Literature] [Patent Literature]

[Patent Document 1] U.S. Patent Application Publication No. 2020/0170146 [Patent Document 2] U.S. Patent Application Publication No. 2021/0216117 [Patent Document 3] U.S. Patent Application Publication No. 2020/0022289

[The problem that the invention aims to solve]

The present disclosure aims to provide a semiconductor device cooling device that improves the performance of semiconductor devices such as memory devices and logic devices. [Solution]

A semiconductor device cooling apparatus according to one embodiment includes: a chamber capable of maintaining a pressure lower than atmospheric pressure; a cooling member disposed within the chamber for holding and cooling the semiconductor device; and a heat transfer portion for exchanging heat with a refrigerator for cooling the cooling member from outside the chamber.

The semiconductor device cooling device of this embodiment can improve the performance of semiconductor devices such as memory devices and logic devices.

A semiconductor device cooling apparatus according to one embodiment includes: a chamber capable of maintaining a pressure lower than atmospheric pressure; a cooling member disposed within the chamber for holding and cooling the semiconductor device; and a heat transfer portion for exchanging heat with a refrigerator for cooling the cooling member from outside the chamber.

The following describes a semiconductor device cooling system according to an embodiment in detail with reference to the drawings. In the following description, components having substantially the same function and structure are designated by the same reference numerals, and duplicate descriptions may be omitted. Each embodiment described below illustrates a device or method for embodying the technical concepts of the embodiment. The technical concepts of the embodiment are not limited to the materials, shapes, structures, and arrangements of the components described below. The technical concepts of the embodiment may be modified in various ways within the scope of the patent application.

[1. First Embodiment] [1-1. Structure of Semiconductor Device Cooling Apparatus 100] A semiconductor device cooling apparatus 100 according to a first embodiment will be described using Figures 1 to 4. Figure 1 is a perspective view showing the structure of a semiconductor device cooling apparatus according to one embodiment. As shown in Figure 1 , the semiconductor device cooling apparatus 100 includes a chamber 110, a cooling member 120, a heat transfer unit 130, a freezer 140, and a controller 180.

Chamber 110 is cylindrical. It includes a first chamber 111 and a second chamber 112. First chamber 111 and second chamber 112 are adjacent to each other along the cylindrical axis (D1) of chamber 110. A partition 113 is provided between first chamber 111 and second chamber 112. Partition 113 separates the interior of first chamber 111 from the interior of second chamber 112. This allows the pressure inside first chamber 111 to be adjusted to a different pressure than that inside second chamber 112.

In the first embodiment, the height of the first chamber 111 and the second chamber 112 is greater than 20 cm and less than 100 cm. In the first embodiment, the diameter (the distance between the inner walls facing each other) of the first chamber 111 and the second chamber 112 is greater than 20 cm and less than 100 cm.

Chamber 110 includes a first flange 115 and a second flange 116. First flange 115 is provided in first chamber 111. Second flange 116 is provided in second chamber 112. However, first flange 115 may also be provided in second chamber 112. Second flange 116 may also be provided in first chamber 111. First flange 115 is connected to a vacuum pump (VAC) provided outside chamber 110. A vacuum valve is provided on first flange 115. The vacuum valve controls the pressure inside first chamber 111. The vacuum pump can maintain the pressure inside first chamber 111 at a pressure lower than atmospheric pressure (a reduced pressure environment). The second flange 116 is a flange through which the lead wire 151, which will be described later, passes. The second flange 116 has a heat insulating function and includes a structure for heat insulating the inside and outside of the second cavity 112.

A lid 119 (see FIG3 ) is disposed on the upper portion of the first chamber 111 to seal the interior of the first chamber 111. However, the lid 119 is omitted in FIG1 and FIG2 for ease of explanation.

In this embodiment, the chamber 110 is exemplified as a cylindrical structure, but the present invention is not limited to this structure. For example, the chamber 110 may be shaped like a prism, a pyramid, or a sphere. In this embodiment, the first chamber 111 is exemplified as a structure connected to a vacuum pump, but the present invention is not limited to this structure. As long as the interior of the first chamber 111 can be controlled to be a reduced-pressure environment, the first chamber 111 may not be connected to the vacuum pump. For example, the interior of the first chamber 111 may be controlled to be a reduced-pressure environment by configuring the chamber 110 in a reduced-pressure environment, configuring the cooling member 120 and the heat transfer portion 130 in the interior of the first chamber 111 in this state, and sealing the first chamber 111. The vacuum pump may be connected to the second chamber 112 instead of the first chamber 111. Alternatively, the vacuum pump may be connected to both the first chamber 111 and the second chamber 112. The partition 113 may not separate the interior space of the first chamber 111 from the interior space of the second chamber 112. In other words, the interiors of both the first chamber 111 and the second chamber 112 may be controlled to a reduced pressure environment using a vacuum pump connected to either the first chamber 111 or the second chamber 112.

A cooling member 120 and a heat transfer portion 130 are provided inside the first chamber 111. The heat transfer portion 130 extends upward from a partition portion 113 corresponding to the bottom of the first chamber 111. In other words, the heat transfer portion 130 has a length in the cylindrical axial direction (D1) of the first chamber 111. The material of the heat transfer portion 130 is a material with high thermal conductivity, such as copper (Cu) or aluminum (Al). As the material of the heat transfer portion 130, a material with a thermal conductivity of 100 [W/m·K] or more can be used. The shape of the heat transfer portion 130 is cylindrical. The diameter of the circle of the cylinder is 2 cm or more. In other words, the width of the heat transfer portion 130 in the direction (D2) perpendicular to the cylindrical axial direction (D1) of the first chamber 111 is 2 cm or more. By using copper or aluminum as the heat transfer member 130 and having a diameter or width of 2 cm or greater, as described above, the semiconductor device 101 can be adequately cooled. For example, if the height of the first chamber 111 and the second chamber 112 are each 20 cm or greater and 100 cm or less, and the diameter of the first chamber 111 and the second chamber 112 are each 20 cm or greater and 100 cm or less, as described above, the cooling efficiency of the semiconductor device 101 can be significantly improved by using copper or aluminum as the heat transfer member 130 and having a diameter or width of 2 cm or greater.

The heat transfer portion 130 contacts the bottom of the first chamber 111. It exchanges heat with the freezer 140 (described later) to cool the cooling member 120. In this embodiment, the heat transfer portion 130 is fixed to the bottom of the first chamber 111. However, this structure is not limiting; the heat transfer portion 130 may also be removable relative to the first chamber 111.

The cooling member 120 is connected to the heat transfer unit 130. Multiple cooling members 120 are provided. Figure 1 shows only a portion of the multiple cooling members 120 (see Figure 2). The cooling member 120 is made of a material with high thermal conductivity, such as copper (Cu) or aluminum (Al). A material with a thermal conductivity of 100 [W/m·K] or higher can be used for the cooling member 120. The cooling member 120 is plate-shaped. The plate has a thickness of at least 1 cm. One side of the plate-shaped cooling member 120 is in contact with the heat transfer unit 130. Specifically, cooling member 120 is shaped like a rectangle having a length in the cylindrical axis direction (D1) of first chamber 111, with the long side of the rectangle contacting heat transfer portion 130. By using copper or aluminum as cooling member 120 as described above, and by ensuring that cooling member 120 has a thickness of at least 1 cm, semiconductor device 101 can be adequately cooled. For example, when the height of the first chamber 111 and the second chamber 112 are each greater than 20 cm and less than 100 cm, and the diameter of the first chamber 111 and the second chamber 112 are each greater than 20 cm and less than 100 cm, as described above, the cooling efficiency of the semiconductor device 101 can be significantly improved by using a material with a thermal conductivity of 100 [W/m·K] or greater as the cooling member 120, and the thickness of the cooling member 120 is greater than 1 cm.

The cooling member 120 is removable relative to the heat transfer portion 130. For example, a groove or protrusion extending along the cylindrical axis (D1) may be formed in the heat transfer portion 130. By sliding the cooling member 120 relative to the groove or protrusion in the cylindrical axis direction, the cooling member 120 can be attached to the heat transfer portion 130. However, the removable structure of the cooling member 120 is not limited to the above structure.

The cooling member 120 includes a first main surface 121 and a second main surface 122. The second main surface 122 is the surface opposite the first main surface 121. Semiconductor devices 101 are arranged on the first and second main surfaces 121, 122. In this embodiment, multiple semiconductor devices 101 are mounted on a printed circuit board 102. The printed circuit board 102 is arranged on the first and second main surfaces 121, 122. The printed circuit boards 102 are mounted on the first and second main surfaces 121, 122 of the cooling member 120 using grease, pins, or screws. In other words, the cooling member 120 holds the semiconductor devices 101. The number of printed circuit boards 102 disposed on the first main surface 121 of the cooling member 120 and the number of semiconductor devices 101 disposed on the printed circuit board 102 are not limited to the example shown in FIG. 1 .

Cooling unit 120 is equipped with a connector 150, a thermometer 160, and a heater 170. Connector 150, thermometer 160, and heater 170 are located closer to freezer 140 than semiconductor devices 101. Connector 150 electrically connects to the plurality of semiconductor devices 101 mounted on printed circuit board 102. Connector 150, thermometer 160, and heater 170 are connected to wiring 151, and are connected to control unit 180 via wiring 151. Power and drive signals are input from control unit 180 to semiconductor device 101 via connector 150. Thermometer 160 measures the temperature of cooling member 120 and transmits information related to the measured temperature to control unit 180 via connector 150 and wiring 151. Heater 170, in response to a signal from control unit 180, raises the temperature of cooling member 120 and prevents overcooling of cooling member 120. Heater 170 is connected to control unit 180 via connector 150 and wiring 151.

Thermometer 160 may also be installed at a location farther from freezer 140 than semiconductor device 101. Thermometer 160 may be installed on heat transfer portion 130, or on both cooling member 120 and heat transfer portion 130. Thermometer 160 may also be installed at multiple locations on cooling member 120. Heater 170 may be installed on heat transfer portion 130, or on both cooling member 120 and heat transfer portion 130.

A wired local area network (LAN) or an optical interconnect can be used as the wiring 151. When an optical interconnect is used, the inside and outside of the second chamber 112 are connected via optical fibers that can transmit light instead of the wiring 151.

Refrigerator 140, or a portion thereof, is located within second chamber 112. The term "a portion of refrigerator 140 located within second chamber 112" refers to, for example, a structure in which the cooling components of refrigerator 140 are located within second chamber 112 and the power supply of refrigerator 140 is located outside second chamber 112. A top plate 141 is located above refrigerator 140. Top plate 141 is connected to the top of second chamber 112, i.e., partition 113. Refrigerator 140 is connected to controller 180 via wiring 151. Refrigerator 140, for example, utilizes circulating helium-4 (He-4) for cooling. In other words, freezer 140 can cool using electricity, without the use of a refrigerant such as liquid nitrogen. The output power of freezer 140 is approximately 100 W. The power efficiency of freezer 140 is 1/50. The cooling temperature of freezer 140 can be varied within a range of, for example, 30 K to 100 K. The height of freezer 140 is 20 cm to 100 cm.

Figure 2 is a top view of the structure of a semiconductor device cooling system according to one embodiment. Figure 2 shows the state after the cover 119 (see Figure 3) has been removed, similar to Figure 1. As shown in Figure 2, when viewing the first chamber 111 in the cylindrical axial direction (D1), multiple cooling members 120 extend radially from the heat transfer portion 130 toward the inner wall of the first chamber 111. The number of cooling members 120 is not limited to the example shown in Figure 2. Printed circuit boards 102 are disposed on both the first and second main surfaces 121, 122 of the cooling members 120.

FIG3 is a cross-sectional view showing the structure of a semiconductor device cooling apparatus according to one embodiment. FIG3 is a cross-sectional view taken along line AA' of FIG2. As shown in FIG3, a cover 119 is provided on the upper portion of the first chamber 111. By sealing the first chamber 111 with the cover 119, the interior of the first chamber 111 is controlled to be a reduced-pressure environment. The cooling member 120 and the heat transfer portion 130 are connected to the partition portion 113 corresponding to the bottom of the first chamber 111. The top plate 141 of the freezer 140 is connected to the partition portion 113 corresponding to the top of the second chamber 112. With this structure, the cooling member 120 and the heat transfer portion 130 can be cooled efficiently. 3 , the bottom of the second chamber 112 is shown as being integrated with the side of the second chamber 112 , but the present invention is not limited to this structure. For example, the bottom may be detachable relative to the side.

Figure 4 is a cross-sectional view illustrating a method for attaching and detaching a semiconductor device in a semiconductor device cooling device according to one embodiment. As shown in Figure 4 , with cover 119 removed, cooling member 120 moves upward, thereby separating from heat transfer portion 130. Similarly, with cover 119 removed, cooling member 120 moves downward along the grooves or protrusions formed in heat transfer portion 130 as described above, thereby attaching cooling member 120 to heat transfer portion 130.

[1-2. Temperature Control Method of Semiconductor Device Cooling Apparatus 100] The temperature control method of the semiconductor device cooling apparatus 100 according to the first embodiment will be described using FIG5 . FIG5 is a flowchart illustrating the temperature control of the cooling member 120 in the semiconductor device cooling apparatus according to one embodiment. The temperature control shown in the following flowchart is performed by the control unit 180.

The temperature control of the cooling member will be described with reference to Figure 5. First, the vacuum pump reduces the pressure inside the first chamber 111 to a pressure lower than atmospheric pressure (a reduced pressure environment). After this reduction, the pressure inside the first chamber 111 is maintained at a pressure lower than atmospheric pressure (a reduced pressure environment). While the pressure inside the first chamber 111 is maintained at a pressure lower than atmospheric pressure (a reduced pressure environment), the control unit 180 determines the operating status of the semiconductor device 101 (step S501: Operating Status). If semiconductor device 101 is inactive for a predetermined period or longer ("No" in S501), control unit 180 continues operating cooler 140 to cool semiconductor device 101 to its idle temperature (step S502: Cooling). On the other hand, if semiconductor device 101 is currently operating or in operation ("Yes" in S501), control unit 180 determines whether the current temperature of cooling member 120 is appropriate as the drive temperature (step S503: Temp.). The idle temperature is lower than the drive temperature. The operating period means that although the semiconductor device 101 is not currently operating, it is scheduled to operate or has the possibility of operating. Regarding the operation of S502, in other words, the control unit 180 controls the temperature of the cooling member 120 to a lower temperature than the operating period of the semiconductor device 101 in S502.

For example, if semiconductor device 101 is a memory system, in S501, control unit 180 determines whether the memory system is in a dormant or active state based on commands sent from the host computer or the memory system's operating history. The driving temperature of semiconductor device 101 refers to the temperature of cooling member 120 when semiconductor device 101 is in an operating state. The resting temperature of semiconductor device 101 refers to the temperature of cooling member 120 when semiconductor device 101 is in a dormant state. For example, if semiconductor device 101 is a memory system as described above, the drive temperature is 70 K to 90 K, and the rest temperature is approximately 30 K. When the memory system is in operation, the drive temperature is applied to ensure that the memory cell transistors operate stably at a predetermined performance level. On the other hand, when the memory system is in rest, the rest temperature is applied to improve the retention characteristics of the memory cell transistors.

In S503, if the current temperature of cooling member 120 is not within the appropriate drive temperature range ("No" in S503), control unit 180 adjusts the temperature (step S504: Adjustment (heating/cooling)). Specifically, if the temperature of cooling member 120 measured by thermometer 160 is below the lower limit of the appropriate drive temperature range, control unit 180 controls the operation of at least one of semiconductor device 101, cooler 140, and heater 170 to increase the temperature of cooling member 120.

To increase the temperature of cooling member 120, control unit 180 may turn on heater 170. Alternatively, control unit 180 may reduce the cooling capacity of operating freezer 140 or stop its operation. Alternatively, control unit 180 may drive semiconductor device 101 to increase the temperature of cooling member 120. For example, if semiconductor device 101 operates based on a command received from the host computer, the driving of semiconductor device 101 may be performed on circuits unrelated to the address specified by the command.

When the temperature of the cooling member 120 measured by the thermometer 160 exceeds the upper limit of the appropriate driving temperature range, the control unit 180 controls the operation of at least one of the semiconductor device 101, the refrigerator 140, and the heater 170 to lower the temperature of the cooling member 120.

To lower the temperature of cooling member 120, control unit 180 may turn heater 170 off if heater 170 is on. Alternatively, if the output power of freezer 140 is not at maximum, control unit 180 may increase the output power of freezer 140. Alternatively, control unit 180 may suppress the operation of semiconductor device 101.

On the other hand, if the current temperature of cooling member 120 is within the appropriate drive temperature range ("YES" in S503), control unit 180 determines whether the current performance of semiconductor device 101 exceeds a predetermined standard (step S505: Performance). Performance evaluation in S505 is performed, for example, by checking the bit error rate during write or read operations, or the cumulative number of write operations per memory cell.

If the performance of semiconductor device 101 deteriorates below a predetermined standard in S505 ("No" in S505), control unit 180 performs recovery processing on semiconductor device 101 (step S506: Recovery). Specifically, the recovery processing of semiconductor device 101 can be performed by returning the pressure inside first chamber 111 to normal pressure, stopping cooling of first chamber 111, opening first chamber 111, removing semiconductor device 101 from the outside, and heating semiconductor device 101 at a temperature lower than the melting point of the solder. It is known that the performance degradation of semiconductor device 101 is caused by degradation of the gate insulating layer included in semiconductor device 101, and that the degradation of the gate insulating layer is repaired by the heat treatment. Specifically, the heat treatment is performed under conditions such as 125°C for one day or more, or 250°C for three hours or more.

The recovery process can also be performed by, for example, turning on heater 170 by control unit 180, without removing the device from first chamber 111. In this case, control unit 180 stops the operation of freezer 140. Alternatively, as part of the recovery process, control unit 180 can generate a notification signal indicating performance degradation related to, for example, degradation of the gate insulation layer of semiconductor device 101, and transmit this notification signal to an external device.

When the recovery process in S506 is completed, the process flow shown in Figure 5 is completed. Alternatively, if the performance of the semiconductor device 101 is above the predetermined standard in S505 ("Yes" in S505), the process flow shown in Figure 5 is completed.

In the example of FIG5 , steps S501 to S506 are described as a series of operations, but the structure is not limited to this. For example, only steps S501 and S502 may be included, and steps S503 to S506 may be omitted. Alternatively, only steps S503 and S504 may be included, and steps S501, S502, S505, and S506 may be omitted. Alternatively, only steps S505 and S506 may be included, and steps S501 to S504 may be omitted. Alternatively, only steps S501 and S502, only steps S503 and S504, or only steps S505 and S506 may be omitted from the structure of FIG5 .

As described above, the semiconductor device cooling device of this embodiment allows the semiconductor device 101 to be driven in a cooled state, thereby improving the performance of the semiconductor device 101. For example, if the semiconductor device 101 is a flash memory, operating the flash memory while maintaining the temperature of the cooling member 120 at an extremely low temperature of 77 K can reduce variations in the electrical characteristics of the memory cell transistors. Consequently, a single memory cell transistor can hold multiple bits of information, for example, 7 bits of information.

[2. Second Embodiment] A semiconductor device cooling apparatus according to a second embodiment will be described. The semiconductor device cooling apparatus 100 according to the second embodiment differs from the semiconductor device cooling apparatus 100 according to the first embodiment in the structure of the cooling member 120. The remaining structure is identical to that of the first embodiment, and therefore, description thereof will be omitted.

[2-1. Structure of Cooling Member 120] Figure 6 illustrates the structure of a cooling member in a semiconductor device cooling device according to one embodiment. Similar to Figure 2 , Figure 6 shows the structure of cooling member 120 when viewed from above (in the direction opposite to D1). As shown in Figure 6 , cooling member 120 includes a first plate-shaped member 123, a second plate-shaped member 124, and a cold storage member 125. For example, the end of first plate-shaped member 123 in the direction D2 is connected to heat transfer unit 130. Second plate-shaped member 124 holds semiconductor device 101 via printed circuit board 102. Cold storage member 125 is disposed between first plate-shaped member 123 and second plate-shaped member 124. As shown in FIG6 , the cold storage member 125 and the second plate-shaped member 124 are disposed on both the first surface 127 and the second surface 128 of the first plate-shaped member 123 .

Copper (Cu) or aluminum (Al) is used as the material for the first plate-shaped member 123 and the second plate-shaped member 124. The thickness of the first plate-shaped member 123 and the second plate-shaped member 124 is at least 1 cm. The material of the first plate-shaped member 123 can be the same as or different from the material of the second plate-shaped member 124. The thickness of the first plate-shaped member 123 can be the same as or different from the thickness of the second plate-shaped member 124.

Cold storage member 125 can be, for example, a member that has latent heat at low temperatures, such as the operating or resting temperatures, and can store externally applied heat, or a member that has a greater heat capacity than plate-shaped members 123 and 124. By providing cold storage member 125 between semiconductor device 101 and first plate-shaped member 123, even if semiconductor device 101 rapidly heats up at a rate exceeding the cooling capacity of refrigerator 140, heat transfer unit 130, and first plate-shaped member 123, cold storage member 125 can mitigate the rate of temperature increase of first plate-shaped member 123. Consequently, the temperature increase of semiconductor device 101 can be suppressed.

As described above, according to the semiconductor device cooling device of this embodiment, even when the semiconductor device 101 rapidly generates heat, the temperature rise of the entire cooling member 120 can be suppressed, thereby suppressing the temperature rise of the semiconductor device 101.

[3. Third Embodiment] A semiconductor device cooling system according to a third embodiment will be described. The semiconductor device cooling system 100 according to the third embodiment differs from the semiconductor device cooling system 100 according to the first embodiment in the structure of the chamber 110. The remaining structure is the same as that of the first embodiment, and therefore its description will be omitted.

[3-1. Structure of Semiconductor Device Cooling System 100] Figure 7 is a cross-sectional view showing the structure of a semiconductor device cooling system according to one embodiment. As shown in Figure 7, a load-lock chamber 200 is disposed above and adjacent to a first chamber 111. A load-lock door 210 is disposed between the first chamber 111 and the load-lock chamber 200. The load-lock door 210 is an openable and closable door. Opening and closing the load-lock door 210 controls whether the first chamber 111 and the load-lock chamber 200 are open or closed. That is, when the load lock door 210 is closed, the pressure inside the first chamber 111 and the pressure inside the load lock chamber 200 can be set to different pressures. Although not shown, similar to the first chamber 111, the load lock chamber 200 is equipped with a flange similar to the first flange 115 (see Figure 1), which is connected to a vacuum pump.

The height of the load lock chamber 200 is 20 cm to 100 cm, similarly to the height of the first chamber 111. The diameter of the load lock chamber 200 is 20 cm to 100 cm, similarly to the diameter of the first chamber 111. A lid 119 is placed above the load lock chamber 200 to seal the interior of the chamber.

[3-2. Operation of Chamber 110] Figures 8 and 9 are cross-sectional views illustrating the operation of the chamber in one embodiment of a semiconductor device cooling system. The operation of chamber 110 when the cooling member 120 installed in first chamber 111 is removed will be described using Figures 8 and 9. First, load lock chamber 200 is evacuated, and the pressure inside load lock chamber 200 is adjusted to the same level as the pressure inside first chamber 111.

After the load-lock chamber 200 is evacuated, as shown in FIG8 , the load-lock door 210 is opened, establishing communication between the first chamber 111 and the load-lock chamber 200. With the load-lock door 210 open, the cooling member 120, with the semiconductor device 101 mounted thereon, is moved from the first chamber 111 to the load-lock chamber 200. This movement of the cooling member 120 is accomplished by a movement mechanism located within the first chamber 111 or the load-lock chamber 200.

After the cooling member 120 is moved to the load-lock chamber 200, the load-lock door 210 is closed, shielding the first chamber 111 and the load-lock chamber 200. With the load-lock door 210 closed, the pressure inside the load-lock chamber 200 is adjusted to atmospheric pressure. Once the pressure reaches atmospheric pressure, as shown in FIG9 , the lid 119 is removed, and the cooling member 120 with the semiconductor device 101 mounted thereon is removed from the load-lock chamber 200.

As described above, according to the semiconductor device cooling system of this embodiment, the cooling member 120, on which the semiconductor device 101 is mounted, can be installed and removed via the load lock chamber 200. As a result, the first chamber 111 is not directly exposed to the external environment, thereby preventing contamination of the interior of the first chamber 111 by the external environment. Furthermore, the semiconductor device can be replaced while the cooling system remains in operation.

[4. Fourth Embodiment] A semiconductor device cooling apparatus according to a fourth embodiment will be described. The semiconductor device cooling apparatus 100 according to the fourth embodiment differs from the semiconductor device cooling apparatus 100 according to the first embodiment in the structures of the cooling member 120 and the heat transfer portion 130. The remaining structures are identical to those of the first embodiment and therefore will not be described here.

[4-1. Structure of Cooling Member 120 and Heat Transfer Section 130] Figure 10 is a cross-sectional view showing the structure of a semiconductor device cooling device according to one embodiment. Figure 10 not only shows the same cross-sectional view as Figure 3 but also illustrates the shape of side surface 126 between first and second main surfaces 121, 122 of cooling member 120. As shown in Figure 10, the width of side surface 126 (the distance between first and second main surfaces 121, 122) of cooling member 120 varies depending on its position along the cylindrical axis (D1) of chamber 110. Specifically, the width of side surface 126 increases closer to freezer 140 and decreases farther away from freezer 140. Specifically, the width T1 of the side surface 126 at the upper end of the cooling member 120 is smaller than the width T2 of the side surface 126 at the lower end of the cooling member 120. Similar to the width of the side surface 126 of the cooling member 120, the diameter of the heat transfer portion 130 increases as it approaches the freezer 140 and decreases as it moves farther away from the freezer 140. Specifically, the width T3 at the upper end of the heat transfer portion 130 is smaller than the width T4 at the lower end of the heat transfer portion 130.

Both the cooling member 120 and the heat transfer portion 130 transfer heat generated by the semiconductor device 101 to the refrigerator 140. This structure suppresses temperature increases in the semiconductor device 101. As shown in Figure 1, multiple semiconductor devices 101 are arranged in the direction D1. Therefore, the portions of the cooling member 120 and heat transfer portion 130 closer to the refrigerator 140 transfer more heat generated by the semiconductor device 101. Therefore, the width and diameter of the portions of the cooling member 120 and heat transfer portion 130 closer to the refrigerator 140 are increased compared to the portions farther away from the refrigerator 140. This prevents heat from stagnating near the refrigerator 140, thereby improving cooling efficiency by the refrigerator 140.

As described above, according to the semiconductor device cooling device of this embodiment, the semiconductor device 101 can be cooled efficiently.

[5. Fifth Embodiment] The fifth embodiment is a memory system 1 that represents an example of the semiconductor device 101 of any of the first to fourth embodiments described above. The memory system of the fifth embodiment includes, for example, a NAND flash memory as a semiconductor memory device and a memory controller that controls the NAND flash memory.

[5-1. Overall Structure of Memory System 1] Figure 11 is a block diagram illustrating the structure of a memory system according to one embodiment. As shown in Figure 11 , memory system 1 includes a memory controller 10 and non-volatile memory 20 comprising multiple memory cells. Memory system 1 can be connected to a host 30. Figure 11 shows memory system 1 connected to host 30. Host 30 is, for example, an electronic device such as a personal computer or portable terminal.

The non-volatile memory 20 includes multiple memory chips 21. The memory controller 10 controls each of the memory chips 21. Specifically, the memory controller 10 writes, reads, and erases data on each of the memory chips 21. Each of the memory chips 21 is connected to the memory controller 10 via a NAND bus.

Each memory chip 21 includes multiple dies 22. A die 22 is a wafer unit where memory cells are formed. Memory chip 21 is constructed by stacking multiple dies 22.

Each die 22 is provided with multiple memory blocks 23. Memory blocks 23 are units that can be bulk erased. All memory cell transistors within a memory block 23 are connected to the same source line. A single memory block 23 is sometimes referred to as a "physical block."

Memory block 23 consists of multiple pages. Writing and reading are performed in units of pages. A memory cell transistor, the smallest unit of memory device, is sometimes referred to simply as a "memory cell." The location of a memory cell within a physical block is sometimes referred to as a "physical address."

Non-volatile memory 20 is a non-volatile memory that stores data non-volatilely. For example, non-volatile memory 20 is a NAND flash memory (hereinafter referred to as NAND memory). In the following description, NAND memory is used as non-volatile memory 20. However, semiconductor storage devices other than NAND memory, such as three-dimensional flash memory, resistance random access memory (ReRAM), and ferroelectric random access memory (FeRAM), can also be used as non-volatile memory 20. The non-volatile memory 20 does not necessarily have to be a semiconductor storage device. This embodiment can be applied to various storage media other than semiconductor storage devices.

The memory system 1 can be a memory card or the like in which the memory controller 10 and the non-volatile memory 20 are packaged as a single package, or can be an SSD (Solid State Drive) or the like.

The memory controller 10 is, for example, a semiconductor integrated circuit (IC) configured as a system on a chip (SoC). The operations of the components of the memory controller 10 described below may be partially or entirely implemented in hardware, or may be implemented by the CPU (Central Processing Unit) executing firmware.

The memory controller 10 controls writing to the non-volatile memory 20 in response to write requests (write commands) from the host 30, controls reading from the non-volatile memory 20 in response to read requests (read commands) from the host 30, and controls erasing of the non-volatile memory 20 in response to erase requests (erase commands) from the host 30. The memory controller 10 includes a processor 11, random access memory (RAM) 12, read-only memory (ROM) 13, a randomizer 14, an error correction circuit (ECC) 15, a compression/decompression circuit 16, a host interface 17, and a memory interface 18. These functional blocks are interconnected via an internal bus 19.

The processor 11 is a control unit that comprehensively controls the various functional blocks of the memory system 1. Upon receiving a request (command) from the host computer 30 via the host interface 17, the processor 11 performs control corresponding to the command. For example, in response to a write command from the host computer 30, the processor 11 instructs the memory interface 18 to write data to the non-volatile memory 20. In response to a read command from the host computer 30, the processor 11 instructs the memory interface 18 to read data from the non-volatile memory 20. In response to the erase command from the host 30, the processor 11 instructs the memory interface 18 to perform an erase operation on the non-volatile memory 20.

When the processor 11 receives a write command from the main computer 30, it determines the storage area (memory area) on the non-volatile memory 20 to which the data temporarily stored in the RAM 12 is to be written. In other words, the processor 11 manages the data write destination. The correspondence between the logical address of the data received by the main computer 30 and the physical address representing the memory area on the non-volatile memory 20 storing the data is stored in an address translation table. When executing a write operation in response to a write command, the processor 11 can store in the RAM 12 the time of the write operation or the time since a certain reference period.

When the processor 11 receives a read command from the main computer 30, it uses the address conversion table to convert the logical address specified by the read command into a physical address and instructs the memory interface 18 to read from the physical address. When the processor 11 executes the read operation corresponding to the read command, it can store the time of the read operation or the time since a certain reference period in the RAM 12.

When the processor 11 receives an erase command from the main computer 30, it uses the address conversion table to convert the logical address specified by the erase command into a physical address and instructs the memory interface 18 to perform an erase operation on the physical address. When executing the erase operation corresponding to the erase command, the processor 11 can store the time of the erase operation or the time since a certain reference period in the RAM 12.

In NAND memory, write and read operations are typically performed in data units called "pages," and erase operations are performed in data units of the physical block. In the following description, "page" refers to the smallest unit of write operation. Multiple memory cells connected to the same word line are called a "memory cell group." In the case of single-level cell (SLC) memory cells, a memory cell group constitutes a page. In the case of multi-bit cells, such as multi-level cells (MLC) with one cell group forming two pages, triple-level cells (TLC) with one cell group forming three pages, or quad-level cells (QLC) with one cell group forming four pages, one cell group corresponds to multiple pages. Each cell is connected to both word lines and bit lines. Therefore, each cell can be identified using both word line and bit line addresses.

The RAM 12 functions as a data buffer, for example. The RAM 12 temporarily holds data received from the host computer 30 until the memory controller 10 stores the data in the non-volatile memory 20. The RAM 12 also temporarily holds data read from the non-volatile memory 20 until the data is sent to the host computer 30. For example, general-purpose memory such as SRAM or DRAM can be used as the RAM 12.

The ROM 13 stores various programs and parameters for operating the memory controller 10. The programs and parameters stored in the ROM 13 are read out to the processor 11 as needed and executed.

The random number generator 14, which includes, for example, a linear feedback shift register, generates a virtual random number uniquely determined for the input seed value. The virtual random number generated by the random number generator 14 is, for example, the value calculated by the processor 11 as the exclusive OR of the written data. This random number randomizes the data written to the non-volatile memory 20. The random number generator 14 derandomizes the data read from the non-volatile memory 20. Derandomization refers to obtaining the original, pre-randomized data from the randomized data.

Based on instructions from the processor 11, the ECC circuit 15 performs ECC encoding (error correction coding) during write operations and ECC decoding (error correction decoding) during read operations. The ECC circuit 15 can employ encoding schemes such as Low-Density Parity-Check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, or Reed-Solomon (RS) codes.

The compression/decompression circuit 16 operates as an encoding unit that compresses data written to the non-volatile memory 20. The compression/decompression circuit 16 also operates as a decoding unit that decompresses data read from the non-volatile memory 20.

The host interface 17 performs standard-compliant processing between the host 30 and the host interface 17. The host interface 17 outputs commands received from the host 30 and data to be written to the internal bus 19. The host interface 17 transmits data read from the non-volatile memory 20 and decompressed by the compression/decompression circuit 16 to the host 30. The host interface 17 also transmits responses from the processor 11 to the host 30.

The memory interface 18 performs write operations and erase operations on the non-volatile memory 20 based on instructions from the processor 11. The memory interface 18 performs read operations from the non-volatile memory 20 based on instructions from the processor 11.

[5-2. Operation of Memory System 1] In the memory system 1 having the above-described structure, when executing a write operation to non-volatile memory 20, the processor 11 instructs the compression/decompression circuit 16 to compress the data. At this time, the processor 11 determines the storage location (storage address) of the written data in non-volatile memory 20 and indicates the determined storage address to the memory interface 18. Based on the instruction from the processor 11, the compression/decompression circuit 16 compresses the data in the RAM 12. Based on instructions from the processor 11, the randomizer 14 randomizes the compressed data on the RAM 12. Based on instructions from the processor 11, the ECC circuit 15 further performs ECC encoding on the randomized data. The write data generated thereby is written to a designated storage address in the non-volatile memory 20 via the memory interface 18.

Meanwhile, when reading from non-volatile memory 20, processor 11 specifies an address on non-volatile memory 20, determines the conditions for reading the memory cell based on the specified address, and instructs memory interface 18 to execute the read operation. Processor 11 instructs ECC circuit 15 to start ECC decoding, random number generator 14 to start derandomization, and compression/decompression circuit 16 to start decompression. Following instructions from the processor 11, the memory interface 18 reads data from a designated address in the non-volatile memory 20 and inputs the resulting data into the ECC circuit 15. The ECC circuit 15 performs ECC decoding on the input data. The randomizer 14 derandomizes the ECC-decoded data. The compression/decompression circuit 16 decompresses the derandomized data. If decompression is successful, the processor 11 stores the decompressed original data in the RAM 12. On the other hand, if ECC decoding, randomization removal, or decompression fails, the processor 11 notifies the host computer 30 of a read error, for example.

While the present invention has been described above with reference to the drawings, the present invention is not limited to the embodiments described above and is capable of modifications as appropriate without departing from the spirit of the present invention. For example, if a semiconductor device cooling system based on the present embodiment is modified by a person skilled in the art by adding, deleting, or modifying components, such modifications are also within the scope of the present invention, as long as they encompass the spirit of the present invention. Furthermore, the embodiments described above can be combined as appropriate, provided they do not conflict with each other. Technical matters common to all embodiments are encompassed by all embodiments, even if not explicitly described.

Even if there are other effects different from the effects brought about by the aspects of the embodiments described above, the effects clearly stated in the description of this specification or the effects that can be easily predicted by those skilled in the art are of course also interpreted as being brought about by the present invention.

1: Memory system 10: Memory controller 11: Processor 12: RAM 13: ROM 14: Random access generator 15: ECC circuit 16: Compression/decompression circuit 17: Host interface 18: Memory interface 19: Internal bus 20: Non-volatile memory 21: Memory chip 22: Die 23: Memory block 30: Host 100: Semiconductor device cooling system 101: Semiconductor device 102: Printed circuit board 110: Chamber 111: First chamber 112: Second chamber 113: Partition 115: First flange 116: Second flange 119: Cover 120: Cooling member 121: First main surface 122: Second main surface 123: First plate member/plate member 124: Second plate member/plate member 125: Cooling member 126: Side surface 127: First surface 128: Second surface 130: Heat transfer unit 140: Refrigerator 141: Top plate 150: Connector 151: Wiring 160: Thermometer 170: Heater 180: Control unit 200: Load lock chamber 210: Load lock door A-A': Wire D1: Cylindrical axis D2: Direction perpendicular to the cylindrical axis (D1) of first chamber 111 S501, S502, S503, S504, S505, S506: Steps T1, T2, T3, T4: Width VAC: Vacuum pump

Figure 1 is a perspective view showing the structure of a semiconductor device cooling apparatus according to one embodiment. Figure 2 is a top view showing the structure of a semiconductor device cooling apparatus according to one embodiment. Figure 3 is a cross-sectional view showing the structure of a semiconductor device cooling apparatus according to one embodiment. Figure 4 is a cross-sectional view showing a method for removing and assembling a semiconductor device in a semiconductor device cooling apparatus according to one embodiment. Figure 5 is a flow chart showing temperature control of a cooling member in a semiconductor device cooling apparatus according to one embodiment. Figure 6 is a diagram showing the structure of a cooling member in a semiconductor device cooling apparatus according to one embodiment. Figure 7 is a cross-sectional view showing the structure of a semiconductor device cooling apparatus according to one embodiment. Figure 8 is a cross-sectional view illustrating the operation of a chamber in a semiconductor device cooling apparatus according to one embodiment. Figure 9 is a cross-sectional view illustrating the operation of a chamber in a semiconductor device cooling apparatus according to one embodiment. Figure 10 is a cross-sectional view illustrating the structure of a semiconductor device cooling apparatus according to one embodiment. Figure 11 is a block diagram illustrating the structure of a memory system according to one embodiment.

100: Semiconductor device cooling device

101: Semiconductor Devices

102:Printed substrate

110: Chamber

111: First Chamber

112: Second Chamber

113: Spacing part

115: First flange

116: Second flange

120: Cooling components

121: First main surface

122: Second main surface

130: Heat transfer unit

140: Freezer

141: Top plate

150: Connector

151:Wiring

160: Thermometer

170: Heater

180: Control Department

D1: Cylindrical Axis

D2: Direction perpendicular to the cylindrical axis (D1) of the first chamber 111

VAC: Vacuum pump

Claims (19)

A semiconductor device cooling system includes: a chamber having an internal structure capable of maintaining a pressure lower than atmospheric pressure; a cooling member disposed within the chamber's internal structure and configured to hold and cool a memory system within the chamber, wherein the memory system includes a memory controller and non-volatile memory and is capable of writing, reading, and erasing data in response to commands from a host computer; and a heat transfer unit that exchanges heat with a refrigerator that cools the cooling member. The cooling member includes a connector electrically connected to the memory system and supplied with power and a drive signal for driving the memory system. The semiconductor device cooling apparatus according to claim 1, wherein the pressure inside the chamber can be reduced to a pressure lower than atmospheric pressure by a vacuum pump. The semiconductor device cooling device according to claim 1, wherein the chamber is cylindrical, and the heat transfer portion has a length in the cylindrical axial direction of the chamber. The semiconductor device cooling device according to claim 3, wherein the cooling member is plate-shaped. The semiconductor device cooling device according to claim 4, wherein the cooling member has a plate thickness of 1 cm or more. The semiconductor device cooling device according to claim 4, wherein the thermal conductivity of the cooling member is 100 [W/m·K] or higher. The semiconductor device cooling device according to claim 4, wherein the cooling member comprises any one of copper and aluminum. The semiconductor device cooling device according to claim 4, wherein the cooling member extends axially along the cylinder and extends from the heat transfer portion toward the inner wall of the chamber. The semiconductor device cooling device according to claim 4, wherein a plurality of cooling members are provided, and when viewed along the axis of the cylinder, the plurality of cooling members extend radially from the heat transfer portion. The semiconductor device cooling device according to claim 5, wherein the heat transfer portion is columnar and has a length in the axial direction of the cylinder, and wherein the width of the heat transfer portion in a direction perpendicular to the axial direction of the cylinder is 2 cm or greater. The semiconductor device cooling device according to claim 1, wherein: the cooling member comprises: a first plate-shaped member connected to the heat transfer portion; a second plate-shaped member for retaining the memory system; and a cold storage member between the first plate-shaped member and the second plate-shaped member. A semiconductor device cooling device as described in claim 1, wherein the cooling component includes a thermometer and a heater. The semiconductor device cooling system according to claim 12 further includes a control unit connected to the thermometer and the heater, wherein the control unit turns on the heater when the temperature measured by the thermometer is below a predetermined temperature. The semiconductor device cooling device according to claim 12 further includes a control unit, wherein: the cooling member includes a thermometer connected to the control unit; the control unit drives the memory system to increase the temperature of the cooling member when the temperature measured by the thermometer is below a predetermined temperature. The semiconductor device cooling device according to claim 1 further includes a control unit. When the memory system is inoperative for a predetermined period or longer, the control unit controls the temperature of the cooling member to a lower temperature than when the memory system is inoperative. The semiconductor device cooling device of claim 1 further includes a control unit, the cooling member includes a heater connected to the control unit, and the control unit turns on the heater to heat the memory system when the performance of the memory system degrades below a predetermined standard. The semiconductor device cooling apparatus according to any one of claims 12 to 16, wherein the pressure inside the chamber can be reduced to a pressure lower than atmospheric pressure by a vacuum pump. The semiconductor device cooling device according to claim 1 further includes a control unit. When the performance of the memory system degrades below a predetermined standard, the control unit generates a notification signal notifying of the performance degradation. The semiconductor device cooling system of claim 1 further includes a load lock chamber adjacent to the chamber via an openable and closable door. When the door is open, the memory system is moved from the chamber to the load lock chamber. When the door is closed, the memory system is removed from the load lock chamber.