TWI889735B - Light receiving element and light receiving device - Google Patents

Abstract

The present invention provides a light receiving element, which comprises: a semiconductor substrate; a photoelectric conversion unit (PD) disposed in the semiconductor substrate (200) and converting light into electric charge; a first charge storage unit (MEM) disposed in the semiconductor substrate and transmitting the electric charge from the photoelectric conversion unit; a first distribution gate (150a) disposed on the front surface of the semiconductor substrate and transmitting the electric charge from the photoelectric conversion unit to the first charge storage unit. The invention discloses a method for distributing the aforementioned charge to the aforementioned charge storage portion; a second charge storage portion (MEM) is arranged in the aforementioned semiconductor substrate and transmits the aforementioned charge from the aforementioned photoelectric conversion portion; and a second distribution gate (150b) is arranged on the front surface of the aforementioned semiconductor substrate and distributes the aforementioned charge from the aforementioned photoelectric conversion portion toward the aforementioned second charge storage portion; and the aforementioned first and second distribution gates each have a pair of embedded gate portions (170a, 170b) embedded in the aforementioned semiconductor substrate.

Description

Light receiving element and light receiving device

This disclosure relates to a light-receiving element and a light-receiving device.

A known method for measuring the distance to an object is a TOF (Time of Flight) sensor (light-receiving device). For example, an indirect TOF sensor irradiates an object with light of a specific period and detects the phase difference between the irradiated light and the reflected light, thereby measuring the distance to the object. Furthermore, TOF sensors repeat light reception multiple times at short intervals, increasing the signal intensity and improving the S/N (Signal/Noise) ratio, enabling highly accurate distance measurement.

[Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Application Laid-Open No. 2019-4149

As mentioned above, a TOF sensor (light-receiving device) repeatedly receives light multiple times at short intervals to improve the signal-to-noise ratio. Therefore, the charge generated by the light-receiving photodiode built into the TOF sensor must be transferred at high speed.

Therefore, in view of such circumstances, this disclosure proposes a light-receiving element and a light-receiving device capable of transferring charge at high speed.

According to the present disclosure, a light-receiving element is provided, which comprises: a semiconductor substrate; a photoelectric conversion unit disposed in the semiconductor substrate and converting light into electric charge; a first charge storage unit disposed in the semiconductor substrate and transmitting the electric charge from the photoelectric conversion unit; a first distribution gate disposed on the front surface of the semiconductor substrate and distributing the electric charge from the photoelectric conversion unit toward the first charge storage unit; a second charge storage unit disposed in the semiconductor substrate and transmitting the electric charge from the photoelectric conversion unit; and a second distribution gate disposed on the front surface of the semiconductor substrate and distributing the electric charge from the photoelectric conversion unit toward the second charge storage unit; and the first and second distribution gates each have a pair of embedded gate units embedded in the semiconductor substrate.

Furthermore, according to the present disclosure, a light receiving device is provided, which has one or more light receiving elements, wherein the light receiving element comprises: a semiconductor substrate; a photoelectric conversion unit disposed in the semiconductor substrate and converting light into electric charge; a first charge storage unit disposed in the semiconductor substrate and receiving the electric charge from the photoelectric conversion unit; a first distribution gate disposed on the front surface of the semiconductor substrate and receiving the electric charge from the photoelectric conversion unit; The first and second distribution gates each include a pair of embedded gate portions embedded in the semiconductor substrate.

1: Ranging module

10: Light-receiving element

12: Pixel array section

20:Irradiation Department

30: Light receiving part

32: Vertical drive circuit

34: Line signal processing circuit

36: Horizontal drive circuit

38: Output circuit

40: Control Unit (Irradiation Control Unit)

42: Pixel drive wiring

44: Control circuit section

46: Horizontal signal line

48: Vertical signal line

50: Distribution transistor driver

52: Signal Processing Unit

54: Data Storage Department

60: Processing Department

100, 100a, 100b, 102a, 102b, 104a, 104b, 106a, 106b, 108a, 108b, 110a, 110b, 112a, 112b, 114a, 114b, 116a, 116b: N-type semiconductor regions

150a: Gate electrode (first distribution gate)

150b: Gate electrode (second distribution gate)

150,152a,152b,156,156a,156b,158,158a,158b,160,160a,160b,162,162a,162b: Gate electrode

154,154a,154b,306,406: Electrode

170, 170a, 170a-1, 170a-2, 170b, 170b-1, 170b-2, 174a, 174a-1, 174a-2, 174b, 174b-1, 174b-2: Embedded gate.

172: Silicon oxide film (low dielectric layer)

172a,172a-1,172a-2,172b,172b-1,172b-2,176a,176a-1,176a-2,176b,176b-1,176b-2,178: Low dielectric layer

200:Semiconductor substrate

202: Anti-reflective film

202a: Moth-eye structure

204: Planarization film

206:Light-shielding film

208: Crystal lens

210: Pixel separation section (first pixel separation section)

210a: Pixel separation section (second pixel separation section)

300: Wiring layer

302,402: Insulation film

304,404: Metal film

400:Substrate

500: Thermally oxidized silicon layer

502: Silicon nitride layer

504: Silicon oxide layer

506,508: Anti-corrosion Agent

510,512: Groove

600,602: Centerline

700:Around

710: Through hole

720: Insulating film (third insulating film) (second insulating layer)

720a: Insulation film/gate insulation film

730: Sidewall

740: Insulation film (third insulation film) (first insulation film)

800: Object

802a,802b: Area

900: Smartphone

901:CPU

902:ROM

903: RAM

904: Storage device

905: Communication Module

906: Communication Network

907: Sensor module

908: Ranging Module

909: Camera Device

910: Display device

911: Speaker

912: Microphone

913: Input device

11000: Endoscopic Surgery System

11101: Lens tube

11102:Camera head

11100: Endoscope

11110: Other surgical instruments

11111:Pneumoperitoneum tube

11112: Energy Disposal Device

11120: Support arm device

11131: Operator (Doctor)

11132: Patient

11133: Hospital bed

11200: Trolley

11201:CCU

11202: Display device

11203: Light source device

11204: Input device

11205: Disposal device control device

11206: Pneumoperitoneum device

11207: Recorder

11208:Printer

11209: Ranging signal processing device

11400: Transmission cable

11401: Lens unit

11402: Camera Department

11403: Drive Department

11404: Communications Department

11405: Camera head control unit

11411: Communications Department

11412: Image Processing Department

11413: Control Department

12000: Vehicle Control System

12001: Communication Network

12010: Drive system control unit

12020: Vehicle System Control Unit

12030: External vehicle information detection unit

12031: Photography Department

12032,15004:iToF sensor

12040: In-vehicle information detection unit

12041: Driver Status Detection Unit

12050: Integrated control unit

12051: Microcomputer

12052: Audio and video output unit

12053: In-vehicle network I/F

12061: Audio Speaker

12062: Display unit

12063: Instrument panel

12100: Vehicles

12101, 12102, 12103, 12104, 12105: Camera Department

12111,12112,12113,12114: Photography range

12201: iToF sensor module

15001: Lens

15002: Semi-reflective mirror

15003: Imaging Component

15005:Memory

A-A’,B-B’,C-C’,D-D’,E-E’,F-F’: line

AMP1, AMP2, AMP3, AMP4: Amplifier transistors

D: Area

FD, FD1, FD2, FD3, FD4: Floating diffusion area

L: Long side

L1, L2: Diameter

MEM1: Charge storage unit (first charge storage unit)

MEM2: Charge storage unit (second charge storage unit)

MEM, MEM3, MEM4: Charge storage unit

O: Center point (center)

OFG, OFG1, OFG2: Charge discharge transistors

PD: Photodiode

RST1, RST2, RST3, RST4: Reset transistors

SEL1, SEL2, SEL3, SEL4: Select transistors

TG, TG1, TG2, TG3, TG4: Transistors

VDD: power supply voltage

VG, VG1, VG2, VG3, VG4: Distribution transistors

VSL, VSL1, VSL2: signal lines

Φ: Phase difference

FIG1 is a block diagram showing an example of the configuration of a ranging module 1 according to an embodiment of the present disclosure.

FIG2A is an explanatory diagram (Part 1) showing an example of the planar configuration of the light receiving portion 30 according to an embodiment of the present disclosure.

Figure 2B is an explanatory diagram showing an example of the planar configuration of the light receiving portion 30 of an embodiment of the present disclosure (Part 2)

FIG2C is an explanatory diagram (Part 3) showing an example of the planar configuration of the light receiving portion 30 according to an embodiment of the present disclosure.

Figure 3 is an equivalent circuit diagram of the light-receiving element 10 according to an embodiment of the present disclosure.

FIG4 is an explanatory diagram illustrating the principle of a distance calculation method using the ranging module 1 according to an embodiment of the present disclosure.

FIG5 is an explanatory diagram showing an example of the planar configuration of the light-receiving element 10 according to the first embodiment of the present disclosure.

Figure 6 is a cross-sectional view of the light-receiving element 10 taken along line A-A' in Figure 5.

Figure 7 is a cross-sectional view of the light-receiving element 10 taken along line B-B' in Figure 5.

Figure 8 is an explanatory diagram used to illustrate this implementation.

Figure 9 is an enlarged view of area D in Figure 6.

FIG10 is an explanatory diagram showing an example of the planar configuration of the light-receiving element 10 according to the first variation of the embodiment.

Figure 11 is an illustrative diagram showing an example planar configuration of the light-receiving element 10 according to Variation 2 of this embodiment.

FIG12 is an explanatory diagram showing a cross-sectional configuration example of the light-receiving element 10 according to Variation 3 of the embodiment.

FIG13 is an explanatory diagram showing a cross-sectional configuration example of the light-receiving element 10 according to Variation 4 of the embodiment.

FIG14 is an explanatory diagram showing a cross-sectional configuration example of the light-receiving element 10 according to Variation 5 of the embodiment.

FIG15 is an explanatory diagram showing a cross-sectional configuration example of a portion of the light-receiving element 10 according to Variation 6 of the embodiment.

FIG16 is an explanatory diagram showing a cross-sectional configuration example of the light-receiving element 10 according to Variation 7 of the embodiment.

FIG17 is an explanatory diagram for illustrating the light-receiving element 10 according to the second embodiment of the present disclosure.

FIG18 is an explanatory diagram showing an example of the planar configuration of the light-receiving element 10 of this embodiment.

FIG19 is an explanatory diagram showing an example of the planar configuration of the light-receiving element 10 according to the first variation of the embodiment.

FIG20 is an explanatory diagram showing an example of the planar configuration of the light-receiving element 10 according to the second variation of the embodiment.

Figure 21A is an explanatory diagram (Part 1) for explaining the manufacturing method of the light-receiving element 10 of this embodiment.

FIG21B is an explanatory diagram (part 2) for explaining the manufacturing method of the light-receiving element 10 of this embodiment.

Figure 21C is an explanatory diagram (part 3) used to illustrate the manufacturing method of the light-receiving element 10 of this embodiment.

Figure 21D is an explanatory diagram (part 4) used to illustrate the manufacturing method of the light-receiving element 10 of this embodiment.

Figure 21E is an explanatory diagram (part 5) used to illustrate the manufacturing method of the light-receiving element 10 of this embodiment.

Figure 21F is an explanatory diagram (part 6) used to illustrate the manufacturing method of the light-receiving element 10 of this embodiment.

FIG22 is an explanatory diagram showing an example of the planar configuration of the light-receiving element 10 according to the third embodiment of the present disclosure.

Figure 23A is a cross-sectional view of the light-receiving element 10 taken along line C-C' in Figure 22.

Figure 23B is a cross-sectional view of the light-receiving element 10 taken along line D-D' in Figure 22.

FIG24 is an explanatory diagram showing an example of the planar configuration of the light-receiving element 10 according to the fourth embodiment of the present disclosure.

Figure 25A is a cross-sectional view of the light-receiving element 10 taken along line E-E' in Figure 24.

Figure 25B is a cross-sectional view of the light-receiving element 10 taken along line F-F' in Figure 24.

FIG26 is a block diagram showing an example of the configuration of a smartphone 900 as an electronic device to which the ranging module 1 according to an embodiment of the present disclosure is applicable.

Figure 27 is a diagram showing an example of the schematic configuration of an endoscopic surgery system.

Figure 28 shows an example of the structure of an endoscope.

Figure 29 is a block diagram showing an example of the functional configuration of the camera head and CCU.

Figure 30 is a block diagram showing an example of the schematic configuration of a vehicle control system.

Figure 31 is an explanatory diagram showing an example of the installation positions of the vehicle's external information detection unit and the camera unit.

Below, preferred embodiments of the present invention are described in detail with reference to the accompanying drawings. Furthermore, in this specification and drawings, components having substantially the same functional configuration are designated with the same reference numerals to avoid repeated description.

In this specification and drawings, multiple components with substantially the same or similar functions may be distinguished by different numerals after the same symbol. However, when there is no need to distinguish the multiple components with substantially the same or similar functions, they are simply given the same symbol. Similarly, similar components in different implementations may be distinguished by different letters after the same symbol. However, when there is no need to distinguish the similar components, they are simply given the same symbol.

The figures referenced in the following description are intended to facilitate the description and understanding of the embodiments of this disclosure. To facilitate understanding, the shapes, dimensions, and proportions shown in the figures may differ from the actual figures. Furthermore, the components and elements of the elements or devices shown in the figures may be modified as appropriate based on the following description and known techniques.

Furthermore, the following description uses the example of applying the embodiments of the present disclosure to a back-illuminated light-receiving device. Therefore, in this light-receiving device, light is incident from the back side of the substrate. Therefore, in the following description, the front side of the substrate refers to the side opposite the back side, assuming the side from which light is incident is the back side.

In the following descriptions, references to specific lengths or shapes do not necessarily refer to mathematically defined values or geometrically defined shapes. Specifically, the following descriptions of specific lengths or shapes also include shapes with a permissible degree of variation (error/deformation) in the components, their manufacturing steps, and their use/operation, as well as shapes similar to these shapes. For example, in the following descriptions, the term "circular" or "substantially circular" is not limited to a true circle and also includes shapes similar to a true circle, such as an ellipse.

Furthermore, in the following description of circuits (electrical connections), unless otherwise specified, "electrically connected" means connecting multiple elements in a manner that allows electrical (signal) conduction. Furthermore, "electrically connected" in the following description includes not only direct electrical connection of multiple elements, but also indirect electrical connection via other elements.

In the following description, the term "shared" means, unless otherwise specified, that other elements are shared by multiple elements of a particular type. In other words, it means that other elements are shared by a specific number of elements of a particular type.

Furthermore, the explanation is carried out in the following order.

1. Example of the configuration of the ranging module 1 according to the embodiment of the present disclosure

2. Example of the structure of the light receiving unit 30 in the embodiment of the present disclosure

3. Equivalent circuit of the light-receiving element 10 of the embodiment of the present disclosure

4. Principle of the distance calculation method using the ranging module 1 of the embodiment of this disclosure

5. Background of the Implementation of this Creation

6. First Implementation Form

7. Second Implementation Form

8. Third Implementation Form

9. Fourth Implementation Form

10. Summary

11. Examples of electronic equipment structures

12. Application of endoscopic surgery system

13. Applications for mobile objects

14. Supplement

<<1. Example of the configuration of the ranging module 1 according to the embodiment of the present disclosure>>

First, referring to Figure 1 , the schematic configuration of a ranging module 1 according to an embodiment of the present disclosure will be described. Figure 1 is a block diagram showing an example configuration of the ranging module 1 according to an embodiment of the present disclosure. Specifically, as shown in Figure 1 , the ranging module 1 may primarily include an irradiation unit 20, a light receiving unit 30, a control unit (irradiation control unit) 40, and a processing unit 60. The following describes the functional blocks of the ranging module 1 according to this embodiment.

(Irradiation part 20)

The irradiation unit 20 includes an LED (Light Emitting Diode) light source (not shown) and an optical element (not shown). The wavelength of the irradiated light can be varied by appropriately selecting the LED light source. Furthermore, in this embodiment, the irradiation unit 20 is described as irradiating infrared light in the wavelength range of 780nm to 1000nm, for example. However, this embodiment is not limited to irradiating such infrared light. Furthermore, the irradiation unit 20 can irradiate the object 800 with irradiation light whose brightness periodically varies in synchronization with a periodic signal, such as a rectangular signal, supplied from the control unit 40 (described later).

(Light receiving unit 30)

The light receiving unit 30 receives the reflected light from the object 800. The light receiving unit 30 includes a light collecting lens (not shown) and a plurality of light receiving elements 10 described later. The light collecting lens has the function of collecting the received light to each light receiving element 10. In addition, the light receiving element 10 generates electric charge (e.g., electrons) based on the intensity of the received light, and drives the built-in transistor (distribution transistor VG, see FIG3 ) in synchronization with a periodic signal such as a rectangular signal supplied from the control unit 40 described later, thereby transmitting the generated electric charge to the charge storage unit MEM (see FIG3 ). The electric charge transmitted to the charge storage unit MEM is then converted into a signal and ultimately transmitted to the processing unit 60. Furthermore, the details of the light-receiving element 10 will be described later.

(Control Unit 40)

The control unit 40 supplies periodic signals to the irradiating unit 20 and the light receiving unit 30, controlling the timing of the irradiated light and the driving timing of the transistors. The frequency of this signal can be, for example, 5 to 20 MHz, but this embodiment is not limited to this frequency. Furthermore, the control unit 40 controls the transistors (distribution transistors VG, see Figure 3) to operate at different timings, such as differential operation.

(Processing Unit 60)

The processing unit 60 can obtain the signal from the light receiving unit 30 and, based on the obtained signal, determine the distance to the object 800 using, for example, an indirect ToF (iToF) method. The method for calculating the distance will be described later.

<<2. Example of the configuration of the light receiving portion 30 in the embodiment of the present disclosure>>

Next, referring to Figures 2A to 2C , an example planar configuration of the light-receiving unit 30 of an embodiment of the present disclosure will be described. Figures 2A to 2C are explanatory diagrams showing an example planar configuration of the light-receiving unit 30 of an embodiment of the present disclosure. Specifically, as shown in Figure 2A , the light-receiving unit 30 of this embodiment includes a pixel array unit 12, a vertical driver circuit unit 32, a row signal processing circuit unit 34, a horizontal driver circuit unit 36, an output circuit unit 38, and a control circuit unit 44, disposed on a semiconductor substrate 200, for example, made of silicon. The following describes the details of each block of the light-receiving unit 30 of this embodiment.

(Pixel array unit 12)

The pixel array section 12 has a plurality of light-receiving elements 10 arranged two-dimensionally in a matrix (row and column) on a semiconductor substrate 200. Each light-receiving element 10 has a photoelectric conversion section (photodiode PD) (not shown) that converts light into electric charge (e.g., electrons), and a plurality of pixel transistors (e.g., MOS (Metal-Oxide-Semiconductor) transistors) (not shown). In other words, the pixel array section 12 has a plurality of pixels that photoelectrically convert incident light and output signals corresponding to the resulting electric charge. The pixel transistors may include, for example, transistors having various functions, such as transmission transistors, selection transistors, reset transistors, and amplifier transistors. Furthermore, details regarding the equivalent circuit of the light-receiving element 10 will be described later.

Here, the column direction refers to the horizontal arrangement of the light-receiving elements 10, and the row direction refers to the vertical arrangement of the light-receiving elements 10. In Figure 2A, the column direction is the left-right direction, while the row direction is the up-down direction. In the pixel array section 12, pixel drive wiring 42 is wired along the column direction for each column of the light-receiving elements 10, and vertical signal lines 48 are wired along the row direction for each row. For example, the pixel drive wiring 42 transmits a drive signal for reading signals from the light-receiving elements 10.

(Vertical drive circuit section 32)

The vertical drive circuit 32, comprised of, for example, a shift register and an address decoder, selects a pixel drive line 42 and supplies a pulse for driving the light-receiving element 10 to the selected pixel drive line 42, thereby driving all light-receiving elements 10 simultaneously or row by row. For example, the vertical drive circuit 32 sequentially selects and scans each light-receiving element 10 in the pixel array 12 in the vertical direction (up and down in FIG. 2A ) by row, and supplies a pixel signal based on the charge generated by the photodiode PD of each light-receiving element 10 in accordance with the amount of light received, via a vertical signal line 48 to the row signal processing circuit 34 (described later).

(Line signal processing circuit section 34)

The row signal processing circuit 34 is configured for each row of light-receiving elements 10 and performs signal processing, such as noise reduction, on the signals output from a row of light-receiving elements 10 for each row. For example, the row signal processing circuit 34 performs signal processing, such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion, to remove fixed-pattern noise inherent to the light-receiving elements 10.

(Horizontal drive circuit section 36)

The horizontal drive circuit 36 is formed, for example, by a shift register and an address decoder. It sequentially selects each of the aforementioned row signal processing circuits 34 by sequentially outputting horizontal scan pulses, and then outputs the signals from each signal processing circuit 34 to the horizontal signal line 46.

(Output circuit section 38)

The output circuit 38 processes and outputs the signals sequentially supplied from the row signal processing circuit 34 via the horizontal signal lines 46. For example, the output circuit 38 can function as a buffering unit, or it can also perform row offset correction and various digital signal processing operations. Buffering refers to temporarily storing signals to compensate for differences in processing speed or transmission speed during signal exchange.

(Control circuit unit 44)

The control circuit 44 receives input clock signals and data indicating operating modes, and outputs data such as internal information of the light-receiving element 10. Specifically, based on the vertical synchronization signal, horizontal synchronization signal, and main clock signal, the control circuit 44 generates a clock signal or control signal that serves as a reference for the operation of the vertical drive circuit 32, the row signal processing circuit 34, and the horizontal drive circuit 36. The control circuit 44 then outputs the generated clock signal or control signal to the vertical drive circuit 32, the row signal processing circuit 34, and the horizontal drive circuit 36.

(Distribution transistor driver 50, signal processing unit 52, data storage unit 54)

As shown in Figures 2B and 2C , the light receiving element 10 can be provided with a distribution transistor driver 50, a signal processing unit 52, and a data storage unit 54. Specifically, the distribution transistor driver 50, the signal processing unit 52, and the data storage unit 54 can be provided on the semiconductor substrate 200. However, this embodiment is not limited to this configuration; the distribution transistor driver 50, the signal processing unit 52, and the data storage unit 54 can also be provided on a separate semiconductor substrate (not shown). First, the distribution transistor driver 50 controls the operation of the distribution transistor VG (see Figure 3 ), which will be described later. For example, the distribution transistor driver section 50 can be disposed adjacent to the pixel array section 12 along the row direction, as shown in FIG2B , or along the column direction, as shown in FIG2C . This is not particularly limited in this embodiment. Furthermore, the signal processing section 52 has at least a computational processing function and performs various signal processing operations, including computational processing, based on the signal output from the output circuit section 38. The data storage section 54 temporarily stores data required for signal processing while the signal processing section 52 is processing the signal.

Furthermore, the planar configuration of the light receiving portion 30 of this embodiment is not limited to the examples shown in Figures 2A to 2C and may include other circuits, etc., without particular limitation.

<<3. Equivalent circuit of the light-receiving element 10 according to the embodiment of the present disclosure>>

Next, referring to FIG3 , the equivalent circuit of the light-receiving element 10 according to an embodiment of the present disclosure will be described. FIG3 is an equivalent circuit diagram of the light-receiving element 10 according to an embodiment of the present disclosure.

Specifically, as shown in Figure 3, the light-receiving element 10 includes a photodiode PD, which serves as a photoelectric conversion element (photoelectric conversion unit) that converts light into charge, and a charge-discharging transistor OFG. (Although the charge-discharging transistor OFG is shown as a single transistor in the equivalent circuit, it may also include multiple transistors electrically connected in parallel.) Furthermore, the light-receiving element 10 includes two distribution transistors VG, a charge storage unit (a first charge storage unit and a second charge storage unit) MEM, a transfer transistor TG, a floating diffusion region FD, a reset transistor RST, an amplifier transistor AMP, and a select transistor SEL.

As shown in Figure 3, in the light-receiving element 10, one of the source and drain electrodes of the charge-discharging transistor OFG is electrically connected to the photodiode PD, which generates charge by receiving light. Furthermore, the other of the source and drain electrodes of the charge-discharging transistor OFG is electrically connected to the power supply circuit (power supply potential VDD). Furthermore, the charge-discharging transistor OFG is turned on in response to the voltage applied to its gate, discharging the charge accumulated in the photodiode PD to the power supply circuit (power supply potential VDD).

As shown in Figure 3, in the light-receiving element 10, one of the source/drain electrodes of distribution transistors VG1 and VG2 is electrically connected to the photodiode PD, while the other of the source/drain electrodes of distribution transistors VG1 and VG2 is electrically connected to the charge storage units MEM1 and MEM2, respectively. Furthermore, distribution transistors VG1 and VG2 can be turned on in response to the voltage applied to their gates (the first distribution gate and the second distribution gate), thereby transferring the charge stored in the photodiode PD to the charge storage units MEM1 and MEM2, respectively. That is, in this embodiment, by varying the voltages applied to the gates of distribution transistors VG1 and VG2 at different timings, the charge stored in the photodiode PD can be distributed to either of the two charge storage units MEM1 and MEM2. In other words, the two charge storage units MEM1 and MEM2 share a single photodiode PD.

As shown in Figure 3, in the light-receiving element 10, one of the source/drain electrodes of the transfer transistors TG1 and TG2 is electrically connected to the other of the source/drain electrodes of the distribution transistors VG1 and VG2 and the charge storage portions MEM1 and MEM2. Furthermore, the other of the source/drain electrodes of the transfer transistors TG1 and TG2 is electrically connected to the floating diffusion regions FD1 and FD2. Furthermore, the transfer transistors TG1 and TG2 can be turned on in response to a voltage applied to their gates (transfer gates), thereby transferring the charge stored in the charge storage portions MEM1 and MEM2 to the floating diffusion regions FD1 and FD2. Furthermore, in the embodiment of the present disclosure, since there are two charge storage portions MEM1 and MEM2, the transfer transistors TG1 and TG2 can share a single floating diffusion region FD.

Furthermore, floating diffusion regions FD1 and FD2 are electrically connected to the gates of amplifier transistors AMP1 and AMP2, which convert charge into voltage and output it as a signal. Furthermore, one of the source/drain electrodes of amplifier transistors AMP1 and AMP2 is electrically connected to one of the source/drain electrodes of select transistors SEL1 and SEL2, which output the converted signal to signal lines VSL1 and VSL2 in response to a select signal. Furthermore, the other of the source/drain electrodes of amplifier transistors AMP1 and AMP2 is electrically connected to a power supply circuit (power potential VDD).

The other of the source/drain electrodes of the select transistors SEL1 and SEL2 is electrically connected to the signal lines VSL1 and VSL2, which transmit the converted voltage as a signal, and is further electrically connected to the row signal processing circuit 34. Furthermore, the gates of the select transistors SEL1 and SEL2 are electrically connected to a select line (not shown) that selects the column for signal output. Furthermore, they are further electrically connected to the vertical drive circuit 32. Specifically, the charge accumulated in the floating diffusion regions FD1 and FD2 is controlled by the select transistors SEL1 and SEL2, converted into a voltage by the amplifier transistors AMP1 and AMP2, and output to the signal lines VSL1 and VSL2.

As shown in Figure 3, the floating diffusion regions FD1 and FD2 are electrically connected to one of the drain/source electrodes of reset transistors RST1 and RST2, which are used to reset the accumulated charge. The gate electrodes of the reset transistors RST1 and RST2 are electrically connected to a reset signal line (not shown), which in turn is electrically connected to the vertical drive circuit portion 32. Furthermore, the other of the drain/source electrodes of the reset transistors RST1 and RST2 is electrically connected to the power supply circuit (power supply potential VDD). Furthermore, the reset transistors RST1 and RST2 can be turned on in response to the voltage applied to their gate electrodes, thereby resetting the charge accumulated in the floating diffusion regions FD1 and FD2 (discharging it to the power supply circuit (power supply potential VDD)).

Furthermore, the equivalent circuit of the light-receiving element 10 of this embodiment is not limited to the example shown in FIG3 , and may include other components, etc., and is not particularly limited.

Here, the operation of the light-receiving element 10 is briefly described.

First, before light reception begins, the charge discharge operation is performed to discharge the photodiode PD. Specifically, the charge discharge transistors OFG1 and OFG2 are turned on, discharging the charge from the photodiode PD to the power supply circuit (power supply potential VDD).

Next, light reception begins, and distribution transistors VG1 and VG2 are controlled with different timings (e.g., differential operation). Specifically, during the first period, distribution transistor VG1 turns on, transferring the charge from photodiode PD to charge storage unit MEM1. Meanwhile, during the second period, distribution transistor VG2 turns on, transferring the charge from photodiode PD to charge storage unit MEM2. In other words, the charge generated in photodiode PD is distributed between charge storage units MEM1 and MEM2 via distribution transistors VG1 and VG2.

Next, the charge discharge operation is performed to discharge the floating diffusion regions FD1 and FD2. Specifically, reset transistors RST1 and RST2 are turned on, discharging the charge in the floating diffusion regions FD1 and FD2 to the power supply circuit (power supply voltage VDD). Subsequently, the charge (KTC noise) generated in the floating diffusion regions FD1 and FD2 is preferably removed by CDS driving.

Then, transfer transistors TG1 and TG2 are turned on, transferring the charge accumulated in charge storage units MEM1 and MEM2 to floating diffusion regions FD1 and FD2. Then, when the light-receiving period ends, each light-receiving element 10 in the pixel array 12 is sequentially selected. In the selected light-receiving element 10, select transistors SEL1 and SEL2 are turned on. This causes the charge accumulated in floating diffusion regions FD1 and FD2 to be output as a signal to signal lines VSL1 and VSL2.

Furthermore, the operation of the light-receiving element 10 in this embodiment is not limited to the example described above; for example, the order of operations may be modified as appropriate. Furthermore, in this embodiment, the distance to the object 800 is determined based on the distribution ratio of the charges accumulated in the two floating diffusion regions FD1 and FD2. The principle behind this is briefly explained below.

<<4. Principle of the distance calculation method using the ranging module 1 of the embodiment of the present disclosure>>

Next, the principle of the distance calculation method (indirect method) using the ranging module 1 of the embodiment of the present disclosure will be described with reference to FIG4 . FIG4 is an explanatory diagram used to illustrate the principle of the distance calculation method using the ranging module 1 of the embodiment of the present disclosure. Specifically, it schematically shows the temporal variation in the intensity of the irradiated light and the reflected light in the ranging module 1.

As shown in Figure 4, ranging module 1 directs light, whose intensity is modulated in a periodic manner, from illuminating unit 20 toward object 800. The illuminating light is reflected by object 800 and detected as reflected light by light receiving unit 30 of ranging module 1. As shown in Figure 4, the detected reflected light (the second section from the top of Figure 4) has a phase difference Φ with respect to the illuminating light (the first section from the top of Figure 4). This phase difference Φ increases as the distance from ranging module 1 to object 800 increases and decreases as the distance from ranging module 1 to object 800 decreases.

As previously described, the light-receiving element 10 of this embodiment includes, for example, differentially energized distribution transistors VG1 and VG2. Therefore, since the operating periods of distribution transistors VG1 and VG2 do not overlap, the charge accumulated in the photodiode PD during the grayed-out regions 802a and 802b in Figure 4 is distributed to the charge storage portions MEM1 and MEM2, respectively. Specifically, the charge distributed to the charge storage portions MEM1 and MEM2 is transferred to the floating diffusion regions FD1 and FD2, ultimately converting them into signals corresponding to the area of the integrated value during the periods in regions 802a and 802b. As can be clearly seen from Figure 4 , the difference between the integrated value of region 802a and the integrated value of region 802b changes according to the phase difference Φ of the reflected light. Therefore, in this embodiment, the distance to object 800 can be calculated by calculating the phase difference Φ based on the difference between the integrated value of region 802a and the integrated value of region 802b. Furthermore, in this embodiment, the distance can also be calculated by calculating the phase difference Φ using the ratio of the integrated values rather than the difference between the integrated values.

<<5. Background of the Implementation of this Creation>>

The above describes the distance measurement module 1, light receiving unit 30, light receiving element 10, and the principles of the distance calculation method of the embodiment of the present disclosure. Before further describing the details of this embodiment, the background of the inventors' creation of this embodiment will be briefly described.

As previously explained, the light receiving unit 30 of the ranging module 1 repeatedly receives light multiple times at short intervals, increasing the signal intensity and improving the S/N ratio, thereby enabling highly accurate ranging. For example, the light receiving unit 30 is required to receive light at a frequency of, for example, several hundred MHz or higher and distribute the generated charge. Therefore, the distribution transistors VG1 and VG2 of the light receiving element 10 of the light receiving unit 30 are required to transfer (distribute) the charge generated in the photodiode PD to the charge storage units MEM1 and MEM2 at high speed while consuming low power.

In response to the aforementioned needs, the present inventors have developed the presently disclosed embodiment. Specifically, in the disclosed embodiment, the gate of the distribution transistor VG comprises a pair of buried gate portions embedded within the semiconductor substrate 200. Because these buried gate portions are embedded within the semiconductor substrate 200, they effectively modulate the potential surrounding the buried gate portions. Consequently, the buried gate portions allow charge generated in the photodiode PD, located deeper within the semiconductor substrate 200, to be transferred to the charge storage portion MEM. Furthermore, in the embodiment of the present disclosure created by the present inventors, the gate of the distribution transistor VG includes two buried gate portions. Therefore, according to this embodiment, the two buried gate portions enable more efficient modulation of the surrounding potential while maintaining low power consumption, resulting in faster charge transfer to the charge storage portion MEM. Furthermore, while the buried gate portions increase parasitic capacitance and thus power consumption, low power consumption can be achieved by optimizing the design and achieving an overall balance. The following describes the embodiments of the present disclosure created by the present inventors in detail.

<<6. First Implementation Form>>

<6.1 Plane Structure>

First, referring to Figure 5 , an example planar structure of the light-receiving element 10 according to the first embodiment of the present disclosure will be described. Figure 5 is an illustrative diagram showing an example planar structure of the light-receiving element 10 according to this embodiment, and is a diagram showing the light-receiving element 10 as viewed from above the front surface of the semiconductor substrate 200. Furthermore, the left-right direction in Figure 5 corresponds to the row direction (left-right direction) in Figure 2A , and the top-bottom direction in Figure 5 corresponds to the row direction (top-bottom direction) in Figure 2A .

As shown in Figure 5, an N-type semiconductor region 100 is formed within a P-type semiconductor substrate 200 in the center of the photodetector 10. This N-type semiconductor region 100 constitutes a portion of the photodiode (photoelectric conversion unit) PD. Furthermore, the gate electrodes (first distributed gate and second distributed gate) 150a and 150b of the distribution transistors VG1 and VG2 are arranged to be linearly symmetrical (substantially linearly symmetrical) with respect to a center line 600 extending vertically (row-wise) through the center point (center) O of the photodiode PD. Furthermore, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 are arranged to overlap at least a portion of the N-type semiconductor region 100.

Specifically, distribution transistor VG1 includes a gate electrode 150a, a gate insulating film (not shown) between gate electrode 150a and semiconductor substrate 200, an N-type semiconductor region 100 serving as a source region, and an N-type semiconductor region 102a serving as a drain region. The N-type semiconductor region 100 serving as the source region also serves as the photodiode PD, while the N-type semiconductor region 102a serving as the drain region also serves as the charge storage unit MEM1. Furthermore, as shown by the dashed lines in FIG5 , gate electrode 150a includes a pair of buried gate portions 170a and 170b (see FIG6 ) embedded in semiconductor substrate 200. The details of buried gate portions 170a and 170b will be described later. The same configuration applies to distribution transistor VG2 as to distribution transistor VG1.

Furthermore, as shown in Figure 5 , the gate electrodes 152a and 152b of the charge-discharging transistors OFG1 and OFG2 are arranged to be linearly symmetrical (substantially linearly symmetrical) with respect to a center line 602 extending in the horizontal direction (row direction) through the center point O of the photodiode PD in the light-receiving element 10. Furthermore, the gate electrodes 152a and 152b of the charge-discharging transistors OFG1 and OFG2 are arranged to overlap with at least a portion of the N-type semiconductor region 100.

Specifically, the charge-discharging transistor OFG1 includes a gate electrode 152a, a gate insulating film (not shown) between the gate electrode 152a and the semiconductor substrate 200, an N-type semiconductor region 100 serving as a source region, and an N-type semiconductor region 104a serving as a drain region. The N-type semiconductor region 100 serving as the source region also serves as a photodiode PD. Furthermore, as indicated by the dashed lines in FIG5 , the gate electrode 152a includes a pair of buried gate portions embedded in the semiconductor substrate 200. The details of these buried gate portions will be described later. Furthermore, the charge discharge transistor OFG2 is the same as the charge discharge transistor OFG1.

Furthermore, charge storage units MEM1 and MEM2, and transfer transistors TG1 and TG2 are arranged in a line-symmetrical manner with respect to center line 600, sandwiching N-type semiconductor region 102 and distribution transistors VG1 and VG2 on both sides. Furthermore, charge storage unit MEM1 and transfer transistor TG1 are arranged adjacent to each other in the vertical direction (row direction) in FIG5 , while charge storage unit MEM2 and transfer transistor TG2 are arranged adjacent to each other in the vertical direction (row direction) in FIG5 .

Specifically, the charge storage unit (first charge storage unit) MEM1 includes, for example, an electrode 154a, an insulating film (not shown) disposed below electrode 154a, and an N-type semiconductor region 102a disposed below the insulating film. Furthermore, the transfer transistor TG1 includes a gate electrode 156a, a gate insulating film (not shown) between the gate electrode 156a and the semiconductor substrate 200, an N-type semiconductor region 106a serving as a source region, and an N-type semiconductor region 108a serving as a drain region. Furthermore, the charge storage unit (second charge storage unit) MEM2 and the transfer transistor TG2 are the same as the charge storage unit MEM1 and the transfer transistor TG1.

Furthermore, reset transistors RST1 and RST2, amplifying transistors AMP1 and AMP2, and select transistors SEL1 and SEL2 are arranged in a line-symmetrical manner with respect to center line 602, sandwiching N-type semiconductor region 102 and charge discharge transistors OFG1 and OFG2 on both sides. Furthermore, reset transistor RST1, amplifying transistor AMP1, and select transistor SEL1 are arranged adjacent to each other in the horizontal direction (row direction) in FIG5 . Reset transistor RST2, amplifying transistor AMP2, and select transistor SEL2 are also arranged adjacent to each other in the horizontal direction (row direction) in FIG5 .

Specifically, reset transistor RST1 includes a gate electrode 158a, a gate insulating film (not shown) between gate electrode 158a and semiconductor substrate 200, an N-type semiconductor region 110a serving as a source region, and an N-type semiconductor region 112a serving as a drain region. The N-type semiconductor region 110a serving as the source region also serves as the floating diffusion region FD1, while the N-type semiconductor region 112a serving as the drain region also serves as the amplifier transistor AMP1. The configuration of reset transistor RST2 is similar to that of reset transistor RST1.

Furthermore, the amplifier transistor AMP1 includes a gate electrode 160a, a gate insulating film (not shown) between the gate electrode 160a and the semiconductor substrate 200, an N-type semiconductor region 112a serving as a drain region, and an N-type semiconductor region 114a serving as a source region. The N-type semiconductor region 112a serving as the drain region also serves as the drain region of the reset transistor RST1. The amplifier transistor AMP2 is similar to the amplifier transistor AMP1.

Furthermore, select transistor SEL1 includes a gate electrode 162a, a gate insulating film (not shown) between gate electrode 162a and semiconductor substrate 200, an N-type semiconductor region 114a serving as a drain region, and an N-type semiconductor region 116a serving as a source region. The N-type semiconductor region 114a serving as the drain region also serves as the source region of amplifier transistor AMP1. Select transistor SEL2 is similar to select transistor SEL1.

Furthermore, the planar structure of the light-receiving element 10 of this embodiment is not limited to the example shown in FIG. 5 , and may include other elements, etc., and is not particularly limited.

<6.2 Sectional Structure>

Next, referring to Figures 6 to 9, an example of the cross-sectional structure of the light-receiving element 10 according to the first embodiment of the present disclosure will be described. Figure 6 is a cross-sectional view of the light-receiving element 10 taken along line A-A' in Figure 5. Specifically, the upper side in Figure 6 corresponds to the back side of the semiconductor substrate 200, and the lower side in Figure 6 corresponds to the front side of the semiconductor substrate 200. Figure 7 is a cross-sectional view of the light-receiving element 10 taken along line B-B' in Figure 5. The upper side in Figure 7 corresponds to the front side of the semiconductor substrate 200, and the lower side in Figure 7 corresponds to the back side of the semiconductor substrate 200. Furthermore, Figure 8 is an explanatory diagram for explaining this embodiment. FIG9 is an enlarged view of area D in FIG6 . The upper side in FIG9 becomes the front side of the semiconductor substrate 200 , and the lower side in FIG9 becomes the back side of the semiconductor substrate 200 .

First, as shown in Figure 6, the light-receiving element 10 includes a semiconductor substrate 200, such as a silicon substrate. Specifically, N-type semiconductor regions 100a and 100b are formed within the P-type semiconductor substrate 200, thereby forming a photodiode PD within the semiconductor substrate 200.

Next, the description will proceed from the upper side in Figure 6 , i.e., the back side of semiconductor substrate 200. A wafer-mounted lens 208 made of, for example, a styrene-based resin, an acrylic resin, a styrene-acrylic copolymer resin, or a silicone-based resin is disposed above the back side of semiconductor substrate 200, upon which reflected light from object 800 is incident. Below wafer-mounted lens 208, a planarization film 204 made of, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), or silicon oxynitride (SiON) is disposed. Furthermore, an anti-reflection film 202, comprising an insulating film, is disposed below planarization film 204. For example, the anti-reflection film 202 may be formed of helium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), silicon oxide, or a laminate thereof.

A light-shielding film 206 is provided above the anti-reflection film 202, in the boundary region with the adjacent light-receiving element 10, to prevent reflected light from the object 800 from entering the adjacent light-receiving element 10. The light-shielding film 206 is made of a material that blocks light, such as tungsten (W), aluminum (Al), or copper (Cu).

Furthermore, below the light-shielding film 206, a pixel isolation portion (first pixel isolation portion) 210 (FFTI) is provided. This portion penetrates the semiconductor substrate 200 to prevent incident light from entering the adjacent light-receiving element 10. The pixel isolation portion 210 may include, for example, a trench extending from the back surface to the front surface of the semiconductor substrate 200, and an insulating film such as silicon oxide or a metal film such as aluminum filling the trench.

Next, the lower side in Figure 6 , or the front side of semiconductor substrate 200, is described. Two distributed transistors VG1 and VG2, serving as vertical transistors, are formed with N-type semiconductor region 100b interposed therebetween. Specifically, distributed transistors VG1 and VG2 each have gate electrodes 150a and 150b, respectively, disposed on the front side of semiconductor substrate 200, for example, made of a polysilicon film. Furthermore, gate electrodes 150a and 150b each have buried gate portions 170a and 170b, respectively, made of a polysilicon film, extending into semiconductor substrate 200 and along the thickness of semiconductor substrate 200. In other words, the buried gate portions 170a and 170b can be said to be buried within the semiconductor substrate 200 and connected to the semiconductor substrate 200 via a gate insulating film (not shown). For example, the buried gate portions 170a and 170b of the distribution transistors VG1 and VG2 are formed by dry etching trenches from the front side of the semiconductor substrate 200, forming a gate insulating film, and then burying a polysilicon film or the like in the trenches. The details of the buried gate portions 170a and 170b of this embodiment will be described later.

Furthermore, the N-type semiconductor region 100b sandwiched between the buried gate portions 170a and 170b preferably has a higher impurity concentration than the N-type semiconductor region 100a constituting the photodiode PD. Furthermore, the impurity concentration of the N-type semiconductor region 100b preferably increases as it approaches the front side of the semiconductor substrate 200.

Furthermore, charge storage units MEM1 and MEM2 are provided within the semiconductor substrate 200, sandwiching the distribution transistors VG1 and VG2 from the left and right sides. For example, the charge storage units MEM1 and MEM2 can be MOS (Metal-Oxide-Semiconductor) capacitors formed by laminating electrodes 154a and 154b comprising a metal film or polysilicon film, an insulating film comprising an oxide film (not shown), and N-type semiconductor regions 102a and 102b (shown as MEM1 and MEM2 in FIG. 6 ).

Furthermore, the gate electrodes 156a and 156b of the transfer transistors TG1 and TG2 are adjacent to the charge storage units MEM1 and MEM2 on the front surface of the semiconductor substrate 200. Furthermore, N-type semiconductor regions 110a and 110b, shown as floating diffusion regions FD1 and FD2, are formed within the semiconductor substrate 200 near the gate electrodes 156a and 156b of the transfer transistors TG1 and TG2.

Furthermore, a wiring layer 300 is provided on the front surface of the semiconductor substrate 200. The wiring layer 300 includes an insulating film 302 and a metal film 304. Furthermore, an electrode 306 is provided on the surface of the wiring layer 300 opposite to the semiconductor substrate 200.

Furthermore, a substrate 400 is provided on the surface of the wiring layer 300 opposite the semiconductor substrate 200. The substrate 400 also includes an insulating film 402 and a metal film 404. Electrodes 406 are provided on the surface of the wiring layer 300. For example, the electrodes 306 of the wiring layer 300 and the electrodes 406 of the substrate 400 can be formed of copper (Cu) or the like and brought into contact with each other, thereby bonding the wiring layer 300 to the substrate 400.

Furthermore, the cross-sectional structure of the light-receiving element 10 of this embodiment is not limited to the example shown in FIG6 . For example, it may also include other elements and is not particularly limited.

Next, referring to FIG7 , the buried gate portions 170a and 170b of this embodiment will be described in detail. As previously described, FIG7 is a cross-sectional view of the light-receiving element 10 taken along line BB' in FIG5 . Specifically, it is a cross-sectional view of the gate electrode 150b and buried gate portions 170b-1 and 170b-2 of the distribution transistor VG2 (note that the gate insulating film is not shown in FIG7 ). As shown in Figure 7 , in this embodiment, the gate electrode 150b of the distribution transistor VG2 includes a pair of buried gate portions 170b-1 and 170b-2 arranged along the vertical direction in Figure 5 , i.e., the row direction in Figure 2A . Furthermore, as indicated by the dashed lines in Figure 5 , the buried gate portions 170b-1 and 170b-2 preferably have a substantially rectangular shape in a cross-section taken along the front surface of the semiconductor substrate 200 through the light-receiving element 10. This rectangle has a long side L extending from the center point O of the photodiode PD toward the charge storage portion MEM2 (see Figure 9 ). Similarly to the gate electrode 150b of the distribution transistor VG2, the gate electrode 150a of the distribution transistor VG1 includes a pair of buried gate portions 170 arranged in the vertical direction in FIG. 5 , i.e., the row direction in FIG. 2A . Furthermore, the buried gate portion 170 of the gate electrode 150a of the distribution transistor VG1 preferably has a substantially rectangular shape in a cross-section taken along the front surface of the semiconductor substrate 200, as indicated by the dashed line in FIG. 5 . The rectangle has a long side L extending from the center point O of the photodiode PD toward the charge storage portion MEM2 (see FIG. 9 ).

Specifically, in this embodiment, as shown in FIG8 , a voltage is applied to buried gate portions 170 b - 1 and 170 b - 2 via gate electrode 150 b , thereby modulating the P-type semiconductor region 700 surrounding buried gate portions 170 b - 1 and 170 b - 2. Furthermore, as shown in FIG9 , charges (electrons) generated in the photodiode PD located deeper within the semiconductor substrate 200 pass through the surrounding region 700 within the semiconductor substrate 200 modulated by the buried gate portion 170 b and are transferred to the charge storage portion MEM2. In this embodiment, the two buried gate portions 170b-1 and 170b-2 can more effectively modulate the potential of the surrounding area 700 while reducing power consumption, thereby transferring charge to the charge storage portion MEM2 at a higher speed.

Furthermore, in this embodiment, the buried gate portions 170b-1 and 170b-2 are formed into a generally rectangular shape, with a long side L extending from the center point O of the photodiode PD toward the charge storage portion MEM2 (see Figure 9). This arrangement allows the long side L to extend in the same direction as charge migration. Therefore, the buried gate portion 170b effectively modulates the area through which charge passes, directing the charge toward the charge storage portion MEM2 along this modulated area.

Furthermore, in this embodiment, as indicated by dashed lines in Figure 5 , the gate electrodes 152a and 152b of the charge-discharging transistors OFG1 and OFG2 also include a pair of buried gate portions 170 embedded in the semiconductor substrate 200 and connected to the semiconductor substrate 200 via a gate insulating film (not shown). With this arrangement, in this embodiment, the two buried gate portions 170 of the gate electrodes 152a and 152b of the charge-discharging transistors OFG1 and OFG2 can more efficiently modulate the surrounding potential with low power consumption, thereby enabling faster charge discharge.

Furthermore, the buried gate portion 170 of the gate electrodes 152a and 152b of the charge-discharging transistors OFG1 and OFG2 preferably has a generally rectangular shape in a cross-section taken along the front surface of the semiconductor substrate 200, as shown by the dashed lines in FIG5 . The rectangle has long sides extending from the center point O of the photodiode PD toward the N-type semiconductor regions 104a and 104b connected to the power circuit (power potential VDD). This arrangement allows for more efficient modulation of the area in which charge can be transferred, enabling faster charge discharge.

That is, according to this embodiment, a light-receiving element 10 capable of transferring charge at high speed can be provided.

<6.3 Variations>

The light-receiving element 10 of the first embodiment of the present disclosure can be modified as described below. Variations 1 through 7 of this embodiment are described below. Furthermore, in all of the light-receiving elements 10 described below, the gate electrode 150 of the distribution transistor VG includes a pair of buried gate portions 170.

(Variation 1)

First, variation 1 will be described with reference to FIG10 . FIG10 is an illustrative diagram showing a planar configuration example of the light-receiving element 10 of variation 1 of this embodiment. In this variation, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 also have a pair of buried gate portions 170. Furthermore, in this variation, as indicated by the dotted lines in FIG10 , each buried gate portion 170 has a generally elliptical shape in a cross-section taken along the front surface of the semiconductor substrate 200, with the ellipse having a major axis extending from the center point O of the photodiode PD toward the charge storage portions MEM1 and MEM2. In this variation, the buried gate portion 170 is formed into a substantially elliptical shape with a major axis extending from the center point O of the photodiode PD toward the charge storage portions MEM1 and MEM2. Similar to the first embodiment, charges can be directed toward the charge storage portions MEM1 and MEM2 at a higher speed.

Furthermore, in this variation, the gate electrodes 152 a and 152 b of the charge discharge transistors OFG1 and OFG2 may also include a pair of buried gate portions 170 buried in the semiconductor substrate 200 . Furthermore, in this variation, the buried gate portion 170 of the gate electrodes 152a and 152b of the charge discharge transistors OFG1 and OFG2 may have a generally elliptical shape in a cross-section taken along the front surface of the semiconductor substrate 200, as shown by the dashed lines in FIG. 10 . The ellipse has a major axis extending from the center point O of the photodiode PD toward the N-type semiconductor regions 104a and 104b connected to the power circuit (power potential VDD).

Furthermore, in this variation 1, the charge storage units MEM1 and MEM2 and the transfer transistors TG1 and TG2 are arranged in a mirror-symmetrical manner with respect to the center line 600, and sandwich the N-type semiconductor region 102 and the distribution transistors VG1 and VG2 on both sides. Furthermore, the charge storage unit MEM1 and the transfer transistor TG1 are arranged adjacent to each other in the vertical direction (row direction) in FIG. 10 , and the charge storage unit MEM2 and the transfer transistor TG2 are arranged adjacent to each other in the vertical direction (row direction) in FIG. 10 .

Furthermore, in this variation 1, reset transistors RST1 and RST2, amplifying transistors AMP1 and AMP2, and select transistors SEL1 and SEL2 are arranged in a mirror-symmetrical manner with respect to centerline 602, sandwiching N-type semiconductor region 102 and charge discharge transistors OFG1 and OFG2 on both sides. Furthermore, reset transistor RST1, amplifying transistor AMP1, and select transistor SEL1 are arranged adjacent to each other in the horizontal direction (row direction) in FIG. 10 . Reset transistor RST2, amplifying transistor AMP2, and select transistor SEL2 are also arranged adjacent to each other in the horizontal direction (row direction) in FIG. 10 .

(Variation 2)

Next, Variation 2 will be described with reference to FIG11 . FIG11 is an illustrative diagram showing a planar configuration example of the light-receiving element 10 according to Variation 2 of this embodiment. In this variation, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 also have a pair of buried gate portions 170. Furthermore, in this variation, each buried gate portion 170 has a generally circular shape in a cross-section taken along the front surface of the semiconductor substrate 200, as indicated by the dashed lines in FIG11 . In this variation, by forming the buried gate portion 170 into a substantially circular shape, shape variations during manufacturing can be avoided, thereby aligning the charge distribution performance of the two distribution transistors VG1 and VG2.

Furthermore, in this variation, the gate electrodes 152a and 152b of the charge discharge transistors OFG1 and OFG2 may also include a pair of buried gate portions 170 embedded in the semiconductor substrate 200. Furthermore, in this variation, the buried gate portions 170 of the gate electrodes 152a and 152b may also have a substantially circular shape in a cross-section taken along the front surface of the semiconductor substrate 200, as shown by the dashed lines in FIG. 11 .

(Variation 3)

Next, variation 3 will be described with reference to FIG12 . FIG12 is an explanatory diagram showing a cross-sectional configuration example of the light-receiving element 10 of variation 3 of the present embodiment. In this variation, the gate electrodes 150a, 150b of the distribution transistors VG1, VG2 also have a pair of buried gate portions 170a, 170b. Furthermore, in this variation, as shown in FIG12 , the light-receiving element 10 has a moth-eye structure 202a having fine concave and convex portions and disposed on the back surface (the surface opposite to the front surface) of the semiconductor substrate 200. Specifically, the moth-eye structure 202a is formed by arranging a plurality of approximately square pyramids having vertices on the side of the semiconductor substrate 200 in a matrix as shown in FIG12 . In this variation, the moth-eye structure 202a is provided to mitigate the drastic change in refractive index at the interface, thereby preventing reflection.

(Variation 4)

Next, Variation 4 will be described with reference to FIG13 . FIG13 illustrates a cross-sectional configuration example of light-receiving element 10 according to Variation 4 of this embodiment. In this variation, gate electrodes 150a and 150b of distribution transistors VG1 and VG2 also have a pair of buried gate portions 170a and 170b. Furthermore, in this variation, as shown in FIG13 , the light-receiving element 10 includes a pixel isolation portion (second pixel isolation portion) 210 a (DTI (Deep Trench Isolation)) extending along the thickness direction of the semiconductor substrate 200 from the back surface (the side opposite to the front surface) of the semiconductor substrate 200 to the middle of the semiconductor substrate 200. This pixel isolation portion 210 a prevents incident light from entering adjacent light-receiving elements 10.

(Variation 5)

Next, Variation 5 will be described with reference to FIG14 . FIG14 illustrates a cross-sectional configuration example of a light-receiving element 10 according to Variation 5 of this embodiment. In this variation, the gate electrodes 150a and 150b of the distribution transistors VG1 and VG2 also include a pair of buried gate portions 170a and 170b. Furthermore, this variation includes charge storage portions MEM1 and MEM2 having vertical electrodes 154a and 154b embedded in the N-type semiconductor regions 102a and 102b within the semiconductor substrate 200. According to this variation, since the charge storage units MEM1 and MEM2 have vertical electrodes, the area of the insulating film (not shown) sandwiched between these vertical electrodes and the N-type semiconductor regions 102a and 102b facing them can be increased. As a result, according to this variation, the increased area further increases the capacitance of the charge storage units MEM1 and MEM2, thereby ensuring a wide dynamic range for the light-receiving element 10.

(Variation 6)

Next, Variation 6 will be described with reference to FIG15 . FIG15 illustrates a cross-sectional configuration example of a portion of light-receiving element 10 according to Variation 6 of this embodiment, corresponding to the cross-sectional view of FIG7 . In this variation, gate electrode 150b of distribution transistor VG2 also includes a pair of buried gate portions 170b-1 and 170b-2. Furthermore, in this variation, as shown in FIG15 , each buried gate portion 170b-1 and 170b-2 has a tapered shape that gradually tapers in the thickness direction of semiconductor substrate 200 from the front surface toward the back surface opposite the front surface. In other words, in this variation, the distance (width) between the facing side surfaces of the pair of buried gate portions 170b-1 and 170b-2 gradually increases in the thickness direction of the semiconductor substrate 200 from the front surface toward the back surface opposite to the front surface.

In this variation, the distance between the facing sides of the pair of buried gate portions 170b-1 and 170b-2 is gradually increased from the front surface of the semiconductor substrate 200 along the thickness of the semiconductor substrate 200. This creates a favorable potential gradient across the thickness of the semiconductor substrate 200, facilitating the concentration of transferred charge near the front surface of the semiconductor substrate 200. Furthermore, in this variation, by concentrating and transferring charge near the front surface of the semiconductor substrate 200, stable charge distribution is achieved, thereby improving distance measurement accuracy.

For example, as shown in Figure 15 , each buried gate portion 170b-1, 170b-2 has a diameter L2 extending from the front surface of the semiconductor substrate 200 along the thickness direction of the semiconductor substrate 200, approximately three-quarters of the length (depth) of each buried gate portion 170b-1, 170b-2. Preferably, the diameter L2 is approximately three-quarters of the length (depth) of the buried gate portion 170b-1, 170b-2 at the front surface of the semiconductor substrate 200. This arrangement prevents the formation of voids within the buried gate portions 170b-1, 170b-2 during formation, thereby maintaining good embedding properties.

(Variation 7)

Next, Variation 7 will be described with reference to Figure 16 . Figure 16 illustrates a cross-sectional configuration example of a light-receiving element 10 according to Variation 7 of this embodiment. In this variation, as shown in Figure 16 , the light-receiving element 10 may include a plurality of, specifically, four, distribution transistors VG. In this variation, the gate electrode (third distribution gate) 150 of each distribution transistor VG also includes a pair of buried gate portions 170, which can distribute charge to the charge storage portion (third charge storage portion) MEM. Furthermore, in this variation, the gate electrode 152 of the charge discharge transistor OFG may also include a pair of buried gate portions buried in the semiconductor substrate 200.

<<7. Second Implementation Form>>

However, in the first embodiment of the present disclosure, the distribution transistor VG has a pair of buried gate portions 170 embedded in the semiconductor substrate 200, resulting in a relatively large parasitic capacitance. Furthermore, this large parasitic capacitance can sometimes slow the speed at which the distribution transistor VG transfers charge. Therefore, in the second embodiment of the present disclosure described below, to reduce the parasitic capacitance of the gate electrode 150 of the distribution transistor VG, a low-dielectric layer is provided in contact with portions of the buried gate portion 170 other than those responsible for charge transfer. This embodiment is described in detail below.

<7.1 Implementation>

First, referring to Figures 17 and 18 , the buried gate portion 170 of the distribution transistor VG of this embodiment will be described. Figure 17 is an explanatory diagram illustrating the light-receiving element 10 of this embodiment, corresponding to the cross-sectional view of Figure 7 . Figure 18 is an explanatory diagram showing an example planar configuration of the light-receiving element 10 of this embodiment. Specifically, it is shown on the front surface of the semiconductor substrate 200, with the gate electrode 150 and other components omitted for ease of illustration.

In this embodiment, as shown in Figures 17 and 18 , the side of one buried gate portion 170b-1, located opposite to the side of the other buried gate portion 170b-2, is in contact with low-dielectric layers 172b-1 and 172b-2. The low-dielectric layer 172b may comprise, for example, an oxide film (e.g., SiO ₂ ) or a nitride film (e.g., SiN). Thus, in this embodiment, by providing the low-dielectric layer 172 in contact with a portion of the buried gate portion 170 other than the portion that functions to transfer charge, an increase in parasitic capacitance of the gate electrode 150 can be suppressed. As a result, in this embodiment, it is possible to prevent the speed of charge transfer by the distribution transistor VG from being slowed down.

Furthermore, in this embodiment, as shown in FIG18 , the gate electrode 152 of the charge-discharging transistor OFG may also include a pair of buried gate portions 174 embedded in the semiconductor substrate 200. Furthermore, regarding the pair of buried gate portions 174a and 174b of the gate electrode 152 of the charge-discharging transistor OFG, the side surface of one buried gate portion 174b-1, which is located opposite to the side surface of the other buried gate portion 174b-2, may also be in contact with low-dielectric layers 176b-1 and 176b-2. The low-dielectric layer 176b may also include, for example, an oxide film or a nitride film. By setting it up in this way, the increase of the parasitic capacitance of the gate electrode 152 of the charge discharge transistor OFG is suppressed, thereby preventing the charge discharge speed of the charge discharge transistor OFG from being slowed down.

<7.2 Variations>

Furthermore, the light-receiving element 10 of the second embodiment of the present disclosure can be modified as described below. Modifications 1 and 2 of this embodiment are described below with reference to Figures 19 and 20 . Figure 19 illustrates a planar configuration example of the light-receiving element 10 of Modification 1 of this embodiment, while Figure 20 illustrates a planar configuration example of the light-receiving element 10 of Modification 2 of this embodiment. Similar to Figure 18 , Figures 19 and 20 depict the front surface of the semiconductor substrate 200, omitting the gate electrode 150 and other components for ease of illustration.

As shown in Figures 19 and 20 , in these variations, the side surface of one of the buried gate portions 170 is in contact with a low-dielectric layer 178 , which includes a device isolation portion for electrically isolating the components on the semiconductor substrate 200 . Furthermore, in these variations, as shown in Figures 19 and 20 , the side surface of one of the pair of buried gate portions 174 a and 174 b of the gate electrode 152 of the charge discharge transistor OFG is also in contact with the low-dielectric layer 178 , which includes a device isolation portion for electrically isolating the components on the semiconductor substrate 200 .

<7.3 Manufacturing Method>

Next, an example of a method for manufacturing the buried gate portion 170 and the low dielectric layer 178 of this embodiment will be described with reference to Figures 21A to 21F. Figures 21A to 21F are explanatory diagrams used to illustrate the method for manufacturing the light-receiving element 10 of this embodiment.

First, as shown in FIG21A , a thermally oxidized silicon layer 500 is formed on the front surface of the semiconductor substrate 200 by thermal oxidation. Furthermore, a silicon nitride layer 502 , a silicon oxide layer 504 , and a patterned resist 506 are formed on the thermally oxidized silicon layer 500 .

Next, dry etching is performed along the pattern of the resist 506 to peel off the silicon oxide layer 504, forming a trench 510 as shown in FIG21B.

Then, thermal oxidation is performed to form a thermally oxidized silicon layer 500 on the bottom and sides of trench 510. Furthermore, as shown in FIG21C , a silicon oxide film (low dielectric layer) 172 is buried within trench 510.

Then, as shown in FIG. 21D , a patterned resist 508 is formed.

Next, as shown in FIG21E , the silicon oxide film 172 is dry-etched along the pattern of the resist 508 to form a trench 512.

Then, polysilicon films (buried gates) 170 and 150 are buried in the trenches 512, and the etch resist 508 and silicon nitride layer 502 are stripped off, thereby obtaining the structure shown in FIG. 21F.

As described above, according to this embodiment, the low dielectric layer 178 is formed in contact with the side of one buried gate portion 170 that is opposite to the side facing the other buried gate portion 170, thereby reducing the parasitic capacitance of the gate electrode 150 of the distribution transistor VG.

<<8. Third Implementation Form>>

Furthermore, in the first and second embodiments and their variations, the insulating films (not shown) of the charge storage units MEM1 and MEM2 and the gate insulating films (not shown) of the amplifying transistors AMP1 and AMP2 can be made thinner. This approach increases the capacitance of the charge storage units MEM1 and MEM2 without increasing their size. Furthermore, random noise in the amplifying transistors AMP1 and AMP2 can be reduced by reducing crystal defects within the gate insulating films, increasing the mutual conductivity gm of the transistors and thereby reducing the impact of crystal defects, or reducing interface energy levels by shortening the heat treatment time or lowering the heat treatment temperature.

Here, referring to Figures 22, 23A, and 23B, a third embodiment of the present disclosure, comprising charge storage units MEM1 and MEM2 and amplifier transistors AMP1 and AMP2 having a thin-film insulating film, will be described. Figure 22 illustrates a planar configuration example of the light-receiving element 10 of this embodiment, viewed from above the front surface of the semiconductor substrate 200, similar to the light-receiving element 10 of the first embodiment. Figure 23A is a cross-sectional view of the light-receiving element 10 taken along line C-C' in Figure 22, and Figure 23B is a cross-sectional view of the light-receiving element 10 taken along line D-D' in Figure 22. Specifically, in Figures 23A and 23B , the upper side is the front side of the semiconductor substrate 200 , and the lower side is the back side of the semiconductor substrate 200 .

Specifically, in this embodiment, as shown in FIG. 23A , for example, the insulating film 720a located below the gate electrode 160 of the amplifier transistor AMP1 covered by the sidewall 730 comprises, for example, an oxide film (third oxide film). The film thickness is thinner than the insulating film 720 located below the gate electrode 158 of the reset transistor RST1 and the gate electrode 162 of the select transistor SEL1, comprising the oxide film (third oxide film).

Furthermore, in this embodiment, as shown in FIG. 23B , for example, the insulating film 720a located below the electrode 154 covered by the sidewall 730 of the charge storage unit MEM1 comprises, for example, an oxide film (first oxide film), and its thickness is thinner than the insulating film 720 located below the gate electrode 156 of the transfer transistor TG1, comprising an oxide film (second oxide film).

Furthermore, in this embodiment, the insulating film 720a located below the gate electrode 160 of the amplifier transistor AMP1 and the insulating film 720a located below the electrode 154 of the charge storage unit MEM1 can be oxide films made of the same material and can have substantially the same film thickness.

More specifically, in this embodiment, the insulating film 720a located below the gate electrode 160 of the amplifying transistor AMP1 and the insulating film 720a located below the electrode 154 of the charge storage unit MEM1 include an oxide film such as silicon oxide (SiO ₂ ) or silicon nitride (SiN). Furthermore, in this embodiment, in view of the effect of reducing random noise and the increase in power consumption due to the increase in leakage current achieved by thinning the film thickness of the insulating film 720a located below the gate electrode 160 of the amplifier transistor AMP1 and the insulating film 720a located below the electrode 154 of the charge storage portion MEM1, it is preferred that the film thickness of the insulating film 720 located below the gate electrodes 156, 158, and 162 of other elements (transmission transistor TG, reset transistor RST, and select transistor SEL) is approximately half of the film thickness, for example, not less than 1.0 nm and not more than 5.0 nm.

Furthermore, in this embodiment, the insulating film 720a located below the gate electrode 160 of the amplifier transistor AMP1 and the insulating film 720a located below the electrode 154 of the charge storage unit MEM1 are preferably wider than the gate electrode 160 and the electrode 154 when viewed from above the semiconductor substrate 200 to avoid interfering with adjacent devices.

Furthermore, in this embodiment, it is not limited to thinning only the insulating film 720a of the charge storage units MEM1 and MEM2 or the gate insulating film 720a of the amplifier transistors AMP1 and AMP2. In this embodiment, only the insulating film 720a of the charge storage units MEM1 and MEM2 can be thinned. Alternatively, the insulating film 720 in contact with the gate electrodes 150, 152, 154, 156, 158, 160, 162 and the electrode 154 of the components on the light-receiving element 10 (charge storage unit MEM, transfer transistor TG, distribution transistor VG, charge discharge transistor OFG, amplifier transistor AMP, reset transistor RST, and select transistor SEL) can be thinned.

As described above, according to this embodiment, by thinning the insulating film 720a of the charge storage unit MEM or the gate insulating film 720a of the amplifier transistor AMP, the capacitance of the charge storage unit MEM can be increased without increasing the size, and random noise of the transistor can be reduced. Therefore, in this embodiment, the structure of the first embodiment described above enables high-speed charge transfer. Furthermore, the structure of the third embodiment increases the capacitance of the charge storage unit MEM used to store the transferred charge, thereby achieving a ranging module 1 with higher ranging accuracy. In addition, the structure of the third embodiment reduces random noise of the transistor, thereby further improving the characteristics of the ranging module 1. Furthermore, this embodiment can be implemented by combining the first and second embodiments and their variations.

<<9. 4th Implementation Form>>

Furthermore, in the third embodiment described above, the insulating film 720a of the charge storage unit MEM or the gate insulating film 720a of the amplifier transistor AMP is thinned, thereby increasing the capacitance of the charge storage unit MEM and reducing random noise in the amplifier transistor AMP. However, while further thinning the gate insulating film 720a can achieve the aforementioned effects, it also increases leakage current, thus limiting the thinning process. Therefore, the inventors of the present invention have considered replacing the insulating film 720a with a high dielectric constant. While the high dielectric film has the same film thickness, it can increase the capacitance of the charge storage unit MEM compared to the oxide film described above. By using a high-dielectric film as the insulating film 720a, even with a reduced film thickness, an increase in leakage current can be avoided, while also achieving both an increase in the capacitance of the charge storage unit MEM and a reduction in random noise of the amplifier transistor AMP.

Here, referring to Figures 24, 25A, and 25B, a fourth embodiment of the present disclosure comprising charge storage units MEM1 and MEM2 and amplifier transistors AMP1 and AMP2, each comprising an insulating film comprising a high dielectric film, will be described. Figure 24 illustrates a planar configuration example of the light-receiving element 10 of this embodiment, viewed from above the front surface of the semiconductor substrate 200, similar to the light-receiving element 10 of the first embodiment. Figure 25A is a cross-sectional view of the light-receiving element 10 taken along line E-E' in Figure 24, and Figure 25B is a cross-sectional view of the light-receiving element 10 taken along line F-F' in Figure 24. Specifically, in Figures 25A and 25B , the upper side is the front side of the semiconductor substrate 200 , and the lower side is the back side of the semiconductor substrate 200 .

Specifically, in this embodiment, as shown in FIG. 25A , for example, the insulating film (third insulating film) 740 located below the gate electrode 160 of the amplifier transistor AMP1, which is covered by the sidewall 730, comprises a high-dielectric film. Furthermore, the relative dielectric constant of the insulating film 740 is higher than that of the insulating film (third insulating film) 720 located below the gate electrode 158 of the reset transistor RST1 and the gate electrode 162 of the select transistor SEL1.

Furthermore, in this embodiment, as shown in FIG. 25B , for example, the insulating film (first insulating film) 740 located below the electrode 154 covered by the sidewall 730 of the charge storage unit MEM1 comprises a high-dielectric film. The relative dielectric constant of the insulating film 740 is higher than that of the insulating film (second insulating layer) 720 located below the gate electrode 156 of the transfer transistor TG1.

Furthermore, in this embodiment, the insulating film 740 located below the gate electrode 160 of the amplifier transistor AMP1 and the insulating film 740 located below the electrode 154 of the charge storage unit MEM1 can be formed of the same material.

More specifically, in this embodiment, the high dielectric film is a material having a relative dielectric constant higher than the relative dielectric constant (3.9) of silicon oxide (SiO ₂ ), preferably a material having a relative dielectric constant of 4 or greater. In this embodiment, the high dielectric film is a metal oxide film, and can be formed of materials such as Al ₂ O ₃ , HfSiON, Y ₂ O ₃ , Ta ₂ O ₅ , La ₂ O ₃ , TiO ₂ , HfO ₂ , ZrO ₂ , and HfZrO ₂ .

When using the aforementioned high-dielectric film as the insulating film 740, metal materials such as TiN, TaN, and NiSi can be used to adjust Vth (threshold voltage) to form the gate electrodes 150, 152, 154, 156, 158, 160, and 162.

Furthermore, in this embodiment, the insulating film 740 located below the gate electrode 160 of the amplifier transistor AMP1 and the insulating film 740 located below the electrode 154 of the charge storage unit MEM1 are preferably wider than the gate electrode 160 and the electrode 154 when viewed from above the semiconductor substrate 200 to avoid interfering with adjacent devices.

Furthermore, in this embodiment, the insulating film 740 of the charge storage units MEM1 and MEM2 or the gate insulating film 740 of the amplifier transistors AMP1 and AMP2 is not limited to being formed of a high dielectric film. In this embodiment, only the insulating film 740 of the charge storage units MEM1 and MEM2 can be formed of a high-dielectric film. Alternatively, the insulating film 720 connecting the gate electrodes 150, 152, 154, 156, 158, 160, and 162 of the elements on the light-receiving element 10 (charge storage unit MEM, transfer transistor TG, distribution transistor VG, charge discharge transistor OFG, amplifier transistor AMP, reset transistor RST, and select transistor SEL) and the electrode 154 can also be formed of a high-dielectric film.

As described above, according to this embodiment, by forming the insulating film 740 of the charge storage unit MEM or the gate insulating film 740 of the amplifier transistor AMP as a high-dielectric film, it is possible to simultaneously increase the capacitance of the _charge storage unit MEM and reduce the random noise of the amplifier transistor AMP without reducing the film thickness, compared to the case of using SiO2. Therefore, in this embodiment, the structure of the first embodiment described above enables high-speed charge transfer. Furthermore, the structure of the fourth embodiment increases the capacitance of the charge storage unit MEM used to store the transferred charge, thereby achieving a ranging module 1 with higher ranging accuracy. Furthermore, the configuration of the fourth embodiment can reduce random noise of the transistor, thereby further improving the characteristics of the ranging module 1. Furthermore, this embodiment can be implemented in combination with the first and second embodiments and their variations.

<<10. Summary>>

As described above, according to the embodiments and variations of the present disclosure, a light-receiving element 10 and a distance-measuring module 1 capable of high-speed charge transfer can be provided.

While the present disclosure has been described above by citing embodiments and their variations, applicable examples, and application examples, the present disclosure is not limited to the aforementioned embodiments and is capable of various modifications. Furthermore, the effects described in this specification are ultimately for illustrative purposes only. The effects of the present disclosure are not limited to those described herein. The present disclosure may also have effects other than those described herein.

Furthermore, in the above-mentioned embodiments and variations of the present disclosure, the conductivity types of the aforementioned semiconductor regions can be reversed. For example, the present embodiments and variations can be applied to devices that use holes instead of electrons as charges.

Furthermore, in the above-mentioned embodiments and variations of the present disclosure, the semiconductor substrate need not necessarily be a silicon substrate, but may be another substrate (e.g., an SOI (Silicon-On-Insulator) substrate or a SiGe substrate). Furthermore, the semiconductor substrate may be a substrate having a semiconductor structure formed thereon.

Furthermore, in the above-mentioned embodiments and variations of the present disclosure, the light receiving element 10 may include the illumination portion and processing circuitry formed together on a single chip, or may be provided within a single package, without particular limitation.

Furthermore, in the embodiments and variations of the present disclosure, methods for forming the aforementioned layers, films, and components include, for example, physical vapor deposition (PVD) and chemical vapor deposition (CVD). Examples of PVD methods include vacuum evaporation using resistive heating or high-frequency heating, EB (electron beam) evaporation, various sputtering methods (magnetron sputtering, RF (radio frequency)-DC (direct current) coupled bias sputtering, ECR (electron cyclotron resonance) sputtering, target sputtering, high-frequency sputtering, etc.), ion plating, laser etching, molecular beam epitaxy (MBE), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, MO (metal organic) CVD, and photo-CVD. Other methods include electrolytic coating or non-electrolytic coating, spin coating, dipping, casting, micro-contact printing, drop coating, screen printing, inkjet printing, lithography, gravure printing, quick-dry printing, and other printing methods. Various coating methods are available, including spraying, air knife coating, doctor blade coating, rod coating, knife coating, extrusion coating, reverse roll coating, transfer roll coating, gravure coating, kiss coating, cast coating, spray coating, slit coating, and calendering coating. Patterning methods for each layer include shadow masking, laser transfer, chemical etching such as photolithography, and physical etching using ultraviolet light or lasers. In addition, planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow soldering. In other words, the devices of the embodiments and variations of the present disclosure can be easily and inexpensively manufactured using existing semiconductor device manufacturing steps.

Furthermore, the steps in the manufacturing methods of the variations of the embodiments disclosed above do not necessarily need to be performed in the order described. For example, the steps may be performed in a different order. Furthermore, the methods used in each step do not necessarily need to be performed in the described order and may be performed using other methods.

<<11. Examples of the structure of electronic equipment>>

Furthermore, in addition to being applicable to the distance measuring module 1 as described above, the light receiving element 10 can also be applied to various electronic devices, such as cameras and smartphones with distance measuring functions. Referring to FIG. 26 , an example configuration of a smartphone 900 as an electronic device to which the present technology is applied will be described. FIG. 26 is a block diagram showing an example configuration of a smartphone 900 as an electronic device to which the distance measuring module 1 according to an embodiment of the present disclosure is applied.

As shown in Figure 26 , smartphone 900 includes a CPU (Central Processing Unit) 901, ROM (Read Only Memory) 902, and RAM (Random Access Memory) 903. Smartphone 900 also includes a storage device 904, a communication module 905, and a sensor module 907. Furthermore, smartphone 900 includes a ranging module 908 that can be used with the ranging module 1 described above. It also includes a camera 909, a display device 910, a speaker 911, a microphone 912, an input device 913, and a bus 914. Furthermore, the smartphone 900 may also include a processing circuit such as a DSP (Digital Signal Processing) instead of the CPU 901, or may also include the CPU 901.

CPU 901 functions as a computational processing device and a control device, controlling all or part of the operations within smartphone 900 according to various programs stored in ROM 902, RAM 903, or storage device 904. ROM 902 stores programs and computational parameters used by CPU 901. RAM 903 stores programs used by CPU 901 and parameters that change during execution. CPU 901, ROM 902, and RAM 903 are interconnected via bus 914. Storage device 904 is a data storage device serving as a memory unit for smartphone 900. The storage device 904 includes, for example, a magnetic storage device such as an HDD (Hard Disk Drive), a semiconductor storage device, an optical storage device, etc. The storage device 904 stores programs executed by the CPU 901, various data, and various data obtained from the outside.

Communication module 905 is a communication interface composed of communication devices for connecting to communication network 906. Communication module 905 can be, for example, a wired or wireless LAN (Local Area Network), Bluetooth (registered trademark), or a WUSB (Wireless USB) communication card. Alternatively, communication module 905 can be a router for optical communication, an ADSL (Asymmetric Digital Subscriber Line) router, or a modem for various communication types. Communication module 905 uses specific protocols such as TCP/IP to transmit and receive signals with the Internet or other communication devices. Furthermore, the communication network 906 connected to the communication module 905 is a network connected via wired or wireless means, such as the Internet, a home LAN, infrared communication, or satellite communication.

The sensor module 907 includes various sensors, such as motion sensors (e.g., accelerometers, gyroscopes, geomagnetic sensors), biometric sensors (e.g., pulse sensors, blood pressure sensors, fingerprint sensors), and position sensors (e.g., GNSS (Global Navigation Satellite System) receivers).

Distance measurement module 908 is mounted on the front of smartphone 900. For example, it can detect the concave and convex shapes or movements of a user's fingertips, palm, face, etc. facing the front of the smartphone 900 as distance measurement results. Such distance measurement results can be used for user authentication or hand gesture recognition. Distance measurement module 908 can also detect the distance between smartphone 900 and object 800, or obtain three-dimensional shape data of the front of object 800.

Camera device 909 is mounted on the front of smartphone 900 and can capture images of objects 800 and the surrounding area of smartphone 900. Specifically, camera device 909 may include an imaging element (not shown) such as a CMOS (Complementary Metal-Oxide-Semiconductor, Complementary MOS) image sensor, and a signal processing circuit (not shown) that performs imaging signal processing on the photoelectrically converted signal from the imaging element. Furthermore, camera device 909 may include an optical system (not shown) including a camera lens, an aperture mechanism, a zoom lens, and a focus lens, as well as a drive system (not shown) that controls the operation of this optical system. Furthermore, the imaging element collects incident light from the object 800 as an optical image. The signal processing circuit converts the formed optical image into photoelectric signals on a pixel-by-pixel basis, reads the signal from each pixel as an imaging signal, and obtains a photographic image through image processing.

Display device 910 is located on the front of smartphone 900 and can be, for example, an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display. Display device 910 can display an operating screen or images captured by the aforementioned camera device 909.

The speaker 911 can, for example, output conversation sounds to the user, or the sounds accompanying the image content displayed by the display device 910.

Microphone 912 can collect, for example, the user's conversation voice, voice including commands for activating functions of smartphone 900, or sounds from the surrounding environment of smartphone 900.

The input device 913 is a user-operated device such as a button, keyboard, touch panel, or mouse. The input device 913 includes an input control circuit that generates an input signal based on user input and outputs it to the CPU 901. By operating the input device 913, the user can input various data or instruct processing operations on the smartphone 900.

The above illustrates an example configuration of a smartphone 900. Each of the aforementioned components can be constructed using general-purpose components or hardware that specializes the functions of each component. The aforementioned configuration may be modified appropriately based on the technological level at the time of implementation.

<<12. Application of Endoscopic Surgery System>>

The technology disclosed herein (the present invention) can be applied to various products. For example, the technology disclosed herein can be applied to endoscopic surgical systems.

FIG27 is a diagram showing an example of the schematic configuration of an endoscopic surgical system to which the technology disclosed herein (the present invention) can be applied.

Figure 27 shows a surgeon (doctor) 11131 performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown, endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as an insufflator tube 11111 or an energy delivery device 11112, a support arm 11120 for supporting endoscope 11100, and a trolley 11200 carrying various devices used for endoscopic surgery.

Endoscope 11100 includes: a barrel 11101, a region of a specific length extending from the front end thereof, which is inserted into a body cavity of a patient 11132; and a camera head 11102 connected to the base end of barrel 11101. In the illustrated example, endoscope 11100 is configured as a rigid scope having a rigid barrel 11101, but endoscope 11100 may also be configured as a flexible scope having a flexible barrel.

An opening into which an objective lens is embedded is provided at the front end of the barrel 11101. A light source device 11203 is connected to the endoscope 11100. Light generated by the light source device 11203 is guided to the front end of the barrel by a light guide extending into the interior of the barrel 11101 and then, through the objective lens, illuminates an object to be observed within the body cavity of a patient 11132. Furthermore, the endoscope 11100 can be a direct-viewing, strabismic, or side-viewing scope. Furthermore, the illuminating unit 20 and the light receiving unit 30 of the distance measurement module 1 of the present embodiment can be built into the front end of the barrel 11101. By incorporating a portion of such a distance measurement module 1, rather than relying solely on the doctor's visual inspection during surgery, the accuracy of the surgery can be further improved by referencing the distance information measured by the distance measurement module 1.

For example, as shown in FIG28 , which illustrates an example of the configuration of an endoscope 11100, the illumination unit 20 and the light receiving unit 30 of the distance measurement module 1 according to an embodiment of the present disclosure, namely, the iToF sensor 15004, are disposed within the camera head 11102. Specifically, reflected light from an observed object (observation light) passes through the lens barrel 11101, is collected by the lens 15001 within the camera head 11102, is reflected by the semi-reflective mirror 15002, and is received by the iToF sensor 15004. Furthermore, the observation light is photoelectrically converted by the iToF sensor 15004, generating an electrical signal corresponding to the observation light. This signal is then stored in the memory 15005 and transmitted to the distance measurement signal processing device 11209, described below.

As shown in Figure 28, an imaging element 15003 is installed within the camera head 11102. Reflected light from the observed object (observation light) passes through the lens barrel 11101, is collected by the lens 15001, reflected by the semi-reflective mirror 15002, and received by the imaging element 15003. The imaging element 15003 converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, and thus an image signal corresponding to the observed image. This image signal is temporarily stored in the memory 15005 and then transmitted as RAW data to the camera control unit (CCU) 11201.

The CCU 11201, which includes a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives image signals from the camera head 11102 and performs various image processing operations, such as development processing (demosaicing), on these image signals to display an image based on these image signals.

The display device 11202 displays an image based on an image signal processed by the CCU 11201 under control of the CCU 11201.

The light source device 11203 includes a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 for imaging the surgical site.

Input device 11204 is the input interface for endoscopic surgery system 11000. Users can input various information or instructions to endoscopic surgery system 11000 via input device 11204. For example, a user can input instructions to change the imaging conditions of endoscope 11100 (such as the type of illumination light, magnification, and focal length).

The treatment device control unit 11205 controls the operation of the energy treatment device 11112, which is used for cauterizing tissue, incising, or sealing blood vessels. The pneumoperitoneum device 11206 inflates the patient's 11132 body cavity by delivering gas through the pneumoperitoneum tube 11111, to ensure the visual field of the endoscope 11100 and the operator's working space. The recorder 11207 records various surgical information. The printer 11208 prints surgical information in various formats, such as text, images, or charts. The ranging signal processing device 11209 is equipped with the control unit 40 and processing unit 60 of the ranging module 1 according to the embodiment of the present disclosure and is capable of obtaining distance information.

Furthermore, the light source device 11203 that supplies irradiation light to the endoscope 11100 for imaging the surgical site can be composed of a white light source, such as an LED, a laser light source, or a combination thereof. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. Furthermore, in this case, by irradiating the observed object with laser light from each of the RGB laser light sources in a time-sharing manner and controlling the drive of the imaging element of the camera head 11102 in synchronization with the irradiation timing, images corresponding to each RGB color can be captured in a time-sharing manner. This method allows color images to be obtained even if the imaging element is not equipped with a color filter.

Furthermore, the light source device 11203 can be controlled to change the intensity of the light it outputs at specific intervals. By controlling the driving of the imaging element of the camera head 11102 in sync with the timing of the light intensity changes, images are captured in a time-sharing manner. These images are then synthesized to produce images with a high dynamic range, without underexposure or overexposure.

Furthermore, the light source device 11203 can also be configured to provide light of a specific wavelength band suitable for special light observation. In special light observation, for example, narrow-band imaging (Narrow Band Imaging) is performed. This utilizes the wavelength dependence of light absorption by body tissues to illuminate with light of a narrower bandwidth than that used for conventional observation (i.e., white light). This allows for high-contrast imaging of specific tissues, such as blood vessels on the surface of mucous membranes. Alternatively, special light observation can be performed using fluorescence generated by irradiated excitation light to obtain images. Fluorescence observation can involve irradiating body tissue with laser light to observe the fluorescence emitted by the tissue (autofluorescence observation). Alternatively, a reagent such as indocyanine green (ICG) can be locally injected into the tissue and then irradiated with laser light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 can be configured to supply narrowband light and/or laser light suitable for this type of special optical observation.

FIG29 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in FIG27 .

The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a driver unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and CCU 11201 are connected to each other via a transmission cable 11400 for communication.

Lens unit 11401 is an optical system installed at the connection point with lens barrel 11101. Observation light captured from the front end of lens barrel 11101 is guided to camera head 11102 and incident on lens unit 11401. Lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

The imaging unit 11402 can consist of a single imaging element (a so-called single-chip design) or multiple elements (a so-called multi-chip design). When the imaging unit 11402 is configured with multiple elements, for example, each imaging element can generate image signals corresponding to RGB, respectively, and these signals can be synthesized to produce a color image. Alternatively, the imaging unit 11402 can be configured with a pair of imaging elements for separately acquiring image signals for the right eye and the left eye, respectively, for 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the tissue at the surgical site. Furthermore, if the imaging unit 11402 is constructed with multiple panels, multiple lens units 11401 can be provided corresponding to each imaging element.

Furthermore, the imaging unit 11402 may not necessarily be located in the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101 directly behind the objective lens.

The drive unit 11403 is composed of an actuator. Under control from the camera head control unit 11405, it moves the zoom lens and focus lens of the lens unit 11401 a specific distance along the optical axis. This allows the magnification and focus of the image captured by the imaging unit 11402 to be appropriately adjusted.

Communication unit 11404 is composed of a communication device used to transmit and receive various information with CCU 11201. Communication unit 11404 transmits the image signal acquired by camera unit 11402 as RAW data to CCU 11201 via transmission cable 11400.

Furthermore, the communication unit 11404 receives control signals for controlling the drive of the camera head 11102 from the CCU 11201 and supplies them to the camera head control unit 11405. These control signals include information related to imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and/or information specifying the magnification and focus of the captured image.

Furthermore, the aforementioned imaging conditions, such as the frame rate, exposure value, magnification, and focus, can be specified by the user or automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 must be equipped with the so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

The communication unit 11411 is composed of a communication device used to transmit and receive various information between the camera head 11102. The communication unit 11411 receives image signals sent from the camera head 11102 via the transmission cable 11400.

Furthermore, the communication unit 11411 transmits a control signal to the camera head 11102 for controlling the driving of the camera head 11102. The image signal or the control signal can be transmitted via electrical communication or optical communication.

The image processing unit 11412 performs various image processing operations on the image signal sent from the camera head 11102 as RAW data.

The control unit 11413 performs various controls related to the endoscope 11100 imaging the surgical area, etc., and the display of images obtained by imaging the surgical area, etc. For example, the control unit 11413 generates control signals for driving the camera head 11102.

Furthermore, the control unit 11413 causes the display device 11202 to display a photographic image showing the surgical site, etc., based on the image signal processed by the image processing unit 11412. In this case, the control unit 11413 can utilize various image recognition techniques to identify various objects within the photographic image. For example, the control unit 11413 can detect the shape or color of the edges of objects contained in the photographic image to identify surgical instruments such as tweezers, specific biological sites, bleeding, and mist generated by the use of the energy treatment device 11112. When causing the display device 11202 to display the photographic image, the control unit 11413 can use this recognition result to overlay various surgical support information on the image of the surgical site. By overlaying surgical support information and providing prompts to the operator 11131, the burden on the operator 11131 can be reduced, allowing the operator 11131 to perform the surgery accurately.

The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 can be an electrical signal cable corresponding to electrical signal communication, an optical fiber corresponding to optical communication, or a composite cable thereof.

Here, in the example shown, wired communication is performed using transmission cable 11400, but wireless communication between camera head 11102 and CCU 11201 is also possible.

The above describes an example of an endoscopic surgical system to which the technology of this disclosure can be applied. The technology of this disclosure can be applied to the imaging unit 11402 and other components described above. Specifically, the light receiving element 10 can be used as a component of the imaging unit 11402. By applying the technology of this disclosure as part of the imaging unit 11402, the distance to the surgical site can be measured with high precision, thereby obtaining a clearer image of the surgical site.

Furthermore, while an endoscopic surgical system is described here as an example, the technology disclosed herein can also be applied to other systems, such as microscopic surgical systems.

<<13. Applications for Mobile Objects>>

The technology disclosed herein (the present invention) can be applied to a variety of products. For example, the technology of the present invention can be implemented as a device mounted on any type of mobile object, including automobiles, electric cars, hybrid cars, motorcycles, bicycles, personal mobility devices, aircraft, drones, ships, robots, etc.

FIG30 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.

Vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001. In the example shown in Figure 30, vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external vehicle information detection unit 12030, an internal vehicle information detection unit 12040, and an integrated control unit 12050. Furthermore, the functional components of integrated control unit 12050 include a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network interface 12053.

The drive system control unit 12010 controls the operation of devices associated with the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for the drive force generating device (e.g., an internal combustion engine or drive motor) that generates the vehicle's drive force; the drive force transmission mechanism that transmits the drive force to the wheels; the steering mechanism that adjusts the vehicle's steering angle; and the braking device that generates the vehicle's braking force.

The vehicle system control unit 12020 controls the operation of various devices installed on the vehicle according to various programs. For example, the vehicle system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, the vehicle system control unit 12020 can be input with radio waves or signals from various switches, which are transmitted from a portable device that replaces the key. The vehicle system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to a camera 12031. The vehicle exterior information detection unit 12030 causes the camera 12031 to capture images outside the vehicle and receive the captured images. Based on the received images, the vehicle exterior information detection unit 12030 can perform object detection processing, such as people, vehicles, obstacles, signs, or text on the road surface, or distance detection processing. Furthermore, the vehicle exterior information detection unit 12030 is connected to an iToF sensor 12032. The iToF sensor 12032 can function as the ranging module 1 in the embodiments of the present disclosure.

The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or non-visible light such as infrared.

The in-vehicle information detection unit 12040 detects information within the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 that detects the driver's condition. Driver status detection unit 12041 may include, for example, a camera that captures the driver's image. Based on the detection information input from driver status detection unit 12041, in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration level, and can also determine whether the driver is dozing off.

Based on information from both inside and outside the vehicle, obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can calculate control target values for the drivetrain, steering mechanism, or braking system, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement ADAS (Advanced Driver Assistance Systems) functions, including collision avoidance or impact mitigation, distance-based following, speed maintenance, collision warning, or lane departure warning.

Furthermore, the microcomputer 12051 controls the power generation device, steering mechanism, and braking system based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby enabling coordinated control for the purpose of autonomous driving, which allows the vehicle to operate independently of the driver.

Furthermore, the microcomputer 12051 can output control commands to the vehicle system control unit 12020 based on external vehicle information obtained by the external vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlights based on the position of the vehicle ahead or oncoming vehicles detected by the external vehicle information detection unit 12030, switching from high beam to low beam, and other coordinated control measures to prevent glare.

The audio and video output unit 12052 transmits at least one of audio and video output signals to an output device that can visually or audibly notify vehicle passengers or the outside of the vehicle of information. In the example of Figure 26 , an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a heads-up display.

Figure 31 shows an example of the installation position of the imaging unit 12031.

In FIG31 , the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

Cameras 12101, 12102, 12103, 12104, and 12105 are located, for example, on the front bumper, sideview mirrors, rear bumper, rear doors, and the upper portion of the windshield of vehicle 12100. Camera 12101 on the front bumper and camera 12105 on the upper portion of the windshield primarily capture images from the front of vehicle 12100. Cameras 12102 and 12103 on the sideview mirrors primarily capture images from the sides of vehicle 12100. The camera unit 12104 mounted on the rear bumper or rear door primarily captures images of the rear of the vehicle 12100. The camera unit 12105 mounted on the upper portion of the windshield within the vehicle is primarily used to detect vehicles or pedestrians ahead, obstacles, traffic signals, traffic signs, lane markings, and the like. Furthermore, the iToF sensor module 12201, which incorporates the illuminating unit 20 and the light receiving unit 30 of the ranging module 1 according to an embodiment of the present disclosure, is mounted, for example, on the front bumper of the vehicle 12100.

Furthermore, Figure 31 shows an example of the shooting ranges of camera units 12101 through 12104. Camera range 12111 represents the shooting range of camera unit 12101 located on the front bumper, camera ranges 12112 and 12113 represent the shooting ranges of camera units 12102 and 12103 located on the rearview mirror, respectively, and camera range 12114 represents the shooting range of camera unit 12104 located on the rear bumper or rear door. For example, by overlaying the image data captured by cameras 12101 through 12104, a bird's-eye view of vehicle 12100 can be obtained.

At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or an imaging element having pixels for phase difference detection.

For example, based on the distance information acquired by the cameras 12101 to 12104, the microcomputer 12051 calculates the distance to each 3D object within the imaging range 12111 to 12114, and the temporal variation of the distance (relative to the speed of the vehicle 12100). This allows the microcomputer 12051 to identify the 3D object closest to the vehicle 12100's path, which is traveling in the same direction as the vehicle 12100 at a specific speed (e.g., 0 km/h or higher), as the leading vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to the leading vehicle and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). This allows for coordinated control, such as autonomous driving, which allows the vehicle to drive independently without relying on the driver's control.

For example, microcomputer 12051 can classify 3D object data related to 3D objects into categories such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles based on distance information obtained from cameras 12101 to 12104, and capture these data for automatic obstacle avoidance. For example, microcomputer 12051 can identify obstacles around vehicle 12100 as visible to the driver and as difficult to identify. Furthermore, microcomputer 12051 determines the collision risk, which indicates the risk of collision with various obstacles. If the collision risk exceeds a set value, indicating a potential collision, it provides driver assistance to avoid collisions by outputting a warning to the driver via audio speaker 12061 or display unit 12062, or by initiating forced deceleration or evasive steering via propulsion system control unit 12010.

At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify pedestrians by determining whether a pedestrian is present in images captured by the imaging units 12101 to 12104. This pedestrian identification is performed by, for example, capturing feature points from images captured by the imaging units 12101 to 12104, which are infrared cameras, and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. When microcomputer 12051 determines that a pedestrian is present in the images captured by imaging units 12101 to 12104 and identifies the pedestrian, audio and video output unit 12052 controls display unit 12062 to overlay a square outline on the identified pedestrian for emphasis. Audio and video output unit 12052 can also control display unit 12062 to display an icon representing the pedestrian at a desired location.

The above describes an example of a vehicle control system to which the disclosed technology can be applied. The disclosed technology can be applied to the exterior vehicle information detection unit 12030 or the imaging unit 12031 described above. Specifically, the light receiving element 10 or the distance measurement module 1 can be used in the distance detection processing block of the exterior vehicle information detection unit 12030 or the imaging unit 12031. By applying the disclosed technology to the vehicle's external information detection unit 12030 or camera unit 12031, the distance to objects such as people, vehicles, obstacles, signs, or text on the road surface can be measured with high precision. Utilizing this distance information can reduce driver fatigue or improve driver and vehicle safety.

<<14. Supplement>>

While preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to the aforementioned examples. A skilled person with ordinary knowledge in the technical field of the present disclosure may conceive of various modifications and alterations within the technical concepts described in the patent application, and it should be understood that such modifications and alterations are also within the technical scope of the present disclosure.

Furthermore, the effects described in this specification are ultimately illustrative or exemplary, and not limiting. That is, in addition to achieving the effects described above, the technology disclosed herein may also achieve other effects that are readily apparent to those skilled in the art based on the description of this specification.

Furthermore, this technology can also adopt the following structure.

(1)

A light-receiving element comprises: a semiconductor substrate; a photoelectric conversion section disposed within the semiconductor substrate and configured to convert light into charge; a first charge storage section disposed within the semiconductor substrate and configured to transfer the charge from the photoelectric conversion section; a first distribution gate disposed on the front surface of the semiconductor substrate and configured to distribute the charge from the photoelectric conversion section to the first charge storage section; a second charge storage section disposed within the semiconductor substrate and configured to transfer the charge from the photoelectric conversion section; and a second distribution gate disposed on the front surface of the semiconductor substrate and configured to distribute the charge from the photoelectric conversion section to the second charge storage section; wherein the first and second distribution gates each have a pair of embedded gate sections embedded in the semiconductor substrate.

(2)

In the light-receiving element of (1) above, specific voltages are applied to the first and second distribution gates at different timings.

(3)

In the light-receiving element of (1) or (2) above, the first and second distribution gates are arranged to be substantially line-symmetrical with each other relative to the center of the photoelectric conversion section when viewed from above the front surface of the semiconductor substrate, and the first and second charge storage sections are arranged to sandwich the first and second distribution gates from both sides.

(4)

The light-receiving element as described in (3) above, wherein in a cross section of the light-receiving element cut along the front surface of the semiconductor substrate, each of the embedded gate portions has a substantially rectangular shape, and the rectangle has a long side extending in a direction from the center of the photoelectric conversion portion toward the first or second charge storage portion.

(5)

The light-receiving element as described in (3) above, wherein in a cross section of the light-receiving element cut along the front surface of the semiconductor substrate, each of the embedded gate portions has a substantially elliptical shape, and the ellipse has a long axis extending from the center of the photoelectric conversion portion toward the first or second charge storage portion.

(6)

As in the light-receiving element of (3) above, in a cross section of the light-receiving element cut along the front surface of the semiconductor substrate, each of the embedded gate portions has a substantially circular shape.

(7)

As in the light-receiving element of (4) above, the width between the mutually facing side surfaces of the pair of embedded gate portions gradually increases in the thickness direction from the front surface of the semiconductor substrate toward the back surface of the semiconductor substrate located on the opposite side to the front surface.

(8)

As in the light-receiving element of (4) above, in a cross section of the light-receiving element cut along the direction in which the pair of embedded gate portions are arranged, each of the embedded gate portions has a tapered shape that gradually narrows in the thickness direction toward the back surface of the semiconductor substrate located on the opposite side to the front surface.

(9)

As in the light-receiving element of (4) above, the side surface of one of the pair of embedded gate portions is located on the opposite side to the side surface of the other embedded gate portion and is in contact with the low dielectric layer.

(10)

As in the light-receiving element of (9) above, the low dielectric layer comprises an oxide film or a nitride film.

(11)

As in the light-receiving element of (9) above, the low dielectric layer is disposed in the element separation portion of the semiconductor substrate.

(12)

The light-receiving element of (1) above is further provided with: a plurality of third charge storage units disposed in the semiconductor substrate for transmitting the charge from the photoelectric conversion unit; and a plurality of third distribution gates disposed on the front surface of the semiconductor substrate for distributing the charge from the photoelectric conversion unit toward the plurality of third charge storage units; and each of the third distribution gates has the aforementioned pair of embedded gate units embedded in the semiconductor substrate.

(13)

The light-receiving element according to any one of (1) to (12) above is further provided with a moth-eye structure having fine concave and convex portions formed on the surface opposite to the aforementioned front surface of the aforementioned semiconductor substrate.

(14)

The light-receiving element according to any one of (1) to (13) above further comprises a first pixel separation portion extending through the semiconductor substrate.

(15)

The light-receiving element according to any one of (1) to (13) above further comprises a second pixel separation portion extending along the thickness direction of the semiconductor substrate from the surface of the semiconductor substrate opposite to the front surface to the middle of the semiconductor substrate.

(16)

The light receiving element as described in any one of (1) to (15) above is further provided with: one or more floating diffusion regions, which are arranged in the aforementioned semiconductor substrate; a first transfer gate, which is arranged on the aforementioned semiconductor substrate and transfers the aforementioned charge transferred to the aforementioned first charge storage portion toward the aforementioned one or more floating diffusion regions; a second transfer gate, which is arranged on the aforementioned semiconductor substrate and transfers the aforementioned charge transferred to the aforementioned first charge storage portion toward the aforementioned one or more floating diffusion regions; 2. The charge storage unit transfers the aforementioned charge toward the aforementioned one or more floating diffusion regions; one or more amplifying transistors amplify the aforementioned charge transferred to the aforementioned floating diffusion region and output it as a pixel signal; one or more selecting transistors output the aforementioned pixel signal in accordance with a selecting signal; and one or more resetting transistors reset the aforementioned charge stored in the aforementioned floating diffusion region.

(17)

The light-receiving element of (16) above, wherein the first and second charge storage portions each have a stack of electrodes, a first oxide film, and a semiconductor layer, and the first and second transfer gates each have a second oxide film disposed between the first and second transfer gates and the semiconductor substrate, and the thickness of the first oxide film is thinner than that of the second oxide film.

(18)

In the light-receiving device of (17) above, the amplifying transistor, the selecting transistor, and the resetting transistor each have a third oxide film provided on the semiconductor substrate, and the thickness of the third oxide film of the amplifying transistor is thinner than that of the third oxide film of the selecting transistor and the resetting transistor.

(19)

In the light-receiving element of any one of (1) to (15) above, the first and second charge storage units each comprise a stack of electrodes, a first oxide film, and a semiconductor layer, and the thickness of the first oxide film is 5.0 nm or less.

(20)

The light-receiving element of (16) above, wherein the first and second charge storage portions each comprise a stack of electrodes, a first insulating film, and a semiconductor layer, and the first and second transfer gates each comprise a second insulating film disposed between the first and second transfer gates and the semiconductor substrate, and the relative dielectric constant of the first insulating film is higher than that of the second insulating film.

(twenty one)

In the light-receiving element of (20) above, the amplifying transistor, the selecting transistor, and the resetting transistor each have a third insulating film provided on the semiconductor substrate, and the relative dielectric constant of the third insulating film of the amplifying transistor is higher than that of the third insulating film of the selecting transistor and the resetting transistor.

(twenty two)

The light-receiving element according to any one of (1) to (15) above, wherein the first and second charge storage units each comprise a stack of electrodes, a first insulating film, and a semiconductor layer, and the relative dielectric constant of the first insulating film is 4 or greater.

(twenty three)

A light receiving device having one or more light receiving elements, wherein the light receiving element comprises: a semiconductor substrate; a photoelectric conversion unit disposed in the semiconductor substrate and converting light into electric charge; a first charge storage unit disposed in the semiconductor substrate and transmitting the electric charge from the photoelectric conversion unit; a first distribution gate disposed on the front surface of the semiconductor substrate and extending from the photoelectric conversion unit toward the front; The first charge storage unit distributes the charge; the second charge storage unit is disposed within the semiconductor substrate and receives the charge from the photoelectric conversion unit; and the second distribution gate is disposed on the front surface of the semiconductor substrate and distributes the charge from the photoelectric conversion unit toward the second charge storage unit. The first and second distribution gates each have a pair of embedded gate portions embedded in the semiconductor substrate.

(twenty four)

The light receiving device as described in (23) above is further provided with: an irradiation unit that irradiates light toward an object by periodically changing the brightness; and an irradiation control unit that controls the irradiation unit; and the photoelectric conversion unit receives the reflected light from the object.

10: Light-receiving element

100, 102a, 102b, 104a, 104b, 106a, 106b, 108a, 108b, 110a, 110b, 112a, 112b, 114a, 114b, 116a, 116b: N-type semiconductor regions

150a: Gate electrode (first distribution gate)

150b: Gate electrode (second distribution gate)

152a, 152b, 156a, 156b, 158a, 158b, 160a, 160b, 162a, 162b: Gate electrodes

154a,154b: Electrode

200:Semiconductor substrate

600,602: Centerline

A-A’, B-B’: line

AMP1, AMP2: Amplifier transistors

FD1, FD2: Floating diffusion area

MEM1: Charge storage unit (first charge storage unit)

MEM2: Charge storage unit (second charge storage unit)

O: Center point (center)

OFG1, OFG2: Charge discharge transistors

PD: Photodiode

RST1, RST2: Reset transistors

SEL1, SEL2: select transistors

TG1, TG2: Transistors

VDD: power supply voltage

VG1, VG2: Distribution transistors

VSL1, VSL2: signal lines

Claims (15)

A light-receiving element comprises: a semiconductor substrate, wherein light is incident from the back surface of the semiconductor substrate, and the front surface of the semiconductor substrate is the surface opposite to the back surface; a photoelectric conversion unit disposed in the semiconductor substrate and converting light into charge; a first charge storage unit disposed in the semiconductor substrate and transmitting the charge from the photoelectric conversion unit; and a first distribution gate disposed on the front surface of the semiconductor substrate. The charge is distributed from the photoelectric conversion section to the first charge storage section; a second charge storage section is disposed within the semiconductor substrate and transfers the charge from the photoelectric conversion section; and a second distribution gate is disposed on the front surface of the semiconductor substrate and distributes the charge from the photoelectric conversion section to the second charge storage section; and the first and second distribution gates each have a pair of embedded gate sections embedded in the semiconductor substrate. The light-receiving element of claim 1, wherein specific voltages are applied to the first and second distributed gates at different timings. The light-receiving element of claim 1, wherein the first and second distribution gates are arranged substantially line-symmetrically with respect to the center of the photoelectric conversion section when viewed from above the front surface of the semiconductor substrate, and the first and second charge storage sections are arranged so as to sandwich the first and second distribution gates from both sides. The light-receiving element of claim 3, wherein, in a cross-section of the light-receiving element taken along the front surface of the semiconductor substrate, each of the embedded gate portions: i) has a substantially rectangular shape, wherein the rectangle has a long side extending from the center of the photoelectric conversion portion toward the first or second charge storage portion; or ii) has a substantially elliptical shape, wherein the elliptical shape has a long axis extending from the center of the photoelectric conversion portion toward the first or second charge storage portion; or iii) has a substantially circular shape. The light-receiving element of claim 4, wherein the width between the mutually facing side surfaces of the pair of embedded gate portions gradually increases in the thickness direction from the front surface of the semiconductor substrate toward the back surface of the semiconductor substrate located on the side opposite to the front surface. The light-receiving element of claim 4, wherein, in a cross-section of the light-receiving element taken along the direction in which the pair of embedded gate portions are arranged, each of the embedded gate portions has a tapered shape that gradually narrows in the thickness direction toward the back surface of the semiconductor substrate located on the side opposite to the front surface. The light-receiving element of claim 4, wherein the side of one of the pair of embedded gate portions is located opposite to the other embedded gate portion and is in contact with the low dielectric layer. The light-receiving element of claim 1 further comprises: a plurality of third charge accumulating sections disposed within the semiconductor substrate and transmitting the charge from the photoelectric conversion section; and a plurality of third distribution gates disposed on the front surface of the semiconductor substrate and distributing the charge from the photoelectric conversion section toward the plurality of third charge accumulating sections; wherein each of the third distribution gates has the aforementioned pair of embedded gate sections embedded in the semiconductor substrate. The light-receiving element according to any one of claims 1 to 8 further comprises: a moth-eye structure provided on a surface opposite to the front surface of the semiconductor substrate and having fine concavities and convexities. The light-receiving element according to any one of claims 1 to 8 further comprises a first pixel separation portion extending through the semiconductor substrate. The light-receiving element according to any one of claims 1 to 8 further comprises a second pixel separation portion extending along the thickness direction of the semiconductor substrate from a surface of the semiconductor substrate opposite to the front surface to the middle of the semiconductor substrate. The light-receiving element of any one of claims 1 to 8 further comprises: one or more floating diffusion regions disposed within the semiconductor substrate; a first transfer gate disposed on the semiconductor substrate for transferring the charge transferred to the first charge storage portion toward the one or more floating diffusion regions; and a second transfer gate disposed on the semiconductor substrate for transferring the charge transferred to the second charge storage portion. The charge storage unit transfers the charge to the one or more floating diffusion regions; one or more amplifying transistors amplify the charge transferred to the floating diffusion region and output it as a pixel signal; one or more selecting transistors output the pixel signal in accordance with a selecting signal; and one or more resetting transistors reset the charge stored in the floating diffusion region. The light-receiving element of claim 12, wherein the first and second charge storage portions each comprise a stack of an electrode, a first oxide film, and a semiconductor layer; the first and second transfer gates each comprise a second oxide film disposed between the first and second transfer gates and the semiconductor substrate; the first oxide film is thinner than the second oxide film, or the first oxide film has a higher relative dielectric constant than the second oxide film. In the light-receiving element of any one of claims 1 to 8, the first and second charge storage units each comprise a stack of an electrode, a first oxide film, and a semiconductor layer, and the thickness of the first oxide film is 5.0 nm or less. A light receiving device comprising one or more light receiving elements according to any one of claims 1 to 14, further comprising: an irradiation unit for irradiating light onto an object by periodically varying the brightness; and an irradiation control unit for controlling the irradiation unit; wherein the photoelectric conversion unit receives light reflected from the object.