TWI889618B - Processing method and polished wafer for final polishing process - Google Patents

Abstract

The present application relates to a processing method and a polished wafer for a final polishing process. The processing method for the final polishing process includes: performing a first polishing on the wafer using a first polishing liquid; performing a second polishing on the wafer that has undergone the first polishing using a second polishing liquid; and performing a third polishing on the wafer that has undergone the second polishing using a third polishing liquid, wherein both the first polishing liquid and the second polishing liquid are added with an alkaline additive, and the third polishing liquid is not added with an alkaline additive.

Description

Processing method and polished wafer for final polishing process

This application claims priority to Chinese Patent Application No. 202411462415.0 filed in China on October 18, 2024, the entire contents of which are incorporated herein by reference.

The present application relates to the field of semiconductor manufacturing technology, and more specifically, to a processing method and a polished wafer for a final polishing process.

In wafer production, usually, a crystal rod is first pulled out using a crystal pulling furnace, and then the crystal rod is cut into multiple ingots. Each ingot is then cut into thin slices of initial wafers by, for example, multi-wire cutting. The initial wafers are then subjected to polishing, epitaxy and other processes to obtain finished wafers.

In the wafer polishing process, usually, it is carried out in the order of double-sided polishing, primary cleaning, edge polishing, secondary cleaning, and final polishing. Final polishing is a key step in wafer surface treatment. Its purpose is to remove the damage layer and surface unevenness that may be introduced in the previous process, and ensure that the wafer surface reaches a high standard of flatness and cleanliness. The quality of the wafer surface after the final polishing process directly determines the quality of the wafer.

However, the final polishing process mainly removes material by applying physical pressure to the wafer surface using a polishing pad and abrasive particles in the polishing liquid. This material removal method has a low rate and is prone to cause defects on the wafer surface, which will have an adverse effect on the surface quality and performance of the wafer.

The purpose of this application is to provide a processing method for the final polishing process, which can reduce the defects caused on the wafer surface while removing the damage caused by the previous process and repairing the mirror surface.

In order to achieve the above object, according to the first aspect of the present application, a processing method for a final polishing process is provided, comprising:

Performing a first polishing on the wafer using a first polishing solution;

Performing a second polishing on the wafer that has undergone the first polishing using a second polishing solution; and

The wafer that has been second-polished is subjected to third-polishing using a third polishing solution.

The first polishing liquid and the second polishing liquid both include alkaline additives, and the third polishing liquid does not include alkaline additives.

In some embodiments, the volume ratio of the alkaline additive to the solvent in the first polishing solution may be greater than the volume ratio of the alkaline additive to the solvent in the second polishing solution.

In some embodiments, the volume ratio of the alkaline additive to the solvent in the first polishing solution may be in the range of 1:2500 to 1:1500, and the volume ratio of the alkaline additive to the solvent in the second polishing solution may be in the range of 1:5000 to 1:2500.

In some embodiments, the alkaline additive can be an inorganic base or an organic base.

In some embodiments, the alkaline additive may include KOH, NaOH or .

In some embodiments, the first polishing may be performed at a first target removal thickness, the second polishing may be performed at a second target removal thickness, and the third polishing may be performed at a third target removal thickness, wherein the first target removal thickness may be greater than the second target removal thickness, and the second target removal thickness may be greater than the third target removal thickness.

In some implementations, the ratio of the first target removal thickness, the second target removal thickness, and the third target removal thickness may be 6:3:1.

In some embodiments, the sum of the first target removal thickness, the second target removal thickness, and the third target removal thickness may be greater than 150% of the thickness of the damaged layer of the wafer to be subjected to the first polishing.

According to the second aspect of the present application, a polished wafer is provided, which is obtained by the processing method for the final polishing process according to the first aspect of the present application, and the number of DIC defects with a size of more than 5nm on the polished wafer is less than 5.

In some embodiments, the number of DIC defects with a size greater than 5 nm on the polished wafer can be less than 3.

According to the above technical solution, the three polishing steps can be used to gradually complete the removal and mirror repair of the previous process damaged layer on the wafer surface. In addition, the first polishing step and the second polishing step remove the wafer surface material at an increased material removal rate by combining chemical corrosion and physical grinding, which effectively shortens the time for clearing the crystal defect area on the wafer surface, helps to avoid the gradual enlargement of the defect area and the tiny defects in the defect area due to physical grinding, thereby reducing the risk of forming DIC defects and reducing the formation of DIC defects on the wafer surface.

The present application is described in detail below with reference to the accompanying drawings and by means of exemplary embodiments. It should be noted that the following detailed description of the present application is for illustrative purposes only and is by no means a limitation of the present application.

As mentioned earlier, before obtaining the finished wafer, it generally needs to go through manufacturing processes such as cutting, slicing, edge grinding, corrosive etching, double-sided grinding, double-sided polishing, edge polishing and final polishing.

Among the various polishing processes in the above-mentioned manufacturing process, according to the order of implementation, the double-sided polishing process is usually carried out at an earlier stage. Its purpose is to remove the damaged layer formed in the previous processes such as cutting and double-sided grinding, and to improve the overall geometric properties of the wafer, such as flatness and thickness uniformity, mainly to make the wafer meet the basic physical properties.

The double-sided polishing process is performed using a double-sided polishing device. The double-sided polishing device generally includes an upper platen and a lower platen arranged opposite to each other and a carrier plate disposed between the upper platen and the lower platen. The carrier plate is used to carry the wafer to be polished. The upper platen and the lower platen include an upper polishing pad and a lower polishing pad, respectively. In the double-sided polishing process, the upper platen and the lower platen simultaneously apply pressure to the wafer carried in the carrier plate, so that the upper polishing pad and the lower polishing pad contact the front and back sides of the wafer respectively, so as to complete the double-sided polishing of the wafer through the movement of the carrier plate relative to the upper platen and the lower platen.

The edge polishing process is mainly performed on the edge of the wafer. It is usually performed after the double-sided polishing process. Its purpose is to improve the flatness of the wafer edge and remove edge defects such as protrusions and micro cracks.

The edge polishing process is performed using an edge polishing device. Generally, the edge polishing device includes a rotatable support plate and an edge polishing head. The support plate is used to carry the wafer to be edge polished and can drive the wafer to rotate about its central axis. The edge polishing head can contact the edge of the rotating wafer during the edge polishing process to achieve polishing of the wafer edge.

At the final stage of the various polishing processes in the above manufacturing process, the wafer that has undergone the above polishing processes such as double-sided polishing process and edge polishing process will finally undergo the final polishing process. The final polishing process is usually performed on the front side of the wafer to remove the damage formed in the previous processes including the previous polishing process and to achieve global flatness of the wafer surface. It is a fine processing to make the wafer surface meet the quality standards required for subsequent device manufacturing (such as photolithography process).

The final polishing process must be carried out with the aid of final polishing equipment capable of carrying out this fine processing.

FIG1 shows an exemplary final polishing device 1 according to the related art. As shown in FIG1 , the final polishing device 1 includes a polishing head 2, a polishing table 3, and a polishing liquid supply line 4. The polishing head 2 holds a wafer to be polished at its lower portion. The polishing table 3 is provided with a polishing pad 5 on its upper surface. The polishing liquid supply line 4 is used to provide the polishing liquid to the polishing pad 5. During the polishing process, the wafer held by the polishing head 2 is pressed against the polishing pad 5 to achieve final polishing of the wafer by means of relative rotation of the polishing pad 5 and the wafer.

Generally, the final polishing process includes rough polishing and fine polishing. In the rough polishing process, a polishing liquid with a larger abrasive particle size is used to remove the micro-damage of the previous layer. In the fine polishing process, a polishing liquid with a smaller abrasive particle size is used to clean and mirror the wafer surface to achieve the required flatness and smoothness of the wafer surface.

In the final polishing process of the related technology, the polishing liquid used for the final polishing only removes the front damaged layer on the wafer surface by physical grinding of abrasive particles. In this case, as mentioned above, different degrees of surface polishing effects are generally obtained by selecting abrasive particles of appropriate size. However, this pure physical grinding polishing process is prone to cause defects on the wafer surface.

In particular, for heavily doped wafers, the wafers have higher hardness due to their higher oxygen content. At the same time, larger crystal-originating particles (COPs) may be gathered at the center of the wafer, as indicated by A on the polished wafer W shown in FIG2. Therefore, after the wafers are processed by pre-processes such as double-sided grinding and low temperature oxidation (LTO), the area where COPs are gathered appears as a crystal defect area.

The inventors noticed that due to the high surface hardness of the heavily doped wafer and the low material removal rate on the wafer surface when the surface is polished by physical grinding, it takes a long time to remove the crystal defect area. This physical grinding process will gradually enlarge the defect area, causing the small crystal defects in the defect area to be enlarged, thereby forming a differential interference contrast (DIC) defect, which is indicated by B on the polished wafer W shown in FIG2. It is understandable that FIG2 is not drawn to scale, and for ease of understanding, the COP and DIC defects on the polished wafer W are schematically enlarged.

It should be understood that, in the present application, a DIC defect refers to a step-shaped defect observed by differential interference contrast technology, for example, using a differential interference contrast microscope. FIG3 exemplarily shows the schematic morphological features of a single DIC defect. As shown in the figure, from the overall morphology, the DIC defect is generally a raised step-shaped defect or a recessed pit-shaped defect. In addition, FIG3 shows the span of the DIC defect in the horizontal direction and the span in the vertical direction, wherein the horizontal direction refers to the direction extending along the plane where the wafer surface is located, and the vertical direction is the direction perpendicular to the plane where the wafer surface is located.

Referring to FIG. 3 , the span of the DIC defect in the vertical direction, i.e., the maximum height difference H, is used to characterize the size of the DIC defect. That is, in this application, the size of the DIC defect refers to the height difference between the highest point and the lowest point of the DIC defect. In other words, the size of the DIC defect is the height difference or height difference between the highest point and the lowest point on the wafer surface where the DIC defect is located, and its unit is nm.

It should be noted that the DIC defect in FIG. 3 is exemplary, and is only used to schematically illustrate the basic morphological features of the DIC defect, and does not mean that the DIC defect is completely consistent with the morphology shown in FIG. 3 .

DIC defects are an important indicator that affects wafer quality and device performance. Too many DIC defects will not only reduce the yield and reliability of wafer products, but also limit the application of wafer products in high-end technology fields.

Therefore, it is desirable to provide a processing method for a final polishing process that can reduce the formation of DIC defects while removing damage from previous processes and repairing the surface of the wafer by mirroring.

Referring to FIG. 4 , according to an embodiment of the present application, a processing method for a final polishing process is provided, comprising:

S100: performing a first polishing on the wafer using a first polishing liquid;

S200: performing a second polishing on the wafer that has undergone the first polishing using a second polishing solution; and

S300: performing a third polishing on the wafer that has undergone the second polishing using a third polishing solution.

The first polishing liquid and the second polishing liquid are both added with alkaline additives, and the third polishing liquid is not added with alkaline additives.

It is understood that the first polishing liquid, the second polishing liquid and the third polishing liquid are all solid-liquid mixtures containing abrasive particles. The abrasive particles are used to physically grind the surface of the wafer to remove the surface material. In addition, the first polishing liquid, the second polishing liquid and the third polishing liquid all contain a solvent for dispersing or dissolving the abrasive particles and other additives such as chemical additives.

The following is a detailed description of each of the above steps.

Step S100 is also called the first polishing step, which is used to remove the previous process damaged layer on the surface of the wafer.

Here, the front process damage layer on the surface of the wafer refers to the area where the damage introduced by the previous processing process (such as double-sided grinding, etc.) before the wafer starts to undergo the first polishing, such as mechanical damage such as micro scratches or cracks.

When an alkaline additive is added to the first polishing solution, the first polishing solution is alkaline, so that the first polishing can combine the physical grinding effect of the abrasive particles and The chemical corrosion produced provides a very large material removal rate, thereby quickly reducing the thickness of the damaged layer of the previous process, shortening the time for the defects in the defect area to expand into DIC defects, thereby reducing the risk of forming DIC defects.

In particular, in the first polishing step, the tip stress principle of chemical etching can be used to quickly remove severe damage. The wafer can be etched quickly along the crystal lattice, further reducing the risk of enlarging tiny crystal defects into DIC defects.

Step S200 is also called the second polishing step, which is used to remove the damage on the surface of the wafer caused by the physical grinding and chemical corrosion in the first polishing step. Alkaline additives are added to the second polishing solution to obtain a relatively high material removal rate through the combination of material grinding and chemical corrosion.

Step S300 is also called the third polishing step, which is used to repair the damage on the surface of the wafer caused by the physical grinding and chemical corrosion of the second polishing, so as to achieve mirroring of the wafer surface and obtain a highly flat and smooth surface.

The third polishing solution does not include alkaline additives to avoid excessive chemical corrosion on the wafer surface, thereby avoiding deterioration of the flatness of the wafer surface and ensuring the final quality of the wafer surface.

Through the above scheme, the removal and mirror repair of the previous process damaged layer on the wafer surface are gradually completed by three polishing steps. In addition, the first polishing step and the second polishing step thin the wafer at an increased material removal rate by combining chemical corrosion and physical grinding, effectively shortening the time to remove the crystal defect area on the wafer surface, helping to avoid the gradual enlargement of the defect area and the tiny defects in the defect area due to long grinding time, thereby reducing the risk of forming DIC defects.

Through the above scheme, the formation of DIC defects can be reduced while removing the damage of the previous process and repairing the mirror surface on the wafer surface, which is conducive to obtaining a polished wafer with no damage layer on the surface, high mirror surface and reduced DIC defects.

According to the implementation of the present application, a polished wafer is also provided, which is obtained by the processing method for the final polishing process according to the implementation of the present application. The processing method for the final polishing process according to the implementation of the present application includes the processing method for the final polishing process according to any of the above-mentioned implementations, and it can be understood that it also includes the processing method for the final polishing process according to any of the implementations mentioned below.

The number of DIC defects with a size of 5 nm or more (i.e., greater than or equal to 5 nm) on the polished wafer obtained in this way is less than 5.

Furthermore, the number of DIC defects with a size of 5 nm or more on the polished wafer obtained in this way can be less than 3.

Specifically, the polished wafer is obtained by performing a first polishing on the wafer using a first polishing liquid, performing a second polishing on the wafer that has undergone the first polishing using a second polishing liquid, and performing a third polishing on the wafer that has undergone the second polishing using a third polishing liquid, wherein both the first polishing liquid and the second polishing liquid are added with alkaline additives, and the third polishing liquid is not added with alkaline additives.

Taking the processing method for the final polishing process according to the related art as comparative example A, and taking the processing method for the final polishing process according to the implementation mode of the present application as implementation example B, FIG5 shows the statistical results of DIC defects of a series of polished wafers obtained in the case of comparative example A and a series of polished wafers obtained in the case of implementation example B in the form of a box plot, wherein the vertical coordinate is the number of DIC defects with a size of more than 5 nm on a single polished wafer measured.

Here, the polished wafer specifically refers to a wafer having a diameter of 300 mm or a 12-inch wafer.

As shown in FIG5 , the average number of DIC defects with a size of 5 nm or more on the polished wafer obtained from comparative example A is 2806.92, and the average number of DIC defects with a size of 5 nm or more on the polished wafer obtained from example B is 0.166667. It can be seen that the processing method for the final polishing process according to the embodiment of the present application can effectively reduce the DIC defects on the polished wafer obtained thereby.

6 shows the number of DIC defects with a size of 5 nm or more in each of the series of polished wafers obtained in the case of comparative example A and the series of polished wafers obtained in the case of embodiment B. From FIG6 , it can be seen that the number of DIC defects in the series of polished wafers fluctuates.

As can be seen from FIG. 6 , the number of DIC defects in a series of polished wafers obtained in Example B is generally low and basically maintained at a consistent level, which indicates that the processing method for the final polishing process according to the implementation method of the present application has high reliability and stability in reducing DIC defects.

In addition, as shown in FIG7 , the number of DIC defects with a size of 5 nm or more on the surface of the polished wafer obtained from Comparative Example A is quite large and densely distributed. As shown in FIG8 , the number of DIC defects with a size of 5 nm or more on the surface of the polished wafer obtained from Example B is extremely small. It can be seen that the surface quality of the polished wafer obtained by the processing method for the final polishing process according to the embodiment of the present application is higher.

In some embodiments, the volume ratio of the alkaline additive to the solvent in the first polishing solution may be greater than the volume ratio of the alkaline additive to the solvent in the second polishing solution, so that the volume ratio of the alkaline additive to the solvent in the first polishing solution is greater than that of the alkaline additive to the solvent in the second polishing solution. The concentration is higher than that in the second polishing liquid. concentration.

In this case, the first polishing step has a stronger alkaline corrosion effect to achieve a relatively stronger polishing ability and a faster polishing rate, so that the damaged layer of the previous process can be quickly removed while reducing the thickness of the damaged layer formed by physical action in this process.

The corrosion effect of the second polishing step is weaker than that of the first polishing step, so that the polishing rate is relatively reduced. In order to remove the damage caused by the chemical corrosion of the first polishing step and the damage of the current layer, it is avoided that the chemical reaction is too strong and causes the deterioration of parameters such as wafer flatness, and a relatively finer polishing effect is achieved than the first polishing step.

It is understood that the initial concentration of the alkaline additive added to the first polishing solution and the initial concentration of the alkaline additive added to the second polishing solution can be the same. For example, the initial concentration of the alkaline additive can be 50 wt%.

For alkaline additives with the same initial concentration, the amount of the alkaline additive added to the solvent of the first polishing solution may be greater than the amount of the alkaline additive added to the solvent of the second polishing solution.

In some embodiments, the volume ratio of the alkaline additive to the solvent in the first polishing solution may be in the range of 1:2500 to 1:1500, and the volume ratio of the alkaline additive to the solvent in the second polishing solution may be in the range of 1:5000 to 1:2500.

If the volume ratio of alkaline additive to solvent in the first polishing solution is higher than 1:1500, the chemical reaction will be too strong, which may lead to deterioration of wafer flatness and other quality issues.

If the volume ratio of the alkaline additive to the solvent in the first polishing solution is lower than 1:2500, the polishing rate of the first polishing process is low, which is not conducive to suppressing the occurrence of DIC defects and is not conducive to equipment capacity matching.

If the volume ratio of alkaline additive to solvent in the second polishing solution is less than 1:5000, the pH change of the second polishing solution is too small, the chemical action is insufficient, and it cannot effectively help reduce the formation of DIC defects.

In some embodiments, the alkaline additive may be an inorganic base.

For example, alkaline additives may include KOH, NaOH or .

In some embodiments, the alkaline additive may be an organic base, such as aminomethyl propanol, quaternary ammonium salt, etc.

In some embodiments, the first polishing may be performed at a first target removal thickness, the second polishing may be performed at a second target removal thickness, and the third polishing may be performed at a third target removal thickness, wherein the first target removal thickness may be greater than the second target removal thickness, and the second target removal thickness may be greater than the third target removal thickness.

In this case, the wafer surface material can be removed in a stepwise manner with a target removal amount. This not only helps to further reduce the probability of DIC defects, but also the amount to be removed in each step can be matched or adapted to the material removal rate of each polishing step, for example, a larger material removal rate matches a larger amount to be removed, thereby optimizing the polishing process and improving the overall efficiency of the final polishing process.

In some embodiments, the ratio of the first target removal thickness, the second target removal thickness, and the third target removal thickness can be 6:3:1 to better match the expected material removal rates of the three steps.

In addition, in order to ensure the stability of the process and ensure sufficient removal of damage from the previous process, in some embodiments, the sum of the first target removal thickness, the second target removal thickness, and the third target removal thickness is greater than 150% of the thickness of the damaged layer of the wafer to be subjected to the first polishing.

It should be understood that the thickness of the front damage layer is calculated according to the average value, and the front damage layer will fluctuate due to process fluctuations and spare parts replacement. In actual production, the fluctuation of the front damage layer can be controlled within 20%. Based on this fluctuation range, the maximum actual damage layer thickness will reach 120% of the thickness of the front damage layer calculated according to the average value. Combining statistical principles and the 1.5 offset sigma management habit in quality management, the maximum actual damage layer thickness may reach about 150% of the thickness of the front damage layer calculated according to the average value. Therefore, by ensuring that the sum of the target removal thickness is greater than the possible maximum value of the actual damaged layer thickness, complete removal of the damage from the previous process can be ensured.

It should be noted that the damage layer here refers to the damage layer existing on the wafer surface when the wafer is to be polished or about to be first polished. The damage layer is the area where the damage is introduced on the wafer surface due to the previous process before the first polishing, such as double-sided polishing.

It is understandable that the thickness of the damaged layer can be measured by selecting a suitable measurement method based on the material, processing process and equipment conditions of the wafer, and no limitation is made here.

FIG9 shows an exemplary final polishing apparatus 10 for performing the embodiment according to the present application. As shown in FIG9 , the final polishing apparatus 10 includes a polishing head 20, a polishing table 30, and a polishing liquid supply line 40. The polishing head 20 holds the wafer to be polished on its lower surface. A polishing pad 31 for contacting the wafer is provided on the upper surface of the polishing table 30. The polishing liquid supply line 40 is used to provide the polishing liquid to the polishing pad 31 so as to polish the wafer through the contact between the polishing pad 31 and the wafer.

The final polishing apparatus 10 may include a first container 50 for storing a first polishing liquid, a second container 60 for storing a second polishing liquid, and a third container 70 for storing a third polishing liquid. By configuring independent containers, it is convenient to adjust the use order and amount of each polishing liquid according to the corresponding polishing steps, thereby improving the flexibility and adaptability of the process.

The following is a description of the process of the final polishing process using the final polishing equipment 10 to perform the embodiment of the present application.

When the final polishing device 10 is used to perform final polishing on the wafer, the wafer is adsorbed and held by the polishing head 20. First, a certain flow of the first polishing liquid is supplied from the first storage tank 50 to the polishing pad 31 via the polishing liquid supply pipeline 40. After the polishing liquid is supplied to the polishing pad 31 and contacts the wafer, the polishing head 20 and the polishing table 30 are driven by their corresponding driving shafts to rotate relative to each other, and pressure is applied to the wafer through the polishing head 20 to complete the first polishing of the wafer.

Subsequently, similarly, a certain flow of the second polishing liquid is supplied from the second storage tank 60 to the polishing pad 31 through the polishing liquid supply pipeline 40 for the second polishing. Finally, a certain flow of the third polishing liquid is supplied from the third storage tank 70 to the polishing pad 31 through the polishing liquid supply pipeline 40 for the third polishing, thereby finally obtaining a polished wafer with the surface damaged layer removed, the surface mirrored and repaired, and the number of DIC defects reduced.

Unless otherwise defined, technical or scientific terms used in this application should have the common meanings understood by people in the field to which this application belongs. The terms "include" and "comprising" are open-ended, that is, systems, devices, products, compositions, formulations or methods that include elements other than those listed after such terms in the claims are still considered to fall within the scope of the claims.

Although the present application has been described with reference to exemplary embodiments, it should be understood that the present application is not limited to the specific embodiments described and shown in detail herein. Various changes may be made to the exemplary embodiments by those skilled in the art without departing from the scope defined by the claims of the present application.

The features mentioned and/or shown in the above description of the exemplary embodiments of the present application may be combined in the same or similar manner into one or more other embodiments, combined with the features in other embodiments, or replace the corresponding features in other embodiments. The technical solutions obtained by these combinations or replacements should also be deemed to be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

1: Final polishing equipment 2: Polishing head 3: Polishing table 4: Polishing liquid supply pipeline 5: Polishing pad A: COP defect B: DIC defect H: Maximum height difference W: Polished wafer S100: Use the first polishing liquid to perform the first polishing on the wafer S200: Use the second polishing liquid to perform the second polishing on the wafer that has been polished for the first time S300: Use the third polishing liquid to perform the third polishing on the wafer that has been polished for the second time 10: Final polishing equipment 20: Polishing head 30: Polishing table 31: Polishing pad 40: Polishing liquid supply pipeline 50: First storage tank 60: Second storage tank 70: Third storage tank

The features and advantages of the embodiments of the present application will become easier to understand through the following description with reference to the accompanying drawings. The accompanying drawings are not drawn to scale and some features may be enlarged or reduced to show the details of specific components. In the accompanying drawings:

FIG. 1 is a schematic diagram of a final polishing device according to the related art.

FIG. 2 is a schematic cross-sectional view of a polished wafer obtained by a processing method for a final polishing process using related technology.

FIG. 3 exemplarily shows the schematic morphological features of a single DIC defect formed on a polished wafer.

FIG. 4 is a flow chart of a processing method for a final polishing process according to an embodiment of the present application.

FIG5 is a comparison diagram of DIC defect test results of a series of polished wafers obtained by a processing method for a final polishing process using related technologies and a series of polished wafers obtained by a processing method for a final polishing process according to an embodiment of the present application.

FIG6 is another comparison diagram of DIC defect test results of a series of polished wafers obtained by using a processing method for a final polishing process using related technologies and a series of polished wafers obtained by using a processing method for a final polishing process according to an embodiment of the present application.

FIG. 7 is a diagram showing the distribution of DIC defects on the surface of a polished wafer obtained by using a processing method for a final polishing process using the related art.

FIG. 8 is a schematic diagram showing the distribution of DIC defects on the surface of a polished wafer obtained by using the processing method for the final polishing process according to an embodiment of the present application.

FIG. 9 is a schematic diagram of an exemplary final polishing apparatus for performing a processing method for a final polishing process according to an embodiment of the present application.

In the accompanying drawings, the same or corresponding technical features or components are represented by the same or corresponding drawing marks.

S100: Use the first polishing liquid to perform the first polishing on the wafer S200: Use the second polishing liquid to perform the second polishing on the wafer that has been first polished S300: Use the third polishing liquid to perform the third polishing on the wafer that has been second polished

Claims (10)

A processing method for a final polishing process, comprising: Performing a first polishing on a wafer using a first polishing liquid; Performing a second polishing on the wafer after the first polishing using a second polishing liquid; and Performing a third polishing on the wafer after the second polishing using a third polishing liquid, wherein both the first polishing liquid and the second polishing liquid include an alkaline additive, and the third polishing liquid does not include an alkaline additive. A processing method for a final polishing process as described in claim 1, wherein the volume ratio of the alkaline additive to the solvent in the first polishing solution is greater than the volume ratio of the alkaline additive to the solvent in the second polishing solution. A processing method for a final polishing process as described in claim 1, wherein the volume ratio of the alkaline additive to the solvent in the first polishing liquid is in the range of 1:2500 to 1:1500, and the volume ratio of the alkaline additive to the solvent in the second polishing liquid is in the range of 1:5000 to 1:2500. The processing method for the final polishing process as described in claim 1, wherein the alkaline additive is an inorganic base or an organic base. The processing method for the final polishing process as described in claim 1, wherein the alkaline additive includes KOH, NaOH or NH ₄ OH. A processing method for a final polishing process as described in claim 1, wherein the first polishing is performed with a first target removal thickness, the second polishing is performed with a second target removal thickness, and the third polishing is performed with a third target removal thickness, wherein the first target removal thickness is greater than the second target removal thickness, and the second target removal thickness is greater than the third target removal thickness. A processing method for a final polishing process as described in claim 6, wherein the ratio of the first target removal thickness, the second target removal thickness and the third target removal thickness is 6:3:1. A processing method for a final polishing process as described in claim 6, wherein the sum of the first target removal thickness, the second target removal thickness and the third target removal thickness is greater than 150% of the thickness of the damaged layer of the wafer to be subjected to the first polishing. A polished wafer, obtained according to the processing method for a final polishing process as described in any one of claims 1 to 8, wherein the number of DIC defects with a size of 5 nm or more on the polished wafer is less than 5. As described in claim 9, the number of DIC defects with a size of more than 5nm on the polished wafer is less than 3.