TWI889699B - Semiconductor package including capacitor - Google Patents

Abstract

A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a sub molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the sub molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the sub molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the sub molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.

Description

Semiconductor package including capacitor

This application relates to semiconductor packages, and more particularly, to semiconductor packages including capacitors.

Cross-references to related applications

This application claims priority to Korean Patent Application No. 10-2020-0061540, filed on May 22, 2020, the entire contents of which are incorporated herein by reference.

Recently, demands for high-speed operation and large-capacity data processing in semiconductor devices have increased. To this end, there is a need to increase the number of signals sent simultaneously to semiconductor devices or the signal transmission speed.

However, as semiconductor devices operate at higher speeds and the number of signals transmitted simultaneously increases, power/ground noise increases. Therefore, a method currently used is to add capacitors (i.e., decoupling capacitors) to the power transmission path to stabilize the power/ground supply.

In an embodiment, a semiconductor package may include: a substrate; a sub-semiconductor package disposed above the substrate, the sub-semiconductor package including: a sub-semiconductor chip having a die pad on its upper surface; a sub-mold layer surrounding a side surface of the sub-semiconductor chip; and a redistribution layer formed above the sub-semiconductor chip and the sub-mold layer, the redistribution layer including a redistribution conductive layer connected to the die pad of the sub-semiconductor chip and extending to the edge of the sub-mold layer. The invention also includes a sub-package interconnect connected to the redistribution pad to electrically connect the sub-semiconductor chip and the substrate; a capacitor formed in the sub-mold layer and including a first electrode, a second electrode, and a main body portion between the first electrode and the second electrode, the first electrode and the second electrode having upper surfaces respectively connected to the redistribution conductive layer; and at least one main semiconductor chip formed above the sub-semiconductor package and electrically connected to the substrate.

100:Substrate

102: Upper surface substrate pad

104: Lower surface substrate pad

110: Semiconductor package

114: Semiconductor Chip

115: Sub-chip pad

115-G: Ground daughter chip pad

115-P: Power sub-chip pad

115-S: Signal sub-chip pad

116:Sub molding layer

117: Sub-package interconnection parts

118: Redistribution Structure

118A: First distributed insulating layer

118B: Redistributed Conductive Layer

118B-G: Ground redistribution conductive layer

118BP: Redistribution Pad

118B-P: Power redistribution conductive layer

118BP-G: Ground redistribution pad

118BP-P: Power redistribution pad

118BP-S: Signal redistribution pad

118B-S: Signal redistribution conducting layer

118C: Second distribution insulating layer

120: First chip layer stack

122: First adhesive layer

124: First main semiconductor chip

125: First chip pad

127: First interconnection element

130: Second chip layer stack

132: Second adhesive layer

134: Second main semiconductor chip

135: Second chip pad

137: Second interconnection

140: External connection terminal

150: Molding layer

160:Capacitor

160': Capacitor

162: First electrode

164: Second electrode

166: Main body

200:Substrate

200':Substrate

210: Semiconductor package

214: Semiconductor Chip

215: Sub-chip pad

215-G: Ground daughter chip pad

215-P: Power sub-chip pad

215-S: Signal sub-chip pad

216:Sub molding layer

217: First sub-package interconnection part

217': First sub-package interconnection part

218A: First distributed insulating layer

218B: Redistributed Conductive Layer

218B': Redistributed Conductive Layer

218B-G: Ground redistribution conductive layer

218BP: Redistribution Pad

218B-P: Power redistribution conductive layer

218BP-G: Ground redistribution pad

218BP-P: Power redistribution pad

218BP-S: Signal redistribution pad

218B-S: Signal redistribution conducting layer

218C: Second distribution insulating layer

220: First chip layer stack

222: First adhesive layer

224: First main semiconductor chip

225: First chip pad

227: First interconnection

230: Second chip layer stack

232: Second adhesive layer

234: Second main semiconductor chip

235: Second chip pad

237: Second interconnection

240: External connection terminal

240': External connection terminal

250: Molding layer

260:Capacitor

262: First electrode

264: Second electrode

266: Main body

270: Sub-via

280: Second sub-package interconnection part

281: Virtual second sub-package interconnection

300:Substrate

300':Substrate

310: Semiconductor package

314: Semiconductor Chip

315: Sub-chip pad

315-G: Grounding daughter chip pad

315-S: Signal sub-chip pad

316:Sub molding layer

317: First sub-package interconnection part

317': First sub-package interconnection part

318A: First distributed insulating layer

318B: Redistributed Conductive Layer

318B': Redistributed Conductive Layer

318B-G: Ground redistribution conductive layer

318BP: Redistribution Pad

318B-P: Power redistribution conductive layer

318BP-G: Ground redistribution pad

318BP-P: Power redistribution pad

318BP-S: Signal redistribution pad

318B-S: Signal redistribution conducting layer

318C: Second distribution insulating layer

320: First chip layer stack

322: First adhesive layer

324: First main semiconductor chip

325: First chip pad

327: First interconnection

330: Second chip layer stack

332: Second adhesive layer

334: Second main semiconductor chip

335: Second chip pad

337: Second interconnection

340: External connection terminal

350: Molding layer

360:Capacitor

362: First electrode

364: Second electrode

370: Sub-via

380: Second sub-package interconnection part

381: Virtual second sub-package interconnection

7800:Memory Card

7810:Memory

7820:Memory controller

7830:Host

8710: Electronic Systems

8711: Controller

8712: Input/Output Device

8713:Memory

8714: Interface

8715: Bus

[Figure 1] is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure.

FIG2 is a plan view illustrating a portion of the semiconductor package shown in FIG1 omitting the first chip stack, the second chip stack, and the interconnects connecting the first chip stack and the second chip stack.

[Figure 3] is a cross-sectional view illustrating the semiconductor package shown in Figure 1.

[Figure 4] is a plan view illustrating the sub-semiconductor package of Figure 1.

FIG5 is a cross-sectional view taken along line A2-A2 ′ in FIG4.

FIG6 is a cross-sectional view taken along line A3-A3 ′ in FIG4.

FIG. 7A is a diagram illustrating an example of the effects of a semiconductor package according to an embodiment of the present disclosure.

[Figure 7B] is a diagram illustrating the effects of the semiconductor package according to the comparative example.

[Figure 8] is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure.

[Figure 9] is a plan view illustrating the sub-semiconductor package of Figure 8.

FIG. 10 is a cross-sectional view taken along line A4-A4 ′ of FIG. 9 .

[FIG. 11] is a cross-sectional view taken along line A5-A5 ' of FIG. 9.

FIG12A is a diagram illustrating an example of the effects of a semiconductor package according to another embodiment of the present disclosure.

[Figure 12B] is a diagram illustrating the effects of the semiconductor package according to the comparative example.

FIG13 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure.

FIG14 is a plan view illustrating a sub-semiconductor package in a semiconductor package according to another embodiment of the present disclosure.

FIG. 15 is a cross-sectional view taken along line A6-A6 ′ of FIG. 14 .

[Figure 16] is a cross-sectional view taken along line A7-A7 ' of Figure 14.

FIG. 17A is a diagram illustrating an example of the effects of a semiconductor package according to another embodiment of the present disclosure.

[Figure 17B] is a diagram used to illustrate the effects of the semiconductor package of the comparative example.

[Figure 18] shows a block diagram of an exemplary electronic system that employs a memory card including a semiconductor package according to an embodiment.

FIG19 is a block diagram illustrating another electronic system including a semiconductor package according to an embodiment.

Hereinafter, various implementations of the present disclosure will be described in detail with reference to the accompanying drawings.

The drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may have been exaggerated to clearly illustrate certain features of the described embodiments. When a particular example is presented in a drawing or description of two or more layers of a multi-layer structure, the relative positional relationships of such layers or the arrangement order of such layers shown reflects the particular implementation of the example being described or illustrated, and different relative positional relationships or arrangement orders of such layers may be possible. Additionally, a described or illustrated example of a multi-layer structure may not reflect all layers present in the particular multi-layer structure (e.g., one or more additional layers may be present between two illustrated layers). As a specific example, when a first layer in a described or illustrated multi-layer structure is referred to as being "on" or "over" a second layer or "on" or "over" a substrate, the first layer may be formed directly on the second layer or substrate, but may also refer to a structure in which one or more other intermediate layers may be present between the first layer and the second layer or substrate.

FIG1 is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure. FIG2 is a plan view illustrating a portion of the semiconductor package shown in FIG1 omitting the first chip stack, the second chip stack, and the interconnects connected to the first chip stack and the second chip stack. FIG3 is a cross-sectional view illustrating the semiconductor package of FIG1 . FIG1 and FIG2 are top views of the semiconductor package and a portion thereof, respectively. FIG3 illustrates a cross section taken along line A1-A1 ′ of FIG1 and FIG2 . FIG4 is a plan view illustrating the sub-semiconductor package of FIG1 , FIG5 is a cross-sectional view taken along line A2-A2 ′ of FIG4 , and FIG6 is a cross-sectional view taken along line A3-A3 ′ of FIG4 .

First, referring to Figures 1 to 3, a semiconductor package according to an embodiment of the present disclosure may include a substrate 100, a sub-semiconductor package 110 disposed above the substrate 100, and a first chip stack 120 and a second chip stack 130 disposed above the sub-semiconductor package 110.

The substrate 100 may be a substrate such as a printed circuit board (PCB) used in a semiconductor package, which has circuits and/or wiring structures for transmitting electrical signals.

The substrate 100 may have an upper surface and a lower surface opposite the upper surface. The sub-semiconductor package 110, the first chip stack 120, and the second chip stack 130 may be disposed above the upper surface of the substrate 100. External connection terminals 140 for connecting the semiconductor package to the outside world may be disposed above the lower surface of the substrate 100. For reference, the upper and lower surfaces described below are used to indicate the relative positions of the respective surfaces of the components and do not indicate absolute positions. For example, if the semiconductor package is turned upside down, unlike in the illustration, the surface on which the sub-semiconductor package 110, the first chip stack 120, and the second chip stack 130 are disposed may be the lower surface of the substrate 100, and the surface on which the external connection terminals 140 are disposed may be the upper surface of the substrate 100.

The substrate 100 may include an upper surface substrate pad 102 and a lower surface substrate pad 104. The upper surface substrate pad 102 may be disposed on the upper surface of the substrate 100 to electrically connect the sub-semiconductor package 110, the first chip stack 120, and the second chip stack 130 to the substrate 100. The lower surface substrate pad 104 may be disposed on the lower surface of the substrate 100 to electrically connect the external connection terminal 140 to the substrate 100. For reference, the substrate pad may mean a conductive element or terminal exposed on the surface of the substrate 100 to electrically connect the substrate 100 to other components. As an example, the upper surface substrate pad 102 may be a bonding finger for wire bonding, and the lower surface substrate pad 104 may be a ball land for bonding with a solder ball. The upper substrate pad 102 and the lower substrate pad 104 can be connected to the circuits and/or wiring structures inside the substrate 100.

The upper surface substrate pad 102 can be arranged on two side edges of the substrate 100 that do not overlap with the sub-semiconductor package 110. For example, the upper surface substrate pad 102 can be arranged on two side edges of the substrate 100 in the first direction. For reference, the first side of the two sides in the first direction can correspond to the upper side of Figures 1 and 2, and the left side of Figure 3. In addition, the second side of the two sides in the first direction can correspond to the lower side of Figures 1 and 2, and the right side of Figure 3. In this embodiment, the upper surface substrate pad 102 can be arranged in a row on each side of the two side edges of the substrate 100 in a second direction intersecting the first direction. However, this embodiment is not limited to this. The number, arrangement, etc. of the upper surface substrate pads 102 can be varied in various ways on each of the two side edges of the substrate 100.

The sub-semiconductor package 110 may have a smaller planar area than the upper surface of the substrate 100. The sub-semiconductor package 110 may be disposed to expose at least two side edges of the substrate 100 in a first direction and/or the upper surface substrate pad 102. For example, the sub-semiconductor package 110 may be disposed in the central region of the substrate 100. The sub-semiconductor package 110 may be attached to the upper surface of the substrate 100 via an insulating adhesive material (not shown), such as a die attach film (DAF).

The sub-semiconductor package 110 may include a sub-semiconductor chip 114, a sub-mold layer 116 surrounding the lower surface and side surfaces of the sub-semiconductor chip 114, and a redistribution structure 118 formed over the upper surfaces of the sub-semiconductor chip 114 and the sub-mold layer 116.

The sub-semiconductor chip 114 may be a semiconductor chip that performs various functions required for the operation of the first main semiconductor chip 124 and/or the second main semiconductor chip 134. As an example, if each of the first main semiconductor chip 124 and the second main semiconductor chip 124 includes a non-volatile memory such as an inverted flash memory, the sub-semiconductor chip 114 may include a controller for controlling the first main semiconductor chip 124 and the second main semiconductor chip 134. However, the present embodiment is not limited thereto, and the sub-semiconductor chip 114 may include volatile memories such as dynamic random access memory (DRAM) and static RAM (SRAM), non-volatile memories such as inverted-and-unintegrated flash memory, resistive RAM (RRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), and ferroelectric RAM (FRAM), or other various active or passive components.

The sub-semiconductor wafer 114 may have a lower surface facing the upper surface of the substrate 100, an upper surface opposite the lower surface, and a side surface connecting the upper and lower surfaces. In this embodiment, the sub-semiconductor wafer 114 may have four side surfaces. The four side surfaces may be located on two sides in the first direction and two sides in the second direction, respectively. For reference, the first side of the two sides in the second direction may correspond to the right side in Figures 1 and 2, while the second side of the two sides in the second direction may correspond to the left side in Figures 1 and 2.

The sub-semiconductor chip 114 can be located in the central area of the sub-semiconductor package 110. This is to ensure that the lengths of the redistributed conductive layers 118B, which will be described later, are as similar as possible.

Sub-die pads 115 can be provided on the upper surface of sub-semiconductor wafer 114. Sub-semiconductor wafer 114 can have a relatively small planar surface area, while the number of sub-die pads 115 can be relatively large. For example, let's assume that sub-semiconductor wafer 114 is a memory controller, and first main semiconductor wafer 124 and second main semiconductor wafer 134 are memory devices. In this case, while the size of sub-semiconductor wafer 114 decreases with technological advancement, a large number of sub-die pads 115 may be required to accommodate a large number of input/output signals, thereby connecting the corresponding first and second wafer stacks 120 and 130 to sub-semiconductor wafer 114 via independent channels. Due to this fact, the sub-wafer pad 115 can be arranged along the entire edge of the sub-semiconductor wafer 114. That is, the sub-wafer pad 115 can be arranged along the first side edge and the second side edge of the sub-semiconductor wafer 114 in the first direction, and along the first side edge and the second side edge of the sub-semiconductor wafer 114 in the second direction.

The sub-mold layer 116 may have an upper surface substantially at the same height as the upper surface of the sub-semiconductor chip 114 while surrounding the side surfaces of the sub-semiconductor chip 114. Therefore, the sub-mold layer 116 may expose the sub-die pad 115 and the upper surface of the sub-semiconductor chip 114. In this embodiment, the sub-mold layer 116 may cover the lower surface of the sub-semiconductor chip 114. However, this embodiment is not limited thereto. In another embodiment, the sub-mold layer 116 may have a lower surface substantially at the same height as the lower surface of the sub-semiconductor chip 114. The sub-mold layer 116 may include various molding materials such as epoxy molding compound (EMC).

The redistribution structure 118 can extend onto the upper surface of the sub-mold layer 116 while being electrically connected to the sub-die pad 115. In other words, the sub-semiconductor package 110 according to this embodiment can be a fan-out package.

In detail, the redistributed structure 118 may include a first redistributed insulating layer 118A, a redistributed conductive layer 118B, and a second redistributed insulating layer 118C. The first redistributed insulating layer 118A may be formed above the upper surfaces of the semiconductor sub-wafer 114 and the mold sub-layer 116. The first redistributed insulating layer 118A may have an opening that exposes the sub-wafer pad 115. The redistributed conductive layer 118B may be formed above the first redistributed insulating layer 118A. The redistributed conductive layer 118B may be electrically connected to the sub-wafer pad 115 through the opening of the first redistributed insulating layer 118A. Second redistributed insulating layer 118C may cover first redistributed insulating layer 118A and redistributed conductive layer 118B. Second redistributed insulating layer 118C may have an opening that exposes an end of redistributed conductive layer 118B. First redistributed insulating layer 118A and second redistributed insulating layer 118C may include insulating materials such as oxide, nitride, or oxynitride. Alternatively, the first redistributed insulating layer 118A and the second redistributed insulating layer 118C may include a resin material such as epoxy, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), silicone, or acrylate. The redistributed conductive layer 118B may include a metal material such as gold, copper, or a copper alloy.

Specifically, the portion of the redistributed conductive layer 118B exposed through the opening in the second redistributed insulating layer 118C is hereinafter referred to as a redistributed pad 118BP. The redistributed conductive layer 118B may extend from the daughter chip pad 115, and each redistributed conductive layer 118B may have a relatively narrow linear portion and a relatively wide plate-shaped end portion located at the end of the linear portion. The opening in the second redistributed insulating layer 118C may expose the plate-shaped end portion of the redistributed conductive layer 118B and may have a planar area that is smaller than or equal to the planar area of the plate-shaped end portion while overlapping the plate-shaped end portion. For ease of illustration, the first and second redistribution insulating layers 118A and 118C of the redistribution structure 118 are not shown in the top views of Figures 1 and 2. Similar to the arrangement of the upper substrate pads 102, the redistribution pads 118BP can be disposed on the first and second side edges of the sub-mold layer 116 in the first direction. Furthermore, the redistribution pads 118BP can be arranged in a row along the second direction at each of the first and second side edges of the sub-mold layer 116. However, the present disclosure is not limited thereto, and the number, arrangement, etc. of the redistribution pads 118BP at each of the first side edge and the second side edge of the sub-mold layer 116 may be varied in various ways.

Depending on the arrangement of the redistribution pads 118BP, the redistribution conductive layer 118B can extend from the sub-wafer pad 115 disposed at the first side edge of the sub-semiconductor wafer 114 in the first and second directions to the redistribution pad 118BP disposed at the first side edge of the sub-mold layer 116 in the first direction. Furthermore, the redistribution conductive layer 118B can extend from the sub-wafer pad 115 disposed at the second side edge of the sub-semiconductor wafer 114 in the first and second directions to the redistribution pad 118BP disposed at the second side edge of the sub-mold layer 116 in the first direction. The redistributed conductive layer 118B extending from the side edges of the sub-semiconductor wafer 114 in the second direction can be curved toward the redistribution pad 118BP. Furthermore, the redistributed conductive layer 118B extending from the side edges of the sub-semiconductor wafer 114 in the first direction does not need to be curved, as these redistributed conductive layers 118B face the redistribution pad 118BP. However, the redistributed conductive layer 118B extending from the side edges of the sub-semiconductor wafer 114 in the first direction can also be curved to have a length similar to that of the redistributed conductive layer 118B extending from the side edges of the sub-semiconductor wafer 114 in the second direction. As a result, the redistributed conductive layer 118B can have a tornado-like shape, for example, a spiral shape, centered around the sub-semiconductor chip 114. This connection scheme can minimize variations in the length of the redistributed conductive layer 118B.

The sub-package interconnect 117 can connect the redistribution pad 118BP and the upper substrate pad 102. This allows the sub-semiconductor die 114 and the substrate 100 to be electrically connected. The sub-package interconnect 117 can be a bonding wire having a first end connected to the upper substrate pad 102 and a second end connected to the redistribution pad 118BP. However, the present embodiment is not limited thereto, and various types of electrical interconnects can be used as the sub-package interconnect 117.

The first chip stack 120 may include a plurality of first main semiconductor chips 124. The first main semiconductor chips 124 may be formed above the sub-semiconductor package 110 and may be stacked vertically relative to the upper surface of the substrate 100. Although the present embodiment illustrates a case where the first chip stack 120 includes four first main semiconductor chips 124, the present disclosure is not limited thereto, and the number of first main semiconductor chips 124 included in the first chip stack 120 may be varied in various ways to include one or more first main semiconductor chips 124.

Each of the first main semiconductor chips 124 may include an inverting and dropping flash memory as described above. However, the present disclosure is not limited thereto, and each of the first main semiconductor chips 124 may include a volatile memory such as dynamic random access memory (DRAM) and static RAM (SRAM), or a non-volatile memory such as resistive RAM (RRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), and ferroelectric RAM (FRAM).

The first main semiconductor chips 124 can be stacked with a predetermined offset in a direction toward a second side in the first direction (e.g., toward the bottom in FIG. 1 and the right in FIG. 3 ). This allows the first chip stack 120 to have a stepped shape when viewed overall. The offset stacking direction of the first main semiconductor chips 124 can be referred to as the first offset direction. Due to this offset stacking, the first side edge of the top surface of each of the first main semiconductor chips 124, except for the topmost first main semiconductor chip 124, is exposed without being covered by the first main semiconductor chip 124 immediately above it. For example, the upper side of the upper surface of each of the remaining first main semiconductor chips 124 in FIG1 and the left side of the upper surface of each of the remaining first main semiconductor chips 124 in FIG3 can be exposed. The first side edge of the upper surface of the uppermost first main semiconductor chip 124 can be exposed without being covered by the lowermost second main semiconductor chip 134 of the second chip stack 130 to be described later. The first chip pad 125 can be set on such an exposed portion of the first main semiconductor chip 124. A plurality of first chip pads 125 can be arranged in a row at the first side edge of the upper surface of each first main semiconductor chip 124 in the second direction. However, the present disclosure is not limited thereto, and the number and arrangement of the first wafer pads 125 at the first side edge of the upper surface of each first main semiconductor wafer 124 may be variously modified. For reference, because the portion of the first wafer stack 120 hidden by the second wafer stack 130 is not illustrated in the top view of FIG. 1 , a portion of the first wafer stack 120, for example, the first side edge portion of the lowermost first main semiconductor wafer 124, is illustrated.

Each first main semiconductor chip 124 may be attached to the sub-semiconductor package 110 or the first main semiconductor chip 124 positioned immediately below it via a first adhesive layer 122. The first adhesive layer 122 may be formed on the lower surface of each first main semiconductor chip 124 to have a shape overlapping the lower surface.

The first chip stack 120 or the first main semiconductor chip 124 may have a smaller planar area than the sub-semiconductor package 110 and may have a larger planar area than the sub-semiconductor chip 114. The first chip stack 120 may be configured to expose at least the redistribution pads 118BP disposed at both side edges of the sub-semiconductor package 110 in the first direction.

The first interconnect 127 can connect vertically adjacent first die pads 125 to one another and can electrically connect the first die pad 125 of the lowermost first main semiconductor die 124 to the upper surface substrate pad 102 located at the first side edge of the substrate 100 in the first direction. This allows the first main semiconductor die 124 to be electrically connected to one another, and the first die stack 120 to be electrically connected to the substrate 100. The first interconnect 127 can be a bonding wire. However, this embodiment is not limited thereto, and various types of electrical interconnects can be used as the first interconnect 127.

The second chip stack 130 may include a plurality of second main semiconductor chips 134. The second main semiconductor chips 134 may be formed above the first chip stack 120 and may be stacked in a vertical direction. Although the present embodiment illustrates a case where the second chip stack 130 includes four second main semiconductor chips 134, the present disclosure is not limited thereto, and the number of second main semiconductor chips 134 included in the second chip stack 130 may be changed to one or more second main semiconductor chips 134 in various ways. In addition, although in the present embodiment, the number of second main semiconductor chips 134 included in the second chip stack 130 is the same as the number of first main semiconductor chips 124 included in the first chip stack 120, it should be noted that these numbers may be different from each other.

Each second main semiconductor chip 134 may include an inverting flash memory as described above. However, the present disclosure is not limited thereto, and each second main semiconductor chip 134 may include a volatile memory such as dynamic random access memory (DRAM) and static RAM (SRAM), or a non-volatile memory such as resistive RAM (RRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), and ferroelectric RAM (FRAM). In this embodiment, the second main semiconductor chip 134 is the same semiconductor chip as the first main semiconductor chip 124. However, in another embodiment, the second main semiconductor chip 134 may be a different semiconductor chip from the first main semiconductor chip 124.

The second main semiconductor chips 134 can be stacked with a predetermined offset in a direction toward the first side in the first direction (for example, toward the upper side in FIG. 1 and the left side in FIG. 3 ). This allows the second chip stack 130 to have a stepped shape when viewed overall. The offset stacking direction of the second main semiconductor chips 134 can be referred to as a second offset direction. The second offset direction can be opposite to the first offset direction. Due to this offset stacking, the second side of the top surface of each of the second main semiconductor chips 134, except for the uppermost second main semiconductor chip 134, can be exposed without being covered by the second main semiconductor chip 134 immediately above it. For example, the lower edge of the upper surface of each of the remaining second main semiconductor chips 134 in Figure 1 and the right edge of the upper surface of each of the remaining second main semiconductor chips 134 in Figure 3 can be exposed. The uppermost second main semiconductor chip 134 can be in a state where its entire upper surface is exposed. The second chip pads 135 can be arranged on the exposed portions of the remaining second main semiconductor chips 134 except the uppermost second main semiconductor chip 134, and the second chip pad 135 of the uppermost second main semiconductor chip 134 can also be arranged at the same position as the second chip pads 135 of the remaining second main semiconductor chips 134. Multiple second chip pads 135 can be arranged in a row at the second side edge of the upper surface of each second main semiconductor chip 134 in the second direction. However, the present disclosure is not limited thereto, and the number and arrangement of the second chip pads 135 at the second side edge of the upper surface of each second main semiconductor chip 134 may be varied in various ways.

In the case where the second main semiconductor wafer 134 is the same semiconductor wafer as the first main semiconductor wafer 124, each second main semiconductor wafer 134 may correspond to a state in which each first main semiconductor wafer 124 is rotated 180 degrees around an axis extending in the vertical direction.

Each second main semiconductor chip 134 may be attached to the second main semiconductor chip 134 immediately below it or the uppermost first main semiconductor chip 124 of the first chip stack 120 via a second adhesive layer 132. The second adhesive layer 132 may be formed on the lower surface of each second main semiconductor chip 134 to have a shape overlapping the lower surface.

The second wafer stack 130 or the second main semiconductor wafer 134 may have a smaller planar area than the sub-semiconductor package 110 and a larger planar area than the sub-semiconductor wafer 114. The second wafer stack 130 may be configured to expose at least two side edges of the sub-semiconductor package 110 in the first direction. In other words, the second wafer stack 130 may be configured to expose the redistribution pad 118BP.

The second interconnect 137 can connect vertically adjacent second die pads 135 to each other and can electrically connect the second die pad 135 of the lowermost second main semiconductor die 134 to the upper surface substrate pad 102 located at the second side edge of the substrate 100 in the first direction. This allows the second main semiconductor die 134 to be electrically connected to each other, and the second die stack 130 to be electrically connected to the substrate 100. The second interconnect 137 can be a bonding wire. However, the present embodiment is not limited thereto, and various types of electrical interconnects can be used as the second interconnect 137.

In the top views of Figures 1 and 2, sub-package interconnect 117, first interconnect 127, and second interconnect 137 are illustrated with solid and dashed lines for easy distinction. However, it should be noted that such solid and dashed lines do not reflect the actual shapes of interconnects 117, 127, and 137.

The sub-semiconductor package 110, the first chip stack 120, and the second chip stack 130 may be covered by a molding layer 150 formed over the substrate 100. The molding layer 150 may include various molding materials such as EMC.

The external connection terminals 140 may include solder balls. However, the present disclosure is not limited thereto, and various conductive terminals such as bumps may be used as the external connection terminals 140.

In the semiconductor package described above, the first die stack 120 can be identified as a single semiconductor die and is connected to the top substrate pad 102 of the substrate 100 via a first interconnect 127. Furthermore, the second die stack 130 can be identified as another single semiconductor die different from the first die stack 120 and is connected to the top substrate pad 102 of the substrate 100 via a second interconnect 137. The sub-semiconductor die 114 can be connected to the top substrate pad 102 of the substrate 100 via a redistribution structure 118 and a sub-package interconnect 117.

Furthermore, in the semiconductor package described above, sub-package interconnect 117 may be individually connected to top substrate pad 102, first interconnect 127 may be individually connected to top substrate pad 102, second interconnect 137 may be individually connected to top substrate pad 102, sub-package interconnect 117 and first interconnect 127 may be jointly connected to top substrate pad 102, or sub-package interconnect 117 and second interconnect 137 may be jointly connected to top substrate pad 102. Top substrate pad 102 individually connected to sub-package interconnect 117 can serve as a power supply voltage pad or a signal transmission pad for sub-semiconductor die 114. The top substrate pad 102 connected solely to the first interconnect 127 can be used as a power voltage supply pad or a signal transmission pad for the first wafer stack 120. The top substrate pad 102 connected solely to the second interconnect 137 can be used as a power voltage supply pad or a signal transmission pad for the second wafer stack 130. The top substrate pad 102 connected jointly to the sub-package interconnect 117 and the first interconnect 127, and/or the top substrate pad 102 connected jointly to the sub-package interconnect 117 and the second interconnect 137, can be used as a ground voltage supply pad. This may mean supplying power or transmitting signals from the substrate 100 to each of the sub-semiconductor die 114, the first die stack 120, and the second die stack 130.

Specifically, power can be supplied or signals can be transmitted to the sub-semiconductor die 114 via the redistributed conductive layer 118B. However, because a large number of redistributed conductive layers 118B are arranged in a limited space, the pitch and/or line width of the redistributed conductive layer 118B may be reduced. In this case, the impedance of the redistributed conductive layer 118B may increase, thereby potentially causing power supply interruptions. To address this issue, as shown in the plan view of FIG. 2 , the sub-semiconductor package 110 may further include a capacitor (see the dashed square) connected to the redistributed conductive layer 118B. The capacitor will be described in more detail below with reference to FIG. 4 to FIG. 6 .

4 to 6 , the sub-die pad 115 on the upper surface of the semiconductor sub-die 114 may include a signal sub-die pad 115-S, a ground sub-die pad 115-G, and a power sub-die pad 115-P. The redistribution conductive layer 118B may include a signal redistribution conductive layer 118B-S connected to the signal sub-die pad 115-S, a ground redistribution conductive layer 118B-G connected to the ground sub-die pad 115-G, and a power redistribution conductive layer 118B-P connected to the power sub-die pad 115-P. Signal redistribution pads 118BP-S may be disposed at the ends of signal redistribution conductive layers 118B-S, ground redistribution pads 118BP-G may be disposed at the ends of ground redistribution conductive layers 118B-G, and power redistribution pads 118BP-P may be disposed at the ends of power redistribution conductive layers 118B-P. The sub-semiconductor die 114 may receive signals from the substrate (see 100 in Figures 1 to 3) via the signal redistribution conductive layers 118B-S. Furthermore, a ground voltage may be provided to the sub-semiconductor die 114 from the substrate (see 100 in Figures 1 to 3) via the ground redistribution conductive layers 118B-G. Furthermore, power voltage can be supplied from the substrate (see 100 in Figures 1 through 3) to the sub-semiconductor die 114 via the power redistribution conductive layers 118B-P. In other words, the ground redistribution conductive layers 118B-G and the power redistribution conductive layers 118B-P can correspond to a power supply path from the substrate 100 to the sub-semiconductor die 114.

A capacitor 160, including a first electrode 162, a second electrode 164, and a main body 166 therebetween, may be provided in the sub-mold layer 116. Main body 166 may have various structures as long as it can store charge according to the voltage applied to first electrode 162 and second electrode 164. For example, capacitor 160 may be an MLCC (multi-layer ceramic capacitor). In this case, main body 166 may have a structure in which multiple ceramic dielectric layers and multiple internal electrodes are alternately stacked.

Capacitor 160 may be embedded in sub-mold layer 116 along with sub-semiconductor chip 114. That is, the side surfaces and bottom surface of capacitor 160 may be surrounded by sub-mold layer 116. Meanwhile, the top surface of capacitor 160 (specifically, the top surfaces of first electrode 162 and second electrode 164) may be exposed by being located at substantially the same height as the top surface of sub-mold layer 116. The top surface of first electrode 162 may be connected to ground redistribution conductive layers 118B-G, and the top surface of second electrode 164 may be connected to power redistribution conductive layers 118B-P. More specifically, the ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P can be connected to the upper surfaces of the first electrode 162 and the upper surfaces of the second electrode 164, respectively, through openings in the first redistribution insulating layer 118A. Meanwhile, the main body 166 can be insulated from the redistribution conductive layer 118B. To this end, the portion of the first redistribution insulating layer 118A corresponding to the main body 166 may not have any openings. For reference, and for ease of description, the first electrode 162 of the capacitor 160 is represented by a non-shaded rectangle, and the second electrode 164 of the capacitor 160 is represented by a shaded rectangle. However, the shadow is only used to distinguish the first electrode 162 from the second electrode 164. In addition, the planar shapes of the first electrode 162 and the second electrode 164 can also be changed in various ways.

As described above, the redistributed conductive layer 118B can also be connected to the daughter die pad 115 through the openings in the first redistributed insulating layer 118A. Therefore, the upper surfaces of the first electrode 162 and the second electrode 164 can be located at substantially the same height as the upper surface of the daughter die pad 115. The upper surface of the main body portion 166 can be located at a lower level than the upper surfaces of the first electrode 162 and/or the second electrode 164, as shown. In this case, the first redistributed insulating layer 118A and the sub-mold layer 116 can be interposed between the main body portion 166 and the redistributed conductive layer 118B. However, in another embodiment, the upper surface of the main body portion 166 may be located at substantially the same height as the upper surface of the first electrode 162 and/or the second electrode 164.

Capacitor 160 can be connected to sub-die pad 115, which supplies power and ground voltage to sub-semiconductor die 114. It can also prevent power shortages during sub-semiconductor die 114 operation. When capacitor 160 is placed adjacent to sub-semiconductor die 114, the power supply path can be shortened, allowing for more efficient performance. In this embodiment, capacitor 160 can be placed closer to sub-die pad 115 than to weight distribution pad 118BP.

In this embodiment, four capacitors 160 may be respectively disposed to face the four side surfaces of the sub-semiconductor chip 114. However, the present disclosure is not limited thereto, and the number and position of the capacitors 160 may be modified in various ways.

Furthermore, one or more signal redistribution conductive layers 118B-S may be disposed between the ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P. The ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P may shield the signal redistribution conductive layer 118B-S therebetween. Consequently, interference between a signal redistribution conductive layer 118B-S disposed between the ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P and another signal redistribution conductive layer 118B-S may be suppressed. For reference, in this case, the main body portion 166 may overlap with one or more signal redistribution conductive layers 118B-S disposed between the ground redistribution conductive layers 118B-G and the power redistribution conductive layers 118B-P.

The above-mentioned semiconductor package can achieve the following effects.

First, because the daughter pads 115 are arranged along the entire edge of the daughter semiconductor die 114, a relatively large number of them can be provided compared to the size of the daughter semiconductor die 114. Furthermore, by redistributing the daughter pads 115 using fan-out technology, connections between the daughter pads 115 and the die pads 125 and 135 of the main semiconductor dies 124 and 134 can be easily achieved. For example, if bond wires were directly connected to the daughter semiconductor die 114, the placement of the daughter pads 115 would be limited due to physical limitations such as the size and travel radius of the wiring capillaries. On the other hand, if the sub-die pad 115 is redistributed using redistribution pad 118BP through fan-out technology, as in this embodiment, the design can be unaffected by this limitation.

Furthermore, because the sub-semiconductor package 110, which is larger than the first main semiconductor die 124, is positioned below the first wafer stack 120 using fan-out technology, the first wafer stack 120 can be formed stably. In a structure where the first wafer stack 120 is formed on the sub-semiconductor die 114, if the sub-semiconductor die 114 is smaller than the first main semiconductor die 124, the first wafer stack 120 may tilt. By substantially increasing the area of the sub-semiconductor die 114 using fan-out technology, this problem can be avoided.

Furthermore, by adjusting the shape and/or layout of the redistributed conductive layer 118B connecting the sub-die pad 115 and the redistributed pad 118BP so that the redistributed conductive layer 118B has similar lengths, the operating characteristics of the semiconductor package can be maintained. For example, when there is a first via connecting from the first die stack 120 to the substrate 100 and a second via connecting from the second die stack 130 to the substrate 100, the paths of the first and second vias can have similar lengths. This minimizes the risk of signal (e.g., data) transmission rates varying from channel to channel.

Furthermore, by placing capacitor 160 adjacent to sub-semiconductor die 114 in sub-mold layer 116, power supply to sub-semiconductor die 114 can be facilitated even when the spacing and/or line width of redistributed conductive layer 118B is reduced.

Furthermore, by placing one or more signal redistribution conductive layers 118B-S between the ground redistribution conductive layer 118B-G and the power redistribution conductive layer 118B-P, interference between the signal redistribution conductive layers 118B-S can be suppressed.

Furthermore, compared to placing capacitors around sub-semiconductor package 110, when capacitor 160 is connected to the redistributed conductive layer 118B in sub-semiconductor package 110, as in this embodiment, the AC path through capacitor 160 can be shortened. Consequently, the impedance of the power supply path can be further reduced. This will be further described with reference to Figures 7A and 7B.

FIG7A is a diagram illustrating an example of the effect of a semiconductor package according to an embodiment of the present disclosure, and FIG7B is a diagram illustrating the effect of a semiconductor package according to a comparative example. FIG7B illustrates a case different from the present embodiment, in which a capacitor 160 ′ is individually provided around a sub-semiconductor package 110.

Referring to FIG. 7A , because capacitor 160 is connected to a certain point of each of ground redistribution conductive layers 118B-G and power redistribution conductive layers 118B-P, a short AC path (see dashed arrows) can be formed that passes through a portion of power redistribution conductive layers 118B-P, capacitor 160, and a portion of ground redistribution conductive layers 118B-G.

7B , a long AC path (see dotted arrow) can be formed that passes through the entire power redistribution conductive layer 118-P, the sub-package interconnect 117, the substrate 100, the external connection terminal 140 for providing a power voltage, the substrate 100, the capacitor 160 ′ , the substrate 100, the external connection terminal 140 for providing a ground voltage, the substrate 100, the sub-package interconnect 117, and the entire ground redistribution conductive layer 118B-G.

As a result, as shown in FIG7A , according to this embodiment, a short AC path can be formed through capacitor 160, thereby reducing the impedance of the power supply path. Therefore, power supply can be easily performed.

FIG8 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure. FIG9 is a plan view illustrating a sub-semiconductor package of FIG8 . FIG10 is a cross-sectional view taken along line A4-A4 ′ in FIG9 , and FIG11 is a cross-sectional view taken along line A5-A5 ′ in FIG9 . FIG8 is based on a cross section taken along line A1-A1 ′ in FIG1 . The following will primarily describe differences from the aforementioned embodiment.

First, referring to Figures 9 to 11 , the sub-semiconductor package 210 of this embodiment may include a sub-semiconductor die 214, a sub-mold layer 216 surrounding at least the side surface of the sub-semiconductor die 214, a redistributed structure comprising a first redistributed insulating layer 218A, a redistributed conductive layer 218B, and a second redistributed insulating layer 218C formed above the upper surfaces of the sub-semiconductor die 214 and the sub-mold layer 216, and a capacitor 260 disposed in the sub-mold layer 216 and comprising a first electrode 262, a second electrode 264, and a body portion 266 therebetween. A sub-die pad 215 may be disposed on the upper surface of the sub-semiconductor die 214. The daughter die pad 215 may include a signal daughter die pad 215-S, a ground daughter die pad 215-G, and a power daughter die pad 215-P. The redistribution conductive layer 218B may include a signal redistribution conductive layer 218B-S connected to the signal daughter die pad 215-S, a ground redistribution conductive layer 218-G connected to the ground daughter die pad 215-G, and a power redistribution conductive layer 218B-P connected to the power daughter die pad 215-P. Signal redistribution pad 218BP-S may be disposed at an end of signal redistribution conductive layer 218B-S, ground redistribution pad 218BP-G may be disposed at an end of ground redistribution conductive layer 218B-G, and power redistribution pad 218BP-P may be disposed at an end of power redistribution conductive layer 218B-P. Ground redistribution conductive layer 218B-G may be connected to ground sub-die pad 215-G and first electrode 262 of capacitor 260 through an opening in first redistribution insulating layer 218A. The power redistribution conductive layer 218B-P can be connected to the power sub-die pad 215-P and the second electrode 264 of the capacitor 260 through the opening of the first redistribution insulating layer 218A.

In addition, the sub-semiconductor package 210 may further include a sub-via 270 connected to the first electrode 262 and the second electrode 264 of the capacitor 260, respectively.

The upper surfaces of the sub-via 270 may be connected to the lower surfaces of the first electrode 262 and the second electrode 264, respectively. The sub-via 270 may extend from the lower surfaces of the first electrode 262 and the second electrode 264 to the lower surface of the sub-mold layer 216 by passing through the sub-mold layer 216. The lower surface of the sub-via 270 may be exposed by being located at the same height as the lower surface of the sub-mold layer 216.

Sub-semiconductor package 210 can be electrically connected to the substrate (see 200 in FIG. 8 ) via interconnects 280 connected to the exposed lower surfaces of sub-vias 270. Interconnects 280 connected to sub-vias 270 will be referred to as second sub-package interconnects 280 to distinguish them from first sub-package interconnects described later. Second sub-package interconnects 280 may include conductors having various three-dimensional shapes, such as balls and pillars, rather than two-dimensional shapes, such as traces. For example, second sub-package interconnects 280 may include solder balls or metal bumps. Although not shown, an additional insulating layer may be provided between the lower surface of sub-mold layer 216 and second sub-package interconnects 280. Openings may be formed in the additional insulating layer to expose the sub-vias 270 for connection to the second sub-package interconnect 280.

The electrical connection between the sub-semiconductor package 210 and the substrate 200 will be described in more detail below with reference to FIG8 . For reference, FIG8 is shown along a cross-section corresponding to line A1-A1 ′ of FIG1 , so that the capacitor 260, the sub-via 270 connected thereto, and the second sub-package interconnect 280 are not actually visible. However, for ease of description, one capacitor 260, the sub-via 270 connected thereto, and the second sub-package interconnect 280 are illustrated.

8 together with FIG. 9 to FIG. 11 , the sub-semiconductor package 210 can be electrically connected to the substrate 200 via the first sub-package interconnect 217 and the second sub-package interconnect 280 .

The first sub-package interconnect 217 can be substantially the same as the sub-package interconnect 117 of the aforementioned embodiment. Specifically, the first sub-package interconnect 217 can connect the redistribution pad 218BP and the substrate 200 to each other, thereby providing an electrical connection between the semiconductor sub-die 214 and the substrate 200. The first sub-package interconnect 217 can be a bonding wire.

On the other hand, the second sub-package interconnect 280 can be connected to the redistribution conductive layer 218B through the sub-via 270 and each of the first electrode 262 and the second electrode 264 of the capacitor 260. Specifically, the second sub-package interconnect 280 can be connected to a point in the redistribution conductive layer 218B other than the redistribution pad 218BP. Thus, it can provide an electrical connection between the sub-semiconductor die 214 and the substrate 200.

Because the second sub-package interconnect 280 is interposed between the sub-semiconductor package 210 and the substrate 200, unlike the sub-mold layer 116 of the aforementioned embodiment, the sub-mold layer 216 can be separated from the substrate 200 by a predetermined distance while not being attached to the substrate 200. This distance may correspond to the height of the second sub-package interconnect 280. The second sub-package interconnect 280 can provide an electrical connection between the sub-semiconductor package 210 and the substrate 200 and also support the sub-semiconductor package 210. Multiple second sub-package interconnects 280 can be provided to overlap each of the first electrode 262 and the second electrode 264 of the capacitor 260. Because the first electrode 262 and the second electrode 264 of the capacitor 260 are arranged along the periphery of the sub-semiconductor die 214, the second sub-package interconnect 280 can adequately support the sub-semiconductor package 210. Furthermore, one or more dummy second sub-package interconnects 281 not connected to the sub-vias 270 can be additionally provided above the lower surface of the sub-mold layer 216. These dummy second sub-package interconnects 281 can prevent the sub-semiconductor package 210 from tilting in one direction or withstand the pressure generated when the first and second die stacks 220 and 230 are mounted above the sub-semiconductor package 210.

FIG8 may further include a first wafer stack 220 and a second wafer stack 230 disposed above the sub-semiconductor package 210. The first wafer stack 220 may include a plurality of first main semiconductor chips 224 and a first adhesive layer 222 for attaching each first main semiconductor chip 224 to a structure below it. The first main semiconductor chips 224 may be offset in the stack in a first offset direction so as to expose a first wafer pad 225 disposed on the upper surface of each first main semiconductor chip 224. The first wafer stack 220 may be electrically connected to the substrate 200 via a first interconnect 227. The second wafer stack 230 may include a plurality of second main semiconductor chips 234 and a second adhesive layer 232 for attaching each second main semiconductor chip 234 to a structure below it. The second main semiconductor chips 234 can be offset in the second offset direction, exposing the second chip pad 235 provided on the upper surface of each second main semiconductor chip 234. The second chip stack 230 can be electrically connected to the substrate 200 via a second interconnect 237. The first chip stack 220 and the second chip stack 230 can be covered with a mold layer 250. External connection terminals 240 can be provided on the lower surface of the substrate 200.

The semiconductor package according to this embodiment can have all the advantages of the semiconductor package according to the above-mentioned embodiment.

Furthermore, as in this embodiment, when sub-vias 270 connected to each of the first electrode 262 and the second electrode 264 of the capacitor 260 are provided in the sub-semiconductor package 210, and a second sub-package interconnect 280 connecting the sub-semiconductor package 210 and the substrate 200 is provided, the DC path between the sub-semiconductor package 210 and the substrate 200 can be shortened, thereby reducing the impedance of the power supply path. Furthermore, multiple DC paths can be formed, which reduces the inductance of the power supply path. As a result, power supply between the sub-semiconductor package 210 and the substrate 200 can be facilitated. This will be further described with reference to Figures 12A and 12B.

FIG12A is a diagram illustrating an example of the effects of a semiconductor package according to another embodiment of the present disclosure, while FIG12B is a diagram illustrating the effects of a semiconductor package according to a comparative example. Unlike the present embodiment, FIG12B illustrates a case where capacitors and sub-vias are not present.

12A, a relatively long DC path can be formed by redistributing the conductive layer 218B, the first sub-package interconnect 217 and the substrate 200 (see the dotted arrow). ). In addition, a relatively short DC path can be formed by redistributing a portion of the conductive layer 218B, the capacitor 260, the sub-via 270, the second sub-package interconnect 280 and the substrate 200 (see the dotted arrow). ).

In other words, you can As shown in the dashed arrow, a short DC path is obtained and and As shown, multiple DC paths are formed.

On the other hand, referring to FIG. 12B , in the comparative example, only a relatively long DC path (see the dotted arrow) passing through the redistribution conductive layer 218B ′ , the first sub-package interconnect 217 ′ , and the substrate 200 ′ can be formed.

As a result, as shown in FIG12A , according to this embodiment, a short DC path and multiple DC paths can be formed, thereby reducing the impedance and inductance of the power supply path. Therefore, power supply can be easily performed.

FIG13 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure. FIG14 is a plan view illustrating a sub-semiconductor package of the semiconductor package according to another embodiment of the present disclosure. FIG15 is a cross-sectional view taken along line A6-A6 ′ in FIG14 , and FIG16 is a cross-sectional view taken along line A7-A7 ′ in FIG14 . The following will mainly describe differences from the above-described embodiments.

First, referring to Figures 14 to 16 , similar to the above-described embodiments, the sub-semiconductor package 310 of this embodiment may include a sub-semiconductor die 314, a sub-mold layer 316 surrounding at least the side surface of the sub-semiconductor die 314, a redistributed structure comprising a first redistributed insulating layer 318A, a redistributed conductive layer 318B, and a second redistributed insulating layer 318C formed above the upper surfaces of the sub-semiconductor die 314 and the sub-mold layer 316, and a capacitor 360 disposed in the sub-mold layer 316 and comprising a first electrode 362, a second electrode 364, and a body portion (not shown) therebetween. A sub-die pad 315 may be disposed on the upper surface of the sub-semiconductor die 314. The daughter die pad 315 may include a signal daughter die pad 315-S, a ground daughter die pad 315-G, and a power daughter die pad 315-P. The redistribution conductive layer 318B may include a signal redistribution conductive layer 318B-S connected to the signal daughter die pad 315-S, a ground redistribution conductive layer 318B-G connected to the ground daughter die pad 315-G, and a power redistribution conductive layer 318B-P connected to the power daughter die pad 315-P. Signal redistribution pad 318BP-S may be disposed at an end of signal redistribution conductive layer 318B-S, ground redistribution pad 318BP-G may be disposed at an end of ground redistribution conductive layer 318B-G, and power redistribution pad 318BP-P may be disposed at an end of power redistribution conductive layer 318B-P. Ground redistribution conductive layer 318B-G may be connected to ground sub-die pad 315-G and first electrode 362 of capacitor 360 through an opening in first redistribution insulating layer 318A. The power redistribution conductive layer 318B-P can be connected to the power sub-die pad 315-P and the second electrode 364 of the capacitor 360 through the opening of the first redistribution insulating layer 318A.

In addition, the sub-semiconductor package 310 may further include sub-vias 370 connected to the ground redistribution conductive layer 318B-G and the power redistribution conductive layer 318B-P, respectively.

Sub-vias 370 can be formed spaced apart from each of the first electrode 362 and the second electrode 364 of capacitor 360. However, as described later, sub-vias 370 can also be positioned closer to sub-die pad 315 than to redistribution pad 318BP to shorten the DC path. Furthermore, sub-vias 370 can be located between first electrode 362 and ground redistribution pad 318BP-G and between second electrode 364 and power redistribution pad 318BP-P.

Sub-vias 370 may be formed to penetrate sub-mold layer 316 and extend from the upper surface to the lower surface of sub-mold layer 316. That is, the upper surface of sub-via 370 may be exposed at substantially the same height as the upper surface of sub-mold layer 316, and the lower surface of sub-via 370 may be exposed at substantially the same height as the lower surface of sub-mold layer 316. Each of ground redistribution conductive layers 318B-G and power redistribution conductive layers 318B-P may be connected to the upper surface of sub-via 370 through an opening in first redistribution insulating layer 318A.

Sub-semiconductor package 310 can be electrically connected to the substrate (see 300 in FIG. 13 ) via a second sub-package interconnect 380 connected to the lower surface of sub-via 370. Second sub-package interconnect 380 can include conductors having various three-dimensional shapes (such as balls and pillars) rather than two-dimensional shapes (such as traces). For example, second sub-package interconnect 380 can include solder balls or metal bumps. Although not shown, an additional insulating layer can be provided between the lower surface of sub-mold layer 316 and second sub-package interconnect 380. An opening can be formed in the additional insulating layer to expose sub-via 370 for connection to second sub-package interconnect 380.

The electrical connection between sub-semiconductor packages 310 and substrate 300 will be described in more detail below with reference to FIG. 13. For reference, FIG. 13 is shown along a cross-section corresponding to line A1-A1 ′ of FIG. 1 , making capacitors 360, sub-vias 370, and second sub-package interconnects 380 invisible. However, for ease of description, one capacitor 360, along with sub-vias 370 and second sub-package interconnects 380 located near one capacitor 360, is illustrated.

13 together with FIG. 14 to FIG. 16 , the sub-semiconductor package 310 can be electrically connected to the substrate 300 via the first sub-package interconnect 317 and the second sub-package interconnect 380 .

The first sub-package interconnect 317 may be substantially the same as the first sub-package interconnect 217 of the aforementioned embodiment. That is, the first sub-package interconnect 317 may provide an electrical connection between the semiconductor sub-die 314 and the substrate 300 by connecting the redistribution pad 318BP and the substrate 300 to each other. The first sub-package interconnect 317 may be a bonding wire.

On the other hand, the second sub-package interconnect 380 can be connected to the redistribution conductive layer 318B through the sub-via 370. Specifically, the second sub-package interconnect 380 can be connected to a point in the redistribution conductive layer 318B other than the redistribution pad 318BP. Thus, an electrical connection can be provided between the sub-semiconductor die 314 and the substrate 300.

Because the second sub-package interconnect 380 is interposed between the sub-semiconductor package 310 and the substrate 300, the sub-mold layer 316 need not be attached to the substrate 300 and may be spaced a predetermined distance from the substrate 300. This distance may correspond to the height of the second sub-package interconnect 380. The second sub-package interconnect 380 provides an electrical connection between the sub-semiconductor package 310 and the substrate 300 and may also support the sub-semiconductor package 310. Multiple second sub-package interconnects 380 may be positioned adjacent to the first electrode 362 and the second electrode 364 of the capacitor 360, respectively. That is, because the second sub-package interconnect 380 is provided along the periphery of the sub-semiconductor die 314, the second sub-package interconnect 380 can fully support the sub-semiconductor package 310. A dummy second sub-package interconnect 381, not connected to the sub-via 370, can be additionally provided above the lower surface of the sub-mold layer 316. The dummy second sub-package interconnect 381 can prevent the sub-semiconductor package 310 from tilting in one direction or can withstand the pressure generated when the first chip stack 320 and the second chip stack 330 are mounted above the sub-semiconductor package 310.

FIG13 may also include a first wafer stack 320 and a second wafer stack 330 disposed above the sub-semiconductor package 310. The first wafer stack 320 may include a plurality of first main semiconductor chips 324 and a first adhesive layer 322 for attaching the first main semiconductor chips 324 to underlying structures. The first main semiconductor chips 324 may be offset in a first offset direction so as to expose a first wafer pad 325 disposed on an upper surface of each first main semiconductor chip 324. The first wafer stack 320 may be electrically connected to the substrate 300 via a first interconnect 327. The second wafer stack 330 may include a plurality of second main semiconductor chips 334 and a second adhesive layer 332 for attaching each second main semiconductor chip 334 to underlying structures. The second main semiconductor chips 334 can be offset in the second offset direction, exposing the second chip pad 335 provided on the upper surface of each second main semiconductor chip 334. The second chip stack 330 can be electrically connected to the substrate 300 via a second interconnect 337. The first chip stack 320 and the second chip stack 330 can be covered with a mold layer 350. External connection terminals 340 can be provided on the lower surface of the substrate 300.

The semiconductor package according to this embodiment can have all the advantages of the semiconductor package according to the above-mentioned embodiment.

Specifically, compared to a case where no sub-vias are present in sub-semiconductor package 310, providing sub-vias 370 connected to each of ground redistribution conductive layers 318B-G and power redistribution conductive layers 318B-P, along with second sub-package interconnects 380 connecting sub-vias 370 and substrate 300, shortens the DC path between sub-semiconductor package 310 and substrate 300, thereby reducing the power supply path. Furthermore, multiple DC paths can be formed, reducing the inductance of the power supply path. Consequently, power can be supplied more easily between sub-semiconductor package 310 and substrate 300. This will be further described with reference to Figures 17A and 17B.

FIG17A is a diagram illustrating an example of the effects of a semiconductor package according to another embodiment of the present disclosure, and FIG17B is a diagram illustrating the effects of a semiconductor package according to a comparative example. Unlike this embodiment, FIG17B illustrates a case where a sub-via does not exist in the sub-semiconductor package 310.

17A, a relatively long DC path can be formed by redistributing the conductive layer 318B, the first sub-package interconnect 317 and the substrate 300 (see the dotted arrow). ). In addition, a relatively short DC path can be formed by redistributing a portion of the conductive layer 318B, the sub-via 370, the second sub-package interconnect 380 and the substrate 300 (see the dotted arrow ).

In other words, you can As shown, a short DC path is obtained, and in addition, the dotted arrow and As shown, multiple DC paths are formed.

On the other hand, referring to FIG. 17B , in the comparative example, only a relatively long DC path (see the dotted arrow) is formed passing through the redistribution conductive layer 318B ′ , the first sub-package interconnect 317 ′ , and the substrate 300 ′ .

As a result, as shown in FIG17A , according to this embodiment, a short DC path and multiple DC paths can be formed, thereby reducing the impedance and inductance of the power supply path. Therefore, power supply can be easily performed.

Through implementations of the present disclosure, a high-capacity and multifunctional semiconductor package can be realized by forming a wafer stack including one or more main semiconductor wafers above a sub-semiconductor package. Furthermore, capacitors can be provided in the sub-semiconductor package to assist in power supply within the semiconductor package.

FIG18 shows a block diagram of an exemplary electronic system including a memory card 7800 that employs at least one semiconductor package according to an embodiment. Memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. Memory 7810 and memory controller 7820 can store data or read stored data. At least one of memory 7810 and memory controller 7820 may include at least one semiconductor package according to the described embodiments.

The memory 7810 may include a non-volatile memory device to which the techniques of the embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 so that the stored data is read or stored in response to a read/write request from the host computer 7830.

FIG19 shows a block diagram of an exemplary electronic system 8710 that includes at least one of the semiconductor packages according to the described embodiments. The electronic system 8710 may include a controller 8711, an input/output device 8712, and a memory 8713. The controller 8711, the input/output device 8712, and the memory 8713 may be connected to each other via a bus 8715 that provides a path for data movement.

In embodiments, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and/or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to embodiments of the present disclosure. The input/output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 may store commands and/or data to be executed by the controller 8711, among other things.

Memory 8713 may include volatile memory devices such as DRAM and/or non-volatile memory devices such as flash memory. For example, flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. Flash memory may also be incorporated into a solid-state drive (SSD). In this case, electronic system 8710 can stably store large amounts of data in the flash memory system.

Electronic system 8710 may also include an interface 8714 configured to send and receive data to and from a communication network. Interface 8714 may be of a wired or wireless type. For example, interface 8714 may include an antenna or a wired or wireless transceiver.

The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smartphone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.

If electronic system 8710 represents equipment capable of performing wireless communications, then electronic system 8710 can be used in a communication system using technologies such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Digital Cellular (NADC), Enhanced Time Division Multiple Access (E-TDMA), Wideband Code Division Multiple Access (WCDMA), CDMA2000, Long Term Evolution (LTE), or Wireless Broadband Internet (Wibro).

Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present teachings as defined by the appended claims.

116: Sub-molding layer 118A: First redistribution insulating layer 118B-G: Ground redistribution conductive layer 118B-P: Power redistribution conductive layer 118B-S: Signal redistribution conductive layer 118C: Second redistribution insulating layer 160: Capacitor 162: First electrode 164: Second electrode 166: Main body

Claims (20)

A semiconductor package includes: a substrate; a sub-semiconductor package, the sub-semiconductor package being arranged above the substrate, the sub-semiconductor package including: a sub-semiconductor chip having a chip pad on an upper surface of the sub-semiconductor chip; a sub-mold layer surrounding a side surface of the sub-semiconductor chip; and a redistribution layer formed on the sub-semiconductor chip. The redistribution layer comprises a redistribution conductive layer connected to the chip pad of the sub-semiconductor chip and extending to the edge of the sub-mold layer, and having a redistribution pad at the end of the redistribution conductive layer; a first sub-package interconnect, the first sub-package interconnect connected to the redistribution pad to electrically connect the sub-semiconductor chip and the substrate; an electrical A capacitor is formed in the sub-mold layer and includes a first electrode, a second electrode, and a main body portion between the first electrode and the second electrode, the first electrode and the second electrode having upper surfaces respectively connected to the redistributed conductive layer; and at least one main semiconductor chip, the at least one main semiconductor chip being formed above the sub-semiconductor package and electrically connected to the substrate, wherein the sub-semiconductor package further includes a sub-via that penetrates the sub-mold layer while being connected to the lower surface of each of the first electrode and the second electrode, and wherein the semiconductor package further includes a second sub-package interconnect, the second sub-package interconnect being disposed between the sub-mold layer and the substrate, the second sub-package interconnect being connected to the sub-via. The semiconductor package of claim 1, wherein the redistributed conductive layer includes a ground redistributed conductive layer to which a ground voltage is applied and a power redistributed conductive layer to which a power voltage is applied, and wherein the first electrode is connected to the ground redistributed conductive layer, and the second electrode is connected to the power redistributed conductive layer. The semiconductor package according to claim 2, wherein the redistribution conductive layer further includes at least one signal redistribution conductive layer, and the at least one signal redistribution conductive layer is located between the ground redistribution conductive layer and the power redistribution conductive layer. The semiconductor package of claim 3, wherein the main body portion overlaps with the at least one signal redistribution conductive layer. The semiconductor package according to claim 2, wherein each of the first electrode and the second electrode is provided closer to the die pad than the redistribution pad. The semiconductor package of claim 1, wherein the redistribution layer further includes a redistribution insulating layer formed between the redistribution conductive layer and the upper surfaces of the sub-semiconductor chip and the sub-mold layer, and wherein the redistribution conductive layer is connected to the chip pad, the first electrode, and the second electrode through openings formed in the redistribution insulating layer. The semiconductor package of claim 1, wherein the at least one main semiconductor chip includes a memory, and wherein the sub-semiconductor chip includes a memory controller. The semiconductor package of claim 1, wherein the first subpackage interconnect comprises a bonding wire, and wherein the second subpackage interconnect comprises at least one of a solder ball and a conductive bump. The semiconductor package of claim 1 further comprising: a dummy second sub-package interconnect, the dummy second sub-package interconnect being disposed between the sub-molding layer and the substrate and not connected to the sub-via. The semiconductor package of claim 1, wherein a first DC path passes through the redistributed conductive layer, the first subpackage interconnect, and the substrate, and wherein a second DC path passes through the redistributed conductive layer, the first electrode or the second electrode, the sub-via, the second subpackage interconnect, and the substrate. A semiconductor package includes: a substrate; a sub-semiconductor package, the sub-semiconductor package being disposed above the substrate, the sub-semiconductor package including: a sub-semiconductor chip having a chip pad on its upper surface; a sub-mold layer surrounding a side surface of the sub-semiconductor chip; and a redistribution layer formed above the sub-semiconductor chip and the sub-mold layer, the redistribution layer including: The sub-molding layer includes a redistributed conductive layer connected to the chip pad of the sub-semiconductor chip and extending to the edge of the sub-molding layer, and having a redistributed pad at the end of the redistributed conductive layer; a first sub-package interconnect, the first sub-package interconnect connected to the redistributed pad to electrically connect the sub-semiconductor chip and the substrate; a capacitor formed in the sub-molding layer and including a first electrode, a second electrode, and a second capacitor between the sub-molding layer and the substrate. a main body portion between a first electrode and a second electrode, the first electrode and the second electrode having upper surfaces connected to the redistributed conductive layer, respectively; and at least one main semiconductor chip, the at least one main semiconductor chip being formed above the sub-semiconductor package and electrically connected to the substrate, wherein the sub-semiconductor package further includes a sub-via, the sub-via penetrating the sub-mold layer and having an upper surface connected to the redistributed conductive layer, and The semiconductor package further includes a second sub-package interconnect disposed between the sub-molding layer and the substrate, the second sub-package interconnect connected to the sub-via. A first DC path passes through the redistribution conductive layer, the first sub-package interconnect, and the substrate, and a second DC path passes through the redistribution conductive layer, the sub-via, the second sub-package interconnect, and the substrate. The semiconductor package of claim 11, wherein the sub-via is connected to the redistributed conductive layer connected to the first electrode while being spaced apart from the first electrode, and wherein the sub-via is connected to the redistributed conductive layer connected to the second electrode while being spaced apart from the second electrode. The semiconductor package according to claim 11, wherein the sub-via is provided between the first electrode and the redistribution pad or between the second electrode and the redistribution pad. The semiconductor package of claim 11, wherein the first subpackage interconnect comprises a bonding wire, and wherein the second subpackage interconnect comprises at least one of a solder ball and a conductive bump. The semiconductor package of claim 11 further comprises: a dummy second sub-package interconnect, the dummy second sub-package interconnect being disposed between the sub-molding layer and the substrate and not connected to the sub-via. A semiconductor package includes: a substrate; a sub-semiconductor package, the sub-semiconductor package being disposed above the substrate, the sub-semiconductor package including: a sub-semiconductor chip having a chip pad on its upper surface; a sub-mold layer surrounding a side surface of the sub-semiconductor chip; and a redistribution layer formed above the sub-semiconductor chip and the sub-mold layer. The redistribution layer includes a redistribution conductive layer connected to the chip pad of the sub-semiconductor chip and extending to the edge of the sub-mold layer, and having a redistribution pad at the end of the redistribution conductive layer; a first sub-package interconnect connected to the redistribution pad to electrically connect the sub-semiconductor chip and the substrate; and a capacitor formed in the sub-mold layer and including a first The sub-semiconductor package comprises a first electrode, a second electrode, and a main body portion between the first electrode and the second electrode, wherein the first electrode and the second electrode have upper surfaces connected to the redistributed conductive layer respectively; and at least one main semiconductor chip, the at least one main semiconductor chip is formed above the sub-semiconductor package and electrically connected to the substrate, wherein the substrate includes a first side edge and a second side edge provided at the substrate in the first direction. Each substrate pad is provided at a position corresponding to a first side edge of the substrate, and wherein the at least one main semiconductor chip includes: at least one first main semiconductor chip, the at least one first main semiconductor chip being connected to the substrate pad provided at the first side edge of the substrate via a first interconnect; and at least one second main semiconductor chip, the at least one second main semiconductor chip being connected to the substrate pad provided at the second side edge of the substrate via a second interconnect. The semiconductor package of claim 16, wherein the at least one first main semiconductor chip comprises a plurality of first main semiconductor chips stacked in an offset manner from the first side toward the second side in the first direction, and wherein the at least one second main semiconductor chip comprises a plurality of second main semiconductor chips stacked in an offset manner from the second side toward the first side in the first direction. The semiconductor package of claim 16, wherein the redistribution pad is provided at each of a first side edge and a second side edge of the sub-mold layer in the first direction, and wherein the first sub-package interconnect connects the redistribution pad provided at the first side edge of the sub-mold layer and the substrate pad provided at the first side edge of the substrate, and connects the redistribution pad provided at the second side edge of the sub-mold layer and the substrate pad provided at the second side edge of the substrate. The semiconductor package of claim 18, wherein the die pad of the sub-semiconductor die is disposed along a first side edge and a second side edge of the sub-semiconductor die in the first direction, and is disposed along a first side edge and a second side edge of the sub-semiconductor die in a second direction, the second direction being perpendicular to the first direction. The semiconductor package of claim 19, wherein the die pad disposed at first side edges of the semiconductor sub-die in the first and second directions extends toward the redistribution pad disposed at first side edges of the sub-mold layer in the first direction, and wherein the die pad disposed at second side edges of the semiconductor sub-die in the first and second directions extends toward the redistribution pad disposed at second side edges of the sub-mold layer in the first direction.