TWI889555B - Electrical characteristics evaluation method, electrical characteristics evaluation device, and electrical characteristics evaluation system - Google Patents
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Abstract
本揭示係以使用評估在半導體裝置之製造工程之中途工程中被製造的元件之電特性的結果,以評估其半導體裝置全體之電特性為目的。本揭示所涉及的電特性評估方法係接收在半導體裝置之製造中途工程中被形成的半導體元件之電特性的結果,對上述半導體裝置之第1等效電路反映上述半導體元件之第2等效電路,並且使用上述半導體元件之電特性而模擬上述第1等效電路的電特性(參照圖1)。The purpose of the present disclosure is to evaluate the electrical characteristics of the entire semiconductor device using the results of evaluating the electrical characteristics of the element manufactured in the process of manufacturing the semiconductor device. The electrical characteristics evaluation method involved in the present disclosure receives the results of the electrical characteristics of the semiconductor element formed in the process of manufacturing the semiconductor device, reflects the second equivalent circuit of the semiconductor element on the first equivalent circuit of the semiconductor device, and simulates the electrical characteristics of the first equivalent circuit using the electrical characteristics of the semiconductor element (refer to FIG. 1).
Description
本揭示係關於評估半導體裝置之電特性的技術。The present disclosure relates to techniques for evaluating the electrical characteristics of semiconductor devices.
下述專利文獻1係針對推定試料之電容特性等的電特性的帶電粒子束裝置而記載。同文獻記載下述事項:『比較器230,比較推定照射結果記憶部228中存放的演算結果(亦即放出量演算部227所做的演算結果)、與電子束照射結果記憶部229中存放的實測結果(亦即檢測器219所做的實測結果)。此處,當藉由比較器230而獲得不一致的比較結果的情形下,藉由演算用網路連線表更新部226更新演算用網路連線表內的元件參數值,運用更新的演算用網路連線表再度進行前述的放出量演算部227至比較器230為止之處理。另一方面,當藉由比較器230而獲得一致的比較結果的情形下,演算用網路連線表更新部226將包含目前的元件參數值之網路連線表存放於推定網路連線表記憶部231作為推定網路連線表』(段落0034)
[先前技術文獻]
[專利文獻]
The following
[專利文獻1]日本特許第7250642號公報[Patent Document 1] Japanese Patent No. 7250642
[發明所欲解決之課題][The problem that the invention wants to solve]
專利文獻1係作成記載半導體裝置之等效電路之構成要素的網路連線表,同時將測量靜電容等的電特性的結果反映在其網路連線表內。專利文獻1記載之測量技術係例如同文獻之圖3A等記載般,可以測量在試料之高度方向之內部形成的半導體元件之靜電容等。該半導體元件係在製造半導體裝置全體的工程中的中途工程被製造。即是,專利文獻1可以說係測量在半導體裝置製造之中途工程被製造的元件之電特性的技術。因此,在同文獻中,反映在網路連線表內的電特性也係如此地在中途工程中被製造的元件之電特性。
另一方面,半導體裝置之之完成品之電特性係例如藉由使測試探針接觸於測量墊而將輸入訊號予以輸入,測量其響應作為輸出訊號來實施。或是,藉由SPICE模擬器等模擬相同的半導體裝置之等效電路,將其結果與參照值予以比較,可以評估其半導體裝置之電特性。On the other hand, the electrical characteristics of the finished semiconductor device are measured by, for example, inputting an input signal by contacting a test probe with a measurement pad and measuring the response as an output signal. Alternatively, the electrical characteristics of the semiconductor device can be evaluated by simulating an equivalent circuit of the same semiconductor device using a SPICE simulator or the like and comparing the result with a reference value.
SPICE模擬器係根據半導體裝置之設計資料,模擬半導體裝置之等效電路。此作為評估半導體裝置之完成品之電特性的手法有效用。另一方面,在半導體裝置製造之中途工程中,若可以評估藉由中途工程製造的元件之電特性,是否適合於朝後續的工程前進(即是,作為中途之成果物的元件是否為良品)即可。專利文獻1可以評估如此的元件之電特性。但是,其評估並非作為半導體裝置之完成品的評估,為作為元件單體的電特性的評估。換言之,在專利文獻1中,就算評估元件的電特性,針對其電特性作為半導體裝置之完成品之電特性而如何地被反映,在專利文獻1也未充分考慮到。The SPICE simulator simulates the equivalent circuit of a semiconductor device based on the design data of the semiconductor device. This is effective as a method for evaluating the electrical characteristics of a finished semiconductor device. On the other hand, in the mid-process of manufacturing a semiconductor device, if the electrical characteristics of a component manufactured by the mid-process can be evaluated to see whether it is suitable for proceeding to the subsequent process (that is, whether the component as the mid-process product is a good product).
本揭示係鑑於上述般之課題而被創作出,使用評估在半導體裝置之製造工程之中途工程中被製造的元件之電特性的結果,以評估其半導體裝置全體之電特性為目的。 [用以解決課題之手段] This disclosure was created in view of the above-mentioned problems, and is intended to evaluate the electrical characteristics of the entire semiconductor device by using the results of evaluating the electrical characteristics of the components manufactured in the middle of the manufacturing process of the semiconductor device. [Means for solving the problem]
本揭示所涉及的電特性評估方法係接收在半導體裝置之製造中途工程中被形成的半導體元件之電特性的結果,對上述半導體裝置之第1等效電路反映上述半導體元件之第2等效電路,並且使用上述半導體元件之電特性而模擬上述第1等效電路的電特性。 [發明之效果] The electrical characteristics evaluation method disclosed herein receives the results of the electrical characteristics of a semiconductor element formed in the process of manufacturing a semiconductor device, reflects the second equivalent circuit of the semiconductor element on the first equivalent circuit of the semiconductor device, and uses the electrical characteristics of the semiconductor element to simulate the electrical characteristics of the first equivalent circuit. [Effect of the invention]
若藉由本揭示所涉及之電特性評估方法時,可以使用評估在半導體裝置之製造工程之中途工程中被製造的元件之電特性的結果,評估其半導體裝置全體之電特性。針對本揭示之其他課題、構成、優點,藉由參照以下的實施型態可明白。By using the electrical characteristics evaluation method disclosed herein, the electrical characteristics of the components manufactured in the middle of the manufacturing process of the semiconductor device can be used to evaluate the electrical characteristics of the entire semiconductor device. Other topics, structures, and advantages of the present disclosure can be understood by referring to the following embodiments.
[本揭示之背景][Background of this disclosure]
針對半導體裝置製造中途工程晶圓之工程管理,認為以滿足裝置製造最終工程晶圓的電特性(含可靠性、良率)規格之方式,使各工程中之形狀(CD值(平均值、偏差)、粗糙度值等)或缺陷密度規格予以預算化,可在各工程判定良好。For the process management of semiconductor device manufacturing mid-process wafers, it is believed that the shape (CD value (average value, deviation), roughness value, etc.) or defect density specifications in each process can be estimated in a way that meets the electrical characteristics (including reliability and yield) specifications of the final process wafers of device manufacturing, so that good judgment can be made in each process.
另一方面,為了輸出期望的裝置動作(電特性),作為什麼樣的佈局需要什麼樣的工程的裝置動作原理驗證之一,有模擬從設計資料至電特性輸出為止的EDA(Electronic Design Automation)工具。藉由有效地活用如此的EDA工具,能夠實現半導體裝置之製造體制之早期啟動或穩定運轉。最者,於前進至最終工程之前,若可以在各工程檢測不良時,則可以快速地反饋於製造工程。On the other hand, in order to output the expected device behavior (electrical characteristics), as one of the device behavior principle verifications, what kind of layout requires what kind of process, there is an EDA (Electronic Design Automation) tool that simulates from design data to electrical characteristics output. By effectively using such EDA tools, it is possible to achieve early startup or stable operation of the manufacturing system of semiconductor devices. In addition, if defects can be detected in each process before moving on to the final process, feedback can be quickly given to the manufacturing process.
隨著裝置構造之三次元化,發展裝置構造變得複雜化及Z方向深孔化,有僅以在使用各工程之圖案等的CD SEM(Critical Dimension Scanning Electron Microscope)的形狀管理,漏檢不良的風險變高,產生良率損失之情況。依此,以使用對Z方向高敏感度的另外手段來判定各工程的良否為佳。尤其,若可以評估電元件所要求的電性特徵量時,則可以防止先前說明的檢漏不良等。As the device structure becomes three-dimensional, the device structure becomes more complex and the holes in the Z direction become deeper. The risk of missing defects increases when only using CD SEM (Critical Dimension Scanning Electron Microscope) to manage the shape of each process, resulting in yield loss. Therefore, it is better to use another method with high sensitivity in the Z direction to determine the quality of each process. In particular, if the electrical characteristic quantity required by the electrical component can be evaluated, the previously described missing defects can be prevented.
網路連線表係表現構成電阻器、電容器、電感器、電晶體和電源等的電路的電元件(組件)的設計資料。如此的網路連線表有當作積體電路(IC:Integrated Circuit)設計模擬之輸入資料使用之情形。IC設計模擬係為了分析網路連線表而決定電路該如何地動作而被實施。半導體裝置係經過複數製造工程而被製造,IC設計模擬係評估經過複數製造工程而被製造的裝置之電特性。A netlist is design data that represents the electrical components (assemblies) that make up a circuit such as a resistor, capacitor, inductor, transistor, and power supply. Such a netlist is sometimes used as input data for integrated circuit (IC) design simulation. IC design simulation is performed to analyze the netlist and determine how the circuit should operate. Semiconductor devices are manufactured through multiple manufacturing processes, and IC design simulation is used to evaluate the electrical characteristics of the device manufactured through multiple manufacturing processes.
被供於模擬的網路連線表所含的組件之規格,雖然通常為從設計資料被導出,但是若可以根據在裝置在完成的製程中可以藉由實測取得的電特性(規格),實行在例如最終工程評估的電特性之模擬時,則可以至半導體裝置之最終工程之前,可以評估藉由時間變化產生,或由於意外產生的製程變化而導致的半導體裝置之工作質量。依此,能夠對製造工程進行快速的反饋等。Although the specifications of the components included in the net connection table provided for simulation are usually derived from the design data, if the electrical characteristics (specifications) that can be obtained by actual measurement in the completed process of the device can be used to simulate the electrical characteristics of the final process evaluation, the working quality of the semiconductor device caused by time changes or unexpected process changes can be evaluated before the final process of the semiconductor device. In this way, rapid feedback can be provided to the manufacturing process.
以下,針對根據在至最終工程為止的中途工程能取得的特定元件之規格的設定,推定能夠在最終工程取得的電特性的方法、電腦所致的實現方法、電腦程式、非暫時性的記錄媒體、裝置及系統,使用圖面予以詳細說明。Hereinafter, a method of estimating electrical characteristics that can be obtained in a final process based on the setting of the specifications of a specific component that can be obtained in an intermediate process leading to the final process, a computer-based implementation method, a computer program, a non-temporary recording medium, a device, and a system will be described in detail using drawings.
作為為了達成上述目的一態樣,提案以“從在裝置製造中途工程中被實測的晶圓所含的電元件之電阻值,或靜電容值等的輸出結果”,轉換成“由裝置製造最終工程晶圓之測試機所輸出的電特性(I-V、Vth、頻率特性等)”,輸出其結果作為特徵的方法等。若藉由如此的方法等時,根據製造製程中途之實測值,能夠預測電測試機等的輸出結果。As one aspect to achieve the above purpose, a method is proposed to convert "the output results of the resistance value or electrostatic capacitance value of the electrical components contained in the wafer measured in the process of device manufacturing" into "the electrical characteristics (I-V, Vth, frequency characteristics, etc.) output by the tester of the wafer in the final process of device manufacturing" and output the results as characteristics. If such a method is used, the output results of the electrical tester can be predicted based on the measured values in the process of manufacturing.
[本揭示之實施型態]
圖1為表示包含能在裝置製造中途工程中測量半導體晶圓所含的電元件之特性的測量工具的電特性評估系統之概要的圖。在圖1例示的系統,包含記憶積體電路之佈局資料及/或記號資料格式(例如,用以記憶GDSII(GDS2)、GL1、OASIS、映射檔案、或設計資料構造的其他格式)的設計資料記憶媒體101、EDA工具102、電特性測量裝置(電特性測量工具)103及一個以上的電腦系統104。再者,在圖1例示的系統中,即使連接光學式檢查裝置OCD(Optical Critical Dimension)、CD-SEM、EBI(Electron Beam Inspection)裝置等的其他測量裝置105亦可。該些裝置(工具)係經由匯流排16被連接成能夠互相通訊。
[Implementation of the present disclosure]
FIG. 1 is a diagram showing an overview of an electrical characteristics evaluation system including a measurement tool capable of measuring the characteristics of electrical components contained in a semiconductor wafer in the process of device manufacturing. The system illustrated in FIG. 1 includes a design
在圖1例示的系統中,包含一個以上的電腦系統104,EDA工具102即使包含用以運算後述模擬或半導體晶圓所含的電路之電特性的軟體、記憶該軟體的記憶媒體、具備用以實施上述軟體的一個以上的處理器的一個電腦系統亦可。即使在構成系統之每裝置各搭載電腦系統亦可,即使以一個工作站實施複數裝置之控制等亦可。In the system shown in FIG. 1, one or
電特性測量裝置103包含帶電粒子束裝置(評估部),其包含檢測對試料照射射束(例如電子束)的束柱,和藉由對試料的射束照射而獲得的二次電子(Secondary Electron:SE)及/或背向散射電子(Backscattered Electron:BSE)的檢測器。在本實施型態中,作為電特性測量裝置103之一例,雖然針對根據藉由帶電粒子束裝置而獲得的亮度資訊(灰階),導出電元件之電阻值或靜電容值等的例予以說明,但是不限定於此,即使根據某種輸入而獲得的輸出資訊,適用求出電阻值或靜電容值的其他導出法亦可。在此情況,即使先將定義畫像資訊或檢測訊號和電特性之關係的模型等記憶於特定的記憶媒體,藉由一個以上的處理器,使用該模型導出電特性亦可。即使模型包含數學模型、資料庫、藉由機械學習已進行學習的學習完模型等亦可。The electrical
將帶電粒子束裝置設為電特性測量裝置103之情況,即使藉由將射束點狀地照射至試料上之特定元件(在晶圓表面可看見的插塞等),電性地接合於該特定元件,並且對一端被接地的電元件供給特定電荷,測量其亮度的手法亦可。When the charged particle beam device is set as the electrical
即使在帶電粒子束裝置之束柱,具備用以將射束聚焦成點狀的透鏡(例如,電磁透鏡),或用以調整射束之照射位置的偏轉器亦可。而且,即使如後述般具備用以對對象試料脈衝狀地照射射束的消隱用偏轉器亦可。消隱用偏轉器係為了應截斷射束往到達至試料,用以使射束朝軸外偏轉。即使藉由重複消隱用偏轉器所致的偏轉之接通斷開,使射束對試料脈衝化地照射亦可。即使在帶電粒子束裝置具備用以控制透鏡等的光學元件之一個以上的電腦系統(控制裝置)亦可。Even in the beam column of the charged particle beam device, it is possible to have a lens (for example, an electromagnetic lens) for focusing the beam into a point shape, or a deflector for adjusting the irradiation position of the beam. Furthermore, it is possible to have a deflector for eliminating the need for irradiating the beam to the target sample in a pulsed manner as described later. The deflector for eliminating the need for deflecting the beam is used to deflect the beam outward from the axis in order to cut off the beam from reaching the sample. It is possible to irradiate the sample with the beam in a pulsed manner by repeatedly turning on and off the deflection caused by the deflector for eliminating the need for deflecting. It is possible to have one or more computer systems (control devices) for controlling optical elements such as lenses in the charged particle beam device.
而且,即使在電特性測量裝置103內建記憶用以根據檢測器輸出評估被連接於成為射束之照射對象的插塞等之端子的電路構成元件之電特性的應用程式的記憶媒體亦可。Furthermore, a storage medium storing an application program for evaluating the electrical characteristics of a circuit component connected to a terminal of a plug or the like to be irradiated with a beam based on the detector output may be built into the electrical
再者,在電特性測量裝置103具備用以對成為電特性之測量對象的對象物(物件)供給特定電荷的電荷供給工具。電荷供給工具包含例如雷射光源,藉由對物件的雷射照射,對物件供給特定電荷。在電荷被供給的狀態,藉由照射脈衝電子束,實行後述的電特性評估。Furthermore, the electrical
圖2為表示當脈衝狀地照射電子束之時,相對於其截斷時間(脈衝束之不照射的時間)變化的SEM畫像之亮度變化的曲線圖。圖2左邊表示靜電容系統缺陷之相對於截斷時間變化的亮度變化,圖2右邊表示電阻系統缺陷之相對於截斷時間變化的亮度變化。Figure 2 is a graph showing the change in brightness of SEM images relative to the change in cutoff time (time when the pulse beam is not irradiated) when the electron beam is irradiated in a pulsed manner. The left side of Figure 2 shows the change in brightness of electrostatic capacitor system defects relative to the change in cutoff time, and the right side of Figure 2 shows the change in brightness of resistor system defects relative to the change in cutoff time.
如圖2例示般,在電阻系統缺陷和靜電容系統缺陷之間,在使截斷時間變化之時的亮度變化之特徵有所不同。依此,即使根據如此的特徵不同,判斷為靜電容系統缺陷或電阻系統缺陷亦可。As shown in FIG2, the characteristics of the brightness change when the cutoff time is changed are different between the resistance system defect and the electrostatic capacitance system defect. Therefore, even if it is different in characteristics, it can be judged as an electrostatic capacitance system defect or a resistance system defect.
靜電容系統之缺陷有隨著截斷時間變長,每個靜電容之亮度之不同變得明確的傾向。即使利用如此的特徵,例如從截斷時間長的區域中的亮度,和在截斷時間長的區域中事先被註冊的亮度之平均值(不同的靜電容缺陷之亮度的平均值)之間的差量,判定缺陷種類亦可。在此情況,例如差量超過特定臨界值之情況判定為靜電容系統缺陷,在特定臨界值以下之情況判定為電阻系統缺陷。The defects of the electrostatic capacitor system tend to become more obvious as the cutoff time becomes longer. Even using such characteristics, it is possible to determine the defect type by the difference between the brightness in the area with a long cutoff time and the average value of the brightness registered in advance in the area with a long cutoff time (the average value of the brightness of different electrostatic capacitor defects). In this case, for example, if the difference exceeds a specific critical value, it is determined to be a defect of the electrostatic capacitor system, and if it is below the specific critical value, it is determined to be a defect of the resistor system.
電阻系統之缺陷會有隨著截斷時間變短,每個電阻之亮度之不同變得明確的傾向。即使利用如此的特徵,被認為例如從截斷時間短的區域中的亮度,和在截斷時間短的區域中事先被註冊的亮度之平均值(不同的靜電容缺陷之亮度的平均值)的差量,判定缺陷種類亦可。在此情況,例如差量超過特定臨界值之情況判定為電阻系統缺陷,在特定臨界值以下之情況判定為靜電容系統缺陷。Resistor system defects tend to become more distinct as the cutoff time becomes shorter. Even using such a feature, it is considered possible to determine the defect type based on the difference between the brightness in the area with a short cutoff time and the average value of the brightness registered in advance in the area with a short cutoff time (the average value of the brightness of different electrostatic capacitor defects). In this case, for example, if the difference exceeds a specific critical value, it is determined to be a resistor system defect, and if it is below the specific critical value, it is determined to be an electrostatic capacitor system defect.
再者,即使使獲得的曲線擬合於表示事先記憶於每缺陷種類的截斷時間之變化,和亮度之變化之關係,因應其一致度,而分類缺陷種類亦可。而且,也可以考慮事先準備(記憶)對應於複數靜電容之複數曲線,及對應於複數電阻之複數曲線,因應一致度,推定靜電容或電阻。Furthermore, even if the obtained curve is fitted to represent the relationship between the change in the cutoff time and the change in brightness for each defect type, the defect type can be classified according to the degree of consistency. In addition, it is also possible to prepare (memorize) multiple curves corresponding to multiple electrostatic capacitances and multiple curves corresponding to multiple resistances in advance, and estimate the electrostatic capacitance or resistance according to the degree of consistency.
即使電阻值和靜電容值係對例如式1、將此予以變形的數學模型、資料庫或以亮度資訊和電特性資訊之資料組被進行學習的模型,藉由輸入亮度資訊而導出亦可。S表示亮度,C表示靜電容,R表示電阻,Q表示藉由射束照射而被蓄積於試料的電荷,Ti1表示作為第1射束照射條件的脈衝射束對試料的第1射束截斷時間,Ti2表示作為第2射束照射條件的脈衝射束對試料的第2射束截斷時間,Tir表示射束之照射時間。Even if the resistance value and the electrostatic capacitance value are mathematical models, databases, or models learned with a data set of brightness information and electrical characteristic information, such as
記憶式1、式1之變形或相當於式1之數學模型的電腦系統,係根據照射射束之截斷時間不同的兩種脈衝射束之時獲得的亮度之差量資訊(ΔS),導出C為靜電容,R為電阻的電特性。該手法只不過為一例,即使使用可以使與電特性之關係模型化的測量,或根據檢查工具輸出資訊之接收,導出上述般之電特性的其他手法亦可。The computer system that memorizes
EDA工具102係半導體裝置之設計、設計支援或以自動實行半導體裝置之動作之分析等的軟體,或用以實行其軟體之一個以上的電腦系統。The
EDA工具102係根據半導體裝置之設計資料、製品媒體、規格等的輸入,自動實行半導體裝置設計之支援等。使用EDA工具102的EDA製程中,包含例如系統設計、邏輯設計、機能驗證、測試用之資料合成和設計、網路連線表驗證、設計計畫、物理實現、在佈局層級上的電路功能之解析和擷取、物理驗證、佈局之幾何形狀之變更(調整)與遮罩資料準備等。The
即使EDA工具102之EDA製程,包含推定半導體製造工程(前工程)之最終階段中之半導體元件之電性輸出特性的處理亦可。再者,不僅EDA製程,即使在半導體裝置之製造工程中實施模擬等,因應模擬之結果而進行對半導體製造製程的反饋及/或前饋亦可。在本實施型態中如後述般,即使在例如半導體裝置之製造工程之中途中,輸入可以藉由中途工程取得的小規模電路之電特性,藉由模擬在最終階段中之半導體元件之電性輸出特性而求出的處理亦可。Even the EDA process of the
為了實行上述般的模擬,EDA工具102取得與從裸晶至最終工程為止被生成的電路有關的資訊,和在現工程中之小規模電路之電特性資訊。即使EDA工具102係具備藉由將從設計資料等被生成的網路連線表之一部分資訊與藉由電特性測量裝置103而獲得的資訊進行置換,生成包含一部分的實測值,根據該網路連線表等,能夠實行透過模擬求出在最終階段之半導體元件之電輸出特性的軟體、記憶應用程式的內部或外部之記憶媒體,實行上述模擬亦可。In order to perform the above-mentioned simulation, the
圖3為表示第1等效電路310和第2等效電路320之關係的側剖面示意圖。第1等效電路310係成為“裝置製造最終工程晶圓”之電測試機之評估對象的電路。第2等效電路320係成為“裝置製造之中途工程的晶圓”之電特性測量裝置103之評估對象的電路或電元件。FIG3 is a schematic side cross-sectional view showing the relationship between the first
半導體裝置係包含屬於構成電路之多數層的電元件,在無加工的晶圓(裸晶)上經由複數製造工程而形成多層構造。有在到達至最終工程的半導體裝置上,設置藉由探針之接觸等而可以測量電特性的電墊311(輸入)及電墊312(輸出)等之情形。藉由監視對該電墊供給特定輸入訊號(電流)之時的輸出訊號(電壓),可以判斷半導體裝置之工作質量或製造工程的適當性。Semiconductor devices include multiple layers of electrical components that constitute circuits, and are formed into multi-layer structures through multiple manufacturing processes on unprocessed wafers (bare crystals). On semiconductor devices that have reached the final process, pads 311 (input) and pads 312 (output) are sometimes provided, which can measure electrical characteristics by contact with a probe, etc. By monitoring the output signal (voltage) when a specific input signal (current) is supplied to the pad, the working quality of the semiconductor device or the suitability of the manufacturing process can be judged.
在半導體裝置之高度方向之內部形成電元件321或322。該些電元件係在半導體裝置製造工程之中途工程中被製造。在使測試探針接觸於電墊311和312而測量輸出訊號之情況,成為測量作為包含該些內部之電元件的半導體裝置全體的電特性。另一方面,在測量電元件321或322之電特性之情況,成為在半導體裝置製造工程之中途工程(即是,在疊層製程中形成電元件321或322之階段)使用電特性測量裝置103而測量其電特性。The
電特性測量裝置103測量電元件321或322之電特性之時,例如專利文獻1記載般,藉由接地些元件並照射帶電粒子束,取得電特性。因此,第2等效電路也係以將該些元件予以接地者來描述。對此,因半導體裝置不被限定為一定要在接地的狀態藉由測試機進行測量,故即使第1等效電路不包含接地亦可。When the electrical
圖4為表示對電墊311供給特定訊號之時,從電墊312獲得的輸出訊號的圖。圖4上段表示被連接於電墊的電路為正常之情況的輸出訊號。圖4下段表示電路存在某種異常之時的輸出訊號例。Fig. 4 is a diagram showing an output signal obtained from
若可以在至裝置製造工程之最終工程之前取得如此的輸出訊號時,則可以快速地朝半導體製造工程進行反饋。在本實施型態中,針對非以實測而係以運算(模擬)導出圖4例示的輸出訊號之例予以說明。If such an output signal can be obtained before the final process of the device manufacturing process, feedback can be quickly provided to the semiconductor manufacturing process. In this embodiment, an example of deriving the output signal shown in FIG. 4 by calculation (simulation) rather than actual measurement is described.
圖5為表示包含半導體裝置之設計工程的半導體裝置之製造製程之一部分的流程圖。FIG. 5 is a flow chart showing a part of a manufacturing process of a semiconductor device including a design process of the semiconductor device.
在步驟S501:EDA製程中,EDA工具102係接收由用以記憶設計資料構造的格式所作成的設計資料、用以在佈局上呈現構成電路之零件的配置或連接的Schematic資料、在特定之半導體製程進行電路設計之時使用的作為設計資訊檔案的PDK(Process Design File)等。In step S501: in the EDA process, the
步驟S502:EDA工具102所含的一個以上之電腦系統(處理器),係根據接收的資料,生成半導體裝置之三次元構造(3D Layout)資料。Step S502: One or more computer systems (processors) included in the
步驟S503~S504:一個以上之電腦系統係基於所生成的3D Layout資料而作成製程流程,同時生成用於之後的模擬的等效電路。Steps S503-S504: One or more computer systems create a process flow based on the generated 3D Layout data and simultaneously generate an equivalent circuit for subsequent simulation.
因藉由步驟S505:製程流程或等效電路之生成等,成為電特性測量裝置103之測量對象的製造工程和其座標變得清楚,故即使電特性測量裝置103基於製程流程資料而作成測量流程亦可。Since the manufacturing process and its coordinates that are the measurement objects of the electrical
步驟S506:在EDA製程中,一個以上之電腦系統係作成後述之S507中之電路解析中使用的裝置模型。裝置模型為例如解析式,在模型作成中,實行該解析式及解析式所含的變數、常數般之模型參數等的作成、設定。Step S506: In the EDA process, one or more computer systems create a device model used in the circuit analysis in S507 described later. The device model is, for example, an analytical expression, and in the model creation, the analytical expression and model parameters such as variables and constants contained in the analytical expression are created and set.
步驟S507:一個以上之電腦系統係針對成為包含測量對象之層的電路全體而生成等效電路之後,根據該等效電路等,實行SPICE(Simulation Program with Integrated Circuit Emphasis)等之電路模擬。電路模擬係以例如電路描述、電路解析、解析結果輸出之順序來實行。在此,將例如以電路圖編輯器被輸入的電路圖轉換為網路連線表,交接給解析引擎而自動地實行模擬。Step S507: After one or more computer systems generate an equivalent circuit for the entire circuit including the layer of the measurement object, they perform circuit simulation such as SPICE (Simulation Program with Integrated Circuit Emphasis) based on the equivalent circuit. Circuit simulation is performed in the order of circuit description, circuit analysis, and analysis result output. Here, the circuit diagram input by the circuit diagram editor is converted into a net connection table, which is handed over to the analysis engine to automatically perform simulation.
步驟S508:一個以上之電腦系統係藉由電路模擬而運算電特性,使被導出的電特性資訊記憶於特定的記憶媒體。一個以上的電腦系統係判斷是否因應被導出的電特性之適當性而判斷電路設計是否適當,因應所需而更新設計資料等。Step S508: One or more computer systems calculate electrical characteristics through circuit simulation, and store the derived electrical characteristics information in a specific storage medium. One or more computer systems determine whether the circuit design is appropriate based on the appropriateness of the derived electrical characteristics, and update the design data as needed.
經由上述般的半導體設計之製程,移行至半導體裝置之製造(量產)階段。在量產工程中,以半導體裝置之製程變動等的適當評估,和朝製造工程的反饋/前饋為佳。於是,在本實施型態中,針對利用在EDA製程所生成的模擬模型,而實施在量產階段中之工程管理的例予以說明。Through the semiconductor design process described above, the semiconductor device manufacturing (mass production) stage is moved to. In the mass production process, it is better to appropriately evaluate the process changes of the semiconductor device and provide feedback/feedback to the manufacturing process. Therefore, in this embodiment, an example of implementing engineering management in the mass production stage using the simulation model generated in the EDA process is explained.
在本實施型態中,雖然針對將與以EDA製程所生成的電路模擬、模型、等效電路等有關的資料,輸入至記憶EDA工具或特定程式的電腦系統的例予以說明,但是不限定於此,即使在量產工程中,使用EDA工具或其他電腦系統重新作成電路模擬、模型、等效電路,根據所獲得的等效電路等,而實施後述的處理亦可。In this embodiment, although an example is given of inputting data related to circuit simulation, model, equivalent circuit, etc. generated by an EDA process into a computer system that stores an EDA tool or a specific program, the present invention is not limited to this. Even in a mass production process, the circuit simulation, model, equivalent circuit, etc. may be recreated using an EDA tool or other computer system, and the processing described later may be performed based on the obtained equivalent circuit, etc.
在步驟S509:量產工程所含的半導體裝置之測量工程中,實行使用電特性測量裝置103的測量。在圖5例示的測量工程中,首先,接收以EDA製程所獲得的電特性輸出資訊。在EDA製程中,因為了適當的設計,藉由模擬求出裝置為正常之情況的電特性,故根據該資料作成參照資訊。在此,接收藉由模擬所求出的電特性,將其電特性設定為成為正常值的基準範圍(正常範圍)。作為參照資訊而使用的資訊不被限定於藉由模擬所獲得者,即使為例如參照處之實測值或其他適當值亦可。In step S509: in the measurement process of the semiconductor device included in the mass production process, measurement using the electrical
步驟S510:經過上述般的準備,實行以量產工程所製造的半導體晶圓之測量。接著,根據對電特性之評估對象,或被連接於評估對象之端子(插塞等)照射射束,實行電特性測量。Step S510: After the above preparations, the semiconductor wafers manufactured by the mass production process are measured. Then, the electrical characteristics are measured by irradiating the electrical characteristics of the evaluation object or the terminal (plug, etc.) connected to the evaluation object with a beam.
步驟S511:被內建在EDA工具102、電特性測量裝置103的一個以上之電腦系統,或能夠通訊地被連接於電特性測量裝置103之其他電腦系統(例如,電腦系統104),係接收靜電容值、電阻值等之半導體裝置之製造工程中途之電元件之電特性測量結果。即使電腦系統藉由其他電腦系統而被求出的電特性資訊亦可,接收被內建在電特性測量裝置103之檢測器輸出,根據該檢測器輸出,運算電特性資訊,並且實施後述的處理亦可。Step S511: One or more computer systems built into the
步驟S512:EDA工具102等係接收對電路模擬供給的裝置模型。雖然該裝置模型係以藉由EDA製程所生成者來說明,但是不被限定於此,即使藉由其他測量結果等,以量產工程作成更新參數後的裝置模型亦可。Step S512: The
步驟S513:EDA工具102等係藉由對裝置模型輸入特定元件之測量結果,更新裝置模型。將例如此時的第1等效電路所含的第2等效電路之電特性與在S510之電特性測量值替換。此時,準備相當於第1等效電路的網路連線表,和與電特性測量裝置103之測量結果(第2等效電路之測量結果)一起表示的GUI(Graphical User Interface)畫面,藉由能夠成為在各製造工程中取得的複數電特性測量結果之中,任意結果的選擇性輸入,可以實施因應能在不同的製造工程中測量的電元件之工作質量的模擬。GUI可以藉由例如電腦系統104而提供。Step S513: The
步驟S514~S515:EDA工具102等係藉由基於在S513部分性地輸入實測值的裝置模型,實行例如SPICE模擬(S514),輸出電特性(I-V,Vth,頻率特性等)。被輸出的電特性係藉由能夠在半導體裝置之製造工程之中途取得的實測值,從更新參數後的裝置模型被導出。因此,可以成為在最終工程之前判斷最終工程中之裝置的適當性。Steps S514-S515: The
步驟S516~S518:被輸出的電特性係與在步驟S509中被取得的參照資訊比較(S516)。根據其比較,實施缺陷判定(S517)。將缺陷判定結果反饋於製造製程(S518)。Steps S516 to S518: The output electrical characteristics are compared with the reference information obtained in step S509 (S516). Based on the comparison, defect determination is performed (S517). The defect determination result is fed back to the manufacturing process (S518).
圖6為電特性評估系統之處理流程圖。實施圖5中說明的流程圖之EDA工具102、電特性測量裝置103及控制該些的電腦系統(包含電腦系統104)可以構成為評估半導體裝置之電特性的電特性評估系統。圖6係相當於將圖5之流程圖之處理順序予以視覺性地改寫。FIG6 is a process flow chart of the electrical characteristics evaluation system. The
EDA工具102係接收設計資料、Schematic資料、PDK等(S501),使用此而作成3D Layout資料(S502)。EDA工具102係根據3D Layout資料而作成製程流程(S503)。EDA工具102係特定半導體元件之測量對象層及測量對象處,同時作成其等效電路(S504~S505)。在此所指的測量對象為在圖3中說明的第2等效電路。EDA工具102係作成最終工程(相當於半導體裝置之完成品)之等效電路之SPICE模擬模型(S506)。
另一方面,電特性測量裝置103係測量半導體元件(相當於第2等效電路)之電特性(S510),將其結果返回至EDA工具102(S513)。On the other hand, the electrical
EDA工具102係將電特性測量裝置103測量到的半導體元件(第2等效電路)之電特性,反映至SPICE模擬模型(S513)。EDA工具102係使用其反映結果,藉由實施半導體裝置全體(即是第1等效電路)之模擬而計算電特性(S514),輸出其結果(S515)。電特性測量裝置103係根據其結果,判定測量處有無缺陷(S516~S517)。The
圖7為電特性評估系統之處理流程圖。在圖6中,雖然一體性地記載電特性測量裝置103和電腦系統104,但是在圖7中將該些分開記載。電特性測量裝置103係藉由對在中途工程中被製造的半導體元件照射帶電粒子束,作成半導體元件之SEM像。電腦系統104係作成其測量配方或第2等效電路之網路連線表等,使用該些,控制取得SEM像的製程。電腦系統104係使用SEM像和第2等效電路之網路連線表,計算第2等效電路之電特性(電阻值或靜電容值),將其結果輸出至EDA工具102。FIG7 is a process flow chart of the electrical characteristic evaluation system. Although FIG6 shows the electrical
EDA工具102 係將第2等效電路之電特性反映在第1等效電路之網路連線表,並且使用此實施SPICE模擬。依此,可以取得電特性測量裝置103測量第2等效電路(即是,在製造中途工程中被作成的半導體元件)之電特性的結果,並且藉由EDA工具102模擬第1等效電路(即是,半導體裝置全體)之電特性。第1等效電路之有無缺陷的判定條件係在製造工程中事先準備,藉由對電腦系統104提供此,可以在電腦系統104中,根據SPICE模擬之結果判定有無缺陷。電腦系統104係輸出其判定結果,因應所需可以對製造工程反饋缺陷主要原因等。The
圖8為電特性評估系統之處理流程圖。在圖7中,針對特定的測量對象層之測量對象處,表示測量電特性之情況的處理流程。即是,圖7係用於僅針對指定位置取得測量結果。對此,在圖8中,進行更全面性地檢查所指定的對象層之對象區域為良品或者為不良品。因此,因電特性測量裝置103作為電特性檢查裝置而進行動作,故即使在圖8中也如此地予以記載。FIG8 is a process flow chart of the electrical characteristic evaluation system. In FIG7, the process flow of measuring electrical characteristics is shown for the measurement object of a specific measurement object layer. That is, FIG7 is used to obtain the measurement result only for the specified position. In contrast, in FIG8, a more comprehensive inspection is performed to check whether the object area of the specified object layer is a good product or a defective product. Therefore, since the electrical
電腦系統104係測量指定區域之電特性,根據其結果,判定指定區域為良品或者為不良品。EDA工具102係取得指定區域之電特性,模擬第1等效電路之電特性。電腦系統104係根據其模擬結果,判定第1等效電路良品或者為不良品。The
圖9為電特性評估系統所提供的使用者介面之一例。該使用者介面係可以在例如電腦系統104中作為GUI來提供。使用者在UI上選擇第1等效電路內所含的組件中之任何一個以上,指示模擬實施。EDA工具102係使用被選擇的組件,和電特性測量裝置103事先測量電元件之電特性的結果,實施模擬。即使一起呈現電元件之電特性亦可。即使UI一起呈現模擬結果以及在圖7說明的Pass/Fail或良品/不良品之判定結果等亦可。FIG9 is an example of a user interface provided by the electrical characteristics evaluation system. The user interface can be provided as a GUI in, for example, a
[針對本揭示之變形例]
在以上的實施型態中,EDA工具102擷取電特性測量裝置103測量電元件321等之電特性的結果之時,電特性測量裝置103係以EDA工具102可以擷取的資料形式,輸出電元件321等之電特性及第2等效電路之網路連線表。EDA工具102係將該些統合至第1等效電路之網路連線表。具體的資料形式或統合處理若因應EDA工具102之規格等而適當設定即可。或是,即使電特性測量裝置103係輸出例如測試資料等的泛用性資料形式,使轉換資料格式的製程介於電特性測量裝置103和EDA工具102之間,使兩者可以資料交換亦可。無論在哪一個情況,電特性測量裝置103皆以EDA工具102最終可以擷取的資料形式,輸出電元件321等之電特性及第2等效電路之網路連線表。
[Variations of the present disclosure]
In the above implementation, when the
在以上的實施型態中,在圖5~圖8說明的處理流程係可以藉由電腦系統(例如電腦系統104)實行安裝有該流程之程式來實現。即使程式係藉由單一程式模組構成亦可,即使分割成複數程式模組而構成亦可。即使各程式模組配置在相同的電腦系統上亦可,即使將任何的程式模組分散配置在兩個以上之電腦系統上亦可。In the above implementation, the processing flow described in FIG. 5 to FIG. 8 can be realized by executing a program installed with the process on a computer system (e.g., computer system 104). The program may be composed of a single program module or may be divided into a plurality of program modules. Each program module may be configured on the same computer system or any program module may be distributed on two or more computer systems.
在以上的實施型態中,即使電腦系統104或與此同等的電腦系統針對EDA工具102、電特性測量裝置103及測量裝置105之各者配置亦可,即使單一的電腦系統控制該些之中之任一者或兩個以上亦可。In the above embodiments, the
在以上的實施型態中,說明電特性測量裝置103係因應電特性評估系統之目的,測量或檢查在半導體裝置之製造中途工程中被製造的半導體元件之電特性。電特性測量裝置103進行的實施並不限定於此,可以實施半導體裝置之電特性之一般評估。在此所指的評估除了測量、檢查等之外,也包含取得半導體裝置之物理性狀態的任意製程。因此,電特性測量裝置103更一般而言具有作為電特性評估裝置的作用。In the above embodiment, the electrical
101:設計資料記憶媒體 102:EDA工具 103:電特性測量裝置 104:電腦系統 105:測量裝置 101: Design data storage medium 102: EDA tool 103: Electrical characteristics measurement device 104: Computer system 105: Measurement device
[圖1]為表示包含能在裝置製造中途工程中測量半導體晶圓所含的電元件之特性的測量工具的電特性評估系統之概要的圖。
[圖2]為表示當脈衝狀地照射電子束之時,相對於其截斷時間(脈衝束之不照射的時間)變化的SEM畫像之亮度變化的曲線圖。
[圖3]為表示第1等效電路310和第2等效電路320之關係的側剖面示意圖。
[圖4]為表示對電墊311供給特定訊號之時,從電墊312獲得的輸出訊號的圖。
[圖5]為表示包含半導體裝置之設計工程的半導體裝置之製造製程之一部分的流程圖。
[圖6]為電特性評估系統之處理流程圖。
[圖7]為電特性評估系統之處理流程圖。
[圖8]為電特性評估系統之處理流程圖。
[圖9]為電特性評估系統所提供的使用者介面之一例。
[FIG. 1] is a diagram showing an overview of an electrical characteristics evaluation system including a measurement tool capable of measuring the characteristics of an electrical element included in a semiconductor wafer in the process of device manufacturing.
[FIG. 2] is a graph showing the change in brightness of an SEM image relative to the change in the cutoff time (time when the pulse beam is not irradiated) when an electron beam is irradiated in a pulsed manner.
[FIG. 3] is a schematic side cross-sectional diagram showing the relationship between the first
101:設計資料記憶媒體 101: Design data storage media
102:EDA工具 102:EDA tools
103:電特性測量裝置 103: Electrical characteristics measurement device
104:電腦系統 104: Computer system
105:測量裝置 105: Measuring device
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| US20180366326A1 (en) * | 2009-06-30 | 2018-12-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| TW201909448A (en) * | 2009-11-27 | 2019-03-01 | 日商半導體能源研究所股份有限公司 | Semiconductor device |
| TWI745357B (en) * | 2016-03-18 | 2021-11-11 | 日商半導體能源研究所股份有限公司 | Semiconductor device, semiconductor wafer, and electronic device |
| TWI779937B (en) * | 2009-07-03 | 2022-10-01 | 日商半導體能源研究所股份有限公司 | Method for manufacturing semiconductor device |
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| US10678978B1 (en) * | 2017-09-30 | 2020-06-09 | Cadence Design Systems, Inc. | Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view |
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| US20180366326A1 (en) * | 2009-06-30 | 2018-12-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| TWI779937B (en) * | 2009-07-03 | 2022-10-01 | 日商半導體能源研究所股份有限公司 | Method for manufacturing semiconductor device |
| TW201909448A (en) * | 2009-11-27 | 2019-03-01 | 日商半導體能源研究所股份有限公司 | Semiconductor device |
| TWI745357B (en) * | 2016-03-18 | 2021-11-11 | 日商半導體能源研究所股份有限公司 | Semiconductor device, semiconductor wafer, and electronic device |
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