TWI889123B - Manufacturing method of non-volatile memory - Google Patents

Abstract

Provided is a manufacturing method of a non-volatile memory. The manufacturing method includes the following steps. A first gate structure and a second gate structure are formed on a substrate in an active area, wherein the first gate structure extends onto an isolation structure. Doping regions are formed in the substrate at both sides of the first gate structure and at both sides of the second gate structure. An inter-gate dielectric layer covering the first gate structure is formed. An inter-layer dielectric layer is formed on the substrate and the isolation structure. A first contact opening, a second contact opening and a control gate opening are formed in the inter-layer dielectric layer. The first contact opening exposes the doped regions, the second contact opening exposes a gate of the second gate structure, and the control gate opening exposes a region where the first gate structure is formed on the isolation structure. A conductive layer is formed in the first contact opening, the second contact opening and the control gate opening.

Description

Manufacturing method of non-volatile memory

The present invention relates to a method for manufacturing a memory, and in particular to a method for manufacturing a non-volatile memory.

Since non-volatile memory can perform multiple operations such as data storage, reading and erasing, and has the advantages of not losing stored data when the power supply is interrupted, short data access time and low power consumption, it has become a type of memory widely used in personal computers and electronic devices.

In particular, for multi-time programmable (MTP) memory, how to effectively improve the coupling ratio between the control gate and the floating gate is a very important issue. Generally speaking, in order to form a control gate with a high coupling ratio with the floating gate, an additional mask is often required in the process of forming the control gate. This makes the process steps more complicated and increases the manufacturing cost.

The present invention provides a method for manufacturing a non-volatile memory, wherein a control gate and a contact window are formed in the same process step.

The manufacturing method of the non-volatile memory of the present invention comprises the following steps: providing a substrate, wherein an isolation structure defining an active region is formed in the substrate; forming a first gate structure and a second gate structure on the substrate in the active region, wherein the first gate structure extends onto the isolation structure; forming a doped region in the substrate on both sides of the first gate structure and on both sides of the second gate structure; forming an inter-gate dielectric layer covering the first gate structure; and forming an inter-layer dielectric layer on the substrate and the isolation structure. A first contact window opening, a second contact window opening, and a control gate opening are formed in the interlayer dielectric layer, wherein the first contact window opening exposes the doped region, the second contact window opening exposes the gate of the second gate structure, and the control gate opening exposes the region on the isolation structure where the first gate structure is formed. A conductive layer is formed in the first contact window opening, the second contact window opening, and the control gate opening.

In one embodiment of the manufacturing method of the non-volatile memory of the present invention, when viewed from a top view, the first gate structure includes a main body portion located on the substrate in the active region and a comb-shaped portion connected to the main body portion and located on the isolation structure.

In one embodiment of the manufacturing method of the non-volatile memory of the present invention, the area exposed by the control gate opening corresponds to the position of the comb-shaped portion.

In one embodiment of the manufacturing method of the non-volatile memory of the present invention, the method for forming the inter-gate dielectric layer includes the following steps. A dielectric material layer is conformally formed on the substrate and the isolation structure. A patterning process is performed to remove part of the dielectric material layer to retain the dielectric material layer covering the first gate structure.

In one embodiment of the method for manufacturing a non-volatile memory of the present invention, after forming the inter-gate dielectric layer and before forming the inter-layer dielectric layer, a metal silicide layer is further formed on the exposed doped region and on the gate of the second gate structure.

In one embodiment of the method for manufacturing a non-volatile memory of the present invention, after forming the inter-gate dielectric layer and before forming the inter-layer dielectric layer, an etch stop layer is conformally formed on the substrate and the isolation structure.

In one embodiment of the manufacturing method of the non-volatile memory of the present invention, the first contact window opening, the second contact window opening and the control gate opening are formed by patterning process using a photomask.

In one embodiment of the manufacturing method of the non-volatile memory of the present invention, the method for forming the conductive layer includes the following steps. Forming a conductive material layer on the substrate and the isolation structure to fill the first contact window opening, the second contact window opening and the control gate opening. Removing the conductive material layer outside the first contact window opening, the second contact window opening and the control gate opening.

In one embodiment of the manufacturing method of the non-volatile memory of the present invention, the inter-gate dielectric layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon nitride layer formed between the first silicon oxide layer and the second silicon oxide layer.

In one embodiment of the manufacturing method of the non-volatile memory of the present invention, the first gate structure and the second gate structure each include a gate dielectric layer, the gate formed on the gate dielectric layer, and a spacer formed on the sidewalls of the gate dielectric layer and the gate.

Based on the above, in the manufacturing method of the non-volatile memory of the present invention, in the process of forming the contact window opening, a control gate opening exposing the area where the control gate is to be formed is formed at the same time, so there is no need to use an additional mask to form the control gate, which simplifies the process steps and reduces the manufacturing cost.

100: Base

102: Isolation structure

104: Mixed area

106: Dielectric material layer

106a: first silicon oxide layer

106b: Second silicon oxide layer

106c: Silicon nitride layer

108: Patterned mask layer

110: Gate dielectric layer

112: Metal silicide layer

114: Etch stop layer

116: Interlayer dielectric layer

118:Conductive layer

120: Control gate

AA: Active Area

CT1, CT2: contact window

G1: First gate structure

G1-1: Main body

G1-2: Comb-shaped part

G1_a, G2_a: Gate dielectric layer

G1_b, G2_b: Gate

G1_c, G2_c: gap wall

G2: Second gate structure

OP1: First contact window opening

OP2: Second contact window opening

OP3: Control gate opening

FIG1 is a top view schematic diagram of the first gate structure and the second gate structure of the non-volatile memory of an embodiment of the present invention.

Figures 2A to 2F are schematic cross-sectional views of the manufacturing process of the non-volatile memory along the I-I section line in Figure 1.

Figures 3A to 3F are schematic cross-sectional views of the manufacturing process of the non-volatile memory along the II-II section line in Figure 1.

The following examples are listed and illustrated in detail, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn in original size. For ease of understanding, the same components will be indicated by the same symbols in the following description.

The terms "include", "including", "have", etc. used in this article are all open terms, which means "including but not limited to".

When the terms "first", "second", etc. are used to describe an element, they are only used to distinguish these elements from each other and do not limit the order or importance of these elements. Therefore, in some cases, the first element may also be called the second element, and the second element may also be called the first element, and this does not deviate from the scope of the present invention.

In addition, the directional terms mentioned in the text, such as "upper", "lower", etc., are only used to refer to the direction of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when an element such as a layer or a film is placed "on" another element, the element can be placed directly on the other element, or there can be an intermediate element. On the other hand, when an element is said to be placed "directly" on another element, there is no intermediate element between the two.

FIG1 is a top view schematic diagram of the first gate structure and the second gate structure of the non-volatile memory of the embodiment of the present invention. FIG2A to FIG2F are cross-sectional schematic diagrams of the manufacturing process of the non-volatile memory along the I-I section line in FIG1. FIG3A to FIG3F are cross-sectional schematic diagrams of the manufacturing process of the non-volatile memory along the II-II section line in FIG1.

First, please refer to FIG. 1, FIG. 2A and FIG. 3A at the same time to provide a substrate 100. In this embodiment, the substrate 100 is a silicon substrate, but the present invention is not limited thereto. Then, an isolation structure 102 is formed in the substrate 100 to define an active area AA. In this embodiment, the isolation structure 102 is a shallow trench isolation (STI) structure, but the present invention is not limited thereto. The method for forming the isolation structure 102 is well known to those skilled in the art and will not be described in detail here.

Next, a first gate structure G1 and a second gate structure G2 are formed on the substrate 100 in the active area AA. The first gate structure G1 and the second gate structure G2 each include a gate dielectric layer, a gate formed on the gate dielectric layer, and a spacer formed on the sidewalls of the gate dielectric layer and the gate. In detail, the first gate structure G1 includes a gate dielectric layer G1_a, a gate G1_b formed on the gate dielectric layer G1_a, and a spacer G1_c formed on the sidewalls of the gate dielectric layer G1_a and the gate G1_b, and the second gate structure G2 includes a gate dielectric layer G2_a, a gate G2_b formed on the gate dielectric layer G2_a, and a spacer G2_c formed on the sidewalls of the gate dielectric layer G2_a and the gate G2_b. In this embodiment, the first gate structure G1 serves as a floating gate in a non-volatile memory, and the second gate structure G2 serves as a select gate. The formation methods of the first gate structure G1 and the second gate structure G2 are well known to those skilled in the art and will not be described in detail herein.

In addition, in this embodiment, the first gate structure G1 extends onto the isolation structure 102. That is, in this embodiment, a portion of the first gate structure G1 is formed on the substrate 100 in the active area AA, and another portion of the first gate structure G1 is formed on the isolation structure 102. The first gate structure G1 formed on the isolation structure 102 is used to couple with the control gate in the non-volatile memory, which will be described later.

In this embodiment, the first gate structure G1 is comb-shaped when viewed from the top, but the present invention is not limited thereto. In other embodiments, the first gate structure G1 may have other shapes, such as straight line, curved line, etc., when viewed from the top. Specifically, in this embodiment, when viewed from the top, the first gate structure G1 includes a main body G1-1 located on the substrate 100 in the active area AA and a comb-shaped part G1-2 connected to the main body G1-1 and located on the isolation structure 102.

After forming the first gate structure G1 and the second gate structure G2, a doped region 104 is formed in the substrate 100 on both sides of the first gate structure G1 and in the substrate 100 on both sides of the second gate structure G2. The doped region 104 can be used as a source/drain region.

Next, please refer to FIG. 2B and FIG. 3B at the same time, and conformally form a dielectric material layer 106 on the substrate 100 and the isolation structure 102. The dielectric material layer 106 is used to form an inter-gate dielectric layer between the floating gate and the control gate. In this embodiment, the dielectric material layer 106 includes a first silicon oxide layer 106a, a second silicon oxide layer 106b, and a silicon nitride layer 106c formed between the first silicon oxide layer 106a and the second silicon oxide layer 106b, but the present invention is not limited thereto.

Then, referring to FIG. 2C and FIG. 3C , a patterned mask layer 108 is formed on the dielectric material layer 106. The patterned mask layer 108 covers the first gate structure G1. In this embodiment, the patterned mask layer 108 is a patterned photoresist layer, but the present invention is not limited thereto. Then, an etching process is performed using the patterned mask layer 108 as an etching mask to remove the dielectric material layer 106 not covered by the patterned mask layer 108, so as to retain the dielectric material layer 106 covering the first gate structure G1. In this way, the dielectric material layer 106 covering the first gate structure G1 forms an inter-gate dielectric layer 110, and the inter-gate dielectric layer 110 covers the top surface and sidewalls of the first gate structure G1.

After forming the inter-gate dielectric layer 110, a metal silicide layer 112 may be formed on the exposed doped region 104 and on the gate G2_b of the second gate structure G2. The metal silicide layer 112 may be formed by, for example, performing a self-aligned silicide (salicide) process.

Then, please refer to FIG. 2D and FIG. 3D at the same time to remove the patterned mask layer 108. In other embodiments, the patterned mask layer 108 may be removed before forming the metal silicide layer 112. Then, an etch stop layer 114 may be conformally formed on the substrate 100 and the isolation structure 102. The etch stop layer 114 is used as an etch stop layer when a contact window is subsequently formed, so it may also be referred to as a contact window etch stop layer (contact etch stop layer, CESL). In this embodiment, the etch stop layer 114 may be a silicon nitride layer. In other embodiments, the etch stop layer 114 may be omitted depending on the actual situation.

After forming the etch stop layer 114, an interlayer dielectric layer 116 is formed on the substrate 100 and the isolation structure 102. In the present embodiment, the interlayer dielectric layer 116 is formed on the etch stop layer 114. The material of the interlayer dielectric layer 116 is, for example, silicon oxide.

Next, referring to FIG. 2E and FIG. 3E , a first contact window opening OP1, a second contact window opening OP2, and a control gate opening OP3 are formed in the interlayer dielectric layer 116. In the present embodiment, the first contact window opening OP1 exposes the metal silicide layer 112 on the doped region 104, and the second contact window opening OP2 exposes the metal silicide layer 112 on the gate G2_b of the second gate structure G2. In addition, the control gate opening OP3 exposes the region on the isolation structure 102 where the first gate structure G1 is formed. In this embodiment, the control gate opening OP3 exposes the area corresponding to the position of the comb-shaped portion G1-2 of the first gate structure G1.

In an embodiment where the metal silicide layer 112 is not formed, the first contact window opening OP1 exposes the doped region 104, and the second contact window opening OP2 exposes the gate G2_b of the second gate structure G2.

Afterwards, please refer to FIG. 2F and FIG. 3F at the same time, and form a conductive layer 118 in the first contact window opening OP1, the second contact window opening OP2, and the control gate opening OP3. In the present embodiment, the material of the conductive layer 118 is tungsten, but the present invention is not limited thereto. The method for forming the conductive layer 118 may include the following steps. First, a conductive material layer is formed on the interlayer dielectric layer 116 to fill the first contact window opening OP1, the second contact window opening OP2, and the control gate opening OP3. Afterwards, for example, a chemical mechanical polishing (CMP) process is performed to remove the conductive material layer outside the first contact window opening OP1, the second contact window opening OP2, and the control gate opening OP3. The conductive layer 118 formed in the first contact window opening OP1 serves as a contact window CT1 electrically connected to the doped region 104, and the conductive layer 118 formed in the second contact window opening OP2 serves as a contact window CT2 electrically connected to the gate G2_b of the second gate structure G2. In addition, the conductive layer 118 formed in the control gate opening OP3 serves as a control gate 120 of the non-volatile memory. In this way, the non-volatile memory of this embodiment is formed.

In this embodiment, since the inter-gate dielectric layer 110 covers the top surface and the sidewalls of the first gate structure G1, the control gate 120 formed in the control gate opening OP3 and the gate G1_b of the first gate structure G1 can be coupled at the top surface and the sidewalls to have a high coupling ratio.

In the manufacturing method of the non-volatile memory of the present embodiment, in the process of forming the contact window opening, a control gate opening is simultaneously formed to expose the area where the control gate is to be formed. In particular, for the interlayer dielectric layer 116, a mask is used to perform a patterning process to simultaneously form the first contact window opening OP1, the second contact window opening OP2 and the control gate opening OP3 in the interlayer dielectric layer 116. In this way, there is no need to use an additional mask to form the control gate, and a control gate 120 with a high coupling ratio with the floating gate (gate G1_b of the first gate structure G1) can be formed on the isolation structure 102.

In addition, in this embodiment, since the control gate 120 and the contact window CT1 electrically connected to the doped region 104 and the contact window CT2 electrically connected to the gate G2_b of the second gate structure G2 can be formed in the same process step, the process steps of the non-volatile memory are effectively simplified.

Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the attached patent application.

102: Isolation structure

110: Gate dielectric layer

114: Etch stop layer

116: Interlayer dielectric layer

G1: First gate structure

OP3: Control gate opening

Claims (10)

A method for manufacturing a non-volatile memory, comprising: Providing a substrate, wherein an isolation structure defining an active region is formed in the substrate; Forming a first gate structure and a second gate structure on the substrate in the active region, wherein the first gate structure extends onto the isolation structure; Forming a doped region in the substrate on both sides of the first gate structure and on both sides of the second gate structure; Forming an inter-gate dielectric layer covering the first gate structure; Forming an inter-layer dielectric layer on the substrate and the isolation structure; A first contact window opening, a second contact window opening, and a control gate opening are formed in the interlayer dielectric layer, wherein the first contact window opening exposes the doped region, the second contact window opening exposes the gate of the second gate structure, and the control gate opening exposes a region corresponding to the entire first gate structure on the isolation structure; and a conductive layer is formed in the first contact window opening, the second contact window opening, and the control gate opening. The method for manufacturing a non-volatile memory as described in claim 1, wherein, viewed from a top view, the first gate structure includes a main body portion located on the substrate in the active area and a comb-shaped portion connected to the main body portion and located on the isolation structure. A method for manufacturing a non-volatile memory as described in claim 2, wherein the area exposed by the control gate opening corresponds to the position of the comb-shaped portion. The method for manufacturing a non-volatile memory as described in claim 1, wherein the method for forming the inter-gate dielectric layer comprises: Forming a dielectric material layer conformally on the substrate and the isolation structure; and Performing a patterning process to remove a portion of the dielectric material layer to retain the dielectric material layer covering the first gate structure. The method for manufacturing a non-volatile memory as described in claim 1, wherein after forming the inter-gate dielectric layer and before forming the inter-layer dielectric layer, a metal silicide layer is further formed on the exposed doped region and on the gate of the second gate structure. The method for manufacturing a non-volatile memory as described in claim 1 further comprises conformally forming an etch stop layer on the substrate and the isolation structure after forming the inter-gate dielectric layer and before forming the inter-layer dielectric layer. The method for manufacturing a non-volatile memory as described in claim 1, wherein the first contact window opening, the second contact window opening and the control gate opening are formed by a patterning process using a mask. The method for manufacturing a non-volatile memory as described in claim 1, wherein the method for forming the conductive layer comprises: forming a conductive material layer on the substrate and the isolation structure to fill the first contact window opening, the second contact window opening and the control gate opening; and removing the conductive material layer outside the first contact window opening, the second contact window opening and the control gate opening. The method for manufacturing a non-volatile memory as described in claim 1, wherein the intergate dielectric layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon nitride layer formed between the first silicon oxide layer and the second silicon oxide layer. A method for manufacturing a non-volatile memory as described in claim 1, wherein the first gate structure and the second gate structure each include a gate dielectric layer, a gate of the first gate structure and a gate of the second gate structure formed on the gate dielectric layer, and a spacer formed on the side walls of the gate dielectric layer, the gate of the first gate structure, and the gate of the second gate structure.

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