TWI889013B - Electronic package and manufacturing method thereof - Google Patents

Abstract

An electronic package, comprising: a circuit structure having opposite first and second sides; an electronic element provided on the first side of the circuit structure; conductive bumps provided on the second side of the circuit structure; an encapsulation layer provided on the first side of the circuit structure to cover the electronic element; and a concave-convex structure formed on the encapsulation layer and defined at least one high heat-absorption area corresponding to at least one of the conductive bumps. The present invention further provides a method for fabricating the electronic package.

Description

Electronic packaging and its manufacturing method

The present invention relates to a semiconductor packaging process, in particular to an electronic packaging component and a manufacturing method thereof that can avoid solder non-wetting.

With the development of technology, the demand for electronic products is moving towards high-end products with high-density circuits, high transmission speeds, high stacking numbers, and large-size designs. As the chip size and number of contacts (I/O) increase, these products are more sensitive to heat. Therefore, the thermal processes in the packaging operation, such as the reflow process, are very likely to cause the overall structure to warp due to the different coefficients of thermal expansion (CTE) between the materials, and may also cause poor reliability due to the concentration of thermal stress inside the structure.

The current Laser Assisted Bonding (LAB) process can selectively heat locally and has the characteristics of rapid temperature rise, so it can greatly shorten the heating process time, thereby reducing the concentration of thermal stress inside the structure, and by controlling the laser wavelength and the characteristics of local heating, the degree of warping can be greatly reduced.

FIG1 is a schematic diagram of a conventional semiconductor package 1. As shown in FIG1, the semiconductor package 1 is a semiconductor chip 11 disposed on a substrate structure 10 having a dielectric layer 100 and a wiring layer 101 in a flip-chip manner (via solder bumps 13), and then the semiconductor chip 11 is encapsulated by a packaging layer 12. Afterwards, the conductive bumps 14 and 15 on the lower side of the substrate structure 10 are connected to the contacts 19 of a circuit board 1a through a plurality of solder materials 16 and 17 by a LAB process.

However, during the LAB process, the heat energy of the laser L can only penetrate the semiconductor chip 11 but cannot penetrate the packaging layer 12, resulting in insufficient heat energy for the conductive bump 14 under the packaging layer 12, thus causing the solder material 16 there to have a non-wetting problem.

Therefore, how to overcome the above-mentioned problems of knowledge and technology has become an urgent issue to be solved.

In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic package, comprising: a circuit structure having a first side and a second side opposite to each other; an electronic component disposed on the first side of the circuit structure; a conductive bump disposed on the second side of the circuit structure; a packaging layer having a first surface and a second surface opposite to each other, and the second surface is disposed on the first side of the circuit structure to cover the electronic component; and a concave-convex structure formed on the first surface of the packaging layer and defining at least one high heat absorption area corresponding to at least one of the conductive bumps.

As mentioned above, in the electronic package, the surface roughness of the high heat absorption area ranges from 5 to 10.

As in the aforementioned electronic package, the concave-convex structure has a plurality of concave portions.

In the aforementioned electronic package, the depth-to-width ratio of each of the plurality of recesses is less than or equal to 3:1.

As in the aforementioned electronic package, the shortest distance between the edges of any two adjacent multiple recesses is greater than or equal to the width of each of the multiple recesses.

In the aforementioned electronic package, the width of each of the plurality of recesses is less than 10μm.

In the aforementioned electronic package, when the thickness of the packaging layer is less than 200 μm, the depth of each of the plurality of recesses is less than 1/3 of the thickness of the packaging layer.

In the aforementioned electronic package, a single high heat absorption area corresponds to a single conductive bump, and the radius of the high heat absorption area is greater than or equal to twice the radius of the conductive bump.

As in the aforementioned electronic package, a plurality of high heat absorption areas correspond to a single conductive bump.

In the aforementioned electronic package, the radius of the circle inscribed in the plurality of high heat absorption regions is greater than or equal to twice the radius of the conductive bump.

As in the aforementioned electronic package, a single high heat absorption area corresponds to a plurality of conductive bumps.

In the aforementioned electronic package, the radius of the high heat absorption area is greater than or equal to twice the radius of the circle inscribed within the plurality of the conductive bumps.

In the aforementioned electronic package, the surface roughness of the high heat absorption area located at the corner of the packaging layer is greater than the surface roughness of the high heat absorption area not located at the corner of the packaging layer.

As in the aforementioned electronic package, the surface roughness of a single high heat absorption area gradually decreases from the center of the area toward the outside.

The present invention further provides a method for manufacturing an electronic package, comprising: providing a circuit structure having a first side and a second side opposite to each other; disposing an electronic component on the first side of the circuit structure; disposing a packaging layer having a first surface and a second surface opposite to each other on the first side of the circuit structure with the second surface to cover the electronic component; forming a concave-convex structure on the first surface of the packaging layer; and disposing a conductive bump on the second side of the circuit structure, and making the concave-convex structure define at least one high heat absorption area corresponding to at least one of the conductive bumps.

In the aforementioned method for manufacturing an electronic package, the concave-convex structure is formed on the first surface of the package layer by etching.

In the aforementioned method for manufacturing an electronic package, the circuit structure includes a fan-out type redistribution circuit layer.

In the aforementioned method for manufacturing electronic packages, the surface roughness of the high heat absorption area ranges from 5 to 10.

In the aforementioned method for manufacturing electronic packages, the concave-convex structure has a plurality of concave portions.

In the aforementioned method for manufacturing electronic packaging, the depth-to-width ratio of each of the plurality of recesses is less than or equal to 3:1, and the shortest distance between the edges of any two adjacent plurality of recesses is greater than or equal to the width of each of the plurality of recesses.

In the aforementioned method for manufacturing electronic packages, a single high heat absorption region corresponds to a single conductive bump, and the radius of the high heat absorption region is greater than or equal to twice the radius of the conductive bump.

In the aforementioned method for manufacturing electronic packages, a plurality of high heat absorption regions correspond to a single conductive bump.

In the aforementioned method for manufacturing electronic packages, a single high heat absorption area corresponds to a plurality of conductive bumps.

In summary, the electronic package and its manufacturing method of the present invention can reduce the reflection of laser light and increase the absorption of laser light by forming a concave-convex structure on the packaging layer, thereby increasing the thermal conductivity of the packaging layer. The higher the surface roughness of the high energy absorption area, the higher the penetration rate of the laser energy, thereby avoiding the problem of non-wetting between the conductive bump and the solder material under the packaging layer. The electronic package and its manufacturing method of the present invention can enable the LAB process to be applied to a coreless packaging substrate that is easy to warp, and has the best effect of improving thermal stress problems.

1:Semiconductor packages

1a,3a: Circuit board

10:Substrate structure

100: Dielectric layer

101,201: Wiring layer

11: Semiconductor chip

12,22: Packaging layer

13: Solder bumps

14,15,24: Conductive bumps

16,17,25: Soldering materials

19,30: Contact

2: Electronic packaging components

20:Line structure

20a: First side

20b: Second side

200: Insulation layer

21: Electronic components

21a: Action surface

21b: Non-active surface

211: Conductor

212: Insulation material

22a: First surface

22b: Second surface

23: Concave and convex structure

231,231’,231”: concave part

9: Support plate

A: Width

B: Shortest distance to edge

C,C’:circle

H,H’,H”: Depth

L:Laser

X, X’: high heat absorption area

Figure 1 is a schematic cross-sectional view of a conventional semiconductor package.

Figures 2A to 2E are cross-sectional schematic diagrams of the manufacturing method of the electronic package of the present invention.

Figures 3A and 3B are cross-sectional schematic diagrams of different embodiments of the concave-convex structure in the electronic package of the present invention.

Figure 3C is a schematic diagram of the top surface of Figure 2E.

Figures 3D to 3G are schematic diagrams of different correspondences between the high heat absorption area and the conductive bump in the electronic package of the present invention.

The following is a specific and concrete example to illustrate the implementation of the present invention. People familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this manual.

It should be noted that the structures, proportions, sizes, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effect and purpose that can be achieved by the present invention. At the same time, the terms such as "above", "first", "second" and "one" used in this specification are only used to facilitate the clarity of the description, and are not used to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships, without substantially changing the technical content, should also be regarded as the scope of implementation of the present invention.

Figures 2A to 2E are cross-sectional schematic diagrams of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A , a circuit structure 20 is disposed on a supporting plate 9, and at least one electronic component 21 is disposed on the circuit structure 20.

In this embodiment, the support plate 9 is, for example, a plate made of a semiconductor material (such as silicon or glass), and the circuit structure 20 is, for example, a packaging substrate with a core layer, a coreless packaging substrate, a silicon interposer (TSI) with a conductive through-silicon via (TSV), or other board types, which have a relative first side 20a and a second side 20b, so that the circuit structure 20 is coupled to the support plate 9 with its second side 20b. For example, the circuit structure 20 includes at least one insulating layer 200 and at least one wiring layer 201 combined with the insulating layer 200, such as at least one fan-out redistribution layer (RDL). It should be understood that the circuit structure 20 can also be other substrates that carry chips, such as lead frames, wafers, or other boards with metal routing, etc., and is not limited to the above.

In this embodiment, the electronic component 21 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. In this embodiment, the electronic component 21 is a semiconductor chip having an active surface 21a and an inactive surface 21b opposite to each other, wherein the active surface 21a has a plurality of electrode pads, and a plurality of conductive bodies 211 such as solder materials, metal pillars or a combination thereof are disposed on the first side 20a of the circuit structure 20 by flip chip method and electrically connected to the layout. The wiring layer 201 of the circuit structure 20 is provided with an insulating material 212 such as a primer or a non-conductive bottom fill film (NCF) to cover the conductive bodies 211; or, the electronic component 21 can be electrically connected to the wiring layer 201 of the circuit structure 20 by a plurality of bonding wires (not shown) by bonding; or, the electronic component 21 can directly contact the wiring layer 201 of the circuit structure 20. Therefore, there are many ways for the electronic component 21 to be electrically connected to the circuit structure 20, which are not limited to the above.

As shown in FIG. 2B , a packaging layer 22 is formed on the first side 20a of the circuit structure 20 so that the packaging layer 22 covers the electronic component 21.

In this embodiment, the packaging layer 22 has a first surface 22a and a second surface 22b opposite to each other, and the second surface 22b is disposed on the first side 20a of the circuit structure 20. In addition, the packaging layer 22 can be an insulating material, such as polyimide (PI), a dry film, a packaging colloid such as epoxy, or a molding compound.

In one embodiment, the first surface 22a of the packaging layer 22 can be optionally leveled with the inactive surface 21b of the electronic component 21 by a flattening process, so that the inactive surface 21b of the electronic component 21 is exposed on the first surface 22a of the packaging layer 22. For example, the flattening process removes part of the material of the electronic component 21 and part of the material of the packaging layer 22 by grinding. It should be understood that the flattening process can also be omitted so that the packaging layer 22 covers the inactive surface 21b of the electronic component 21.

As shown in FIG. 2C , a concave-convex structure 23 is formed on the first surface 22a of the packaging layer 22.

In this embodiment, plasma etching is used to remove part of the material of the first surface 22a of the packaging layer 22 to form the concave-convex structure 23. As shown in FIG3A , the concave-convex structure 23 has a plurality of concave portions 231, each of which has a depth H and a width A, and any two adjacent concave portions 231 have a shortest edge distance B.

In one embodiment, the aspect ratio between the depth H and the width A may be less than or equal to 3:1.

In one embodiment, the shortest distance B between the edges of any two adjacent recesses 231 is greater than or equal to the width A of each recess 231.

In one embodiment, the width A of each recess 231 is less than 10 μm.

In one embodiment, the depth H of each recess 231 can be determined by the thickness of the packaging layer 22. For example, when the thickness of the packaging layer 22 is less than 200 μm, the depth H of each recess 231 is less than 1/3 of the thickness of the packaging layer 22.

As shown in FIG. 2D , the support plate 9 is removed to expose the second side 20b of the circuit structure 20 , and then a plurality of conductive bumps 24 are arranged on the second side 20b of the circuit structure 20 , and a singulation process is performed along the cutting path Y shown in FIG. 2C to obtain the electronic package 2 of the present invention, wherein the conductive bumps 24 are electrically connected to the wiring layer 201 so that the electronic component 21 is electrically connected to the conductive bumps 24 .

In this embodiment, the concave-convex structure 23 defines at least one high heat absorption area X, and the high heat absorption area X can correspond to at least one conductive bump 24 when vertically projected from the first surface 22a to the second surface 22b, and the vertical projection does not pass through the electronic component 21. It should be understood that if the packaging layer 22 is not flattened, the concave-convex structure 23 will also be formed on the packaging layer 22 directly above the electronic component 21, so that the packaging layer 22 directly above the electronic component 21 can also define a high heat absorption area X.

In one embodiment, the surface roughness Ra of the high heat absorption region X is in the range of 5 to 10. In addition, as shown in FIG3A , the surface roughness Ra of a single high heat absorption region X may be uniform. As shown in FIG3B , the surface roughness Ra of a single high heat absorption region X may be inconsistent, and the surface roughness Ra of the high heat absorption region X gradually decreases from the center of the region toward the outside, for example, the depth H of the concave portion 231 near the center of the region is greater than the depth H' of the adjacent concave portion 231', and the depth H' of the concave portion 231' is greater than the depth H' of the concave portion 231", so that the surface roughness of the center of the high heat absorption region X is the highest. In addition, each high heat absorption area X may have different surface roughness Ra according to the actual temperature performance or the location where the solder material is not wetted. As shown in FIG. 3C , the surface roughness Ra of the high heat absorption area X located at the corner of the packaging layer 22 may be greater than the surface roughness Ra of the high heat absorption area X' not located at the corner of the packaging layer 22.

In one embodiment, as shown in FIG. 3D , a single high heat absorption region X may correspond to a single conductive bump 24 in a center-aligned manner, and the radius D of the high heat absorption region X is greater than or equal to twice the radius d of the conductive bump 24, but is not limited thereto. In another embodiment, as shown in FIG. 3E , a single high heat absorption region X may correspond to a single conductive bump 24 in a center-nonaligned manner, as long as the conductive bump 24 falls within the range of the high heat absorption region X.

In one embodiment, as shown in FIG. 3F , a plurality of high heat absorption regions X correspond to a single conductive bump 24, and the radius D’ of the circle C inscribed in the plurality of high heat absorption regions X is greater than or equal to twice the radius d of the conductive bump 24, but the invention is not limited thereto. In another embodiment, as shown in FIG. 3G , a single high heat absorption region X corresponds to a plurality of conductive bumps 24, and the radius D of the high heat absorption region X is greater than or equal to twice the radius d’ of the circle C’ inscribed in the plurality of conductive bumps 24, but the invention is not limited thereto.

It should be understood that there are many ways for the high heat absorption area X to correspond to the conductive bump 24, but the present invention only needs the conductive bump 24 to intersect with the high heat absorption area X, for example, the area of the high heat absorption area X and the conductive bump 24 are substantially overlapped in the vertical direction. In addition, the number and position of the conductive bump 24 can be adjusted according to the needs and the range of thermal impact to target the distribution of the high heat absorption area X, and there is no special limitation.

In the subsequent process, as shown in FIG. 2E , the electronic package 2 can be connected to a contact 30 of a circuit board 3a by its conductive bump 24 through a solder material 25, and then a re-welding process is performed to re-weld the solder material 25 by laser L-assisted heating (LAB process), wherein the laser L is irradiated from the packaging layer 22 toward the circuit structure 20, and the thermal conductivity of the laser L penetrating the packaging layer 22 can be improved by the concave-convex structure 23, and the heat energy is transferred to the second side 20b of the circuit structure 20, so as to strengthen the heating and re-welding of the solder material 25 on the conductive bump 24.

The present invention further provides an electronic package 2, including a circuit structure 20, an electronic component 21, a packaging layer 22, a concave-convex structure 23 and a conductive bump 24.

In this embodiment, the circuit structure 20 has a first side 20a and a second side 20b opposite to each other, and the circuit structure 20 includes at least one insulating layer 200 and at least one wiring layer 201 combined with the insulating layer 200, such as at least one fan-out type redistribution wiring layer (RDL).

In this embodiment, the electronic element 21 has an active surface 21a and an inactive surface 21b opposite to each other. The active surface 21a has a plurality of electrode pads, which are disposed on the first side 20a of the circuit structure 20 by a plurality of conductive bodies 211 such as solder materials, metal pillars or a combination thereof by flip chip method and electrically connected to the wiring layer 201, and the conductive bodies 211 are coated with an insulating material 212 such as a primer or a non-conductive bottom fill film (NCF).

In this embodiment, the packaging layer 22 has a first surface 22a and a second surface 22b opposite to each other, and the second surface 22b is disposed on the first side 20a of the circuit structure 20 to cover the electronic component 21, and the first surface 22a of the packaging layer 22 can be optionally aligned with the inactive surface 21b of the electronic component 21 through a flattening process, so that the inactive surface 21b of the electronic component 21 is exposed on the first surface 22a of the packaging layer 22.

In this embodiment, a concave-convex structure 23 is formed on the first surface 22a of the packaging layer 22 by plasma etching. The concave-convex structure 23 has a plurality of concave portions 231, each concave portion 231 has a depth H and a width A, and the shortest edge distance B is between any two adjacent concave portions 231.

In one embodiment, the aspect ratio between the depth H and the width A may be less than or equal to 3:1.

In one embodiment, the shortest distance B between the edges of any two adjacent recesses 231 is greater than or equal to the width A of each recess 231.

In one embodiment, the width A of each recess 231 is less than 10 μm.

In one embodiment, the depth H of each recess 231 can be determined by the thickness of the packaging layer 22. For example, when the thickness of the packaging layer 22 is less than 200 μm, the depth H of each recess 231 is less than 1/3 of the thickness of the packaging layer 22.

In this embodiment, the conductive bumps 24 are disposed on the second side 20b of the circuit structure 20, wherein the conductive bumps 24 are electrically connected to the wiring layer 201 so that the electronic element 21 is electrically connected to the conductive bumps 24.

In this embodiment, the concave-convex structure 23 defines at least one high heat absorption area X, and the high heat absorption area X is vertically projected from the first surface 22a to the second surface 22b and can correspond to at least one conductive bump 24, and the vertical projection will not pass through the electronic component 21.

In one embodiment, the surface roughness Ra of the high heat absorption area X ranges from 5 to 10.

In one embodiment, the surface roughness Ra of a single high heat absorption region X may be consistent. In another embodiment, the surface roughness Ra of a single high heat absorption region X may be inconsistent, for example, the surface roughness Ra of the high heat absorption region X gradually decreases from the center of the region toward the outside.

In one embodiment, the surface roughness Ra of the high heat absorption area X located at the corner of the packaging layer 22 may be greater than the surface roughness Ra of the high heat absorption area X' not located at the corner of the packaging layer 22.

In one embodiment, a single high heat absorption area X corresponds to a single conductive bump 24 in a center-aligned or center-nonaligned manner, as long as the radius D of the high heat absorption area X is greater than or equal to twice the radius d of the conductive bump 24.

In one embodiment, a plurality of high heat absorption regions X correspond to a single conductive bump 24, and the radius D' of the circle C inscribed in the plurality of high heat absorption regions X is greater than or equal to twice the radius d of the conductive bump 24. In another embodiment, a single high heat absorption region X corresponds to a plurality of conductive bumps 24, and the radius D of the high heat absorption region X is greater than or equal to twice the radius d' of the circle C' inscribed in the plurality of conductive bumps 24.

In summary, the electronic package and its manufacturing method of the present invention can reduce the reflection of laser light and increase the absorption of laser light by forming a concave-convex structure on the packaging layer, thereby increasing the thermal conductivity of the packaging layer. The higher the surface roughness of the high energy absorption area, the higher the penetration rate of the laser energy, thereby avoiding the problem of non-wetting between the conductive bump and the solder material under the packaging layer. The electronic package and its manufacturing method of the present invention can enable the LAB process to be applied to a coreless packaging substrate that is easy to warp, and has the best effect of improving thermal stress problems.

The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.

2: Electronic packaging

20:Line structure

20a: First side

20b: Second side

200: Insulation layer

201: Wiring layer

21: Electronic components

21a: Action surface

21b: Non-active surface

211: Conductor

212: Insulation material

22: Packaging layer

22a: First surface

22b: Second surface

23: Concave and convex structure

24: Conductive bumps

X: High heat absorption area

Claims (23)

An electronic package includes: a circuit structure having a first side and a second side opposite to each other; an electronic component disposed on the first side of the circuit structure; a conductive bump and a solder material, wherein the conductive bump is disposed on the second side of the circuit structure and the conductive bump directly contacts the solder material; a packaging layer formed in one piece and having a first surface and a second surface opposite to each other, and the second surface is disposed on the first side of the circuit structure to directly cover the electronic component; and a concave-convex structure formed directly on the first surface of the packaging layer, and the concave-convex structure defines at least one high heat absorption area corresponding to at least one of the conductive bumps and the solder material in sequence by vertical projection from the first surface toward the second surface, and the vertical projection does not pass through the electronic component. An electronic package as described in claim 1, wherein the surface roughness of the high heat absorption area ranges from 5 to 10. An electronic package as described in claim 1, wherein the concave-convex structure has a plurality of concave portions. An electronic package as described in claim 3, wherein the aspect ratio of each of the plurality of recesses is less than or equal to 3:1. An electronic package as described in claim 3, wherein the shortest distance between the edges of any two adjacent recesses is greater than or equal to the width of each of the recesses. An electronic package as described in claim 3, wherein the width of each of the plurality of recesses is less than 10 μm. An electronic package as described in claim 3, wherein when the thickness of the packaging layer is less than 200 μm, the depth of each of the plurality of recesses is less than 1/3 of the thickness of the packaging layer. An electronic package as described in claim 1, wherein a single high heat absorption area corresponds to a single conductive bump, and the radius of the high heat absorption area is greater than or equal to twice the radius of the conductive bump. An electronic package as described in claim 1, wherein a plurality of high heat absorption regions correspond to a single conductive bump. An electronic package as described in claim 9, wherein the radius of the circle inscribed in the plurality of high heat absorption regions is greater than or equal to twice the radius of the conductive bump. An electronic package as described in claim 1, wherein a single high heat absorption area corresponds to a plurality of conductive bumps. An electronic package as described in claim 11, wherein the radius of the high heat absorption area is greater than or equal to twice the radius of the circle inscribing the plurality of conductive bumps. The electronic package as described in claim 1, wherein the surface roughness of the high heat absorption area located at the corner of the packaging layer is greater than the surface roughness of the high heat absorption area not located at the corner of the packaging layer. An electronic package as described in claim 1, wherein the surface roughness of a single high heat absorption region gradually decreases from the center of the region toward the outside. A method for manufacturing an electronic package includes: providing a circuit structure having a first side and a second side opposite to each other; arranging an electronic component on the first side of the circuit structure; arranging a package layer having a first surface and a second surface opposite to each other on the first side of the circuit structure with the second surface to directly cover the electronic component; directly forming a concave-convex structure on the first surface of the package layer; and arranging a conductive bump on the second side of the circuit structure, wherein the conductive bump directly contacts a solder material, and the concave-convex structure defines at least one high heat absorption region corresponding to at least one conductive bump and the solder material in sequence in a vertical projection from the first surface to the second surface, and the vertical projection does not pass through the electronic component. A method for manufacturing an electronic package as described in claim 15, wherein the concave-convex structure is formed on the first surface of the package layer by etching. A method for manufacturing an electronic package as described in claim 15, wherein the circuit structure includes a fan-out redistribution circuit layer. A method for manufacturing an electronic package as described in claim 15, wherein the surface roughness of the high heat absorption area ranges from 5 to 10. A method for manufacturing an electronic package as described in claim 15, wherein the concave-convex structure has a plurality of concave portions. A method for manufacturing an electronic package as described in claim 19, wherein the depth-to-width ratio of each of the plurality of recesses is less than or equal to 3:1, and the shortest distance between the edges of any two adjacent plurality of recesses is greater than or equal to the width of each of the plurality of recesses. A method for manufacturing an electronic package as described in claim 15, wherein a single high heat absorption region corresponds to a single conductive bump, and the radius of the high heat absorption region is greater than or equal to twice the radius of the conductive bump. A method for manufacturing an electronic package as described in claim 15, wherein a plurality of high heat absorption regions correspond to a single conductive bump. A method for manufacturing an electronic package as described in claim 15, wherein a single high heat absorption area corresponds to a plurality of conductive bumps.

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