TWI888260B - Refresh control circuit - Google Patents

Abstract

A refresh control circuit includes a clock signal generator, a plurality of pulse number adjusters and a plurality of address counters. The clock signal generator generates a clock signal. The pulse number adjusters receive the clock signal, and during a time period, respectively generate a plurality of adjusted clock signals by adjusting pulse number of the clock signal according to a plurality of data retention information. The address counters respectively generate a plurality of refresh address information according to the adjusted clock signals. The refresh address information respectively correspond to a plurality of memory banks of a memory device. The memory banks respectively perform refresh operations according to the refresh address information.

Description

Refresh control circuit

The present invention relates to a refresh control circuit, and in particular to a refresh control circuit capable of improving the efficiency of refresh operations.

In dynamic random access memory, the storage capacitor in its memory cell will leak over time, so it is necessary to perform refresh actions on the memory cell regularly. The refresh actions of dynamic random access memory can be divided into burst refresh actions (Burst Refresh) and distributed refresh actions (Distributed Refresh).

In dynamic random access memory, not all memory cells have the same data retention. Therefore, if a consistent refresh frequency is used to refresh all memory cells, many unnecessary refresh operations will inevitably occur. This will reduce the access bandwidth of the memory and increase unnecessary power consumption. Therefore, how to optimize the refresh operation of the memory is an important topic for engineers in this field.

The refresh control circuit of the present invention includes a clock signal generator, a plurality of pulse quantity adjusters and a plurality of address counters. The clock signal generator generates a clock signal. The pulse quantity adjuster is coupled to the clock signal generator. The pulse quantity adjuster receives the clock signal and, in a time cycle, adjusts the pulse quantity of the clock signal according to a plurality of data retention information to generate a plurality of adjusted clock signals respectively. The address counters are respectively coupled to the pulse quantity adjusters to generate a plurality of refresh address information according to the adjusted clock signal. The refresh address information corresponds to a plurality of memory banks of the memory device and is used to enable the memory banks to perform refresh actions respectively according to the refresh address information.

Based on the above, in the refresh control circuit of the present invention, the data retention information of multiple memory banks of the memory device is recorded, and the pulse number of the clock signal corresponding to the counted refresh address information is adjusted according to the data retention information. In this way, the frequency of each memory bank performing the refresh action can be associated with its data retention information, and the performance of the refresh action of the memory device can be effectively improved.

100, 200, 300, 500: Refresh control circuit

111~114, 211~214, 311~314, 511, 512: memory bank

121~124, 221~224, 321~324, 550: address counter

131~134: Pulse quantity adjuster

140, 240, 340, 560: Clock signal generator

231~234: Gate control circuit

250, 350: database

331~334: Frequency divider

511, 522: switch

531, 532: Information change detector

541, 542: Multiplexer

570: Electronic fuse circuit

A0~A4: bits

ADD: Count information

ADR1~ADR4: Refresh address information

C1, C2: control signal

DRI1~DRI4: Data retention information

OSC: clock signal

POSC1~POSC4: adjusted clock signal

S410~S450: Steps

FIG1 is a schematic diagram of a refresh control circuit of an embodiment of the present invention.

FIG2 is a schematic diagram of a refresh control circuit of another embodiment of the present invention.

FIG3 is a schematic diagram of a refresh control circuit of another embodiment of the present invention.

FIG4 is a flow chart showing the method of generating data preservation information of an embodiment of the present invention.

FIG5 is a schematic diagram of a refresh control circuit of another embodiment of the present invention.

FIG6 is a schematic diagram showing the generation method of refresh address information of the refresh control circuit of the embodiment of FIG5 of the present invention.

Please refer to FIG. 1, which shows a schematic diagram of a refresh control circuit of an embodiment of the present invention. The refresh control circuit 100 can be applied in a memory device, wherein the memory device can be a dynamic random access memory device. The refresh control circuit 100 includes a clock signal generator 140, a plurality of pulse quantity adjusters 131-134, and a plurality of address counters 121-124. The address counters 121-124 correspond to a plurality of memory banks 111-114 of the memory device, respectively. The clock signal generator 140 is used to generate a clock signal OSC. The clock signal OSC can be used as a clock basis for the refresh control circuit 100 to perform a refresh action. The pulse quantity adjusters 131-134 are coupled to the clock signal generator 140 and receive the clock signal OSC provided by the clock signal generator 140. In addition, the pulse quantity adjusters 131-134 receive data preservation information DRI1-DRI4 respectively. The data preservation information DRI1-DRI4 respectively indicates the data preservation of the data memory banks 111-114. The pulse quantity adjusters 131-134 adjust the pulse quantity of the clock signal OSC according to the received data preservation information DRI1-DRI4 in a time cycle to generate a plurality of adjusted clock signals POSC1-POSC4 respectively.

Please note that the pulse quantity adjusters 131~134 can retain or reduce the pulse quantity of the clock signal OSC according to the data retention information DRI1~DRI4, and generate the adjusted clock signals POSC1~POSC4 respectively.

Taking the pulse quantity adjuster 131 as an example, when the corresponding memory 111 is detected to have a low data retention rate and needs to be refreshed at a relatively high frequency, the pulse quantity adjuster 131 can retain all pulse quantities of the clock signal OSC in a time cycle to generate the corresponding adjusted clock signal POSC1. Taking the pulse quantity adjuster 132 as an example, if the data retention rate detected by the corresponding memory 112 is higher than the data retention rate of the memory 111, it means that the frequency of the refresh action required by the memory 112 can be lower than that of the memory 111. Therefore, the pulse quantity adjuster 132 can reduce the pulse quantity in the above time period and reduce the execution frequency of the refresh action of the memory bank 112.

It is worth mentioning that in this embodiment, the data preservation information DRI1~DRI4 can be obtained by testing the memory banks 111~114 respectively through the testing device. In this embodiment, each memory bank 111~114 can have multiple word lines. The testing device can perform data preservation tests on the memory cells on the multiple word lines on each memory bank 111~114, and generate the data preservation information DRI1~DRI4 corresponding to each memory bank 111~114 according to the word line with the worst data preservation on each memory bank 111~114.

In this embodiment, the above-mentioned test device can be a test machine outside the memory device.

On the other hand, the address counters 121-124 are respectively coupled to the pulse quantity adjusters 131-134 and the corresponding memory banks 111-114. The address counters 121-124 respectively receive the adjusted clock signals POSC1-POSC4 generated by the pulse quantity adjusters 131-134, and respectively perform address counting according to the pulses on the adjusted clock signals POSC1-POSC4. The address counters 121-124 respectively generate refresh address information ADR1-ADR4. The memory banks 111-114 can respectively perform data refresh operations on the memory cells of each bit line according to the refresh address information ADR1-ADR4.

In this embodiment, the address counters 121-124 can be implemented by any counting circuit known to those skilled in the art, such as a ripple counter composed of multiple T-type flip-flops connected in series or a synchronous counter constructed by multiple D-type flip-flops, without any specific limitation. In addition, the clock signal generator 140 can also be implemented by any clock generation circuit known to those skilled in the art, without any specific limitation.

As can be seen from the above description, the refresh control circuit 100 of the embodiment of the present invention can control the counting frequency of the refresh address information ADR1~ADR4 by controlling the pulse number of the clock signal OSC. In this way, corresponding to the memory banks 111~114 with different data retention levels, the refresh control circuit 100 can control the refresh frequency of the memory banks 111~114 by controlling the counting frequency of the refresh address information ADR1~ADR4. In this way, the refresh control circuit 100 can adjust the refresh action performed on each memory bank 111~114 according to the data retention level of each memory bank 111~114, thereby improving the performance of the refresh action.

Please refer to FIG. 2 , which shows a schematic diagram of a refresh control circuit of another embodiment of the present invention. The refresh control circuit 200 includes a clock signal generator 240, a plurality of gate control circuits 231 to 234, a plurality of address counters 221 to 224, and a database 250. Corresponding to the embodiment of FIG. 1 , in this embodiment, the pulse quantity adjusters 131 to 134 are respectively implemented through the gate control circuits 231 to 234. In detail, the address counters 221 to 224 correspond to a plurality of memory banks 211 to 214 of the memory device, respectively. The clock signal generator 240 is used to generate a clock signal OSC as a clock basis for the refresh control circuit 200 to perform a refresh operation. The gate control circuits 231~234 are coupled to the clock signal generator 240 and receive the clock signal OSC provided by the clock signal generator 240.

In this embodiment, the gate control circuits 231-234 receive data retention information DRI1-DRI4, and in a time cycle, the gate control circuits 231-234 respectively determine whether to mask the pulse on the clock signal OSC and the number of pulses to be masked according to the received data retention information DRI1-DRI4, and thereby generate a plurality of adjusted clock signals POSC1-POSC4.

In this embodiment, in a time interval, the clock signal OSC has four pulses, and the data retention information DRI1-DRI4 indicates that the data retention levels of the memory banks 211-214 are arranged from low to high, namely DRI1, DRI2, DRI3, and DRI4. The gate control circuit 231 can decide not to mask the pulse on the clock signal OSC according to the data retention information DRI1, and make the generated adjusted clock signal POSC1 the same as the clock signal OSC. The gate control circuit 232 can decide to mask one pulse on the clock signal OSC according to the data retention information DRI2, and make the generated adjusted clock signal POSC2 have three pulses in a time interval. The gate control circuit 233 determines the two pulses on the mask clock signal OSC according to the data preservation information DRI3, and makes the generated adjusted clock signal POSC3 have two pulses in a time interval. The gate control circuit 234 can determine the three pulses on the mask clock signal OSC according to the data preservation information DRI4, and makes the generated adjusted clock signal POSC4 have one pulse in a time interval. In this embodiment, the data preservation information DRI1~DRI4 represents the data preservation, which is positively correlated with the number of pulses of the clock signal OSC to be masked by the corresponding gate control circuits 231~234.

On the other hand, the database 250 is coupled to the gate circuits 231-234. The database 250 is used to store data retention information DRI1-DRI4 and provide the data retention information DRI1-DRI4 to the gate circuits 231-234 respectively. In this embodiment, the test device can perform a test operation on the data retention of the memory libraries 211-214 of the memory device and store the test results (data retention information DRI1-DRI4) in the database 250. The database 250 can be a non-volatile memory device, such as a read-only memory, a flash memory or an electronic fuse circuit.

Incidentally, in this embodiment, each gate control circuit 231-234 can be implemented by a digital circuit. For example, the gate control circuits 231-234 can receive the data preservation information DRI1-DRI4 in digital code, and determine the number of pulses in the clock signal OSC to be masked according to the data preservation information DRI1-DRI4. Each gate control circuit 231-234 can determine 0 or more pulses in the masked clock signal OSC. Moreover, each adjusted clock signal POSC1-POSC4 can have at least one pulse in a time interval.

The above time range can be set by the designer according to actual needs, without any specific restrictions.

Please refer to FIG. 3 below, which is a schematic diagram of a refresh control circuit of another embodiment of the present invention. The refresh control circuit 300 includes a clock signal generator 340, a plurality of frequency dividers 331-334, a plurality of address counters 321-324, and a database 350. Corresponding to the embodiment of FIG. 1, in this embodiment, the pulse quantity adjusters 131-134 are implemented through frequency dividers 331-334, respectively. In this embodiment, compared with the embodiment of FIG. 2, the refresh control circuit 300 adjusts the pulse quantity of the clock signal OSC in a time period through the frequency dividers 331-334. In detail, the frequency dividers 331-334 receive the data retention information DRI1-DRI4 provided by the database 350, respectively. The frequency dividers 331-334 set the frequency divider according to the data preservation information DRI1-DRI4 received respectively, and perform the frequency divider operation on the clock signal OSC. Among them, corresponding to the relatively high data preservation information DRI1-DRI4, each frequency divider 331-334 can be set to have a relatively high frequency divider. Conversely, corresponding to the relatively low data preservation information DRI1-DRI4, each frequency divider 331-334 can be set to have a relatively low frequency divider. In this embodiment, the frequency divider can be any real number greater than or equal to 1.

To further explain, when the frequency division number is larger, the number of pulses of each adjusted clock signal POSC1~POSC4 in a time interval will be smaller. In this way, the refresh address information generated by the update of the corresponding bit address counter 321~324 can be reduced, and the refresh frequency of each corresponding memory bank 311~314 can be reduced. Conversely, when the frequency division number is smaller, the number of pulses of each adjusted clock signal POSC1~POSC4 in a time interval will increase. In this way, the refresh address information generated by the update of the corresponding bit address counter 321~324 can be improved, and the refresh frequency of each corresponding memory bank 311~314 can be increased. In other words, the frequency division number of each frequency divider 331~334 is positively correlated with the data retention level represented by the corresponding data retention level information DRI1~DRI4.

It is worth mentioning that in the embodiments of Figures 1 to 3, the number of memory banks can be any number, and the four memory banks shown in Figures 1 to 3 are only examples for illustration and are not intended to limit the scope of implementation of the present invention.

Please refer to FIG. 4 below, which is a flow chart of the method for generating data preservation information of an embodiment of the present invention. In step S410, test information can be written to multiple memory cells in the tested memory bank. This test information can be a background pattern. Then, in step S420, a data preservation test action is performed on the tested memory bank. Among them, the data preservation test action performed in step S420 can be implemented by applying any data preservation test action on memory in the field, without specific restrictions.

In step S430, the information is read out for the memory cells in the tested memory bank, and the test result is determined to be passed or failed by comparing the written information and the read information. It is worth mentioning that when the read information in step S430 matches the written information, the data preservation test time can be further increased, and step S410 is returned to perform the next data preservation test. Among them, steps S410 to S430 can be repeated multiple times, and the state of the data preservation in the tested memory bank can be tested.

According to the above test results, in step S440, the data preservation of the tested memory can be rated and data preservation information can be generated. In step S450, the data preservation information of each corresponding memory can be recorded. And return to step S410 to perform the data preservation test action of the next memory.

The above-mentioned action flow can be executed by a test device, and the test device can be a test machine outside the memory device.

Please refer to FIG5, which shows a schematic diagram of a refresh control circuit of another embodiment of the present invention. The refresh control circuit 500 includes a clock signal generator 560, an address counter 550, multiplexers 541, 542, information transition detectors 531, 532, switches 521, 522, and an electronic fuse circuit 570. The clock signal generator 560 is used to generate a clock signal OSC. The address counter 550 is coupled to the clock signal generator 560 to perform a counting operation according to the clock signal OSC, and thereby generate count information ADD having N bits, wherein N is an integer greater than 2. The multiplexers 541, 542 are coupled to the address counter 550 and receive the count information ADD together. Furthermore, multiplexers 541 and 542 are coupled to the electronic fuse circuit 570 and receive data retention information DRI1 and DRI2 provided by the electronic fuse circuit 570, respectively.

In this embodiment, multiplexers 541 and 542 can select M bits of N-bit count information ADD according to data retention information DRI1 and DRI2, respectively, to generate refresh address information ADR1 and ADR2, respectively.

To further illustrate, a schematic diagram of the generation method of refresh address information of the refresh control circuit of the embodiment of FIG. 5 of the present invention can be synchronously referred to in FIG. 6. In the embodiment of FIG. 5, the address counter 550 can generate count information ADD having 5 bits A0~A4 in multiple count cycles PL (0~15). Bit A0 can be the least significant bit of the count information ADD, and bit A4 can be the most significant bit of the count information ADD. When the memory bank 511 has a relatively low data retention rate, the multiplexer 541 can select the relatively low three bits (bits A0~A2) to generate the refresh address information ADR1 according to the corresponding data retention rate information DRI1. When the memory bank 512 has a relatively high data retention rate, the multiplexer 542 can select the relatively high three bits (bits A2~A4) to generate the refresh address information ADR2 according to the corresponding data retention rate information DRI2.

As shown in FIG. 6 , the change rate of the refresh address information ADR1 can be higher than the change rate of the refresh address information ADR2. In this way, the memory bank 511 with a relatively low data retention rate can be set to perform a relatively high-frequency refresh action, and the memory bank 512 with a relatively high data retention rate can be set to perform a relatively low-frequency refresh action.

Please refer to Figure 5 again. On the other hand, the information transition detectors 531 and 532 are coupled to the multiplexers 541 and 542 respectively. The information transition detectors 531 and 532 receive the refresh address information ADR1 and ADR2 provided by the multiplexers 541 and 542 respectively. The information transition detectors 531 and 532 are used to detect the transition status of the refresh address information ADR1 and ADR2 to generate control signals C1 and C2 respectively. The information transition detectors 531 and 532 transmit the generated control signals C1 and C2 to switches 521 and 522 respectively. The switch 521 is coupled between the multiplexer 541 and the memory bank 511, and the switch 522 is coupled between the multiplexer 542 and the memory bank 512. Switches 521 and 522 receive control signals C1 and C2 respectively, and are disconnected or turned on according to the control signals C1 and C2 respectively.

In detail, taking the information transition detector 531 as an example, when the information transition detector 531 detects that the refresh address information ADR1 has not changed, the information transition detector 531 can provide a control signal C1 to disconnect the switch 521. Conversely, when the information transition detector 531 detects that the refresh address information ADR1 has changed, the information transition detector 531 can provide a control signal C1 to turn on the switch 521.

That is, only when the refresh address information ADR1 changes, the switch 521 can be turned on and transmit the new refresh address information ADR1 to the memory bank 511. In this way, the memory bank 511 can perform a refresh operation for the newly generated refresh address information ADR1.

In this embodiment, the information transition detectors 531 and 532 can detect whether the logic value of each bit in the refresh address information ADR1 and ADR2 has changed. The information transition detectors 531 and 532 can be implemented by using a detection circuit for a logic value change edge known to a person skilled in the art, without any particular restrictions. In addition, the switches 521 and 522 can be implemented by using a switch circuit known to a person skilled in the art, and the multiplexers 541 and 542 can be implemented by using a multiplexer circuit known to a person skilled in the art, without any particular restrictions.

It is worth mentioning that in the embodiment of FIG. 5 , the number of memory banks can be any number, and the two memory banks shown in the figure are only examples for illustration and are not intended to limit the scope of implementation of the present invention.

In summary, the refresh control circuit of the present invention adjusts the pulse number of the clock signal used to count the refresh address according to the data retention of the memory bank, and thereby controls the execution frequency of the refresh action of the memory bank. In this way, memory banks with different data retention can perform refresh actions at different frequencies. This effectively reduces the number of unnecessary refresh actions in the memory device and improves the performance of the refresh action of the memory device.

100: Refresh control circuit

111~114: Memory Bank

121~124: Address counter

131~134: Pulse quantity adjuster

140: Clock signal generator

ADR1~ADR4: Refresh address information

DRI1~DRI4: Data retention information

OSC: clock signal

POSC1~POSC4: adjusted clock signal

Claims (5)

A refresh control circuit is applicable to a memory device, comprising: a clock signal generator, generating a clock signal; a plurality of pulse quantity adjusters, coupled to the clock signal generator, receiving the clock signal, wherein the pulse quantity adjusters adjust the pulse quantity of the clock signal according to a plurality of data retention information in a time cycle to generate a plurality of adjusted clock signals respectively; and a plurality of address counters, respectively coupled to the pulse quantity adjusters, adjusting the pulse quantity of the clock signal according to the adjusted clock signal. The post-processing clock signal is used to generate multiple refresh address information, and the refresh address information corresponds to multiple memory banks of the memory device. The memory banks are refreshed according to the refresh address information, wherein each pulse quantity adjuster includes: a gate control circuit, which determines the number of N pulses of the clock signal to be masked in the time period according to the corresponding data retention information to generate the corresponding processed clock signal, wherein N is an integer greater than or equal to 0. The refresh control circuit as described in claim 1 further includes: a database coupled to the plurality of pulse quantity adjusters for storing the data retention information. In the refresh control circuit as described in claim 2, a test device tests the memory banks of the memory device and obtains the data retention information corresponding to the memory banks respectively, and the test device stores the data retention information in the database. A refresh control circuit as described in claim 2, wherein the database is a read-only memory, a flash memory or an electronic fuse circuit. A refresh control circuit as described in claim 1, wherein the data retention level represented by each data retention level information is positively correlated with the number of pulses of the clock signal to be masked by each corresponding gate control circuit.

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