TWI888174B - Magnetic Memory Device - Google Patents

Abstract

The magnetic memory device of the present invention stabilizes magnetization reversal. The magnetic memory device of the present invention includes: a first conductive layer extending along a first direction; a second conductive layer extending along the first direction and arranged with the first conductive layer along a second direction intersecting the first direction; a first magnetoresistance effect element electrically connected to the first conductive layer; a second magnetoresistance effect element electrically connected to the second conductive layer; and a third conductive layer extending along the second direction and connected to the first magnetoresistance effect element. In a write operation of writing data to the first magnetoresistance effect element, a first current is applied to the first conductive layer, a second current is applied to the second conductive layer, and a third current is applied to the third conductive layer independently of the first current and the second current.

Description

Magnetic Memory Device

Embodiments relate to a magnetic memory device.

Magnetic memory devices using magnetoresistive elements as memory elements are known. Various methods have been proposed in the industry as a method of writing data to magnetoresistive elements. For example, as a method of writing data without passing current directly through the magnetoresistive element, a method using spin orbit torque is known. [Prior Technical Literature] [Patent Literature]

[Patent Document 1] U.S. Patent Application Publication No. 2021/0125654 [Patent Document 2] U.S. Patent Application Publication No. 2019/0051815 [Patent Document 3] U.S. Patent Application Publication No. 2019/0244646

[The problem the invention is trying to solve]

The magnetic memory device of the present invention stabilizes the magnetization reversal. [Technical means for solving the problem]

The magnetic memory device of the implementation form includes: a first conductive layer, a second conductive layer, a third conductive layer, a first magnetoresistance effect element, and a second magnetoresistance effect element. The first conductive layer extends along the first direction. The second conductive layer extends along the first direction and is arranged with the first conductive layer along a second direction intersecting the first direction. The first magnetoresistance effect element is electrically connected to the first conductive layer. The second magnetoresistance effect element is electrically connected to the second conductive layer. The third conductive layer extends along the second direction and is connected to the first magnetoresistance effect element. In a writing operation of writing data to the first magnetoresistive element, a first current is applied to the first conductive layer, a second current is applied to the second conductive layer, and a third current is applied to the third conductive layer independently of the first current and the second current.

Hereinafter, several embodiments will be described with reference to the drawings. In addition, in the following description, common reference symbols are attached to components having the same function and structure. Furthermore, in the case of distinguishing multiple components having a common reference symbol, the common reference symbol is attached with a suffix to distinguish them. In addition, in the case of multiple components that do not need to be specially distinguished, the multiple components are only attached with a common reference symbol without a suffix. Suffixes are not limited to subscripts or superscripts, and include, for example, lowercase letters added to the end of the reference symbol, symbols, and indexes indicating arrangement, etc.

In this specification, a magnetic memory device is, for example, an MRAM (Magnetoresistive Random Access Memory). The magnetic memory device includes a magnetoresistive element as a memory element. The magnetoresistive element is a resistance change element having a tunneling magnetoresistive effect (magnetoresistive effect) through a magnetic tunnel junction (MTJ). The magnetoresistive element is also called an MTJ element.

1. First Implementation Form The magnetic memory device of the first implementation form is described.

1.1 Structure First, the structure of the magnetic memory device of the first embodiment is described.

1.1.1 Magnetic memory device FIG. 1 is a block diagram showing an example of the structure of the magnetic memory device of the first embodiment. The magnetic memory device 1 includes: a memory cell array 10, a column selection circuit 11, a row selection circuit 12, a decoding circuit 13, a write circuit 14, a read circuit 15, a voltage generating circuit 16, an input-output circuit 17, and a control circuit 18.

The memory cell array 10 is a memory unit for storing data of the magnetic memory device 1. The memory cell array 10 has a plurality of memory cells MC. Each of the plurality of memory cells MC establishes a corresponding relationship with a row and a column. The memory cells MC in the same row establish a corresponding relationship with the same word line WL. The memory cells MC in the same row establish a corresponding relationship with the same read bit line RBL.

The column selection circuit 11 is a circuit for selecting a column of the memory cell array 10. The column selection circuit 11 is connected to the memory cell array 10 via the word line WL. The column selection circuit 11 is supplied with the decoding result (column address) of the address ADD from the decoding circuit 13. The column selection circuit 11 selects the word line WL corresponding to the column based on the decoding result of the address ADD. Hereinafter, the selected word line WL is referred to as the selected word line WL. In addition, the word lines WL other than the selected word line WL are referred to as the non-selected word lines WL.

The row selection circuit 12 is a circuit for selecting a row of the memory cell array 10. The row selection circuit 12 is connected to the memory cell array 10 via the read bit line RBL. The row selection circuit 12 is supplied with the decoding result (row address) of the address ADD from the decoding circuit 13. The row selection circuit 12 selects the read bit line RBL corresponding to the row based on the decoding result of the address ADD. Hereinafter, the selected read bit line RBL is referred to as the selected bit line RBL. In addition, the read bit lines RBL other than the selected bit line RBL are referred to as non-selected bit lines RBL.

The decoding circuit 13 is a decoder that decodes the address ADD from the input-output circuit 17. The decoding circuit 13 supplies the decoded result of the address ADD to the column selection circuit 11 and the row selection circuit 12. The address ADD includes a row address and a column address.

The write circuit 14 includes, for example, a write driver (not shown). The write circuit 14 writes data to the memory cell MC.

The readout circuit 15 includes, for example, a sense amplifier (not shown). The readout circuit 15 reads data from the memory cell MC.

The voltage generating circuit 16 uses the power supply voltage provided from the outside (not shown) of the magnetic memory device 1 to generate voltages for various operations of the memory cell array 10. For example, the voltage generating circuit 16 generates various voltages required for writing operations and outputs them to the writing circuit 14. Also, for example, the voltage generating circuit 16 generates various voltages required for reading operations and outputs them to the reading circuit 15.

The input-output circuit 17 is responsible for communication with the outside of the magnetic memory device 1. The input-output circuit 17 transmits the address ADD from the outside of the magnetic memory device 1 to the decoding circuit 13. The input-output circuit 17 transmits the command CMD from the outside of the magnetic memory device 1 to the control circuit 18. The input-output circuit 17 sends and receives various control signals CNT between the outside of the magnetic memory device 1 and the control circuit 18. The input-output circuit 17 transmits the data DAT from the outside of the magnetic memory device 1 to the write circuit 14, and outputs the data DAT transmitted from the read circuit 15 to the outside of the magnetic memory device 1.

The control circuit 18 includes, for example, a processor such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory). The control circuit 18 controls the operations of the column selection circuit 11, the row selection circuit 12, the decoding circuit 13, the write circuit 14, the read circuit 15, the voltage generation circuit 16, and the input/output circuit 17 in the magnetic memory device 1 based on the control signal CNT and the command CMD.

1.1.2 Memory cell array Next, the structure of the memory cell array of the magnetic memory device of the first embodiment is described.

Fig. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array of the first embodiment. In Fig. 2, various components are displayed by classification by including a suffix of an index ("<>").

The memory cell array 10 includes a plurality of word lines WL, a plurality of read bit lines RBL, a write bit line WBL, a source line SL, and a plurality of memory strings MS. Furthermore, the memory cell array 10 includes a plurality of switch elements SEL3. The plurality of word lines WL include (M+1) word lines WL＜0＞, ..., WL＜m＞, ..., and WL＜M＞. M is an integer greater than 2 (0＜m＜M). In addition, in the example of FIG. 2 , the case where M is an integer greater than 2 is shown, but it is not limited to this. For example, M can be 0 or 1. The plurality of read bit lines RBL include (N+1) read bit lines RBL＜0＞, ..., RBL＜n＞, ..., and RBL＜N＞. N is an integer greater than or equal to 2 (0＜n＜N). The plurality of switch elements SEL3 include (N+1) switch elements SEL3＜0＞, ..., and SEL3＜N＞. The plurality of memory strings MS include (M+1) memory strings MS＜0＞, ..., MS＜m＞, ..., and MS＜M＞. The memory strings MS＜0＞ to MS＜M＞ are respectively associated with the word lines WL＜0＞ to WL＜M＞. The memory strings MS＜0＞ to MS＜M＞ have the same structure. The following description will be made taking the memory string MS＜m＞ as an example.

The memory string MS<m> includes a switch element SEL1<m>, a wiring SOTL<m>, and (N+1) memory cells MC<m,0>, ..., MC<m,n>, ..., and MC<m,N>.

The switch element SEL1<m> is a three-terminal switch element such as a MOSFET. Specifically, the switch element SEL1<m> has a first terminal connected to the wiring SOTL<m>, a second terminal connected to the write bit line WBL, and a control terminal connected to the word line WL<m>.

The wiring SOTL<m> has: a first end connected to the first end of the switch element SEL1<m>, a second end connected to the source line SL, and a central portion between the two ends. In the central portion of the wiring SOTL<m>, (N+1) memory cells MC<m,0>, ..., MC<m,n>, ..., and MC<m,N> are separated from each other and connected. Hereinafter, the portion of the central portion of the wiring SOTL<m> that is connected to any of the memory cells MC<m,0> to MC<m,N> is also referred to as a "cell portion". The portion between two adjacent cell portions in the central portion of the wiring SOTL<m> is also referred to as a "wiring" portion. Each cell portion of the wiring SOTL<m> has a first end connected to the write bit line WBL via a switch element SEL1<m> and a second end connected to the source line SL.

Memory cells MC<m,0> to MC<m,N> are connected to read bit lines RBL<0> to RBL<N>, respectively. Memory cells MC<m,0> to MC<m,N> have the same structure. The following description will be made by taking memory cell MC<m,n> as an example.

The memory cell MC＜m,n＞ includes a cell portion corresponding to the memory cell MC＜m,n＞ in the wiring SOTL＜m＞, a switch element SEL2＜m,n＞, and a magnetoresistive element MTJ＜m,n＞.

The switch element SEL2<m,n> is a three-terminal switch element such as MOSFET. The switch element SEL2<m,n> has a first terminal connected to the magnetoresistive element MTJ<m,n>, a second terminal connected to the read bit line RBL<n>, and a control terminal.

The magnetoresistive element MTJ＜m,n＞ connects the switch element SEL2＜m,n＞ and the cell portion of the wiring SOTL＜m＞ corresponding to the memory cell MC＜m,n＞ in series. The magnetoresistive element MTJ＜m,n＞ is a resistance change element. The magnetoresistive element MTJ＜m,n＞ functions as a memory element that stores data in a non-volatile manner according to the change of the resistance state.

As described above, each memory string MS includes (N+1) memory cells MC connected to one wiring line SOTL. Therefore, the memory cell array 10 includes (M+1)×(N+1) memory cells MC<0,0>, ..., MC<0,n>, ..., MC<0,N>, ..., MC<m,0>, ..., MC<m,n>, ..., MC<m,N>, ..., MC<M,0>, ..., MC<M,n>, ..., and MC<M,N> by having (M+1) memory strings MS.

Each of the switching elements SEL3＜0＞～SEL3＜N＞ is a three-terminal switching element such as a MOSFET. Each of the switching elements SEL3＜0＞～SEL3＜N＞ has the same structure. The following is explained by taking the switching element SEL3＜n＞ as an example. The switching element SEL3＜n＞ is arranged on the path of the read bit line RBL＜n＞. At the first end of the switching element SEL3＜n＞, (M+1) switching elements SEL2＜0,n＞～SEL2＜M,n＞ are commonly connected via the read bit line RBL＜n＞. Thereby, the switching element SEL3＜n＞ can control whether the voltage applied to the read bit line RBL＜n＞ is transmitted to the (M+1) switching elements SEL2＜0,n＞～SEL2＜M,n＞.

1.1.3 Memory string Next, the structure of the memory string of the magnetic memory device of the first embodiment is described. Hereinafter, the surface parallel to the surface of the substrate on which the memory cell array 10 is set is set as the XY plane. The direction in which the memory cell array 10 is set with respect to the substrate surface is set as the Z direction or the upward direction. The directions intersecting each other in the XY plane are set as the X direction and the Y direction.

FIG3 is a cross-sectional view showing an example of a cross-sectional structure of a portion of the memory string of the first embodiment. As shown in FIG3, the memory string MS<m> includes: a conductive layer 30, a plurality of element layers 40, a plurality of conductive layers 50, a plurality of element layers 60, a plurality of conductive layers 70, and a plurality of conductive layers 80. FIG3 shows, as an example, a portion of the wiring SOTL<m> in the memory string MS<m> and three memory cells MC<m,n-1>, MC<m,n>, and MC<m,n+1> connected to the portion of the wiring SOTL<m>.

(Overall structure) First, the overall structure of the memory string MS is explained.

An insulating layer 20 is provided on a substrate (not shown). A conductive layer 30 is provided on the upper surface of the insulating layer 20. The conductive layer 30 extends in the X direction. The conductive layer 30 is used as a wiring SOTL<m>. The portion of the conductive layer 30 that overlaps with the element layer 40 when viewed in the Z direction is used as a cell portion. The portion of the conductive layer 30 that does not overlap with the element layer 40 when viewed in the Z direction is used as a wiring portion.

The conductive layer 30 is a continuous film containing a heavy metal having non-magnetic and conductive properties. The conductive layer 30 contains, as a heavy metal, at least one element selected from tungsten (Ta), tungsten (W), ruthenium (Re), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), copper (Cu), nimium (Os), iridium (Ir), platinum (Pt), gold (Au), manganese (Mn), lead (Pb), bismuth (Bi), antimony (Sb), tellurium (Te), selenium (Se), and polonium (Po). The element contained as a heavy metal in the conductive layer 30 may include oxides, nitrides, or sulfides. In addition, when tungsten (W) or tungsten (Ta) is contained, the structure of the element is preferably a β structure. Conductive oxides such as ruthenium oxide (RuO ₂ ) or iridium oxide (IrO ₂ ) can be used for the conductive layer 30. Alternatively, dichalcogenide transition metals having a two-dimensional layered structure such as WTe ₂ , WS ₂ , or WSe ₂ can be used for the conductive layer 30. The conductive layer 30 can be composed of a single layer containing the above-mentioned materials, or can be composed of a plurality of layers containing the above-mentioned materials. The conductive layer 30 mainly generates spins caused by the spin Hall effect by the current flowing through the conductive layer 30. In addition, spin torque caused by the spin splitting effect, spin torque caused by the Rashba effect, etc. are sometimes generated. These spin torques are collectively referred to as spin-orbit torque (SOT). The spin-orbit torque acts on the portion of the device layer 40 that is in contact with the conductive layer 30.

A plurality of element layers 40 are disposed on the upper surface of the conductive layer 30. Each of the plurality of element layers 40 has a columnar shape extending along the Z direction. Each of the plurality of element layers 40 is used as a magnetoresistive element MTJ. The details of the structure of the element layer 40 will be described later.

A conductive layer 50 is disposed on the upper surface of each of the plurality of device layers 40. Each of the plurality of conductive layers 50 has a columnar shape extending along the Z direction. Each of the plurality of conductive layers 50 serves as an electrode for electrically connecting the device layer 40 and the device layer 60.

The device layer 60 is disposed on the upper surface of each of the plurality of conductive layers 50. Each of the plurality of device layers 60 has a columnar shape extending along the Z direction. Each of the plurality of device layers 60 is used as a 3-terminal switch device. The details of the structure of the device layer 60 will be described later.

A conductive layer 70 is disposed on the upper surface of each of the plurality of element layers 60. Each of the plurality of conductive layers 70 has a columnar shape extending along the Z direction. Each of the plurality of conductive layers 70 serves as an electrode for electrically connecting the element layer 60 and the conductive layer 80.

A conductive layer 80 is disposed on the upper surface of each of the plurality of conductive layers 70. Each of the plurality of conductive layers 80 extends along the Y direction. The plurality of conductive layers 80 are arranged along the X direction. Each of the plurality of conductive layers 80 is used as a readout bit line RBL.

The element layer 40 , the conductive layer 50 , the element layer 60 , the conductive layer 70 , and the conductive layer 80 are covered with an insulating layer 90 .

(Magnetoresistance effect element MTJ) Next, the structure of the magnetoresistance effect element MTJ contained in the memory string MS is explained.

Each of the plurality of element layers 40 includes a ferromagnetic layer 41, a non-magnetic layer 42, a ferromagnetic layer 43, a non-magnetic layer 44, and a ferromagnetic layer 45. The ferromagnetic layer 41, the non-magnetic layer 42, the ferromagnetic layer 43, the non-magnetic layer 44, and the ferromagnetic layer 45 are sequentially stacked from bottom to top.

The ferromagnetic layer 41 is provided in contact with the upper surface of the conductive layer 30. The ferromagnetic layer 41 is a conductive film having ferromagnetism. The ferromagnetic layer 41 is used as a memory layer. The ferromagnetic layer 41 has an easy magnetization axis in a direction perpendicular to the film surface (Z direction). The spin-orbit moment generated in the conductive layer 30 acts on the ferromagnetic layer 41. When the spin-orbit moment of a predetermined magnitude acts, the magnetization direction of the ferromagnetic layer 41 is reversed.

The ferromagnetic layer 41 is generally a ferromagnetic layer using any one element selected from cobalt (Co), iron (Fe), and nickel (Ni). Cobalt-iron (CoFe) alloy, iron (Fe), cobalt-iron-boron (CoFeB), iron-boron (FeB), cobalt-boron (CoB), and cobalt-iron-nickel-boron (CoFeNiB) are representative ferromagnetic layers of perpendicular magnetization. They have a body-centered cubic structure (BCC structure). In addition, as an element replacing boron (B), phosphorus (P), carbon (C), etc. can also be cited. The above-mentioned magnetic materials such as CoFeB generate perpendicular magnetic anisotropy at the interface by contacting with an oxide having a NaCl (001) structure. MgO (001)/CoFeB laminated film is a typical example.

A non-magnetic layer 42 is disposed on the upper surface of the ferromagnetic layer 41. The non-magnetic layer 42 is an insulating film having non-magnetic properties. The non-magnetic layer 42 is used as a tunnel barrier layer. The non-magnetic layer 42 is disposed between the ferromagnetic layer 41 and the ferromagnetic layer 43, and forms a magnetic tunnel junction together with the two ferromagnetic layers. That is, a magnetoresistance effect is generated in the magnetic tunnel junction portion. Furthermore, when an initial amorphous layer such as cobalt iron boron (CoFeB) is used as the interface layer of the ferromagnetic layer 41, the non-magnetic layer 42 functions as a seed material that becomes a crystal nucleus for growing a crystalline film from the interface with the ferromagnetic layer 41 during the crystallization process of the ferromagnetic layer 41. Similarly, when cobalt iron boron (CoFeB) is used as the interface layer of the ferromagnetic layer 43, the non-magnetic layer 42 also functions as a seed material for the ferromagnetic layer 43. Here, the initial amorphous layer is a layer that is in an amorphous state immediately after film formation and is crystallized after annealing. The non-magnetic layer 42 has a tetragonal or cubic structure with the film surface oriented to the (001) plane. As an oxide used for the non-magnetic layer 42, for example, magnesium oxide (MgO) is representative. As another example of an oxide used for the non-magnetic layer 42, magnesium aluminum oxide (MgAlOx) and the like can also be cited. The following is an explanation of the case where magnesium oxide (MgO) is used. Magnesium oxide (MgO) has a NaCl structure. When magnesium oxide (MgO) is used for the non-magnetic layer 42, the (001) interface of magnesium oxide (MgO) is integrated with the (001) interface of cobalt iron boron (CoFeB) and epitaxially grown by annealing. Therefore, cobalt iron boron (CoFeB) has a body-centered cubic structure oriented to (001).

A ferromagnetic layer 43 is provided on the upper surface of the non-magnetic layer 42. The ferromagnetic layer 43 is a conductive film having ferromagnetism. The ferromagnetic layer 43 is used as a reference layer (Reference Layer). The ferromagnetic layer 43 has an easy magnetization axis in a direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic layer 43 is fixed. In addition, "fixed magnetization direction" means that the magnetization direction will not change due to a torque of a magnitude that can reverse the magnetization direction of the ferromagnetic layer 41. In the example of FIG. 3 , the magnetization direction of the ferromagnetic layer 43 is oriented in the direction of the ferromagnetic layer 41. Usually, an interface layer is included in the ferromagnetic layer 43. As the interface layer of the ferromagnetic layer 43, an initial amorphous layer of cobalt iron boron (CoFeB) or the like is used. Furthermore, an auxiliary ferromagnetic layer is provided in contact with the surface of the cobalt iron boron (CoFeB) layer opposite to the surface in contact with the magnesium oxide (MgO) layer. The auxiliary ferromagnetic layer includes, for example, an alloy film of at least one selected from cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd). In addition, as the auxiliary ferromagnetic layer, a multilayer film such as a Co/Pt multilayer film or a Co/Pd multilayer film can also be used. The cobalt iron boron (CoFeB) layer serving as the initial amorphous layer is used in a stacked manner with the above-mentioned CoPt, CoPd, Co/Pt laminated film, Co/Pd laminated film, etc. In this case, the interface layer in the ferromagnetic layer 43, such as the above-mentioned CoFeB layer, forms MgO with (001) orientation closer to the non-magnetic layer 42 than other layers.

A non-magnetic layer 44 is disposed on the upper surface of the ferromagnetic layer 43. The non-magnetic layer 44 is a non-magnetic conductive film. The non-magnetic layer 44 is used as a spacer layer. The non-magnetic layer 44 is composed of, for example, an element selected from ruthenium (Ru), niobium (Os), rhodium (Rh), iridium (Ir), and chromium (Cr) or an alloy thereof.

A ferromagnetic layer 45 is provided on the upper surface of the non-magnetic layer 44. The ferromagnetic layer 45 is a conductive film having ferromagnetism. The ferromagnetic layer 45 is used as a shift canceling layer. The ferromagnetic layer 45 has an easy magnetization axis in a direction (Z direction) perpendicular to the film surface. The ferromagnetic layer 45 includes, for example, an alloy layer of at least one selected from cobalt platinum (CoPt), cobalt palladium (CoPd), cobalt palladium platinum (CoPdPt), and cobalt chromium platinum (CoCrPt). In addition, as the ferromagnetic layer 45, a multilayer film such as a Co/Pt multilayer film, a Co/Pd multilayer film, and a Co/Ni multilayer film can also be used.

The ferromagnetic layer 43 and the ferromagnetic layer 45 are antiferromagnetically coupled via the nonmagnetic layer 44. That is, the ferromagnetic layer 43 and the ferromagnetic layer 45 are coupled in a manner that their magnetization directions are antiparallel to each other. The antiferromagnetic magnetic coupling of the ferromagnetic layer 43, the nonmagnetic layer 44, and the ferromagnetic layer 45 is called SAF (Synthetic Anti-Ferromagnetic) coupling. Through the SAF coupling state, the ferromagnetic layer 45 offsets the effect of the leakage magnetic field of the ferromagnetic layer 43 on the change of the magnetization direction of the ferromagnetic layer 41, and can reduce the actual effect of the leakage magnetic field of the ferromagnetic layer 43 on the ferromagnetic layer 41.

The magnetoresistive element MTJ can take a low resistance state or a high resistance state according to whether the magnetization directions of the memory layer and the reference layer are parallel or antiparallel. In the magnetic memory device 1, the magnetization direction of the memory layer relative to the magnetization direction of the reference layer is controlled by not passing the write current through the magnetoresistive element MTJ. Specifically, a write method using the spin-orbit moment generated by the current flowing through the wiring SOTL is adopted.

When a write current Ic0 of a certain magnitude flows in the X direction in the wiring SOTL, the magnetization directions of the memory layer and the reference layer are parallel to each other. In the case of the parallel state, the resistance value of the magnetoresistive element MTJ is the lowest, and the magnetoresistive element MTJ is set to a low resistance state. This low resistance state is called the "P (Parallel) state" and is defined as, for example, the state of data "0".

Furthermore, when the write current Ic1 flows in the opposite direction of the write current Ic0 in the wiring SOTL, the relative relationship between the magnetization directions of the memory layer and the reference layer is antiparallel. In the case of the antiparallel state, the resistance value of the magnetoresistive element MTJ is the highest, and the magnetoresistive element MTJ is set to a high resistance state. This high resistance state is called "AP (Anti-Parallel) state" and is defined as, for example, the state of data "1".

In addition, the method of defining data "1" and data "0" is not limited to the above example. For example, the P state can be defined as data "1" and the AP state can be defined as data "0".

(Switching element SEL2) Next, the structure of the switching element SEL2 included in the memory string MS is explained.

The device layer 60 includes a semiconductor film 61, an insulating film 62, and a conductive layer 63. The device layer 60 has, for example, a SGT (Surrounding Gate Transistor) structure.

The semiconductor film 61 is provided in the center of the element layer 60 as viewed in the Z direction. The semiconductor film 61 extends in the Z direction and has a lower end in contact with the conductive layer 50 and an upper end in contact with the conductive layer 70. The semiconductor film 61 serves as a current path (channel) of the switch element SEL2. The semiconductor film 61 contains, for example, silicon (Si).

The insulating film 62 covers the side surface of the semiconductor film 61. The insulating film 62 serves as a gate insulating film of the switch element SEL2. The insulating film 62 contains, for example, silicon oxide (SiO ₂ ).

The conductive layer 63 covers a portion of the side surface of the insulating film 62. The conductive layer 63 serves as a gate of the switch element SEL2. The conductive layer 63 contains, for example, tungsten (W).

1.2 Writing operation Next, the writing operation of the magnetic memory device of the first embodiment is described.

1.2.1 Example 1 First, the first example of the write operation is described. The first example of the write operation corresponds to the case where the write current Ic0 flows through the wiring SOTL and the data "0" is written.

FIG. 4 is a diagram showing an example of a voltage applied to a memory cell array in the first example of a write operation of a magnetic memory device of the first embodiment. FIG. 4 shows an example of a voltage applied to three wirings SOTL<m-1>, SOTL<m>, and SOTL<m+1> in the memory cell array 10, and three read bit lines RBL<n-1>, RBL<n>, and RBL<n+1>. In addition, in FIG. 4, an "○" is attached to each of the switch elements SEL2 and SEL3 in the on state, and an "×" is attached to each of the switch elements SEL2 and SEL3 in the off state. Furthermore, in FIG. 4, the memory cell MC<m,n> of the write object (i.e., the selected state) is shown with a shaded shape.

In the first case of performing a write operation on the selected memory cell MC<m,n>, all switch elements SEL2 are in the off state. Switch elements SEL3<n-1>, SEL3<n>, and SEL3<n+1> are in the on state. Moreover, all other switch elements SEL3 are in the off state.

Furthermore, voltages Vc0 and VSS are applied to the first and second ends of wiring SOTL＜m＞, respectively. Voltage VSS is, for example, 0 V. Voltage Vc0 is a voltage for flowing write current Ic0＜m＞ (not shown) in wiring SOTL. Furthermore, voltage VSS is applied to the first and second ends of wirings SOTL＜m-1＞ and SOTL＜m+1＞ located on both sides of wiring SOTL＜m＞. In addition, although not shown in FIG. 4 , voltage VSS is applied to the first and second ends of each of other wirings SOTL.

Furthermore, voltages VSS and Vw are applied to the first and second ends of the selection bit line RBL<n>, respectively. The first end of the selection bit line RBL<n> is the end on the opposite side of the switching element SEL3<n> and the memory cell array 10. The second end of the selection bit line RBL<n> is the end on the side sandwiching the memory cell array 10 with the switching element SEL3<n>. The voltage Vw is a voltage for causing a current Iw0<n> (not shown) to flow through the selection bit line RBL<n>.

The voltages k ₁ Vw and VSS are applied to the first and second ends of the non-selected bit line RBL<n-1> located at one of the two neighbors of the selected bit line RBL<n>, respectively. The first end of the non-selected bit line RBL<n-1> is the end on the opposite side of the switching element SEL3<n-1> and the memory cell array 10. The second end of the non-selected bit line RBL<n-1> is the end on the side sandwiching the memory cell array 10 with the switching element SEL3<n-1>. The voltage k ₁ Vw is k ₁ times the voltage Vw (0<k ₁ <1). The voltage k ₁ Vw is a voltage for causing a current Iw0 <n-1> to flow through the non-selected bit line RBL <n-1>.

The voltages VSS and k ₂ Vw are applied to the first and second ends of the non-selected bit line RBL<n+1> located at the other of the two neighbors of the selected bit line RBL<n>, respectively. The first end of the non-selected bit line RBL<n+1> is the end on the opposite side of the switching element SEL3<n+1> and the memory cell array 10. The second end of the non-selected bit line RBL<n+1> is the end on the side sandwiching the memory cell array 10 with the switching element SEL3<n+1>. The voltage k ₂ Vw is a voltage k ₂ times the voltage Vw (0<k ₂ <1). Voltage _k2 Vw is a voltage for causing current Iw0<n+1> to flow through the non-selected bit line RBL<n+1>. In addition, _k1 and _k2 may be different from each other or may be equal.

Fig. 5 is a diagram showing an example of the current and magnetic field applied to the memory cell array in the first example of the write operation of the magnetic memory device of the first embodiment. Fig. 5 shows the currents Ic0<m>, Iw0<n>, Iw0<n-1>, and Iw0<n+1>, and the magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> respectively generated by the voltages Vc0, Vw, _k1Vw , and _k2Vw shown in Fig. 4, and the change of the magnetization direction of the selected memory cell MC<m,n>.

As described above, voltages Vc0 and VSS are applied to both ends of wiring SOTL＜m＞, respectively. As a result, a write current Ic0＜m＞ flows from the left side of the conductive layer 30 to the right side of the conductive layer 30 (+X direction in FIG. 5). By flowing the write current Ic0＜m＞ through the conductive layer 30, a spin-orbit moment is generated that intends to make the magnetization direction of the ferromagnetic layer 41 parallel to the ferromagnetic layer 43. The spin-orbit moment acts on all ferromagnetic layers 41 that are connected to the conductive layer 30.

As described above, voltages VSS and Vw are applied to both ends of the selected bit line RBL<n>, respectively. Voltages k ₁ Vw and VSS are applied to both ends of the unselected bit line RBL<n-1>, respectively. Voltages VSS and k ₂ Vw are applied to both ends of the unselected bit line RBL<n+1>, respectively. As a result, in the conductive layer 80 corresponding to the selected bit line RBL<n>, a current Iw0<n> flows from the deep side of the paper to the front side of the paper (-Y direction of FIG. 5 ). In the conductive layer 80 corresponding to the unselected bit line RBL<n-1>, a current Iw0<n-1> flows from the front side of the paper to the deep side of the paper (+Y direction of FIG. 5 ). In the conductive layer 80 corresponding to the selected bit line RBL＜n+1＞, a current Iw0＜n+1＞ flows from the deep side of the paper to the near side of the paper (-Y direction in FIG. 5). The currents Iw0＜n-1＞ and Iw0＜n+1＞ are, for example, k ₁ times and k ₂ times the current Iw0＜n＞. That is, the current values of the currents Iw0＜n-1＞ and Iw0＜n+1＞ are smaller than the current value of the current Iw0＜n＞.

By currents Iw0<n>, Iw0<n-1>, and Iw0<n+1>, magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> are applied near the interface between the conductive layer 30 and the ferromagnetic layer 41 corresponding to the selected memory cell MC<m,n>, respectively. The magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> are concentric circles centered on the currents Iw0<n>, Iw0<n-1>, and Iw0<n+1>, respectively, and are applied in a counterclockwise direction relative to the direction of the currents Iw0<n>, Iw0<n-1>, and Iw0<n+1>.

Thus, in the example of FIG. 5 , the magnetic field Hw0<n> applied to the selected memory cell MC<m,n> is in the direction (+X direction) in which the current Ic0<m> flows. Furthermore, in the example of FIG. 5 , the directions of the magnetic fields Hw0<n-1> and Hw0<n+1> applied to the selected memory cell MC<m,n> are in the direction inclined toward the -Z direction relative to the direction in which the current Ic0<m> flows. Moreover, the magnetic fields Hw0<n-1> and Hw0<n+1> applied to the selected memory cell MC<m,n> are applied in the direction of mutual reinforcement in the -Z direction. Therefore, the composite magnetic field of the magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> applied to the selected memory cell MC<m,n> is a magnetic field having a component in the +X direction and a component in the -Z direction.

In addition, the direction of the magnetic field Hw0<n> is determined by the material constituting the conductive layer 30. Therefore, the direction of the magnetic field Hw0<n> may be the opposite direction (-X direction) to the direction in which the current Ic0<m> flows. In addition, the direction of the composite magnetic field of the magnetic field Hw0<n-1> and Hw0<n+1> has a component of the magnetization direction (-Z direction) of the ferromagnetic layer 41 determined by the writing operation.

The X-direction component of the synthetic magnetic field of the magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> applied to the selected memory cell MC<m,n> assists the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> due to the spin-orbit moment. The Z-direction component of the synthetic magnetic field of the magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> applied to the selected memory cell MC<m,n> increases the reversal speed of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> due to the spin-orbit moment and suppresses setbacks during the reversal process. Thereby, the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> is reversed to be parallel to the magnetization direction of the ferromagnetic layer 43 .

By operating as described above, data "0" is written into the selected memory cell MC<m,n>.

1.2.2 Example 2 Next, the second example of the write operation is described. The second example of the write operation corresponds to the case where the write current Ic1 flows through the wiring SOTL and the data "1" is written.

Fig. 6 is a diagram showing an example of a voltage applied to a memory cell array in the second example of a write operation of the magnetic memory device of the first embodiment. Fig. 6 corresponds to Fig. 4 of the first example of a write operation.

In the second case of performing a write operation on the selected memory cell MC<m,n>, all switch elements SEL2 are in the off state. Switch elements SEL3<n-1>, SEL3<n>, and SEL3<n+1> are in the on state. Moreover, all other switch elements SEL3 are in the off state.

Furthermore, voltages VSS and Vc1 are applied to the first and second ends of the wiring SOTL＜m＞, respectively. Voltage Vc1 is a voltage for causing a write current Ic1＜m＞ (not shown) to flow through the wiring SOTL. Thus, the polarity of the voltage applied to the wiring SOTL＜m＞ in the second example of the write operation is reversed from the voltage applied to the wiring SOTL＜m＞ in the first example of the write operation, and the magnitude may also be different. Furthermore, voltage VSS is applied to the first and second ends of each of the wirings SOTL＜m-1＞ and SOTL＜m+1＞ located on both sides of the wiring SOTL＜m＞. In addition, although not shown in FIG. 6 , voltage VSS is applied to the first and second ends of each of the other wirings SOTL.

The voltages VSS and Vw are applied to the first and second ends of the selected bit line RBL<n>, respectively. The voltages VSS and k ₁ Vw are applied to the first and second ends of the unselected bit line RBL<n-1>, respectively. The voltages k ₂ Vw and VSS are applied to the first and second ends of the unselected bit line RBL<n+1>, respectively. Thus, the voltage applied to the selected bit line RBL<n> in the second example of the write operation is the same as the voltage applied to the selected bit line RBL<n> in the first example of the write operation. On the other hand, the voltages applied to the non-selected bit lines RBL<n-1> and RBL<n+1> in the second example of the write operation have polarities opposite to those of the voltages applied to the non-selected bit lines RBL<n-1> and RBL<n+1> in the first example of the write operation.

Fig. 7 is a diagram showing an example of the current and magnetic field applied to the memory cell array in the second example of the writing operation of the magnetic memory device of the first embodiment. Fig. 7 corresponds to Fig. 5 of the first example of the writing operation.

As described above, voltages VSS and Vc1 are applied to both ends of wiring SOTL<m>, respectively. As a result, a write current Ic1<m> flows from the right side of the conductive layer 30 to the left side of the conductive layer 30 (-X direction in FIG. 7). By flowing the write current Ic1<m> through the conductive layer 30, a spin-orbit moment is generated that intends to make the magnetization direction of the ferromagnetic layer 41 antiparallel to the ferromagnetic layer 43. The spin-orbit moment acts on all ferromagnetic layers 41 that are in contact with the conductive layer 30.

Furthermore, as described above, voltages VSS and Vw are applied to both ends of the selected bit line RBL<n>, respectively. Voltages VSS and k ₁ Vw are applied to both ends of the unselected bit line RBL<n-1>, respectively. Voltages k ₂ Vw and VSS are applied to both ends of the unselected bit line RBL<n+1>, respectively. As a result, in the conductive layer 80 corresponding to the selected bit line RBL<n>, a current Iw1<n> flows from the deep side of the paper to the front side of the paper (-Y direction of FIG. 7 ). In the conductive layer 80 corresponding to the unselected bit line RBL<n-1>, a current Iw1<n-1> flows from the deep side of the paper to the front side of the paper (-Y direction of FIG. 7 ). In the conductive layer 80 corresponding to the selected bit line RBL＜n+1＞, a current Iw1＜n+1＞ flows from the front side of the paper to the back side of the paper (+Y direction in FIG. 7). The currents Iw1＜n-1＞ and Iw1＜n+1＞ are, for example, k ₁ times and k ₂ times of the current Iw1＜n＞, respectively. That is, the current values of the currents Iw1＜n-1＞ and Iw1＜n+1＞ are smaller than the current value of the current Iw1＜n＞.

By means of currents Iw1＜n＞, Iw1＜n-1＞, Iw1＜n+1＞, magnetic fields Hw1＜n＞, Hw1＜n-1＞, and Hw1＜n+1＞ are applied near the interface between the conductive layer 30 and the ferromagnetic layer 41 corresponding to the selected memory cell MC＜m,n＞, respectively. The direction of the magnetic field Hw1＜n＞ applied to the selected memory cell MC＜m,n＞ is opposite to the direction of the current Ic1＜m＞ (+X direction). The directions of the magnetic fields Hw1＜n-1＞ and Hw1＜n+1＞ applied to the selected memory cell MC＜m,n＞ are inclined toward the +Z direction relative to the direction of the current Ic1＜m＞. Furthermore, the magnetic fields Hw1<n-1> and Hw1<n+1> applied to the selected memory cell MC<m,n> are applied in a mutually reinforcing direction in the +Z direction. Therefore, the composite magnetic field of the magnetic fields Hw1<n>, Hw1<n-1>, and Hw1<n+1> applied to the selected memory cell MC<m,n> is a magnetic field having a component in the +X direction and a component in the +Z direction.

In addition, the direction of the magnetic field Hw1<n> is the same as the direction of the magnetic field Hw0<n>, and is determined by the material constituting the conductive layer 30. Therefore, the direction of the magnetic field Hw1<n> does not change regardless of the data written. In addition, the direction of the composite magnetic field of the magnetic field Hw1<n-1> and Hw1<n+1> has a component of the magnetization direction (+Z direction) of the ferromagnetic layer 41 determined by the writing operation.

The X-direction component of the synthetic magnetic field of the magnetic fields Hw1<n>, Hw1<n-1>, and Hw1<n+1> applied to the selected memory cell MC<m,n> assists the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> due to the spin-orbit moment. The Z-direction component of the synthetic magnetic field of the magnetic fields Hw1<n>, Hw1<n-1>, and Hw1<n+1> applied to the selected memory cell MC<m,n> increases the reversal speed of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> due to the spin-orbit moment and suppresses setbacks during the reversal process. Thereby, the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> is reversed to be antiparallel to the magnetization direction of the ferromagnetic layer 43 .

By operating as described above, data "1" is written into the selected memory cell MC<m,n>.

In addition, the synthetic magnetic field of the magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> in the first example of the write operation, and the synthetic magnetic field of the magnetic fields Hw1<n>, Hw1<n-1>, and Hw1<n+1> in the second example of the write operation also act on the non-selected memory cells MC<m,n-1> and MC<m,n+1>. However, the magnitude of the synthetic magnetic field applied to the non-selected memory cells MC<m,n-1> and MC<m,n+1> is sufficiently small relative to the magnitude of the magnetic field used to reverse the magnetization direction of the ferromagnetic layer 41. Therefore, in any of the first and second examples of the write operation, data is not written to the non-selected memory cells MC<m,n-1> and MC<m,n+1>.

1.2.3 Current application timing Next, the application timing of the current applied during the write operation is described. Below, six application examples that are applicable to both the first and second examples of the write operation are described. Below, for the sake of convenience, currents Ic0 and Ic1 are simply recorded as currents Ic. Similarly, currents Iw0＜n＞ and Iw1＜n＞, Iw0＜n-1＞ and Iw1＜n-1＞, and Iw0＜n+1＞ and Iw1＜n+1＞ are simply recorded as currents Iw＜n＞, Iw＜n-1＞, and Iw＜n+1＞, respectively. (First application example) FIG. 8 is a diagram showing the first application example of the application timing of the current applied during the write operation of the magnetic memory device of the first embodiment. The first application example corresponds to the situation where the application start time of the current Ic is roughly the same as the application start time of the currents Iw<n>, Iw<n-1>, and Iw<n+1>, and the application end time of the current Ic is roughly the same as the application end time of the currents Iw<n>, Iw<n-1>, and Iw<n+1>.

As shown in FIG8 , the application start time Tcs of the current Ic can be roughly consistent with the application start time Tws<n> of the current Iw<n>, the application start time Tws<n-1> of the current Iw<n+1>, and the application start time Tws<n+1> of the current Iw<n+1>. In addition, the application end time Tce of the current Ic can be roughly consistent with the application end time Twe<n> of the current Iw<n>, the application end time Twe<n-1> of the current Iw<n+1>, and the application end time Twe<n+1> of the current Iw<n+1>. (Second application example) FIG9 is a diagram showing the second application example of the application timing of the current applied in the write operation of the magnetic memory device of the first embodiment. The second application example corresponds to the situation where the application start time of the current Ic is roughly the same as the application start time of the currents Iw<n>, Iw<n-1>, and Iw<n+1>, and the application end time of the current Ic is different from the application end time of the currents Iw<n>, Iw<n-1>, and Iw<n+1>.

As shown in FIG9 , the application start time Tcs of the current Ic may be substantially consistent with the application start time Tws<n> of the current Iw<n-1>, the application start time Tws<n-1> of the current Iw<n+1>, and the application start time Tws<n+1> of the current Iw<n+1>. Furthermore, the application end time Tce of the current Ic may be different from the application end time Twe<n> of the current Iw<n>, the application end time Twe<n-1> of the current Iw<n-1>, and the application end time Twe<n+1> of the current Iw<n+1>.

In addition, FIG. 9 shows the situation where the application of currents Iw<n>, Iw<n-1>, and Iw<n+1> is completed after the application of current Ic is completed, but the second application example is not limited to this. For example, the second application example may include the situation where the application of current Ic is completed after the application of currents Iw<n>, Iw<n-1>, and Iw<n+1> is completed. However, from the perspective of improving the stability of the magnetization reversal of the ferromagnetic layer 41, it is more preferable that the application of currents Iw<n>, Iw<n-1>, and Iw<n+1> is completed after the application of current Ic is completed. (Third application example) FIG. 10 is a diagram of the third application example showing the application timing of the current applied in the write operation of the magnetic memory device of the first embodiment. The third application example corresponds to the situation where the application start time of the current Ic is different from the application start time of the currents Iw<n>, Iw<n-1>, and Iw<n+1>, and the application end time of the current Ic is different from the application end time of the currents Iw<n>, Iw<n-1>, and Iw<n+1>.

As shown in FIG10 , the application start time Tcs of the current Ic may be different from the application start time Tws<n> of the current Iw<n-1>, the application start time Tws<n-1> of the current Iw<n+1>, and the application start time Tws<n+1> of the current Iw<n+1>. Furthermore, the application end time Tce of the current Ic may be different from the application end time Twe<n> of the current Iw<n>, the application end time Twe<n-1> of the current Iw<n-1>, and the application end time Twe<n+1> of the current Iw<n+1>.

In addition, in FIG. 10, similarly to FIG. 9, the situation where the application of currents Iw<n>, Iw<n-1>, and Iw<n+1> is terminated after the application of current Ic is terminated is shown, but the second application example is not limited thereto. For example, the third application example may include the situation where the application of current Ic is terminated after the application of currents Iw<n>, Iw<n-1>, and Iw<n+1> is terminated. However, from the viewpoint of improving the stability of the magnetization reversal of the ferromagnetic layer 41, it is more preferable that the application of currents Iw<n>, Iw<n-1>, and Iw<n+1> is terminated after the application of current Ic is terminated. (Fourth application example) Figure 11 is a diagram showing the fourth application example of the application timing of the current applied in the write operation of the magnetic memory device of the first embodiment. The fourth application example corresponds to the situation where the application start time of the current Iw<n> is different from the application start time of the current Iw<n-1> and Iw<n+1>, and the application end time of the current Iw<n> is roughly the same as the application end time of the current Iw<n-1> and Iw<n+1>.

As shown in FIG11 , the application start time Tws<n> of the current Iw<n> may be different from the application start time Tws<n-1> of the current Iw<n-1> and the application start time Tws<n+1> of the current Iw<n+1>. Furthermore, the application end time Twe<n> of the current Iw<n> may be substantially the same as the application end time Twe<n-1> of the current Iw<n-1> and the application end time Twe<n+1> of the current Iw<n+1>.

In addition, FIG. 11 shows the situation where the application of currents Iw<n-1> and Iw<n+1> starts after the application of current Iw<n> starts, but the fourth application example is not limited to this. For example, the fourth application example may include the situation where the application of current Iw<n> starts after the application of currents Iw<n-1> and Iw<n+1> starts. (Fifth application example) FIG. 12 is a diagram of the fifth application example showing the application timing of the current applied in the write operation of the magnetic memory device of the first embodiment. The fifth application example corresponds to the situation where the application start time of the current Iw<n> is different from the application start time of the currents Iw<n-1> and Iw<n+1>, and the application end time of the current Iw<n> is different from the application end time of the currents Iw<n-1> and Iw<n+1>.

As shown in FIG12 , the application start time Tws<n> of the current Iw<n> may be different from the application start time Tws<n-1> of the current Iw<n-1> and the application start time Tws<n+1> of the current Iw<n+1>. Furthermore, the application end time Twe<n> of the current Iw<n> may be different from the application end time Twe<n-1> of the current Iw<n-1> and the application end time Twe<n+1> of the current Iw<n+1>.

In addition, in FIG. 12, similarly to FIG. 11, the situation where the application of the currents Iw<n-1> and Iw<n+1> is started after the application of the current Iw<n> is started is shown, but the fourth application example is not limited thereto. For example, the fourth application example may include the situation where the application of the current Iw<n> is started after the application of the currents Iw<n-1> and Iw<n+1> is started.

In addition, FIG. 12 shows the situation where the application of currents Iw<n-1> and Iw<n+1> is completed after the application of current Iw<n> is completed, but the fifth application example is not limited to this. For example, the fifth application example may include the situation where the application of current Iw<n> is completed after the application of currents Iw<n-1> and Iw<n+1> is completed. (Sixth application example) FIG. 13 is a diagram of the sixth application example showing the application timing of the current applied in the write operation of the magnetic memory device of the first embodiment. The sixth application example corresponds to the situation where the application start time of the current Iw<n> is roughly the same as the application start time of the currents Iw<n-1> and Iw<n+1>, and the application end time of the current Iw<n> is different from the application end time of the currents Iw<n-1> and Iw<n+1>.

As shown in FIG13 , the application start time Tws<n> of the current Iw<n> may be substantially the same as the application start time Tws<n-1> of the current Iw<n-1> and the application start time Tws<n+1> of the current Iw<n+1>. Furthermore, the application end time Twe<n> of the current Iw<n> may be different from the application end time Twe<n-1> of the current Iw<n-1> and the application end time Twe<n+1> of the current Iw<n+1>.

In addition, in FIG. 13, similarly to FIG. 12, the situation where the application of the currents Iw<n-1> and Iw<n+1> is terminated after the application of the current Iw<n> is terminated is shown, but the fifth application example is not limited thereto. For example, the sixth application example may include the situation where the application of the current Iw<n> is terminated after the application of the currents Iw<n-1> and Iw<n+1> is terminated.

1.3 Effect of the first embodiment According to the first embodiment, when the magnetoresistive element MTJ＜m,n＞ is written, the current Ic＜m＞ is applied to the wiring SOTL＜m＞. Moreover, the currents Iw＜n＞, Iw＜n-1＞, and Iw＜n+1＞ are respectively applied to the read bit lines RBL＜n＞, RBL＜n-1＞, and RBL＜n+1＞ in a manner that repeats the period of applying the current Ic＜m＞. In this way, the magnetic fields Hw＜n＞, Hw＜n-1＞, and Hw＜n+1＞ can be applied near the interface between the ferromagnetic layer 41 corresponding to the magnetoresistive element MTJ＜m,n＞ and the wiring SOTL＜m＞.

The direction of the magnetic field Hw<n> is parallel to the +X direction. Therefore, the magnetic field Hw<n> can assist the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> due to the spin-orbit moment. The magnetic fields Hw<n-1> and Hw<n+1> have a component in the +Z direction when the magnetization direction of the ferromagnetic layer 41 is reversed to the +Z direction, and have a component in the -Z direction when the magnetization direction of the ferromagnetic layer 41 is reversed to the -Z direction. Therefore, the magnetic fields Hw<n-1> and Hw<n+1> can improve the stability of the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> due to the spin-orbit moment.

2. Second Implementation Form Next, the magnetic memory device of the second implementation form is described. In the second implementation form, the point where the wiring SOTL is set for each memory cell MC is different from the first implementation form. The following mainly describes the structure and operation that are different from the first implementation form. The description of the structure and operation that are the same as the first implementation form is appropriately omitted.

2.1 Memory Cell Array FIG. 14 is a circuit diagram showing an example of the circuit structure of the memory cell array of the second embodiment. FIG. 14 corresponds to FIG. 2 of the first embodiment.

The memory cell array 10 includes a plurality of word lines WL, a plurality of read bit lines RBL, a plurality of write bit lines WBL, and a plurality of memory cells MC. In addition, the memory cell array 10 includes a plurality of switch elements SEL3.

The plurality of switch elements SEL3 have the same structure as the plurality of switch elements SEL3 of the first embodiment. The plurality of word lines WL include (M+1) word lines WL＜0＞, ..., WL＜m＞, ..., and WL＜M＞. The plurality of read bit lines RBL include (N+1) read bit lines RBL＜0＞, ..., RBL＜n＞, ..., and RBL＜N＞. The plurality of write bit lines WBL include (N+1) write bit lines WBL＜0＞, ..., WBL＜n＞, ..., and WBL＜N＞. The plurality of switch elements SEL3 include (N+1) switch elements SEL3＜0＞, ..., and SEL3＜N＞. The plurality of memory cells MC include (M+1)×(N+1) memory cells MC＜0,0＞, …, MC＜0,n＞, …, MC＜0,N＞, …, MC＜m,0＞, …, MC＜m,n＞, …, MC＜m,N＞, …, MC＜M,0＞, …, MC＜M,n＞, …, and MC＜M,N＞. The memory cells MC＜0,0＞ to MC＜M,N＞ have the same structure. The following description is made by taking the memory cell MC＜m,n＞, the word line WL＜m＞, the read bit line RBL＜n＞, and the write bit line WBL＜n＞ connected to the memory cell MC＜m,n＞ as an example.

The memory cell MC<m,n> includes switch elements SEL1<m,n> and SEL2<m,n>, a wiring SOTL<m,n>, and a magnetoresistive element MTJ<m,n>.

The switch element SEL1<m,n> has a first terminal connected to the wiring SOTL<m,n>, a second terminal connected to the write bit line WBL<n>, and a control terminal.

The wiring SOTL<m,n> has a first end connected to the first end of the switch element SEL1<m,n>, a second end connected to the word line WL<m>, and a center portion between the two ends. The magnetoresistive element MTJ<m,n> is connected to the center portion of the wiring SOTL<m,n>.

The magnetoresistive element MTJ<m,n> has a first end connected to the center portion of the wiring SOTL<m,n> and a second end connected to the switch element SEL2<m,n>.

The switch element SEL2<m,n> has a first end connected to the second end of the magnetoresistive element MTJ<m,n>, a second end connected to the read bit line RBL<n>, and a control end.

As described above, one memory cell MC includes a set of one wiring SOTL and one magnetoresistive element MTJ.

2.2 Memory Cell Next, the structure of the memory cell of the magnetic memory device of the second embodiment is described.

FIG15 is a cross-sectional view showing an example of a cross-sectional structure of a portion of the memory cell array of the second embodiment. FIG15 shows, as an example, three memory cells MC<m,n-1>, MC<m,n>, and MC<m,n+1> arranged along the X direction. As shown in FIG15 , each of the memory cells MC<m,n>, MC<m,n-1>, and MC<m,n+1> includes a conductive layer 30A, an element layer 40, a conductive layer 50, an element layer 60, a conductive layer 70, and a conductive layer 80.

The cross-sectional structure of the memory cells MC＜m,n-1＞, MC＜m,n＞, and MC＜m,n+1＞ of the second embodiment is identical to the cross-sectional structure of the memory cells MC＜m,n-1＞, MC＜m,n＞, and MC＜m,n+1＞ of the first embodiment, except that the conductive layer 30A used as the wiring SOTL is provided separately for each memory cell MC.

That is, the conductive layer 30A<m,n-1>, the conductive layer 30A<m,n>, and the conductive layer 30A<m,n+1> are sequentially arranged and separated from each other along the X direction. The conductive layer 30A<m,n-1>, the conductive layer 30A<m,n>, and the conductive layer 30A<m,n+1> each extend along the X direction. The memory cell MC<m,n-1> is disposed on the upper surface of the conductive layer 30A<m,n-1>. The memory cell MC<m,n> is disposed on the upper surface of the conductive layer 30A<m,n>. The memory cell MC<m,n+1> is disposed on the upper surface of the conductive layer 30A<m,n+1>.

2.2 Writing Operation Next, the writing operation of the magnetic memory device of the second embodiment is described.

2.2.1 Example 1 First, let’s explain the first example of writing action.

FIG16 is a diagram showing an example of voltage applied to the memory cell array in the first example of the write operation of the magnetic memory device of the second embodiment. FIG16 corresponds to FIG4 of the first embodiment. FIG16 shows an example of voltage applied to the three read bit lines RBL<n-1>, RBL<n>, and RBL<n+1>, the three write bit lines WBL<n-1>, WBL<n>, and WBL<n+1>, and the three word lines WL<m-1>, WL<m>, and WL<m+1> in the memory cell array 10. In addition, in Fig. 16, the switch elements SEL1, SEL2 and SEL3 in the on state are each annotated with "○", and the switch elements SEL1, SEL2 and SEL3 in the off state are each annotated with "×". In addition, in Fig. 16, the memory cell MC<m,n> of the writing object (i.e., the selection state) is shown with shading.

In the case of the first example of performing a write operation on the selected memory cell MC＜m,n＞, the switch element SEL1＜m,n＞ is in the on state. Moreover, all the switch elements SEL1 except the switch element SEL1＜m,n＞ are in the off state. All the switch elements SEL2 are in the off state. The switch elements SEL3＜n-1＞, SEL3＜n＞, and SEL3＜n+1＞ are in the on state. Moreover, all other switch elements SEL3 are in the off state.

A voltage Vc0 is applied to word line WL<m>. Furthermore, a voltage VSS is applied to other word lines WL including word lines WL<m-1> and WL<m+1>. Furthermore, a voltage VSS is applied to all write bit lines WBL. Thus, voltages Vc0 and VSS are applied to both ends of wiring SOTL<m,n>, respectively.

The voltages VSS and Vw are applied to the first and second ends of the selected bit line RBL<n>, respectively. Furthermore, the voltages k ₃ Vw and VSS are applied to the first and second ends of the non-selected bit line RBL<n-1> located at one of the two neighbors of the selected bit line RBL<n>, respectively. The voltage k ₃ Vw is a voltage k ₃ times the voltage Vw (k ₃ is a positive real number). The voltages VSS and k 4 Vw are applied to the first and second ends of the non-selected bit line RBL<n+1> located at the other of the two neighbors of the selected bit line RBL<n>, respectively. The voltage k ₄ Vw is _a voltage k ₄ times the voltage Vw (k ₄ is a positive real number). In addition, _k3 and _k4 may be different from each other or may be equal to each other.

Fig. 17 is a diagram showing an example of the current and magnetic field applied to the memory cell array in the first example of the writing operation of the magnetic memory device of the second embodiment. Fig. 17 corresponds to Fig. 5 of the first embodiment.

As described above, voltages Vc0 and VSS are applied to both ends of the wiring SOTL＜m,n＞, respectively. As a result, a write current Ic0＜m＞ flows from the left side of the paper to the right side of the paper (+X direction in FIG. 17) of the conductive layer 30A corresponding to the selected memory cell MC＜m,n＞. By the write current Ic0＜m＞ flowing through the conductive layer 30A corresponding to the selected memory cell MC＜m,n＞, a spin-orbit moment is generated that intends to make the magnetization direction of the ferromagnetic layer 41 corresponding to the selected memory cell MC＜m,n＞ parallel to the ferromagnetic layer 43 corresponding to the selected memory cell MC＜m,n＞.

Furthermore, as described above, voltages VSS and Vw are applied to both ends of the selected bit line RBL<n>, respectively. Voltages k ₃ Vw and VSS are applied to both ends of the unselected bit line RBL<n-1>, respectively. Voltages VSS and k ₄ Vw are applied to both ends of the unselected bit line RBL<n+1>, respectively. As a result, in the conductive layer 80 corresponding to the selected bit line RBL<n>, a current Iw0<n> flows from the deep side of the paper to the front side of the paper (-Y direction of FIG. 17). In the conductive layer 80 corresponding to the unselected bit line RBL<n-1>, a current Iw0<n-1> flows from the front side of the paper to the deep side of the paper (+Y direction of FIG. 17). In the conductive layer 80 corresponding to the selected bit line RBL＜n+1＞, a current Iw0＜n+1＞ flows from the deep side of the paper to the near side of the paper (-Y direction of FIG. 17). The currents Iw0＜n-1＞ and Iw0＜n+1＞ of the second embodiment are, for example, k ₃ times and k ₄ times the current Iw0＜n＞, respectively. That is, the current values of the currents Iw0＜n-1＞ and Iw0＜n+1＞ of the second embodiment may be smaller than the current value of the current Iw0＜n＞, or may be larger than the current value of the current Iw0＜n＞.

By applying currents Iw0＜n＞, Iw0＜n-1＞, and Iw0＜n+1＞, magnetic fields Hw0＜n＞, Hw0＜n-1＞, and Hw0＜n+1＞ are respectively applied near the interface between the conductive layer 30A corresponding to the selected memory cell MC＜m,n＞ and the ferromagnetic layer 41 corresponding to the selected memory cell MC＜m,n＞.

The magnitude and direction of the current Ic0, that is, the magnitude and direction of the magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> are the same as those in the first embodiment. Therefore, data "0" is written to the selected memory cell MC<m,n>.

2.2.2 Example 2 Next, we will explain the second example of writing action.

Fig. 18 is a diagram showing an example of a voltage applied to a memory cell array in the second example of a write operation of the magnetic memory device of the second embodiment. Fig. 18 corresponds to Fig. 16 of the first example of a write operation.

In the case of the second example in which the write operation is performed on the selected memory cell MC＜m,n＞, the switch element SEL1＜m,n＞ is in the on state. Moreover, all the switch elements SEL1 except the switch element SEL1＜m,n＞ are in the off state. All the switch elements SEL2 are in the off state. The switch elements SEL3＜n-1＞, SEL3＜n＞, and SEL3＜n+1＞ are in the on state. Moreover, all other switch elements SEL3 are in the off state.

A voltage Vc1 is applied to the write bit line WBL<n>. Furthermore, a voltage VSS is applied to other write bit lines WBL including the write bit lines WBL<n-1> and WBL<n+1>. Furthermore, a voltage VSS is applied to all word lines WL. Thus, voltages VSS and Vc1 are applied to both ends of the wiring SOTL<m,n>, respectively.

The voltages VSS and Vw are applied to the first and second ends of the selected bit line RBL<n>, respectively. The voltages VSS and k ₃ Vw are applied to the first and second ends of the unselected bit line RBL<n-1>, respectively. The voltages k ₄ Vw and VSS are applied to the first and second ends of the unselected bit line RBL<n+1>, respectively. In this way, as in the first embodiment, the voltage applied to the selected bit line RBL<n> in the second example of the write operation of the second embodiment is the same as the voltage applied to the selected bit line RBL<n> in the first example of the write operation of the second embodiment. On the other hand, in the second example of the write operation of the second implementation form, the voltages applied to the non-selected bit lines RBL＜n-1＞ and RBL＜n+1＞ have polarities opposite to those of the voltages applied to the non-selected bit lines RBL＜n-1＞ and RBL＜n+1＞ in the first example of the write operation of the second implementation form.

Fig. 19 is a diagram showing an example of the current and magnetic field applied to the memory cell array in the second example of the writing operation of the magnetic memory device of the second embodiment. Fig. 19 corresponds to Fig. 17 of the first example of the writing operation.

As described above, voltages VSS and Vc1 are applied to both ends of the wiring SOTL＜m,n＞, respectively. As a result, a write current Ic1＜m＞ flows from the right side of the paper to the left side of the paper (-X direction in FIG. 19) of the conductive layer 30A corresponding to the selected memory cell MC＜m,n＞. By the write current Ic1＜m＞ flowing through the conductive layer 30A corresponding to the selected memory cell MC＜m,n＞, a spin-orbit moment is generated that intends to make the magnetization direction of the ferromagnetic layer 41 corresponding to the selected memory cell MC＜m,n＞ antiparallel to the ferromagnetic layer 43 corresponding to the selected memory cell MC＜m,n＞.

Furthermore, as described above, voltages VSS and Vw are applied to both ends of the selected bit line RBL<n>, respectively. Voltages VSS and k ₃ Vw are applied to both ends of the unselected bit line RBL<n-1>, respectively. Voltages k ₄ Vw and VSS are applied to both ends of the unselected bit line RBL<n+1>, respectively. As a result, in the conductive layer 80 corresponding to the selected bit line RBL<n>, a current Iw1<n> flows from the deep side of the paper to the near side of the paper (-Y direction of FIG. 19). In the conductive layer 80 corresponding to the unselected bit line RBL<n-1>, a current Iw1<n-1> flows from the deep side of the paper to the near side of the paper (-Y direction of FIG. 19). In the conductive layer 80 corresponding to the selected bit line RBL<n+1>, a current Iw1<n+1> flows from the front side of the paper to the back side of the paper (the +Y direction in FIG. 19 ).

By applying currents Iw1＜n＞, Iw1＜n-1＞, and Iw1＜n+1＞, magnetic fields Hw1＜n＞, Hw1＜n-1＞, and Hw1＜n+1＞ are respectively applied near the interface between the conductive layer 30A corresponding to the selected memory cell MC＜m,n＞ and the ferromagnetic layer 41 corresponding to the selected memory cell MC＜m,n＞.

The magnitude and direction of the current Ic1 and the magnitude and direction of the magnetic fields Hw1<n>, Hw1<n-1>, and Hw1<n+1> can be the same as those in the first embodiment. Therefore, data "1" is written to the selected memory cell MC<m,n>.

2.3 Effect of the second embodiment According to the second embodiment, when the magnetoresistive element MTJ＜m,n＞ is written, a current Ic＜m＞ is applied to the wiring SOTL＜m,n＞. Furthermore, currents Iw＜n＞, Iw＜n-1＞, and Iw＜n+1＞ are applied to the read bit lines RBL＜n＞, RBL＜n-1＞, and RBL＜n+1＞ respectively in a manner that repeats the period of applying the current Ic＜m＞. Thus, magnetic fields Hw＜n＞, Hw＜n-1＞, and Hw＜n+1＞ can be applied in the same direction and magnitude as in the first embodiment near the interface between the ferromagnetic layer 41 corresponding to the magnetoresistive element MTJ＜m,n＞ and the wiring SOTL＜m＞. Therefore, similar to the first embodiment, the magnetic field Hw＜n＞ can assist the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC＜m,n＞ caused by the spin-orbit moment. In addition, the magnetic fields Hw＜n-1＞ and Hw＜n+1＞ can improve the stability of the magnetization direction reversal of the ferromagnetic layer 41 of the selected memory cell MC＜m,n＞ caused by the spin-orbit moment.

Furthermore, in the writing operation to the magnetoresistive element MTJ＜m,n＞, no current flows through the wiring SOTL＜m,n-1＞ and SOTL＜m,n+1＞. Thus, in the second embodiment, in the writing operation to the magnetoresistive element MTJ＜m,n＞, the possibility of erroneous writing of data to the magnetoresistive element MTJ＜m,n-1＞ and MTJ＜m,n+1＞ is low. Therefore, the currents Iw＜n-1＞ and Iw＜n+1＞ of the second embodiment can be smaller than the current Iw＜n＞, or can be larger than the current Iw＜n＞. Therefore, the constraints of the writing operation can be relaxed.

3. Variations, etc. In addition, the first and second embodiments described above are not limited to the above examples, and various variations can be applied.

In the first and second embodiments described above, the current Iw<n-1> is applied to the read bit line RBL<n-1> and the current Iw<n+1> is applied to the read bit line RBL<n+1> during the write operation of the magnetoresistive element MTJ<m,n>, but the present invention is not limited thereto. For example, either the current Iw<n-1> or the current Iw<n+1> may be applied. In this case, as in the first and second embodiments described above, the stability of the magnetization direction reversal of the ferromagnetic layer 41 of the selected memory cell MC<m,n> due to the spin-orbit moment can be improved.

Furthermore, in the above-mentioned first embodiment and second embodiment, the case where the currents Iw＜n-1＞ and Iw＜n+1＞ are applied in directions antiparallel to each other is described, but the present invention is not limited thereto. For example, if the following conditions are met, the currents Iw＜n-1＞ and Iw＜n+1＞ can be applied in directions parallel to each other. The conditions include: the synthetic magnetic field of the magnetic fields Hw＜n-1＞ and Hw＜n+1＞ has a component in the +Z direction when the magnetization direction of the ferromagnetic layer 41 in the magnetoresistive effect element MTJ＜m,n＞ is reversed to the +Z direction, and has a component in the -Z direction when the magnetization direction of the ferromagnetic layer 41 is reversed to the -Z direction. In this case, as in the first and second embodiments described above, the stability of the magnetization direction reversal of the ferromagnetic layer 41 of the selected memory cell MC<m,n> due to the spin-orbit moment can be improved.

In the first and second embodiments described above, the magnetoresistive effect element MTJ is described as a bottomless structure in which the ferromagnetic layer 41 is disposed below the ferromagnetic layer 43, but the present invention is not limited thereto. For example, the magnetoresistive effect element MTJ may be a topless structure in which the ferromagnetic layer 41 is disposed above the ferromagnetic layer 43. In this case, the conductive layer 30 is disposed above the ferromagnetic layer 41.

Furthermore, in the above-mentioned first embodiment and second embodiment, the case where the ferromagnetic layer 41 is arranged on the upper surface of the conductive layer 30 is described, but it is not limited to this. The ferromagnetic layer 41 can be arranged above the conductive layer 30 via an intermediate layer. The intermediate layer can, for example, include a conductive layer of copper (Cu) or the like and an insulating layer of magnesium oxide (MgO) or the like. In the case where the magnetoresistive effect element MTJ is a bottomless structure, the intermediate layer can function as a base layer of the magnetoresistive effect element MTJ. In the case where the magnetoresistive effect element MTJ is a topless structure, the intermediate layer can function as a covering layer of the magnetoresistive effect element MTJ.

In the first and second embodiments described above, the case where the switch elements SEL1, SEL2, and SEL3 are 3-terminal switch elements is described, but the present invention is not limited thereto. For example, the switch elements SEL1, SEL2, and SEL3 may be 2-terminal switch elements.

When the voltage applied between the two terminals of a 2-terminal switch element does not reach the critical voltage Vth, it becomes a "high resistance" state or an "off" state, such as an electrically non-conductive state. When the voltage applied between the two terminals of a 2-terminal switch element is greater than the critical voltage Vth, it becomes a "low resistance" state or an "on" state, such as an electrically conductive state. Regardless of the polarity of the voltage applied between the two terminals (regardless of the direction of the flowing current), the 2-terminal switch element can switch the flow or cut off of the current according to the magnitude of the voltage applied to the corresponding memory cell MC.

Even when a 2-terminal switch element is used for the switch elements SEL2 and SEL3, the stability of the write operation can be improved by utilizing the synthetic magnetic field of the magnetic fields Hw＜n＞, Hw＜n-1＞, and Hw＜n+1＞, as in the case of using a 3-terminal switch element.

Although several embodiments of the present invention are described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are included in the invention described in the patent application and its equivalents.

1: Magnetic memory device 10: Memory cell array 11: Column selection circuit 12: Row selection circuit 13: Decoding circuit 14: Write circuit 15: Read circuit 16: Voltage generation circuit 17: Input/output circuit 18: Control circuit 20, 90: Insulator layer 30, 30A, 50, 63, 70, 80: Conductive layer 40, 60: Element layer 41, 43, 45: Ferromagnetic layer 42, 44: Non-magnetic layer 61: Semiconductor film 62: Insulator film ADD: Address CMD :Command CNT:Control signal DAT:Data Ic, Ic0＜m＞, Ic1＜m＞:Write current/current Iw0＜n-1＞, Iw0＜n＞, Iw0＜n+1＞, Iw＜n-1＞, Iw＜n＞, Iw＜n+1＞, Iw1＜n-1＞, Iw1＜n＞, Iw1＜n+1＞:Current Hw0＜n-1＞, Hw0＜n＞, Hw0＜n+1＞, Hw1＜n-1＞, Hw1＜n＞, Hw1＜n+1＞:Magnetic field k ₁ Vw, k ₂ Vw, k ₃ Vw, k ₄ Vw, Vc0, Vc1, VSS, Vw: voltage MC: memory cell MC＜0,0＞~MC＜0,N＞, MC＜m,0＞~MC＜m,N＞, MC＜M,0＞~MC＜M,N＞: memory cell MS＜0＞~MS＜M＞: memory string MTJ, MTJ＜0,0＞~MTJ＜0,N＞, MTJ＜m,0＞~MTJ＜m,N＞, MTJ＜M,0＞~MTJ＜M,N＞: magnetoresistive element RBL: readout bit Line/select bit line./non-select bit line RBL＜0＞~RBL＜N＞: read bit line RBL＜n-1＞: non-select bit line/read bit line RBL＜n＞: read bit line/select bit line/read bit line RBL＜n+1＞: non-select bit line/select bit line/read bit line SEL1＜0＞~SEL1＜M＞,SEL1＜0,0＞~SEL1＜0,N＞,SEL1＜m,0＞~SEL1＜m,N＞,SE L1＜M,0＞~SEL1＜M,N＞,SEL2,SEL2＜0,0＞~SEL2＜0,N＞,SEL2＜m,0＞~SEL2＜m,N＞,SEL2＜M,0＞~SEL2＜M,N＞,SEL3＜0＞~SEL3＜N＞: Switching element SOTL＜0＞~SOTL＜M＞,SOTL＜0,0＞~SOTL＜0,N＞,SOTL＜m,0＞~SOTL＜m,N＞,SOTL＜ M,0＞~SOTL＜M,N＞: Wiring SL: Source line Tce,Twe＜n-1＞,Twe＜n＞,Twe＜n+1＞: End time of current application Tcs,Tws＜n-1＞,Tws＜n＞,Tws＜n+1＞: Start time of current application WBL,WBL＜0＞~WBL＜N＞: Write bit line WL: Word line/Select word line/Non-select word line WL＜0＞~WL＜M＞: Word line X,Y,Z: Direction

FIG. 1 is a block diagram showing an example of the configuration of the magnetic memory device of the first embodiment. FIG. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array of the first embodiment. FIG. 3 is a cross-sectional view showing an example of the cross-sectional structure of a portion of the memory string of the first embodiment. FIG. 4 is a diagram showing an example of the voltage applied to the memory cell array in the first example of the write operation of the magnetic memory device of the first embodiment. FIG. 5 is a diagram showing an example of the current and magnetic field applied to the memory cell array in the first example of the write operation of the magnetic memory device of the first embodiment. FIG. 6 is a diagram showing an example of a voltage applied to a memory cell array in the second example of a write operation of a magnetic memory device of the first embodiment. FIG. 7 is a diagram showing an example of a current and a magnetic field applied to a memory cell array in the second example of a write operation of a magnetic memory device of the first embodiment. FIG. 8 is a diagram showing a first example of an application sequence of a current applied in a write operation of a magnetic memory device of the first embodiment. FIG. 9 is a diagram showing a second example of an application sequence of a current applied in a write operation of a magnetic memory device of the first embodiment. FIG. 10 is a diagram showing a third example of an application sequence of a current applied in a write operation of a magnetic memory device of the first embodiment. FIG. 11 is a diagram showing the fourth application example of the application timing of the current applied in the write operation of the magnetic memory device of the first embodiment. FIG. 12 is a diagram showing the fifth application example of the application timing of the current applied in the write operation of the magnetic memory device of the first embodiment. FIG. 13 is a diagram showing the sixth application example of the application timing of the current applied in the write operation of the magnetic memory device of the first embodiment. FIG. 14 is a circuit diagram showing an example of the circuit structure of the memory cell array of the second embodiment. FIG. 15 is a cross-sectional view showing an example of the cross-sectional structure of a part of the memory cell array of the second embodiment. FIG. 16 is a diagram showing an example of a voltage applied to a memory cell array in the first example of a write operation of a magnetic memory device in the second embodiment. FIG. 17 is a diagram showing an example of a current and a magnetic field applied to a memory cell array in the first example of a write operation of a magnetic memory device in the second embodiment. FIG. 18 is a diagram showing an example of a voltage applied to a memory cell array in the second example of a write operation of a magnetic memory device in the second embodiment. FIG. 19 is a diagram showing an example of a current and a magnetic field applied to a memory cell array in the second example of a write operation of a magnetic memory device in the second embodiment.

20,90: Insulating layer

30,50,63,70,80: Conductor layer

40,60: Component layer

41,43,45: Ferromagnetic layer

42,44: Non-magnetic layer

61:Semiconductor film

62: Insulating body membrane

Ic0<m>: write current/current

Iw0<n-1>,Iw0<n>,Iw0<n+1>: current

Hw0<n-1>,Hw0<n>,Hw0<n+1>: magnetic field

MC<m,n-1>,MC<m,n>,MC<m,n+1>: memory cells

MS<m>: memory string

MTJ: Magnetoresistive element

RBL<n-1>: Non-select bit line/read bit line

RBL<n>: Read bit line/Select bit line/Read bit line

RBL<n+1>: non-select bit line/select bit line/read bit line

SEL2: Switching element

SOTL<m>: Wiring

X,Y,Z: Direction

Claims (17)

A magnetic memory device, comprising: a first conductive layer extending along a first direction; a second conductive layer extending along the first direction and arranged with the first conductive layer along a second direction intersecting the first direction; a first magnetoresistance effect element electrically connected to the first conductive layer; a second magnetoresistance effect element electrically connected to the second conductive layer; and a third conductive layer extending along the second direction and connected to the first magnetoresistance effect element; and in a writing operation of writing data to the first magnetoresistance effect element, a first current is applied to the first conductive layer, a second current is applied to the second conductive layer, A third current is applied to the third conductive layer independently of the first current and the second current. The magnetic memory device of claim 1 further comprises: a fourth conductive layer extending along the first direction and arranged along the second direction with the first conductive layer on the opposite side of the first conductive layer and the second conductive layer; and a third magnetoresistance effect element connected to the fourth conductive layer; and in the writing operation, a fourth current is applied to the fourth conductive layer. A magnetic memory device as claimed in claim 2, wherein the second magnetoresistance element and the third magnetoresistance element are adjacent to the first magnetoresistance element in the second direction. A magnetic memory device as claimed in claim 2, wherein the direction of the second current is antiparallel to the direction of the fourth current. A magnetic memory device as claimed in claim 1, wherein the magnetic field applied to the first magnetoresistance element based on the first current and the second current has: a component in the second direction, and a component in a third direction intersecting the first direction and the second direction. A magnetic memory device as claimed in claim 1, wherein the third conductive layer is further connected to the second magnetoresistive element. A magnetic memory device as claimed in claim 1, wherein the second current is smaller than the first current. The magnetic memory device of claim 1 further comprises a fifth conductive layer extending along the second direction and connected to the second magnetoresistive element. A magnetic memory device as claimed in claim 1, wherein the first magnetoresistance effect element comprises: a first ferromagnetic layer connected to the third conductive layer; a second ferromagnetic layer; and a non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer. A magnetic memory device as claimed in claim 9, wherein the magnetization direction of the first ferromagnetic layer is changed from a third direction intersecting the first direction and the second direction to a fourth direction antiparallel to the third direction by the aforementioned writing operation; and the magnetic field generated by the aforementioned second current has a component antiparallel to the aforementioned third direction and parallel to the aforementioned fourth direction. A magnetic memory device as claimed in claim 1, wherein the third conductive layer contains at least one element selected from tungsten (Ta), tungsten (W), rhodium (Re), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), copper (Cu), nimium (Os), iridium (Ir), platinum (Pt), gold (Au), manganese (Mn), lead (Pb), bismuth (Bi), antimony (Sb), tellurium (Te), selenium (Se), and polonium (Po). A magnetic memory device as claimed in claim 1, wherein the first moment when the application of the first current begins and the second moment when the application of the second current begins are substantially consistent with the third moment when the application of the third current begins; and the fourth moment when the application of the first current ends and the fifth moment when the application of the second current ends are substantially consistent with the sixth moment when the application of the third current ends. A magnetic memory device as claimed in claim 1, wherein the first moment when the application of the first current begins and the second moment when the application of the second current begins are substantially the same as the third moment when the application of the third current begins; and the fourth moment when the application of the first current ends and the fifth moment when the application of the second current ends are different from the sixth moment when the application of the third current ends. A magnetic memory device as claimed in claim 1, wherein the first moment when the application of the first current begins and the second moment when the application of the second current begins are different from the third moment when the application of the third current begins; and the fourth moment when the application of the first current ends and the fifth moment when the application of the second current ends are different from the sixth moment when the application of the third current ends. A magnetic memory device as claimed in claim 1, wherein the first moment when the application of the first current begins is different from the second moment when the application of the second current begins; and the fourth moment when the application of the first current ends is roughly the same as the fifth moment when the application of the second current ends. A magnetic memory device as claimed in claim 1, wherein the first moment when the application of the first current begins is different from the second moment when the application of the second current begins; and the fourth moment when the application of the first current ends is different from the fifth moment when the application of the second current ends. A magnetic memory device as claimed in claim 1, wherein the first moment when the application of the first current begins is substantially the same as the second moment when the application of the second current begins; and the fourth moment when the application of the first current ends is different from the fifth moment when the application of the second current ends.