TWI887610B - Method for wafer treatment - Google Patents

Abstract

A method for wafer treatment includes providing a wafer including a main surface, a surface layer and a base layer; and performing at least one laser process to irradiate the whole surface layer with laser to thereby generate a plurality of defect regions in the surface layer, and the defect regions form at least one array of defect regions.

Description

Wafer processing method

The present invention relates to a wafer processing method, and in particular to a processing method for the inside of a wafer.

In the semiconductor manufacturing process, an epitaxial process is usually performed to form an epitaxial layer on a wafer. The epitaxial layer can be a semiconductor layer, including a stress buffer layer, a high resistance layer, a carrier transport layer and/or a capping layer, but is not limited thereto. Then, appropriate semiconductor processes, such as thin film processes, etching processes, patterning processes, doping processes, etc., are performed to form semiconductor devices. However, especially heteroepitaxy or homoepitaxy with doping concentrations that differ by more than two orders of magnitude, after the epitaxial process is completed, considerable stress is usually generated at the interface between the wafer and the epitaxial layer. This stress usually comes from the mismatch of the lattice constant or the mismatch of the coefficient of thermal expansion (CTE) between the wafer and the epitaxial layer.

For example, when forming a gallium nitride epitaxial layer on a silicon wafer using an epitaxial process, the lattice mismatch between silicon and gallium nitride is 17% and the thermal expansion coefficient mismatch is 54%, which causes the surface of the silicon wafer to bend and generates stress, lattice defects or cracks in the epitaxial layer. The defects and stress will not only cause the wafer to bend significantly and become brittle after epitaxial deposition, making subsequent device processing difficult, but will also affect the electron mobility, breakdown voltage or other electrical properties of subsequent semiconductor devices, thereby reducing the reliability of semiconductor devices.

To solve the above problems, a buffer epitaxial layer with a super lattice structure or a lattice constant gradient structure (gradient layer) can be set between the wafer and the epitaxial layer, but this will increase the complexity of the process. On the other hand, the materials that can match the wafer and the epitaxial layer at the same time are too limited, which will reduce the flexibility of the process. Therefore, the industry needs a processing method that can release the stress between the wafer and the epitaxial layer.

To achieve the above-mentioned purpose, the present invention provides a wafer processing method, which includes providing a wafer, the wafer including a main surface, a surface layer and a main layer, wherein the surface layer is located between the main surface and the main layer; and performing at least one laser process to fully irradiate the surface layer with a laser, thereby generating a plurality of defect regions in the surface layer, and the plurality of defect regions constitute at least one defect array. The defect region referred to in the present invention may be a single crystal of the same material with a variation in lattice constant, a polycrystalline morphology, amorphous silicon, a tiny bubble, a vaporization region or a cavity, and may constitute a defect array.

The defect array formed by the wafer processing method of the present invention can effectively absorb the stress of the epitaxial layer subsequently set on the wafer, and has the advantages of simple steps and low cost.

100: Wafer

100A: Main layer

100B: Surface layer

100T: Main surface

110: Unprocessed area

200: First defect area

200a: First sub-defect area

200b: Second sub-defect area

200c: The third sub-defect area

202: Second defect area

302: First horizontal plane

304: Second level

306: The third level

A1: The first defect array

A2: The second defect array

a1: array unit length

a2: array unit width

F: Focus

G: Laser generating device

G1: First laser generating device

G2: Second laser generating device

H1: First Depth

H2: Second Depth

L:Laser

La: light spot

Lv: Focus depth

Lv1: First focus depth

Lv2: Second focus depth

Lv3: Third focus depth

P: Scan path

P1: First scanning path

P2: Second scanning path

T: Scan width

θ ₁ : Laser angle

θ ₂ : Angle

D1: First direction

D2: Second direction

X: X axis

Y:Y axis

Z:Z axis

S1-S2: Steps

Figure 1 is a three-dimensional schematic diagram of the first laser process performed in an embodiment of the present invention.

Figure 2 is a three-dimensional schematic diagram of the laser process of an embodiment of the present invention.

Figure 3 is a cross-sectional schematic diagram of the first laser process performed in an embodiment of the present invention.

Figure 4 is a schematic cross-sectional view of an embodiment of the present invention after the first laser process is performed.

Figure 5 is a cross-sectional schematic diagram of another embodiment of the present invention after the first laser process is performed.

Figure 6 is a cross-sectional schematic diagram of another embodiment of the present invention after the first laser process is performed.

Figure 7 is a three-dimensional schematic diagram of the first laser process and the second laser process in an embodiment of the present invention.

FIG8 is a schematic cross-sectional view of an embodiment of the present invention after the first laser process and the second laser process are performed.

Figure 9 is a top view schematic diagram of a defect array of an embodiment of the present invention.

FIG. 10 is a top view of the laser scanning path of the laser process in different embodiments of the present invention.

Figure 11 is a flow chart of the wafer processing method of the present invention.

In order to enable a person skilled in the art who is familiar with the technical field to which the present invention belongs to further understand the present invention, several preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with the accompanying drawings. Moreover, a person skilled in the art who is familiar with the technical field to which the present invention belongs can also refer to the following embodiments without departing from the spirit of the present invention, and replace, reorganize, and mix the features in several different embodiments to complete other embodiments.

FIG1 is a three-dimensional schematic diagram of a first laser process according to an embodiment of the present invention. The wafer 100 includes a main surface 100T, a surface layer 100B and a main layer 100A, wherein the surface layer 100B is located between the main surface 100T and the main layer 100. The material of the wafer 100 is, for example, a single crystal wafer substrate composed of one or more elements such as silicon, silicon carbide, gallium nitride, aluminum nitride, gallium arsenide, indium phosphide, sapphire, or a composite single crystal wafer composed of the above materials stacked together, but is not limited thereto. On the other hand, according to different requirements, the wafer 100 can be doped with different concentrations of dopants, such as group IIIA or group VA elements, and the doping concentration can be 10^16 atoms/cm3 to 10^18 atoms/cm3, but is not limited thereto. According to the different rigidity performance of the material of the wafer 100, the thickness of the wafer 100 can be 0.3 mm to 1.5 mm. The thickness of the surface layer 100B herein is determined according to the main material, doping concentration or epitaxial thickness of the epitaxial layer subsequently formed on the main surface 100T. For example, if the difference in lattice constant and thermal expansion coefficient between the wafer 100 and the epitaxial layer formed thereon is greater or the difference in doping concentration between the two is greater, the lattice mismatch is more serious, and the thickness of the surface layer 100B is greater at this time. In one embodiment, the thickness of the surface layer 100B may be 50 microns to 500 microns. It should be noted that the surface layer 100B of the wafer 100 is substantially a homogeneous structure before the laser process is performed, that is, each region of the surface layer 100B has substantially the same lattice size, crystal plane, crystal type and/or doping concentration.

The first laser process implemented in this embodiment is performed along multiple paths parallel to the first direction D1, and the first laser process is fully performed on the surface layer 100B. For example, the laser generating device G generates laser L, and the laser L is used to irradiate the surface layer 100B of the wafer 100 to form a plurality of first defect regions (not shown) in the surface layer 100B, and the plurality of first defect regions constitute a first defect array (not shown).

It should be noted that the defect region described herein (including the first defect region, the second defect region, the third defect region or any other defect region) means that the defect density, the number of voids, the number of grain boundaries and/or the crystal type in the region are different from other regions of the surface layer 100B.

It should be noted that, when the laser is irradiated on a certain layer, it means that the focus of the laser is in the layer. For example, when the laser L is irradiated on the surface layer 100B, it means that the focus of the laser L emitted by the laser generating device G is in the surface layer 100B.

It should be noted that the laser process implemented in the present invention is to form a defect array inside the wafer 100 (e.g., the surface layer 100B). Therefore, the laser wavelength of the laser process implemented must have the property of penetrating or partially penetrating the wafer, so that the energy of the laser will not be greatly absorbed or reflected by the wafer before reaching the predetermined depth. For example, when the material of the wafer is silicon, the laser wavelength of the laser process implemented must be greater than 1300 nanometers.

In FIG. 1 , the laser L has a laser angle θ ₁ with the main surface 100T of the wafer 100 . In one embodiment, the laser angle of the first laser process may be 30° to 90°.

FIG2 is a three-dimensional schematic diagram of a laser process of an embodiment of the present invention, and further magnifies the laser L emitted by the laser generating device G. The laser generating device G can perform a laser process along the scanning path P and other scanning paths. The laser L emitted by the laser generating device G has a focus F, and the laser L has a spot La on the outermost exposed surface of the wafer 100 (e.g., the main surface 100T). It should be noted that although the focus F of the laser L in FIG2 is located above the outermost exposed surface of the wafer 100, when the focus F of the laser L is located below the outermost exposed surface (e.g., the main surface 100T), the outermost exposed surface of the wafer 100 will still have a spot La.

FIG3 is a schematic cross-sectional view of an embodiment of the present invention performing the first laser process. The focal depth Lv of the first laser process may be located at 0.01 micrometers to 50 micrometers below the main surface 100T. In one embodiment, the pulse frequency of the first laser process is 1 kHz to 2 MHz, or 10 kHz to 100 kHz, but is not limited thereto. According to different requirements, the pulse frequency may be adjusted according to the type of material and the lateral size of the defective area. The pulse width may be 100 femtoseconds to 500 nanoseconds, or 0.2 nanoseconds (i.e., 200 picoseconds) to 10 nanoseconds, but is not limited thereto. When the pulse width of the laser is shorter, such as 300 picoseconds, it may be combined with a higher pulse frequency, such as above MHz. The pulse energy of the first laser process can be 600uJ/pulse to 20uJ/pulse. It should be noted that the pulse energy referred to in the present invention is the energy delivered by the laser in each pulse, and the energy received by the irradiated surface of the wafer per unit time is not only related to the pulse energy, but also to the pulse width and pulse frequency. Specifically, the energy (uJ/ns) received by the irradiated surface of the wafer per unit time can be obtained by dividing the pulse energy by the pulse width. For a laser device of a given power, when the pulse frequency is increased, the pulse energy will be reduced. In addition, if the laser pulse width is adjusted from the nanosecond level to the picosecond or femtosecond level, the laser peak power will be higher, which means it will be easier to produce a high defect density array. Therefore, the laser pulse energy used to produce a defect array also has a certain relationship with the surface roughness of the wafer.

FIG4 is a schematic cross-sectional view of an embodiment of the present invention after the first laser process is performed, wherein a plurality of first defect regions 200 are provided on the surface layer 100B of the wafer 100. The first defect regions 200 of the present embodiment are all located on the same horizontal plane, for example, parallel to the plane defined by the X-axis and the Y-axis. In other words, the focal depth (parallel to the Z-axis) of the present embodiment is a constant. It should be noted that the first defect regions 200 shown in FIG4 are not only distributed in the cross-sectional view shown in FIG4 (i.e., the vertical plane parallel to the X-axis and the Z-axis), but the first defect regions 200 may also be distributed in other multiple vertical planes parallel to the X-axis and the Z-axis. Therefore, when viewed from above, a plurality of first defect regions 200 located on the same horizontal plane constitute a first defect array, and the first defect array has a first depth H1. Specifically, the first depth H1 is the depth of the first defect array below the main surface 100T, and the first depth H1 can be 0.01 microns to 50 microns.

The first defect region 200 is a specific region modified by laser. According to the energy and time of the laser, the defect density, the number of voids, the number of grain boundaries and/or the crystal type of the first defect region 200 may be different from other regions of the surface layer 100B. According to an embodiment of the present invention, the crystal type and the number of grain boundaries of the defect region 200 are different from those of the surface layer 100B of the wafer 100. For example, the crystal type of the first defect region 200 is polycrystalline and has more grain boundaries, but the crystal type of the surface layer 100B outside the first defect region 200 is single crystal and has almost no grain boundaries, or the crystal and composition of the first defect region 200 are different from those of the wafer 100, but it is not limited thereto. The crystal type of the first defect region 200 and the crystal type of the surface layer 100B of the wafer 100 may be different. For example, the crystal type of the first defect region 200 is polycrystalline or amorphous, and the crystal type of the surface layer 100B of the wafer 100 is single crystal, but it is not limited thereto.

According to the energy and spot size diameter of the laser, the projection area of each first defect region 200 can be 1 square micron to 10 ⁴ square microns.

Adjacent first defect regions 200 can be separated from each other. According to one embodiment, the first defect regions 200 are intermittently distributed along the X axis so that adjacent first defect regions 200 do not directly contact each other. By providing the first defect regions 200, for example, discontinuous and periodically distributed first defect regions 200, there will be an untreated region 110 (for example, a region not treated by laser) between two adjacent first defect regions 200, so that multiple first defect regions 200 and adjacent untreated regions 110 located on the same horizontal plane can produce a stress buffering effect, and can serve as a stress buffer layer for subsequent epitaxial growth.

According to one embodiment, adjacent first defect regions 200 may partially contact each other, so that each first defect region 200 is continuously distributed along at least one direction. In this embodiment, adjacent first defect regions 200 can be regarded as being formed by alternating first sub-defect regions (not shown) and second sub-defect regions (not shown) along at least one direction, and the lattice defect density, lattice constant, crystal plane and/or crystal type of the first sub-defect region are different from the lattice defect density, lattice constant, crystal plane and/or crystal type of the second sub-defect region. At this time, as long as at least one of the sub-defect regions has a periodic distribution, the defect array formed by them can absorb the stress generated at the interface between the wafer 100 and the epitaxial layer.

FIG5 is a cross-sectional schematic diagram of another embodiment of the present invention after the first laser process is performed. This embodiment is substantially the same as the first laser process shown in FIG4 , except that the first laser process of this embodiment includes a first sub-laser process, a second sub-laser process, and a third sub-laser process that are sequentially and cyclically performed to generate sub-defect regions 200a, 200b, and 200c, respectively. The first sub-laser process has a first focus depth Lv1, the second sub-laser process has a second focus depth Lv2, and the third sub-laser process has a third focus depth Lv3. The first focus depth Lv1 is greater than the second focus depth Lv2, the second focus depth Lv2 is greater than the third focus depth Lv3, and the first focus depth Lv1, the second focus depth Lv2, and the third focus depth Lv3 are located at 0.01 micrometers to 10 micrometers below the main surface 100T. In one embodiment, the first focus depth Lv1 differs from the second focus depth Lv2 by 1 micron to 3 microns, and the second focus depth Lv2 differs from the third focus depth Lv3 by 1 micron to 3 microns. In addition, other laser parameters of the first sub-laser process, the second sub-laser process, and the third sub-laser process, such as pulse energy, pulse width, spot size, etc., can be the same or different, depending on actual needs.

In FIG5 , every three sub-defect regions 200a, 200b, and 200c form a regular unit similar to a ladder, and the regular unit may extend along the X-axis. The plurality of first sub-defect regions 200a may be located at the same depth and distributed on a first horizontal plane 302 parallel to the X-axis and the Y-axis to form a first sub-defect array. Similarly, the plurality of second sub-defect regions 200b and the plurality of third sub-defect regions 200c may be located at the same depth, and distributed on a second horizontal plane 304 and a third horizontal plane 306 parallel to the X-axis and the Y-axis to form a second sub-defect array and a third sub-defect array. The first depth of the first defect array is the average depth of the first sub-defect array, the second sub-defect array, and the third sub-defect array, that is, the average of the first focus depth Lv1, the second focus depth Lv2, and the third focus depth Lv3.

FIG6 is a cross-sectional schematic diagram of another embodiment of the present invention after the first laser process is performed. As shown in FIG6, this embodiment is substantially the same as the first laser process shown in FIG5. The first laser process may also include a first sub-laser process, a second sub-laser process, and a third sub-laser process that are performed sequentially and cyclically to generate sub-defect regions 200a, 200b, and 200c, respectively. The first sub-defect region 200a, the second sub-defect region 200b, and the third sub-defect region 200c may form a regular unit similar to a wave shape, and the regular unit may extend along the X-axis. For example, a first defect region 200a formed by the first sub-laser process may form a trough of the wave-shaped unit, and a third defect region 200c formed by the third sub-laser process may form a peak of the wave-shaped unit.

When the defect array is composed of multiple defect areas with different focus depths (such as ladder-shaped regular units or wavy regular straight lines), the stress at the interface between the wafer and the epitaxial layer can be effectively dispersed after the epitaxial layer is subsequently formed, thereby avoiding stress accumulation in the epitaxial layer or causing the main surface of the wafer to bend or even break.

FIG7 is a three-dimensional schematic diagram of the first laser process and the second laser process according to an embodiment of the present invention. In the process of performing the first laser process, the laser will fully irradiate the surface layer 100B along multiple paths parallel to the first direction D1 (e.g., the first scanning path P1 and other parallel paths); in the process of performing the second laser process, the laser will fully irradiate the surface layer 100B along multiple paths parallel to the second direction D2 (e.g., the second scanning path P2 and other parallel paths). According to one embodiment, for example, a first laser generating device G1 generates laser L, and the laser L is used to irradiate the surface layer 100B of the wafer 100 to form a plurality of first defect regions (not shown), and the plurality of first defect regions form a first defect array (not shown) on a horizontal plane; a second laser generating device G2 generates laser L, and the laser L is used to irradiate the surface layer 100B of the wafer 100 to form a plurality of second defect regions (not shown), and the plurality of second defect regions form a second defect array (not shown) on a horizontal plane.

In FIG. 7 , a scanning path P1 extending along the first direction D1 and a scanning path P2 extending along the second direction D2 have an angle θ ₂ therebetween. The angle θ ₂ may be 30° to 90°.

Similar to the embodiment of FIG. 4 , the second laser process can be performed along the second direction D2, and its focal depth can be 0.01 microns to 10 microns below the main surface, and the focal depth is a constant value. The focal depths of the first laser process and the second laser process can be the same or different.

According to one embodiment, the first laser process and the second laser process are performed sequentially and cyclically. For example, after the first laser process is performed along a certain path (e.g., the first scanning path P1), the second laser process is performed along another path (e.g., the second scanning path P2), and then the above processes are performed cyclically.

Similar to the embodiment of FIG. 5 , the second laser process may include a fourth sub-laser process, a fifth sub-laser process, and a sixth sub-laser process that are sequentially and cyclically performed, the fourth sub-laser process has a fourth focal depth, the fifth sub-laser process has a fifth focal depth, the sixth sub-laser process has a sixth focal depth, the fourth focal depth is greater than the fifth focal depth, the fifth focal depth is greater than the sixth focal depth, and the fourth focal depth, the fifth focal depth, and the sixth focal depth are located 0.01 micrometers to 10 micrometers below the main surface 100T. The correspondingly formed plurality of fourth sub-defect regions constitute a fourth sub-defect array on a horizontal plane, the plurality of fifth sub-defect regions constitute a fifth sub-defect array on a horizontal plane, and the plurality of sixth sub-defect regions constitute a sixth sub-defect array on a horizontal plane. The fourth sub-defect array, the fifth sub-defect array, and the sixth sub-defect array may together constitute a second defect array. Any one of the first focal depth, the second focal depth, and the third focal depth of the first laser process is different from any one of the fourth focal depth, the fifth focal depth, and the sixth focal depth of the second laser process.

In FIG. 7 , the first laser process and the second laser process are performed simultaneously, and then an annealing treatment is selectively performed to irradiate the main surface 100T or the surface layer 100B of the wafer 100 with a laser, thereby changing the crystallinity of the surface layer 100B, or the first laser process is performed first, and then a first annealing treatment is selectively performed to eliminate the stress generated by the laser process by the annealing treatment, and then the second laser process is performed, and then a second annealing treatment is selectively performed to prevent the accumulation of stress. It should be noted that although the laser process of a specific wavelength can penetrate the wafer, it will inevitably cause a slight shift in the lattice on the penetration path (for example, less than 5Å). Since the first annealing treatment is performed before the second laser process, it can ensure that the slightly shifted lattice is restored to the lattice state before the laser process to control the accuracy of the second laser process.

In one embodiment, the first laser process and the second laser process have the same pulse energy, so the first defect region and the second defect region formed have substantially the same or similar defect density, number of voids, number of grain boundaries and/or crystal morphology. In addition, depending on actual needs, the laser parameters of the first laser process and the second laser process, such as pulse energy, pulse width and spot size, can be the same or different.

FIG8 is a schematic cross-sectional view of an embodiment of the present invention after the first laser process and the second laser process are performed, wherein a plurality of first defect regions 200 are provided on the surface layer 100B of the wafer 100, and the plurality of first defect regions 200 are distributed on a horizontal plane to form a first defect array A1, and the first defect array A1 has a first depth H1. The surface layer 100B of the wafer 100 also has a plurality of second defect regions 202, and the plurality of second defect regions 202 are distributed on another horizontal plane to form a second defect array A2, and the second defect array A2 has a second depth H2. In this embodiment, the first depth H1 is different from the second depth H2, and the first depth H1 is greater than the second depth H2. It should be noted that the first defect region 200 and the second defect region 202 shown in FIG. 8 are not only distributed in the cross-section shown in FIG. 8 (i.e., the vertical plane parallel to the X-axis and the Z-axis), but the first defect region 200 and the second defect region 202 may also be distributed in other multiple vertical planes parallel to the X-axis and the Z-axis.

In another embodiment, the first depth H1 of the first defect array A1 may be the same as the second depth H2 of the second defect array A2, any first defect region 200 of the first defect array A1 does not contact any second defect region 202 of the second defect array A2, and a second defect region 202 may exist between any two adjacent first defect regions 200.

It should be noted that since the first direction of the first laser process and the second direction of the second laser process are not parallel to each other, and the scanning intervals of the first laser generating device and the second laser generating device can be adjusted according to the defect array to be formed, that is, in the top view direction of the wafer 100, part of the first defect area 200 and the second defect area 202 may not overlap.

Similarly, according to different requirements, the wafer processing method of the present invention further includes performing a third laser process along a third direction to form a plurality of third defect regions in the surface layer 100B to form a third defect array on a certain horizontal plane, so that the surface layer 100B of the wafer 100 has the first defect array, the second defect array and the third defect array at the same time.

FIG9 is a top view schematic diagram of a defect array according to an embodiment of the present invention, wherein the defect array has an array unit length a1 and an array unit width a2, the array unit length a1 is parallel to the Y axis, and the array unit width a2 is parallel to the X axis. The array unit length a1 and the array unit width a2 of this embodiment are the same, so the defect array of FIG9 can be regarded as being composed of a plurality of defective square grid units. In another embodiment, the array unit length a1 is greater than the array unit width a2, so that the defect array can be regarded as being composed of a plurality of defective rectangular units. In another embodiment, the array unit length a1 has an angle of 30° to 60° with the Y axis, and the array unit width a2 is parallel to the X axis. In this way, the defect array can be regarded as composed of multiple defect parallelogram units.

FIG. 10 shows a top view of a laser scanning path for laser processes in different embodiments of the present invention. The scanning paths P for two or more laser processes in the present invention may be the same or different. As shown in FIG. 10( a ), the scanning path P may be linear along the Y axis, and two adjacent scanning paths P have a scanning width T. The scanning width of the laser may be 2 microns to 100 microns. The scanning pitch of the laser is the spacing distance between lasers emitted by the laser generating device. In one embodiment, the scanning pitch is 1 micron to 100 microns. As shown in FIG. 10(b), the scanning path P can be performed linearly along the X axis; as shown in FIG. 10(c), in the case of performing two or more laser processes, the scanning path P of the first laser process can be performed linearly along the Y axis, and the second laser process can be performed linearly along the X axis, or the first laser process can be performed linearly along the X axis, and the second laser process can be performed linearly along the Y axis; as shown in FIG. 10(d), in the case of performing three or more laser processes, the scanning path P of the first laser process can be performed linearly along the Y axis, and the second laser process can be performed sequentially along two other different scanning directions.

FIG11 is a flow chart of the wafer processing method of the present invention. In FIG11 , the wafer processing method may include steps S1 and S2. As shown in FIG11 , in step S1, a wafer is provided. In step S2, at least one laser process is performed to fully irradiate the surface layer with laser, thereby generating a plurality of defects in the surface layer, and the plurality of defects constitute at least one defect array. According to different requirements, after executing step S2, the wafer processing method further includes performing an annealing process to irradiate the main surface or the surface layer of the wafer with laser, thereby changing the crystallinity of the surface layer.

According to the above-mentioned embodiment of the present invention, a laser process is performed to form a plurality of defects in the surface layer of the wafer to form at least one defect array. When an epitaxial layer is subsequently grown on the main surface of the wafer, the defect array is beneficial for buffering or absorbing the stress caused by the lattice constant mismatch or thermal expansion coefficient mismatch between the wafer and the epitaxial layer. Compared with first setting a buffer epitaxial layer on the wafer to solve the above-mentioned problem, the present invention has the advantages of simple steps and low cost, and since there is no need to grow an additional buffer epitaxial layer, the thickness of the semiconductor device can be reduced and even the degree of subsequent wafer thinning can be reduced.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: wafer 100A: main layer 100B: surface layer 100T: main surface G: laser generating device L: laser θ ₁ : laser angle D1: first direction

Claims (10)

A wafer processing method comprises: Providing a wafer, the wafer comprising a main surface, a surface layer and a main layer, wherein the surface layer is located between the main surface and the main layer; Performing at least one laser process, irradiating the surface layer with a laser along a plurality of laser scanning paths, thereby generating a plurality of defect regions in the surface layer, wherein the plurality of defect regions constitute at least one defect array, wherein the focusing depth of the laser process is located 0.01 micrometers to 10 micrometers below the main surface; and After performing the at least one laser process, growing an epitaxial layer on the main surface of the wafer. The wafer processing method as described in item 1 of the patent application scope, wherein the implementation of the at least one laser process comprises: Implementing a first laser process, irradiating the surface layer with a laser so that the multiple defect regions extend along a first direction, the laser focus depth is 0.01 micron to 50 microns below the main surface, and the focus depth is a constant value. The wafer processing method as described in item 1 of the patent application, wherein performing the at least one laser process comprises: performing a first laser process to irradiate the surface layer with a laser so that the multiple defect regions extend along a first direction, wherein performing the first laser process comprises: performing a first sub-laser process, a second sub-laser process and a third sub-laser process sequentially and cyclically, wherein the first sub-laser process has a first focal depth, the second sub-laser process has a second focal depth, and the third sub-laser process has a third focal depth, and the first focal depth, the second focal depth and the third focal depth are located at 0.01 micrometers to 50 micrometers below the main surface, wherein the first focal depth is greater than the second focal depth, and the second focal depth is greater than the third focal depth. The wafer processing method as described in item 1 of the patent application scope, wherein the implementation of the at least one laser process comprises: Implementing a first laser process, irradiating the surface layer with a laser, so that a portion of the multiple defect regions extend along a first direction, the laser focus depth is located at 0.01 microns to 10 microns below the main surface, and the focus depth is a constant value; and Implementing a second laser process, irradiating the surface layer with a laser, so that another portion of the multiple defect regions extend along a second direction, the laser focus depth is located at 0.01 microns to 10 microns below the main surface, and the focus depth is a constant value, wherein there is an angle between the first direction and the second direction, the angle is 30° to 90°, the focus depth of the first laser process and the focus depth of the second laser process are the same or different from each other, wherein the first laser process and the second laser process are implemented sequentially and cyclically. The wafer processing method as described in item 1 of the patent application scope, wherein performing the at least one laser process comprises: Performing a first laser process to irradiate the surface layer with a laser so that a portion of the multiple defect regions extend along a first direction, wherein performing the first laser process comprises: Performing a first sub-laser process, a second sub-laser process and a third sub-laser process sequentially and cyclically, wherein the first sub-laser process has a first focus depth, the second sub-laser process has a second focus depth, the third sub-laser process has a third focus depth, and the first focus depth, the second focus depth and the third focus depth are located at 0.01 microns to 10 microns below the main surface; and Performing a second laser process to irradiate the surface layer with a laser so that another portion of the multiple defect regions extend along a second direction, wherein performing the second laser process comprises: A fourth sub-laser process, a fifth sub-laser process and a sixth sub-laser process are sequentially and cyclically performed, wherein the fourth sub-laser process has a fourth focal depth, the fifth sub-laser process has a fifth focal depth, and the sixth sub-laser process has a sixth focal depth, and the fourth focal depth, the fifth focal depth and the sixth focal depth are located at 0.01 micrometers to 50 micrometers below the main surface; wherein there is an angle between the first direction and the second direction, and the angle is 30° to 90°, wherein the first focal depth is greater than the second focal depth, the second focal depth is greater than the third focal depth, the fourth focal depth is greater than the fifth focal depth, the fifth focal depth is greater than the sixth focal depth, and any one of the first focal depth, the second focal depth and the third focal depth is different from any one of the fourth focal depth, the fifth focal depth and the sixth focal depth. As described in item 5 of the patent application scope, the wafer processing method, wherein the implementation time of the first laser process is the same as the implementation time of the second laser process, or the implementation time of the first laser process is earlier than the implementation time of the second laser process. A wafer processing method as described in item 4 or 5 of the patent application scope, wherein the first laser process and the second laser process have the same pulse energy. As described in the wafer processing method of item 1 of the patent application scope, the at least one defect array includes: a first defect array, located at a first depth below the main surface; and a second defect array, located at a second depth below the main surface, wherein the first depth is different from the second depth. As described in item 1 of the patent application scope, in the process of implementing the at least one laser process, the scanning path of each laser is linear, the scanning pitch is 1 micron to 100 microns, and the scanning width is 2 microns to 100 microns. The wafer processing method as described in Item 1 of the patent application scope further comprises: Performing an annealing process by irradiating the main surface or the surface layer of the wafer with a laser to change the crystallinity of the surface layer.

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