TWI886603B - Chip package with heat dissipation function - Google Patents

Abstract

A chip package with heat dissipation effect comprises a substrate, at least one chip, an insulating layer and a composite heat dissipation layer, each of the chips is a horizontal chip or a vertical chip, the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is arranged on a copper layer surface of the copper layer, wherein the graphene layer has a high thermal conductivity; wherein the composite heat dissipation layer is located on the surface of the chip The upper part of the chip package is used to directly produce heat dissipation effect for the chip package, effectively solving the problem that the existing chip package is prone to poor heat dissipation and is not conducive to the market competitiveness of the product, so as to enhance the market competitiveness of the product; wherein the composite heat dissipation layer can be set on the surface of an insulating layer of the insulating layer in an adhesive manner, so as to speed up the efficiency of mass production at the manufacturing end.

Description

Chip package with heat dissipation function

The present invention relates to a chip package, in particular to a chip package with heat dissipation function.

As the performance of electronic products continues to improve, the waste heat generated by the chip packaging inside the product is also increasing, causing the chip packaging to have poor heat dissipation, which greatly affects the normal operation of electronic products and is not conducive to the market competitiveness of products. From the above, it can be seen that the known chip packaging heat dissipation technology should be improved.

Therefore, a chip package with heat dissipation function is urgently awaited by the relevant industries.

The main purpose of the present invention is to provide a chip package with heat dissipation effect, which includes a substrate, at least one chip, an insulating layer and a composite heat dissipation layer. Each chip is a horizontal chip or a vertical chip. The composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is arranged on a copper layer surface of the copper layer, wherein the graphene layer has a high thermal conductivity effect; wherein the composite heat dissipation layer is located on the upper part of the chip package to directly generate a heat dissipation effect for the chip package, effectively solving the problem that the existing chip package is prone to poor heat dissipation and is not conducive to the market competitiveness of the product.

To achieve the above-mentioned object, the present invention provides a chip package with heat dissipation effect, the chip package comprises a substrate, at least one chip, an insulating layer and a composite heat dissipation layer; wherein the substrate has a substrate circuit layer; wherein each of the chips is a horizontal chip, each of the chips has a first chip surface and an opposite second chip surface, the second chip surface faces the substrate, and the second chip surface has at least two horizontally separated crystal pads, each of the crystal pads is electrically connected and arranged on the substrate circuit layer. wherein the insulating layer is disposed on the substrate and covers each of the chips, and the insulating layer has an insulating layer surface; wherein the composite heat dissipation layer is disposed on the insulating layer surface of the insulating layer, and the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is disposed on a copper layer surface of the copper layer; wherein each of the chips is electrically connected to the outside through the substrate circuit layer of the substrate; wherein the composite heat dissipation layer is located on the chip package The upper part of the chip package is used to directly generate heat dissipation effect for the chip package; wherein the manufacturing method of the chip package includes the following steps: step S1: providing a substrate, wherein the substrate has a substrate circuit layer; step S2: arranging at least one chip on the substrate circuit layer of the substrate, wherein each of the chips is a horizontal chip, each of the chips has a first chip surface and an opposite second chip surface, the second chip surface faces the substrate, and the second chip surface has at least two horizontally separated The invention relates to a method for manufacturing a chip package of a semiconductor device and a semiconductor device. The chip package comprises: a step S3: providing an insulating layer on the substrate and covering each chip with the insulating layer; wherein the insulating layer has an insulating layer surface; and a step S4: providing a composite heat dissipation layer on the insulating layer surface of the insulating layer, wherein the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is provided on a copper layer surface of the copper layer, thereby completing a chip package to improve the market competitiveness of the product.

In a preferred embodiment of the present invention, the composite heat dissipation layer is disposed on the insulating layer surface of the insulating layer in an adhesive manner.

In a preferred embodiment of the present invention, the graphene layer is further formed on the surface of the copper layer of the copper layer in a coating manner.

In a preferred embodiment of the present invention, the substrate further includes at least one substrate blind hole, a first substrate surface and an opposite second substrate surface, and the second substrate surface faces each of the chips; wherein the substrate circuit layer further includes at least one first circuit layer, at least one second circuit layer and at least one substrate conductive pillar, each of the first circuit layers is arranged on the second substrate surface, each of the second circuit layers is arranged on the first substrate surface, each of the substrate conductive pillars is arranged in each of the substrate blind holes, and each of the first circuit layers can be electrically connected to each of the second circuit layers through each of the substrate conductive pillars; wherein each of the crystal pads of each of the chips is further arranged on each of the first circuit layers of the substrate circuit layer.

In a preferred embodiment of the present invention, the chip package further comprises an outer protective layer, which is disposed on the substrate and has at least one opening for exposing the substrate circuit layer to the outside.

The present invention further provides a chip package with heat dissipation effect, the chip package comprising a substrate, at least one chip, an insulating layer and a composite heat dissipation layer; wherein the substrate has a substrate circuit layer; wherein each of the chips is a vertical chip, each of the chips has a first chip surface and an opposite second chip surface, the second chip surface faces the substrate, wherein the first chip surface and the second chip surface are The first chip has at least two crystal pads on its surface, and each of the crystal pads on the second chip surface is electrically connected to the substrate circuit layer; wherein the insulating layer is disposed on the substrate and covers each of the chips, and the insulating layer has an insulating layer surface, and the insulating layer surface has at least one first insulating layer blind hole and at least one second insulating layer blind hole, and each of the first insulating layer blind holes is provided for each of the crystal pads on the first chip surface. The pad is electrically connected to the outside, each of the second insulating layer blind holes penetrates the insulating layer up and down, and each of the second insulating layer blind holes is provided with a conductive column, and one end of the conductive column close to the substrate is electrically connected to the substrate circuit layer; wherein the composite heat dissipation layer is provided on the insulating layer surface of the insulating layer, and the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is provided on one end of the copper layer. The copper layer is formed on the surface of the copper layer, wherein the copper layer further forms at least one patterned metal layer for electrical connection with each of the crystal pads in each of the blind holes of the first insulating layer and the conductive pillars in each of the blind holes of the second insulating layer; wherein each of the chips is electrically connected to the outside through the substrate circuit layer of the substrate; wherein the composite heat dissipation layer is located on the upper part of the chip package for directly generating heat dissipation for the chip package The manufacturing method of the chip package comprises the following steps: step S1: providing a substrate, wherein the substrate has a substrate circuit layer; step S2: arranging at least one chip on the substrate circuit layer of the substrate, wherein each of the chips is a vertical chip, each of the chips has a first chip surface and an opposite second chip surface, the second chip surface faces the substrate, wherein the first chip surface is disposed on the substrate circuit layer of the substrate; The first chip surface and the second chip surface each have at least two crystal pads, and each of the crystal pads on the second chip surface is electrically connected and arranged on the substrate circuit layer; step S3: an insulating layer is arranged on the substrate and the insulating layer covers each of the chips, and at least one first insulating layer blind hole is formed on the insulating layer by a drilling forming technology, wherein the insulating layer has an insulating layer surface, wherein each of the The first insulating layer blind hole is used to expose each of the pads on the surface of the first chip; step S4: a composite heat dissipation layer is arranged on the surface of the insulating layer of the insulating layer, wherein the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is arranged on the surface of a copper layer of the copper layer; step S5: at least one second insulating layer blind hole is formed on the composite heat dissipation layer by using a drilling forming technology holes, and at the same time, the copper layer of the composite heat sink layer forms at least one patterned metal layer, wherein each of the patterned metal layers is electrically connected to each of the wafer pads located in each of the blind holes of the first insulation layer; step S6: forming a conductive column in each of the blind holes of the second insulation layer, wherein each of the conductive columns is electrically connected to each of the patterned metal layers, thereby completing a chip package to help enhance the market competitiveness of the product.

In a preferred embodiment of the present invention, in the step S5, the drilling operation for forming each blind hole in the second insulating layer is further a laser via forming operation; wherein in the step S6, the conductive column is further formed by electroplating technology.

In a preferred embodiment of the present invention, the composite heat dissipation layer is disposed on the insulating layer surface of the insulating layer in an adhesive manner.

In a preferred embodiment of the present invention, the graphene layer is further formed on the surface of the copper layer of the copper layer in a coating manner.

In a preferred embodiment of the present invention, the substrate further includes at least one substrate blind hole, a first substrate surface and an opposite second substrate surface, and the second substrate surface faces each of the chips; wherein the substrate circuit layer further includes at least one first circuit layer, at least one second circuit layer and at least one substrate conductive pillar, each of the first circuit layers is arranged on the second substrate surface, each of the second circuit layers is arranged on the first substrate surface, each of the substrate conductive pillars is arranged in each of the substrate blind holes, and each of the first circuit layers can be electrically connected to each of the second circuit layers through each of the substrate conductive pillars; wherein each of the crystal pads of each of the chips is further arranged on each of the first circuit layers of the substrate circuit layer.

In a preferred embodiment of the present invention, the chip package further comprises an outer protective layer, which is disposed on the substrate and has at least one opening for exposing the substrate circuit layer to the outside.

The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Of course, these are merely examples and are not intended to be limiting. In addition, in various examples, the disclosure may repeatedly reference numbers and/or letters. This repetition is for the purpose of simplicity and clarity and does not in itself dictate the relationship between the various embodiments and/or configurations discussed.

The structure and technical features of the present invention are described in detail below with reference to the drawings, wherein each drawing is only used to illustrate the structural relationship and related functions of the present invention, and therefore the size of each component in each drawing is not drawn according to the actual scale and is not used to limit the present invention.

1 and 5 , the present invention provides a chip package 1 with heat dissipation function. The chip package 1 includes a substrate 10 , at least one chip 20 , an insulating layer 30 and a composite heat dissipation layer 40 .

The substrate 10 has a substrate circuit layer 11; wherein the substrate 10 further includes at least one substrate blind hole 12, a first substrate surface 13 and an opposite second substrate surface 14, but not limited to those shown in FIGS. 2 and 6, and the second substrate surface 14 faces each of the chips 20, as shown in FIGS. 3 and 7; wherein the substrate circuit layer 11 further includes at least one first circuit layer 111, at least one second circuit layer 112 and at least one substrate conductive pillar 113, but not limited to those shown in FIGS. 2 and 6, each of the first circuit layers 111 is disposed on the second substrate surface 14, each of the second circuit layers 112 is disposed on the first substrate surface 13, each of the substrate conductive pillars 113 is disposed in each of the substrate blind holes 12, and each of the first circuit layers 111 can be electrically connected to each of the second circuit layers 112 via each of the substrate conductive pillars 113, as shown in FIGS. 2 and 6. In a preferred embodiment of the chip package 1 of the present invention, the number of each substrate blind hole 12 of the substrate 10 is 2 but not limited to that shown in FIG. 1 .

Referring to FIGS. 1 and 5 , according to the type of each chip 20 in the chip package 1 of the present invention, a horizontal chip or a vertical chip is selected. The chip package 1 of the present invention can be further divided into a first embodiment in which the type of each chip 20 is selected as a horizontal chip (as shown in FIG. 1 ), and a second embodiment in which the type of each chip 20 is selected as a vertical chip (as shown in FIG. 5 ) but not limited thereto. The differences between the first embodiment and the second embodiment are respectively described below:

The embodiment shown in FIG. 1 is the first embodiment of the present invention. In the first embodiment, each chip 20 is a horizontal chip. Each chip 20 has a first chip surface 21 and an opposite second chip surface 22. The second chip surface 22 faces the substrate 10, and the second chip surface 22 has at least two horizontally separated crystal pads 23. Each crystal pad 23 is electrically connected and arranged on the substrate circuit layer 11; wherein each crystal pad 23 of each chip 20 is further arranged on each first circuit layer 111 of the substrate circuit layer 11 but not limited to that shown in FIG. 1. In a preferred embodiment of the chip package 1 of the present invention, the number of each crystal pad 23 of each chip 20 is 2 but not limited to that shown in FIG. 1.

Referring to FIG. 1 , the insulating layer 30 is disposed on the substrate 10 and covers each of the chips 20 . The insulating layer 30 has an insulating layer surface 31 .

Referring to FIG. 1 , the composite heat sink 40 is disposed on the insulating layer surface 31 of the insulating layer 30 . The composite heat sink 40 is composed of a copper layer 41 and a graphene layer 42 , and the graphene layer 42 is disposed on a copper layer surface 411 of the copper layer 41 .

Referring to FIG. 1 , each chip 20 is electrically connected to the outside via the substrate circuit layer 11 of the substrate 10 .

Referring to FIG. 1 , the composite heat sink 40 is located on the upper portion of the chip package 1 to directly generate heat dissipation for the chip package 1 .

The manufacturing method of the chip package 1 (as shown in FIG. 1 ) of the first embodiment of the present invention comprises the following steps:

Step S1: providing a substrate 10 as shown in FIG. 2 ; wherein the substrate 10 has a substrate circuit layer 11 as shown in FIG. 2 .

Step S2: at least one chip 20 is arranged on the substrate circuit layer 11 of the substrate 10 as shown in FIG. 3 ; wherein each chip 20 is a horizontal chip, each chip 20 has a first chip surface 21 and an opposite second chip surface 22, the second chip surface 22 faces the substrate 10, and the second chip surface 22 has at least two horizontally separated crystal pads 23, each of which is electrically connected and arranged on the substrate circuit layer 11 as shown in FIG. 3 .

Step S3: an insulating layer 30 is disposed on the substrate 10 and the insulating layer 30 covers each of the chips 20 as shown in FIG. 4 ; wherein the insulating layer 30 has an insulating layer surface 31 as shown in FIG. 4 .

Step S4: a composite heat dissipation layer 40 is disposed on the insulating layer surface 31 of the insulating layer 30, thereby completing a chip package 1 as shown in FIG. 1; wherein the composite heat dissipation layer 40 is composed of a copper layer 41 and a graphene layer 42, and the graphene layer 42 is disposed on a copper layer surface 411 of the copper layer 41 as shown in FIG. 1.

Referring to FIG. 1 , the composite heat dissipation layer 40 is attached to the insulating layer surface 31 of the insulating layer 30 by gluing but without limitation, so that the manufacturing end can manufacture and store the composite heat dissipation layer 40 in advance, and can be directly extracted from the warehouse when the manufacturing end needs to use it, which helps the manufacturing end to speed up the efficiency of mass production.

Referring to FIG. 1 , the graphene layer 42 is further formed on the copper layer surface 411 of the copper layer 41 by coating but not limited thereto, which helps the manufacturing end to execute more diversified manufacturing projects.

Referring to FIG. 1 , the chip package 1 further includes an outer protective layer 50 but is not limited thereto. The outer protective layer 50 is disposed on the substrate 10 and has at least one opening 51 for exposing the substrate circuit layer 11 to the outside, which helps to enhance the structural strength of the chip package 1. In a preferred embodiment of the chip package 1 of the present invention, the number of each opening 51 of each outer protective layer 50 is 2 but is not limited thereto as shown in FIG. 1 .

The embodiment shown in FIG. 5 is the second embodiment of the present invention. In the second embodiment, each chip 20 is a vertical chip. Each chip 20 has a first chip surface 21 and an opposite second chip surface 22. The second chip surface 22 faces the substrate 10. The first chip surface 21 and the second chip surface 22 each have at least two pads 23. Each pad 23 on the second chip surface 22 is electrically connected and arranged on the substrate circuit layer 11 as shown in FIG. 5. In a preferred embodiment of the chip package 1 of the present invention, the number of each pad 23 on the first chip surface 21 of each chip 20 is 2 but not limited as shown in FIG. 5, and the number of each pad 23 on the second chip surface 22 of each chip 20 is 2 but not limited as shown in FIG. 5.

Referring to FIG. 5 , the insulating layer 30 is disposed on the substrate 10 and covers each of the chips 20. The insulating layer 30 has an insulating layer surface 31. The insulating layer surface 31 has at least one first insulating layer blind hole 32 and at least one second insulating layer blind hole 33. Each of the first insulating layer blind holes 32 is used to electrically connect each of the wafer pads 23 on the first chip surface 21 to the outside. Each of the second insulating layer blind holes 33 penetrates the insulating layer 30 up and down and a conductive column 60 is disposed in each of the second insulating layer blind holes 33. One end of the conductive column 60 close to the substrate 10 is electrically connected to the substrate circuit layer 11. In a preferred embodiment of the chip package 1 of the present invention, the number of each first insulating layer blind hole 32 of the insulating layer 30 is 2 but not limited as shown in FIG. 5 , and the number of each second insulating layer blind hole 33 of the insulating layer 30 is 1 but not limited as shown in FIG. 5 .

Referring to FIG. 5 , the composite heat sink 40 is disposed on the insulating layer surface 31 of the insulating layer 30. The composite heat sink 40 is composed of a copper layer 41 and a graphene layer 42, and the graphene layer 42 is disposed on a copper layer surface 411 of the copper layer 41; wherein the copper layer 41 further forms at least one patterned metal layer 41a for electrical connection with each of the crystal pads 23 in each of the first insulating layer blind holes 32 and the conductive pillars 60 in each of the second insulating layer blind holes 33, as shown in FIG. 5 .

5 , each chip 20 is electrically connected to the outside via the substrate circuit layer 11 of the substrate 10 .

5 , the composite heat sink 40 is located on the upper portion of the chip package 1 to directly generate heat dissipation for the chip package 1 .

The manufacturing method of the chip package 1 of the second embodiment of the present invention (as shown in FIG. 5 ) comprises the following steps:

Step S1: providing a substrate 10 as shown in FIG6 ; wherein the substrate 10 has a substrate circuit layer 11 as shown in FIG6 .

Step S2: at least one chip 20 is arranged on the substrate circuit layer 11 of the substrate 10 as shown in FIG. 7 ; wherein each chip 20 is a vertical chip, each chip 20 has a first chip surface 21 and an opposite second chip surface 22, the second chip surface 22 faces the substrate 10, wherein the first chip surface 21 and the second chip surface 22 each have at least two crystal pads 23, and each crystal pad 23 on the second chip surface 22 is electrically connected and arranged on the substrate circuit layer 11 as shown in FIG. 7 .

Step S3: an insulating layer 30 is disposed on the substrate 10 and the insulating layer 30 covers each of the chips 20 as shown in FIG8 , and at least one first insulating layer blind hole 32 is formed on the insulating layer 30 by a drilling forming process as shown in FIG9 ; wherein the insulating layer 30 has an insulating layer surface 31 as shown in FIGS. 8 and 9 ; wherein each of the first insulating layer blind holes 32 allows each of the wafer pads 23 on the first chip surface 21 to be exposed to the outside as shown in FIG9 .

Step S4: a composite heat dissipation layer 40 is disposed on the insulating layer surface 31 of the insulating layer 30 as shown in FIG. 10 ; wherein the composite heat dissipation layer 40 is composed of a copper layer 41 and a graphene layer 42 , and the graphene layer 42 is disposed on a copper layer surface 411 of the copper layer 41 as shown in FIG. 10 .

Step S5: using a drilling forming process to form at least one second insulating layer blind hole 33 in the composite heat sink layer 40, and at the same time forming at least one patterned metal layer 41a on the copper layer of the composite heat sink layer 40 as shown in FIG. 11; wherein each of the patterned metal layers 41a is electrically connected to each of the wafer pads 23 located in each of the first insulating layer blind holes 32 as shown in FIGS. 5 and 11; wherein the drilling forming operation for forming each of the second insulating layer blind holes 33 is further a laser via forming operation but is not limited thereto.

Step S6: forming a conductive pillar 60 in each of the second insulating layer blind holes 33 as shown in FIG. 5 , wherein each of the conductive pillars 60 is electrically connected to each of the patterned metal layers 41 a, thereby completing a chip package 1 as shown in FIG. 5 ; wherein the conductive pillar 60 is further formed by electroplating technology but is not limited thereto.

Referring to FIG. 5 , the composite heat dissipation layer 40 is attached to the insulating layer surface 31 of the insulating layer 30 by gluing but without limitation, so that the manufacturing end can manufacture and store the composite heat dissipation layer 40 in advance, and can be directly extracted from the warehouse when the manufacturing end needs to use it, which helps the manufacturing end to speed up the efficiency of mass production.

Referring to FIG. 5 , the graphene layer 42 is further formed on the copper layer surface 411 of the copper layer 41 by coating but not limited thereto, which helps the manufacturing end to execute more diversified manufacturing projects.

Referring to FIG. 5 , the chip package 1 further includes an outer protective layer 50 but is not limited thereto. The outer protective layer 50 is disposed on the substrate 10 and has at least one opening 51 for exposing the substrate circuit layer 11 to the outside, which helps to enhance the structural strength of the chip package 1. In a preferred embodiment of the chip package 1 of the present invention, the number of each opening 51 of each outer protective layer 50 is 2 but is not limited thereto as shown in FIG. 5 .

Compared with the existing chip packages, the chip package 1 of the present invention has the following advantages:

(1) The composite heat sink 40 of the present invention is located on the upper part of the chip package 1 and is used to directly generate heat dissipation effect for the chip package 1 as shown in FIGS. 1 and 5 , wherein the composite heat sink 40 is composed of the copper layer 41 and the graphene layer 42. It is known that the graphene material itself has the property of high thermal conductivity, so that the composite heat sink 40 has high thermal conductivity due to the graphene layer 42, that is, the composite heat sink 40 can improve the heat dissipation effect of the chip package 1 through the graphene layer 42, effectively solving the problem that the existing chip package is prone to poor heat dissipation and is not conducive to the market competitiveness of the product, thereby improving the market competitiveness of the product.

(2) In the second embodiment of the chip package 1 of the present invention (as shown in FIG. 5 ), the copper layer 41 is further formed into at least one patterned metal layer 41 a for electrical connection with each of the crystal pads 23 in each of the first insulating layer blind holes 32 and the conductive pillars 60 in each of the second insulating layer blind holes 33 as shown in FIG. 5 . That is, the copper layer 41 in the composite heat sink 40 of the present invention can be further formed into a conductive wiring layer to directly provide electrical connection with each of the crystal pads 23 on the first chip surface 21 and the conductive pillars 60, so that the manufacturing end can avoid the step of manufacturing the conductive wiring layer, which helps to save costs on the manufacturing end.

The above are only preferred embodiments of the present invention, which are only illustrative and not restrictive of the present invention. A person skilled in the art will understand that many changes, modifications, and even equivalent changes may be made within the spirit and scope defined by the claims of the present invention, but all of them will fall within the scope of protection of the present invention.

1: Chip package 10: Substrate 11: Substrate circuit layer 111: First circuit layer 112: Second circuit layer 113: Substrate conductive pillar 12: Substrate blind hole 13: First substrate surface 14: Second substrate surface 20: Chip 21: First chip surface 22: Second chip surface 23: Chip pad 30: Insulation layer 31: Insulation layer surface 32: First insulation layer blind hole 33: Second insulation layer blind hole 40: Composite heat dissipation layer 41: Copper layer 41a: Patterned metal layer 42: Graphene layer 411: Copper layer surface 50: Outer sheath 51:Open your mouth 60:Conductive pillar

FIG. 1 is a schematic plan view of a side section of the first embodiment of the present invention (the chip is a horizontal chip). FIG. 2 is a schematic plan view of a side section of the substrate of the first embodiment of the present invention. FIG. 3 is a schematic view of a chip (horizontal chip) being arranged on the substrate in FIG. 2. FIG. 4 is a schematic view of an insulating layer being arranged on the substrate in FIG. 3. FIG. 5 is a schematic plan view of a side section of the first embodiment of the present invention (the chip is a vertical chip). FIG. 6 is a schematic plan view of a side section of the substrate of the second embodiment of the present invention. FIG. 7 is a schematic view of a chip (vertical chip) being arranged on the substrate in FIG. 6. FIG. 8 is a schematic view of an insulating layer being arranged on the substrate in FIG. 7. FIG9 is a schematic diagram of forming a blind hole of the first insulating layer on the insulating layer in FIG8 by using a drilling forming technique. FIG10 is a schematic diagram of providing a composite heat dissipation layer on the insulating layer in FIG9. FIG11 is a schematic diagram of forming a blind hole of the second insulating layer on the composite heat dissipation layer in FIG10 by using a drilling forming technique.

without

1: Chip packaging

10:Substrate

11: Substrate circuit layer

111: First circuit layer

112: Second circuit layer

113:Substrate conductive pillar

12:Substrate blind hole

13: Surface of first substrate

14: Surface of the second substrate

20: Chip

21: First chip surface

22: Second chip surface

23: Crystal pad

30: Insulation layer

31: Insulation layer surface

40: Composite heat dissipation layer

41: Copper layer

42: Graphene layer

411: Copper layer surface

50: Outer protective layer

51: Open mouth

Claims (9)

A chip package with heat dissipation function, comprising: A substrate having a substrate circuit layer; At least one chip, each of which is a horizontal chip, each of which has a first chip surface and an opposite second chip surface, the second chip surface faces the substrate, and the second chip surface has at least two horizontally separated crystal pads, each of which is electrically connected and arranged on the substrate circuit layer; An insulating layer, which is arranged on the substrate and covers each side of each chip and the first chip surface, and the insulating layer has an insulating layer surface; and A composite heat sink layer is provided on the surface of the insulation layer in isolation from each chip and is not in contact with the first chip surface of each chip. The composite heat sink layer is composed of a copper layer and a graphene layer, and the graphene layer is provided on a copper layer surface of the copper layer; Each chip is electrically connected to the outside through the substrate circuit layer of the substrate; The composite heat sink layer is located on the upper part of the chip package to directly generate heat dissipation effect for the chip package; The manufacturing method of the chip package includes the following steps: Step S1: Provide a substrate; wherein the substrate has a substrate circuit layer; Step S2: at least one chip is arranged on the substrate circuit layer of the substrate; wherein each chip is a horizontal chip, each chip has a first chip surface and an opposite second chip surface, the second chip surface faces the substrate, and the second chip surface has at least two horizontally separated crystal pads, each of which is electrically connected and arranged on the substrate circuit layer; Step S3: an insulating layer is arranged on the substrate and the insulating layer covers each side surface of each chip and the first chip surface; wherein the insulating layer has an insulating layer surface; and Step S4: a composite heat dissipation layer is disposed on the surface of the insulation layer of the insulation layer; wherein the composite heat dissipation layer is disposed on the surface of the insulation layer of the insulation layer in isolation from each of the chips and does not contact the first chip surface of each of the chips; wherein the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is directly coated on a copper layer surface of the copper layer by coating, thereby completing a chip package. A chip package as described in claim 1, wherein the composite heat dissipation layer is disposed on the insulating layer surface of the insulating layer in an adhesive manner. A chip package as described in claim 1, wherein the substrate further comprises at least one substrate blind hole, a first substrate surface and an opposite second substrate surface, the second substrate surface is facing each of the chips; wherein the substrate circuit layer further comprises at least one first circuit layer, at least one second circuit layer and at least one substrate conductive pillar, each of the first circuit layers is arranged on the second substrate surface, each of the second circuit layers is arranged on the first substrate surface, each of the substrate conductive pillars is arranged in each of the substrate blind holes, and each of the first circuit layers can be electrically connected to each of the second circuit layers through each of the substrate conductive pillars; wherein each of the crystal pads of each of the chips is further arranged on each of the first circuit layers of the substrate circuit layer. A chip package as described in claim 1, wherein the chip package further comprises an outer protective layer, which is disposed on the substrate and has at least one opening for exposing the substrate circuit layer to the outside. A chip package with heat dissipation function, comprising: A substrate having a substrate circuit layer; At least one chip, each of which is a vertical chip, each of which has a first chip surface and an opposite second chip surface, and the second chip surface faces the substrate; wherein the first chip surface and the second chip surface each have at least two crystal pads, and each of the crystal pads on the second chip surface is electrically connected and arranged on the substrate circuit layer; An insulating layer is disposed on the substrate and covers the side surfaces of each chip and the surface of the first chip. The insulating layer has an insulating layer surface. The insulating layer surface has at least one first insulating layer blind hole and at least one second insulating layer blind hole. Each of the first insulating layer blind holes is used to electrically connect each of the crystal pads on the surface of the first chip to the outside. Each of the second insulating layer blind holes passes through the insulating layer up and down and each of the second insulating layer blind holes is provided with a conductive column. The end of the conductive column close to the substrate is electrically connected to the substrate circuit layer; and A composite heat sink layer is disposed on the insulating layer surface of the insulating layer in isolation from each chip and is not in contact with the first chip surface of each chip. The composite heat sink layer is composed of a copper layer and a graphene layer, and the graphene layer is disposed on a copper layer surface of the copper layer; wherein the copper layer further forms at least one patterned metal layer for electrical connection with each of the crystal pads in the blind holes of the first insulating layer and the conductive pillars in the blind holes of the second insulating layer; wherein each chip is electrically connected to the outside through the substrate circuit layer of the substrate; The composite heat sink is located on the upper part of the chip package to directly generate heat dissipation for the chip package; The manufacturing method of the chip package includes the following steps: Step S1: providing a substrate; wherein the substrate has a substrate circuit layer; Step S2: setting at least one chip on the substrate circuit layer of the substrate; wherein each chip is a vertical chip, each chip has a first chip surface and an opposite second chip surface, the second chip surface faces the substrate, wherein the first chip surface and the second chip surface each have at least two crystal pads, and each crystal pad on the second chip surface is electrically connected and arranged on the substrate circuit layer; Step S3: an insulating layer is provided on the substrate and the insulating layer covers the side surfaces of each chip and the surface of the first chip, and at least one first insulating layer blind hole is formed on the insulating layer by a drilling forming process; wherein the insulating layer has an insulating layer surface; wherein each first insulating layer blind hole allows each of the wafer pads on the surface of the first chip to be exposed to the outside; Step S4: a composite heat dissipation layer is provided on the surface of the insulation layer of the insulation layer; wherein the composite heat dissipation layer is provided on the surface of the insulation layer of the insulation layer in isolation from each of the chips and does not contact the first chip surface of each of the chips; wherein the composite heat dissipation layer is composed of a copper layer and a graphene layer, and the graphene layer is directly coated on a copper layer surface of the copper layer by coating; Step S5: Form at least one blind hole of the second insulating layer in the composite heat sink layer by using a drilling forming process, and at the same time form at least one patterned metal layer in the copper layer of the composite heat sink layer; wherein each of the patterned metal layers is electrically connected to each of the wafer pads in each of the blind holes of the first insulating layer; and Step S6: Form a conductive column in each of the blind holes of the second insulating layer, wherein each of the conductive columns is electrically connected to each of the patterned metal layers, thereby completing a chip package. The chip package as described in claim 5, wherein in the step S5, the drilling operation for forming each blind hole in the second insulation layer is further a laser via forming operation; wherein in the step S6, the conductive column is further formed by using a plating process. A chip package as described in claim 5, wherein the composite heat dissipation layer is disposed on the insulating layer surface of the insulating layer in an adhesive manner. A chip package as described in claim 5, wherein the substrate further comprises at least one substrate blind hole, a first substrate surface and an opposite second substrate surface, the second substrate surface is facing each of the chips; wherein the substrate circuit layer further comprises at least one first circuit layer, at least one second circuit layer and at least one substrate conductive pillar, each of the first circuit layers is arranged on the second substrate surface, each of the second circuit layers is arranged on the first substrate surface, each of the substrate conductive pillars is arranged in each of the substrate blind holes, and each of the first circuit layers can be electrically connected to each of the second circuit layers through each of the substrate conductive pillars; wherein each of the crystal pads of each of the chips is further arranged on each of the first circuit layers of the substrate circuit layer. A chip package as described in claim 5, wherein the chip package further comprises an outer protective layer, wherein the outer protective layer is disposed on the substrate, and the outer protective layer has at least one opening for exposing the substrate circuit layer to the outside.