TWI886005B - Memory management method and data storage system - Google Patents

Abstract

A memory management method and a data storage system are disclosed. The method includes: obtaining an operation command from a host system; marking a first physical page in a memory device as invalid according to the operation command, and setting a first physical block including the first physical page in the memory device as a locked block; determining whether a total number of a spare block in the memory device is less than a first threshold; if so, determining whether any physical block belonging to the locked block meets an unlock condition; if the first physical block belonging to the locked block meets the unlock condition, releasing the first physical block as the spare block; determining whether the total number of the spare block is less than a second threshold being less than the first threshold; and if the total number of the spare block is less than the second threshold, performing a garbage collection operation.

Description

Memory management method and data storage system

The present invention relates to a memory management method and a data storage system.

With the advancement of technology, people have higher and higher requirements for the performance of storage devices. Generally speaking, memory devices (such as flash memory devices) use internal physical blocks in a rotating manner. For example, when the host system wants to store data in the memory device, the memory controller can select an idle block from the memory device to store the data. When the host system wants to delete the data in the memory device, the memory controller can mark the physical page currently storing the data as invalid, and wait for the right time to erase the physical block containing the physical page as a whole, so as to facilitate the subsequent re-storage of new data to the physical block.

However, in the prior art, once the physical pages in a physical block in a memory device have been marked as invalid in response to a specific type of operation instruction, the memory device will actively perform garbage collection (GC) on the physical block the next time it is in an idle state, so as to erase the data that the host system wants to clear as quickly as possible. However, this operation method also has defects. For example, when the vast majority of physical pages in a physical block are still in a valid state (i.e., storing valid data), the memory device needs to spend relatively more system resources (such as power and time) to perform garbage collection on the physical block, resulting in a waste of system resources. In addition, excessively frequent garbage collection of physical blocks may also unnecessarily increase write amplification (WAF), thereby shortening the life of the memory device.

The present invention provides a memory management method and a data storage system, which can improve the above-mentioned problems and effectively extend the service life of the memory device without affecting the performance of the memory device as much as possible.

The embodiment of the present invention provides a memory management method for a memory device, wherein the memory management method: obtains an operation instruction from a host system; marks a first physical page in the memory device as invalid according to the operation instruction, and sets a first physical block in the memory device containing the first physical page as a locked block; determines whether the total number of idle blocks in the memory device is less than a first critical value; if the total number of idle blocks is less than the first critical value, determines whether any physical block belonging to the locked block is invalid; whether the first physical block belonging to the locked block meets the unlocking condition; if the first physical block belonging to the locked block meets the unlocking condition, releasing the first physical block as the idle block; determining whether the total number of the idle blocks in the memory device is less than a second critical value, wherein the second critical value is less than the first critical value; if the total number of the idle blocks is less than the second critical value, performing a garbage collection operation; and if the total number of the idle blocks is not less than the second critical value, not performing the garbage collection operation.

The embodiment of the present invention further provides a data storage system, which includes a host system and a memory device. The memory device is coupled to the host system. The host system is used to provide an operation instruction, and the memory device is used to: mark a first physical page in the memory device as invalid according to the operation instruction, and set a first physical block in the memory device containing the first physical page as a locked block; determine whether the total number of idle blocks in the memory device is less than a first critical value; if the total number of idle blocks is less than the first critical value, determine whether any physical block belonging to the locked block meets the unlocking condition. ; if the first physical block belonging to the locked block meets the unlocking condition, releasing the first physical block as the idle block; determining whether the total number of the idle blocks in the memory device is less than a second critical value, wherein the second critical value is less than the first critical value; if the total number of the idle blocks is less than the second critical value, performing a garbage collection operation; and if the total number of the idle blocks is not less than the second critical value, not performing the garbage collection operation.

Based on the above, after obtaining the operation instruction from the host system, the first physical page in the memory device can be marked as invalid according to the operation instruction. At the same time, the first physical block in the memory device including the first physical page can be set as a locked block. During the operation of the memory device, the memory device can automatically determine whether the total number of idle blocks is less than the first critical value. If the total number of idle blocks is less than the first critical value, the memory device can preferentially determine whether any physical block belonging to the locked block meets the unlocking condition. If the first physical block belonging to the locked block meets the unlocking condition, the memory device may automatically release the first physical block as an idle block to increase the number of idle blocks. On the other hand, the memory device may simultaneously determine whether the total number of idle blocks is less than a second threshold value. In particular, the second threshold value may be less than the first threshold value. If the total number of idle blocks is less than the second threshold value, the memory device may automatically perform a garbage collection operation in the background to further increase the number of idle blocks. However, if the total number of idle blocks is not less than the second threshold value, the garbage collection operation may not be performed. In this way, the problem that the conventional memory device may perform garbage collection operations too frequently and shorten the service life of the memory device can be improved, and the service life of the memory device can be effectively extended without affecting the performance of the memory device as much as possible.

FIG1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Referring to FIG1 , the data storage system 10 includes a host system 11 and a memory device 12. The host system 11 can store data in the memory device 12 or read data from the memory device 12. For example, the host system 11 is any system that can actually cooperate with the memory device 12 to store data, such as a smart phone, a tablet computer, a laptop computer, a desktop computer, an industrial computer, a server, a game console, or a computer installed in a specific carrier (such as a vehicle, an aircraft, or a ship, etc.). In addition, the memory device 12 can be various non-volatile memory devices such as a flash drive, a memory card, a solid state drive (SSD), a secure digital (SD) card, a compact flash (CF) card, or an embedded storage device.

In one embodiment, the host system 11 includes a processor 111 and a connection interface 112. The processor 111 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural network processing unit (NPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application specific integrated circuits (ASIC), programmable logic devices (PLD), or other similar devices or combinations of these devices. The processor 111 is used to control the operation of the host system 11 in whole or in part. In the following embodiments, the operation description of the processor 111 may be equivalent to the operation description of the host system 11.

The connection interface 112 is coupled to the processor 111 and is used to transmit signals (including data or instructions) to the memory device 12 or receive signals from the memory device 12. In one embodiment, the host system 11 also includes any practically required hardware devices, such as a power management circuit, a network interface card, a keyboard (or a touch pad), a screen and/or a speaker, etc.

In one embodiment, the memory device 12 includes a connection interface 121, a memory controller 122, and a memory module 123. The connection interface 121 is used to connect to the connection interface 112 of the host system 11 and communicate with the host system 11 through the connection interface 112. In one embodiment, the connection interfaces 112 and 121 comply with the NVM Express (NVMe) interface specification. In one embodiment, the connection interfaces 112 and 121 may also comply with various connection interface standards such as Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Peripheral Component Interconnect Express (PCI Express), or Universal Serial Bus (USB).

The memory controller 122 is coupled to the connection interface 121 and the memory module 123. The memory controller 122 is used to control the overall operation of the memory device 12. For example, the memory controller 122 can access or control the memory module 123 according to the instructions from the host system 11. For example, the memory controller 122 can perform operations such as writing, reading, and erasing data in the memory module 123 according to the instructions from the host system 11. In one embodiment, the memory controller 122 includes a flash memory controller. In the following embodiments, the operation description of the memory controller 122 may be equivalent to the operation description of the memory device 12.

The memory module 123 is used to store data written by the host system 11. For example, the memory module 123 may include a single level cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell can store one bit), a multi level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell can store two bits), a triple level cell (TLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell can store three bits), a quad level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell can store three bits), or a quad level cell (MLC) NAND type flash memory module. The memory module 123 may be a QLC (quad-quad-cell) NAND type flash memory module (i.e., a flash memory module in which one memory cell can store 4 bits), other types of flash memory modules, or non-volatile memory modules with the same or similar characteristics. In addition, the memory cells in the memory module 123 store data by changing the critical voltage.

In one embodiment, the processor 111 may provide an operation instruction to the memory device 12. For example, the operation instruction may be transmitted to the memory device 12 via a connection between the host system 11 and the memory device 12. For example, the connection may be established by performing a handshake operation between the host system 11 and the memory device 12. How to perform a handshake operation belongs to the prior art in the technical field and will not be described in detail herein.

In one embodiment, the operation instruction indicates to delete or erase data belonging to at least one logical address (also referred to as the first logical address). The first logical address is mapped to at least one physical page (also referred to as the first physical page) in the memory module 123. For example, the operation instruction includes a Trim instruction or an instruction with similar functions.

In one embodiment, the memory controller 122 may obtain the operating instructions from the host system 11. For example, the memory controller 122 may obtain the operating instructions from the host system 11 through the connection.

In one embodiment, according to the operation instruction, the memory controller 122 may mark the first physical page as invalid. In one embodiment, the operation of marking the first physical page as invalid may be equal to or replaced by the operation of marking the data stored in the first physical page as invalid data.

In one embodiment, according to the operation instruction, the memory controller 122 may set the physical block (also referred to as the first physical block) in the memory module 123 including the first physical page as a locked block. It should be noted that after the first physical block is set as the locked block, the first physical block will be in a locked state and will not temporarily participate in the garbage collection (GC) operation for the memory module 123.

In one embodiment, after triggering the garbage collection operation for the memory module 123, the physical blocks in the memory module 123 that are set as lock blocks (i.e., physical blocks in a lock state) will not be recycled (e.g., recycled as new idle blocks). Alternatively, from another perspective, after triggering the garbage collection operation for the memory module 123, only the physical blocks in the memory module 123 that are not set as lock blocks (i.e., physical blocks that are not in a lock state) can be recycled (e.g., recycled as new idle blocks).

FIG2 is a schematic diagram showing how a first physical page is marked as invalid according to an operation instruction from a host system according to an embodiment of the present invention. Referring to FIG1 and FIG2 , it is assumed that the first physical block is a physical block 21. The physical block 21 includes a plurality of physical pages 201(1)-201(n).

The memory controller 122 may obtain an operation instruction 22 from the host system 11. For example, the operation instruction 22 may instruct to delete or erase data belonging to a first logical address, and the first logical address is mapped to a physical page 201(i) in a physical block 21. According to the operation instruction 22, the memory controller 122 may mark the physical page 201(i) in the physical block 21 as invalid (equivalent to marking the data stored in the physical page 201(i) as invalid data).

On the other hand, in response to the operation instruction 22, the memory controller 122 may set the physical block 21 as a locked block. At this time, the physical block 21 is in a locked state. In particular, after the physical block 21 is set as a locked block, the physical block 21 will not participate in the garbage collection operation for the memory module 123 until the physical block 21 is unlocked (i.e., the physical block 21 is not in a locked state). In other words, after the physical block 21 is unlocked, the physical block 21 that is not in a locked state can participate in the garbage collection operation.

In one embodiment, by setting the first physical block partially marked as invalid based on the operation instruction as a locked block, unnecessary garbage collection operations can be avoided for the first physical block when it is not necessary, thereby reducing unnecessary waste of system information and reducing write amplification (WAF). In this way, the service life of the memory device 12 can be effectively extended without affecting the performance of the memory device 12 as much as possible.

In one embodiment, the memory controller 122 may continue to receive one or more operation instructions 22 and gradually mark the physical pages 201(1)-201(n) as invalid. In one embodiment, at least one of the physical pages 201(1)-201(n) may also be marked as invalid based on other operations performed by the memory controller 122, which are not described in detail here.

In one embodiment, the memory controller 122 may continuously monitor the total number of idle blocks in the memory module 123. For example, an idle block refers to a physical block in the memory module 123 that does not store any valid data. In one embodiment, an idle block refers to a physical block in the memory module 123 that is associated with a free pool. In one embodiment, an idle block (e.g., a physical block associated with a free pool) may be erased. However, it should be noted that the idle block does not include any physical block that currently belongs to a locked block.

Taking FIG. 2 as an example, assume that the current physical block 21 belongs to the locked block. In this case, even if all physical pages 201(1)-201(n) in the physical block 21 have been marked as invalid (equivalent to physical pages 201(1)-201(n) storing no valid data), the physical block 21 currently belonging to the locked block (i.e., in a locked state) is still not considered as an idle block. However, in one embodiment, after the physical block 21 is unlocked, the physical block 21 can be switched or determined to be an idle block and can be associated with the idle pool.

In one embodiment, the memory controller 122 may determine whether the total number of idle blocks in the memory module 123 is less than a threshold value (also referred to as a first threshold value). If the total number of idle blocks in the memory module 123 is less than the first threshold value, the memory controller 122 may further determine whether any physical block belonging to the locked block meets a specific condition (also referred to as an unlocking condition). For example, the unlocking condition includes that all physical pages in a single physical block belonging to the locked block are marked as invalid (equivalent to that all physical pages in a single physical block belonging to the locked block do not store valid data).

In one embodiment, when the total number of idle blocks in the memory module 123 is less than the first critical value, if the memory controller 122 determines that a physical block belonging to the locked block meets the unlocking condition, the memory controller 122 may switch the physical block from the locked state to the unlocked state and release the physical block as a (new) idle block. For example, the physical block released as an idle block may be associated with an idle pool and may be erased.

In one embodiment, when the total number of idle blocks in the memory module 123 is less than the first critical value, the memory controller 122 may determine whether all physical pages in the first physical block belonging to the locked block are marked as invalid. If all physical pages in the first physical block are marked as invalid, the memory controller 122 may determine that the first physical block meets the unlocking condition. However, if all physical pages in the first physical block are not marked as invalid, the memory controller 122 may determine that the first physical block does not meet the unlocking condition.

Taking FIG. 2 as an example, in one embodiment, when the total number of idle blocks in the memory module 123 is less than the first critical value, if all physical pages 201(1)-201(n) in the physical block 21 currently belonging to the locked block have been marked as invalid (equivalent to the physical pages 201(1)-201(n) not storing valid data), the memory controller 122 may determine that the physical block 21 meets the unlocking condition and unlock the physical block 21. Then, the memory controller 122 may release the physical block 21 as a (new) idle block. For example, after releasing the physical block 21 as a (new) idle block, the physical block 21 may be associated with the idle pool and may be erased. However, in one embodiment, if at least one physical page in the physical block 21 currently belonging to the locked block is still valid (i.e., at least one physical page in the physical block 21 still stores valid data), the memory controller 122 may determine that the physical block 21 does not meet the unlocking condition.

In one embodiment, when the total number of idle blocks in the memory module 123 is less than the first critical value, by releasing the blocks that meet the unlocking condition as idle blocks, the total number of idle blocks in the current memory module 123 can be increased. In one embodiment, by releasing the blocks that meet the unlocking condition as idle blocks to increase the total number of idle blocks in the current memory module 123, the execution of the garbage collection operation can be delayed and/or the execution frequency of the garbage collection operation can be reduced.

In one embodiment, if all physical blocks belonging to the locked block do not meet the unlocking condition, the memory controller 122 may not release any physical block belonging to the locked block as an idle block. In other words, if all physical blocks belonging to the locked block do not meet the unlocking condition, the memory controller 122 may maintain the locking state of these physical blocks and not unlock or release these physical blocks.

In one embodiment, if the total number of idle blocks in the memory module 123 is not less than (e.g., greater than or equal to) a first critical value, the memory controller 122 may not release any physical block belonging to the locked block as an idle block. In this way, unnecessary garbage collection operations can be avoided for the first physical block when it is not necessary, thereby reducing unnecessary waste of system information and reducing write amplification (WAF). In this way, the service life of the memory device 12 can be effectively extended without affecting the performance of the memory device 12.

In one embodiment, the memory controller 122 may also determine whether the total number of idle blocks in the memory module 123 is less than another threshold value (also referred to as a second threshold value). In particular, the second threshold value may be less than the first threshold value. For example, assuming that the first threshold value is "10", the second threshold value may be "5". However, both the first threshold value and the second threshold value may be adjusted according to practical needs, as long as the specification that the second threshold value is less than the first threshold value is met.

In one embodiment, if the total number of idle blocks in the memory module 123 is less than the second threshold value, the memory controller 122 may perform a garbage collection operation. In other words, in response to the total number of idle blocks in the memory module 123 being less than the second threshold value, a garbage collection operation may be triggered. In the garbage collection operation, the memory controller 122 may select at least one physical block from the memory module 123 as a source block and select at least one physical block from the memory module 123 (e.g., an idle pool) as a target block. The memory controller 122 may read and collect valid data from the source block and centrally store the collected valid data in the target block. After all valid data in a physical block belonging to the target block is moved or copied to the source block, the physical block can be released as an idle block and can be associated with the idle pool. At the same time, the physical block (i.e., the idle block) can be erased and wait for new data to be written. However, if the total number of idle blocks in the memory module 123 is not less than the second critical value, the memory controller 122 may not perform the garbage collection operation.

FIG3 is a schematic diagram showing different types of management operations for locked blocks in a memory module according to the total number of idle blocks in the memory module according to an embodiment of the present invention. Referring to FIG1 to FIG3 , in one embodiment, if the total number of idle blocks in the memory module 123 is not less than (e.g., greater than or equal to) a threshold value THR(1) (i.e., a first threshold value), the memory controller 122 may not release any locked blocks in the memory module 123. In one embodiment, when the total number of idle blocks in the memory module 123 is not less than a threshold value THR(1), the execution of unnecessary garbage collection operations can be reduced by maintaining some physical blocks in the memory module 123 in a locked state.

In one embodiment, if the total number of idle blocks in the memory module 123 is less than the threshold value THR(1), the memory controller 122 may release the locked blocks that meet the unlocking conditions in the memory module 123. In one embodiment, when the total number of idle blocks in the memory module 123 is less than the threshold value THR(1), by releasing the locked blocks that meet the unlocking conditions in the memory module 123, the total number of idle blocks in the memory module 123 may be increased, thereby also delaying or reducing the execution of unnecessary garbage collection operations.

In one embodiment, if the total number of idle blocks in the memory module 123 further decreases to less than the critical value THR(2) (i.e., the second critical value), the memory controller 122 may trigger and execute a garbage collection operation. By executing a garbage collection operation to release new idle blocks, the memory device 12 may be maintained to operate normally.

In one embodiment, the processor 111 may provide a configuration instruction to the memory device 12. For example, the configuration instruction may be transmitted to the memory device 12 via a connection between the host system 11 and the memory device 12. The configuration instruction is used to set (including adjust or update) the first threshold value.

In one embodiment, the memory controller 122 may obtain the setting instruction from the host system 11. The memory controller 122 may set (including adjust or update) the first critical value according to the setting instruction. For example, the setting instruction may carry setting information corresponding to the first critical value. After obtaining the setting instruction, the memory controller 122 may set (including adjust or update) the first critical value according to the setting information in the setting instruction.

In one embodiment, the memory controller 122 may monitor the total number of locked blocks. The memory controller 122 may provide quantity information related to the locked blocks to the host system 11. For example, the quantity information may reflect the total number of locked blocks. In one embodiment, after receiving the quantity information, the processor 111 may provide the setting instruction according to the quantity information.

In one embodiment, the first threshold value may be positively correlated with the total number of locked blocks. In one embodiment, in response to the total number of locked blocks increasing (e.g., increasing to a value higher than a first preset number), the processor 111 may instruct the memory controller 122 to increase the first threshold value through the setting instruction. On the other hand, in one embodiment, in response to the total number of locked blocks decreasing (e.g., decreasing to a value lower than a second preset number, which may be less than the first preset number), the processor 111 may instruct the memory controller 122 to decrease the first threshold value through the setting instruction.

In one embodiment, by appropriately adjusting the first critical value, a better balance can be achieved between maintaining the locking of physical blocks and increasing the number of idle blocks. For example, in one embodiment, when the total number of locked blocks gradually increases (e.g., increases to a value higher than a first preset number), by increasing the first critical value, unlocking of locked blocks that meet the conditions can be triggered in advance. In this way, the total number of idle blocks in the memory module 123 can be appropriately increased or maintained when locking blocks is already used to reduce garbage collection operations. On the other hand, in one embodiment, when the total number of locked blocks decreases (e.g., decreases to less than a second preset number), the first critical value can be lowered to delay the triggering of unlocking the locked blocks that meet the conditions. This can avoid excessive release of locked blocks, thereby losing the original intention of locking some physical blocks to reduce unnecessary garbage collection operations.

FIG. 4 is a flow chart of a memory management method according to an embodiment of the present invention. Referring to FIG. 4 , in step S401, an operation instruction is obtained from a host system. In step S402, a first physical page in a memory device is marked as invalid according to the operation instruction, and a first physical block in the memory device containing the first physical page is set as a locked block. In step S403, it is determined whether the total number of idle blocks in the memory device is less than a first critical value. If the total number of idle blocks is not less than the first critical value, the process returns to step S401.

If the total number of idle blocks is less than the first critical value, in step S404, it is determined whether any physical block belonging to the locked block meets the unlocking condition. If a physical block belonging to the locked block meets the unlocking condition, in step S405, the physical block meeting the unlocking condition is released as an idle block. After step S405, the process may proceed to step S501 of FIG. 5 . In addition, if all physical blocks belonging to the locked block do not meet the unlocking condition, the process may proceed to step S501 of FIG. 5 after step S404.

FIG5 is a flow chart of a memory management method according to an embodiment of the present invention. Referring to FIG5, in step S501, it is determined whether the total number of idle blocks in the memory device is less than a second critical value, wherein the second critical value is less than the first critical value. If the total number of idle blocks is less than the second critical value, in step S502, a garbage collection operation is performed. However, if the total number of idle blocks is not less than the second critical value, in step S503, a garbage collection operation is not performed.

However, each step in FIG. 4 and FIG. 5 has been described in detail above, and will not be repeated here. It is worth noting that each step in FIG. 4 and FIG. 5 can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. In addition, the methods in FIG. 4 and FIG. 5 can be used in conjunction with the above exemplary embodiments, or can be used alone, and the present invention is not limited thereto.

In summary, the memory management method and data storage system proposed in the embodiment of the present invention can set the physical blocks in the memory module that are partially marked as invalid based on a specific type of operation instruction from the host system as locked blocks. In this way, it is possible to avoid unnecessary garbage collection operations on some physical blocks when it is not necessary, thereby reducing unnecessary waste of system information and reducing write amplification (WAF). In addition, according to the total number of idle blocks in the memory module, some locked blocks that meet the unlocking conditions can be unlocked and become new idle blocks. Thus, the memory management method and data storage system proposed in the embodiment of the present invention can effectively extend the service life of the memory device without affecting the performance of the memory device as much as possible.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10: Data storage system 11: Host system 111: Processor 112: Connection interface 12: Memory device 121: Connection interface 122: Memory controller 123: Memory module 21: Physical block 201(1)~201(n): Physical page 22: Operation instruction THR(1), THR(2): Critical value S401~S405, S501~S503: Steps

FIG. 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. FIG. 2 is a schematic diagram of marking a first physical page as invalid according to an operation instruction from a host system according to an embodiment of the present invention. FIG. 3 is a schematic diagram of performing different types of management operations on locked blocks in a memory module according to the total number of idle blocks in the memory module according to an embodiment of the present invention. FIG. 4 is a flow chart of a memory management method according to an embodiment of the present invention. FIG. 5 is a flow chart of a memory management method according to an embodiment of the present invention.

S401~S405: Steps

Claims (12)

A memory management method for a memory device, the memory management method comprising: Obtaining an operation instruction from a host system; Marking a first physical page in the memory device as invalid according to the operation instruction, and setting a first physical block in the memory device containing the first physical page as a locked block; Determining whether the total number of idle blocks in the memory device is less than a first critical value; If the total number of the idle blocks is less than the first critical value, determining whether any physical block belonging to the locked block meets the unlocking condition; If the first physical block belonging to the locked block meets the unlocking condition, the first physical block is released as the idle block; Determine whether the total number of the idle blocks in the memory device is less than a second critical value, wherein the second critical value is less than the first critical value; If the total number of the idle blocks is less than the second critical value, perform a garbage collection operation; and If the total number of the idle blocks is not less than the second critical value, do not perform the garbage collection operation, Wherein the step of determining whether any physical block belonging to the locked block meets the unlocking condition includes: If all the physical pages in the first physical block are marked as invalid, it is determined that the first physical block meets the unlocking condition; and If all the physical pages in the first physical block are not marked as invalid, it is determined that the first physical block does not meet the unlocking condition. The memory management method as described in claim 1, wherein the operation instruction indicates to delete or erase data belonging to a first logical address, and the first logical address is mapped to the first physical page. The memory management method as described in claim 1 further includes: Obtaining a configuration instruction from the host system; and Setting the first critical value according to the configuration instruction. The memory management method as described in claim 3, wherein the step of setting the first critical value according to the setting instruction includes: Providing quantity information related to the locked block to the host system so that the host system provides the setting instruction, wherein the quantity information reflects the total number of the locked blocks. The memory management method as described in claim 1, wherein the first threshold value is positively correlated to the total number of locked blocks. The memory management method as described in claim 1 further includes: If the total number of the idle blocks is not less than the first critical value, any physical block belonging to the locked block is not released as the idle block. A data storage system comprises: a host system; and a memory device coupled to the host system, wherein the host system is used to provide an operation instruction, and the memory device is used to: mark a first physical page in the memory device as invalid according to the operation instruction, and set a first physical block in the memory device containing the first physical page as a locked block; determine whether the total number of idle blocks in the memory device is less than a first critical value; if the total number of the idle blocks is less than the first critical value, determine whether any physical block belonging to the locked block meets the unlocking condition; If the first physical block belonging to the locked block meets the unlocking condition, the first physical block is released as the idle block; Determine whether the total number of the idle blocks in the memory device is less than a second critical value, wherein the second critical value is less than the first critical value; If the total number of the idle blocks is less than the second critical value, perform a garbage collection operation; and If the total number of the idle blocks is not less than the second critical value, do not perform the garbage collection operation, Wherein the operation of determining whether any physical block belonging to the locked block meets the unlocking condition includes: If all the physical pages in the first physical block are marked as invalid, it is determined that the first physical block meets the unlocking condition; and If all the physical pages in the first physical block are not marked as invalid, it is determined that the first physical block does not meet the unlocking condition. A data storage system as described in claim 7, wherein the operation instruction indicates to delete or erase data belonging to a first logical address, and the first logical address is mapped to the first physical page. A data storage system as described in claim 7, wherein the host system is further used to provide a setting instruction, and the memory device is further used to set the first critical value according to the setting instruction. A data storage system as described in claim 9, wherein the memory device is further used to provide quantity information related to the locked block to the host system, and the host system is further used to provide the setting instruction based on the quantity information, and the quantity information reflects the total number of the locked blocks. A data storage system as described in claim 7, wherein the first threshold value is positively correlated to the total number of locked blocks. The data storage system as described in claim 7, wherein the memory device is further used to: If the total number of the idle blocks is not less than the first critical value, any physical block belonging to the locked block is not released as the idle block.

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