TWI885697B - Burn-in test structure - Google Patents
Burn-in test structure Download PDFInfo
- Publication number
- TWI885697B TWI885697B TW113101407A TW113101407A TWI885697B TW I885697 B TWI885697 B TW I885697B TW 113101407 A TW113101407 A TW 113101407A TW 113101407 A TW113101407 A TW 113101407A TW I885697 B TWI885697 B TW I885697B
- Authority
- TW
- Taiwan
- Prior art keywords
- test structure
- conductive
- electronic carrier
- burn
- carrier
- Prior art date
Links
Images
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
本發明涉及一種半導體測試結構,尤指一種可改善電壓降的預燒測試結構。 The present invention relates to a semiconductor test structure, and in particular to a pre-burn test structure capable of improving voltage drop.
因應科技發展及產品需求,高功率晶片(例如AI/CPU晶片)的設計及製造日益複雜,其消耗功率也逐步上升。高功率晶片在出廠前皆必須進行高溫下的老化/預燒/崩應(Burn-in)測試,以確認其可靠度。這種測試主要採用預燒測試板(Burn-in Board,BIB),並於預燒測試板上裝設高功率晶片,由預燒測試板中的銅層傳遞電壓/電流至高功率晶片。在此測試過程中,由於高功率晶片需要供給低電壓/大電流(300A以上),銅層阻抗將隨著電流大小而會出現不等電壓降(IR Drop),將對測試造成影響。 In response to technological development and product demand, the design and manufacturing of high-power chips (such as AI/CPU chips) are becoming increasingly complex, and their power consumption is gradually increasing. High-power chips must undergo aging/pre-burning/breakdown (Burn-in) tests at high temperatures before leaving the factory to confirm their reliability. This test mainly uses a pre-burn test board (Burn-in Board, BIB), and installs a high-power chip on the pre-burn test board. The copper layer in the pre-burn test board transmits voltage/current to the high-power chip. During this test process, since high-power chips need to be supplied with low voltage/high current (more than 300A), the copper layer impedance will have different voltage drops (IR Drop) depending on the current size, which will affect the test.
因此,如何克服上述習知技術的種種問題,實已成目前亟欲解決的課題。 Therefore, how to overcome the above-mentioned problems of knowledge and technology has become an urgent issue to be solved.
鑑於上述習知技術之種種缺失,本發明提供一種預燒測試結構,包括:電子載板,具有相對之第一表面及第二表面;至少一測試單元,設於該電子載板的該第一表面上;至少一承載元件,設於該電子載板的該第二表面上;以及至少一導電元件,設於該承載元件內及該電子載板的該第二表面上,並鄰近該測試單元之一側。 In view of the various deficiencies of the above-mentioned prior art, the present invention provides a pre-burn test structure, comprising: an electronic carrier having a first surface and a second surface opposite to each other; at least one test unit disposed on the first surface of the electronic carrier; at least one supporting element disposed on the second surface of the electronic carrier; and at least one conductive element disposed in the supporting element and on the second surface of the electronic carrier, and adjacent to one side of the test unit.
如前述之預燒測試結構中,該導電元件包含本體及連接部,該本體沿一軸線延伸形成,並設於鄰近該測試單元之一側,該連接部沿該軸線自該本體的一端朝外延伸,並外露於該承載元件。 As in the aforementioned pre-burn test structure, the conductive element includes a body and a connecting portion. The body is formed by extending along an axis and is disposed on one side adjacent to the test unit. The connecting portion extends outward from one end of the body along the axis and is exposed to the supporting element.
如前述之預燒測試結構中,該導電元件更包含複數導電柱,該複數導電柱彼此相間隔地沿垂直該軸線的方向自該本體朝外延伸,並貫穿該電子載板而凸出於該第一表面,且鄰近該測試單元之一側。 As in the aforementioned pre-burn test structure, the conductive element further includes a plurality of conductive posts, which extend outward from the body in a direction perpendicular to the axis at intervals, penetrate the electronic carrier, protrude from the first surface, and are adjacent to one side of the test unit.
如前述之預燒測試結構中,該電子載板更具有位於該第一表面上的線路層,該複數導電柱電性連接該線路層。 As in the aforementioned pre-burn test structure, the electronic carrier further has a circuit layer located on the first surface, and the plurality of conductive posts are electrically connected to the circuit layer.
如前述之預燒測試結構中,該導電元件更包含絕緣層,該絕緣層包覆於該本體外側,且該複數導電柱及該連接部外露於該絕緣層。 As in the aforementioned pre-burn test structure, the conductive element further includes an insulating layer, the insulating layer is coated on the outer side of the body, and the plurality of conductive posts and the connecting portion are exposed on the insulating layer.
如前述之預燒測試結構中,該連接部用以連接系統電源或接地。 As in the aforementioned pre-burn test structure, the connection portion is used to connect the system power supply or ground.
如前述之預燒測試結構中,該承載元件具有沿該軸線延伸形成的凹槽,該導電元件設於該凹槽內。 As in the aforementioned pre-burn test structure, the supporting element has a groove extending along the axis, and the conductive element is disposed in the groove.
如前述之預燒測試結構中,該導電元件之材質為銅。 As mentioned above in the pre-burn test structure, the material of the conductive element is copper.
如前述之預燒測試結構中,該導電元件之數量為二個,分別鄰近該測試單元之相對二側。 As in the aforementioned pre-burn test structure, the number of the conductive elements is two, adjacent to two opposite sides of the test unit.
如前述之預燒測試結構中,該導電元件及該承載元件未對應位於該測試單元的正下方。 As in the aforementioned pre-burn test structure, the conductive element and the supporting element are not located directly below the test unit.
綜上所述,本發明預燒測試結構中以承載元件承載導電元件,使導電元件可設計成能夠便於大電流傳輸的規格,大電流不經由電子載板內的銅層長距離傳輸,故可有效解決先前技術中電壓降之問題,因而電子載板內的銅層厚度及層數亦可減少,可進一步降低電子載板的製作成本。再者,導電元件未對應位於測試單元的正下方,故不妨礙電子載板的散熱功能。 In summary, the pre-burn test structure of the present invention uses a carrier element to carry a conductive element, so that the conductive element can be designed to facilitate large current transmission. The large current does not pass through the copper layer in the electronic substrate for long-distance transmission, so it can effectively solve the problem of voltage drop in the previous technology. Therefore, the thickness and number of copper layers in the electronic substrate can also be reduced, which can further reduce the manufacturing cost of the electronic substrate. In addition, the conductive element is not located directly below the test unit, so it does not hinder the heat dissipation function of the electronic substrate.
1:預燒測試結構 1: Pre-burn test structure
11:電子載板 11: Electronic carrier
11a:第一表面 11a: First surface
11b:第二表面 11b: Second surface
111:線路層 111: Line layer
12:測試單元 12: Test unit
13:承載元件 13: Carrying components
131:凹槽 131: Groove
14:導電元件 14: Conductive element
141:本體 141:Entity
142:連接部 142:Connection part
143:導電柱 143:Conductive pillar
144:絕緣層 144: Insulation layer
X:軸線 X: axis
圖1為本發明預燒測試結構之前視示意圖。 Figure 1 is a schematic diagram of the pre-burning test structure of the present invention from the front view.
圖2為本發明預燒測試結構之側面示意圖。 Figure 2 is a side view of the pre-burning test structure of the present invention.
圖3為本發明預燒測試結構中導電元件之示意圖。 Figure 3 is a schematic diagram of the conductive element in the pre-burning test structure of the present invention.
圖4為本發明預燒測試結構之另一實施例之前視示意圖。 Figure 4 is a front view schematic diagram of another embodiment of the pre-burning test structure of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following is a specific and concrete example to illustrate the implementation of the present invention. People familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this manual.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結 構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」、「至少一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "above", "first", "second", "at least one" etc. used in this specification are only used to facilitate the description, and are not used to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships, without substantially changing the technical content, should also be regarded as the scope of implementation of the present invention.
請參閱圖1、圖2及圖3,本發明預燒測試結構1包括電子載板11、至少一測試單元12、至少一承載元件13及至少一導電元件14。
Please refer to Figures 1, 2 and 3. The
電子載板11具有相對之第一表面11a及第二表面11b。在本實施例中,電子載板11為預燒測試板(BIB)。
The
測試單元12設於電子載板11的第一表面11a上。在本實施例中,測試單元12為晶片插槽,用以裝設高功率晶片。
The
於一實施例中,測試單元12的數量可以是複數個,並以陣列方式設於電子載板11的第一表面11a上,以同時對複數個高功率晶片進行測試。
In one embodiment, the number of
承載元件13設於電子載板11的第二表面11b上。在本實施例中,承載元件13為托架,具有沿軸線X延伸形成的凹槽131,並以凹槽131面對第二表面11b的方向透過例如螺絲鎖固於電子載板11上,鎖固的位置並未對應位於測試單元12的正下方,而是鄰近測試單元12之一側。
The supporting
於一實施例中,承載元件13之數量可為二個以上,分別鄰近測試單元12之相對二側。若測試單元12為複數個並呈陣列形式時,承載
元件13可分別設於同一列(或同一行)測試單元12之相對二側,且皆未對應位於同一列(或同一行)測試單元12的正下方。
In one embodiment, the number of the supporting
導電元件14設於承載元件13內及電子載板11的第二表面11b上,並鄰近測試單元12的一側。
The
在本實施例中,導電元件14包含本體141、連接部142、複數導電柱143及絕緣層144。本體141概略呈長條狀(或電纜)並沿軸線X延伸形成,設於凹槽131內而鄰近測試單元12之一側。連接部142沿軸線X自本體141的一端朝外延伸,並外露於承載元件13,用以連接系統電源或接地。系統電源可例如為低電壓高電流的直流電,以供給至測試單元12。
In this embodiment, the
複數導電柱143彼此相間隔地沿垂直軸線X自本體141朝外延伸,並貫穿電子載板11的第二表面11b及第一表面11a,進而凸出於第一表面11a,且相間隔地鄰近測試單元12的一側。於一實施例中,導電柱143的數量可根據測試單元12的排版形式及功率來加以設計。
A plurality of
絕緣層144包覆於本體141外側,以與承載元件13絕緣。但絕緣層144未包覆複數導電柱143及連接部142,以令複數導電柱143及連接部142外露於絕緣層144及承載元件13。
The insulating
在本實施例中,導電元件14之材質為銅。
In this embodiment, the material of the
於一實施例中,導電元件14的數量可配合承載元件13的數量,例如前述承載元件13的數量為二個時,導電元件14的數量也是二個,此時導電元件14也是分別鄰近測試單元12的相對二側,且並未對應位於測試單元12的正下方。
In one embodiment, the number of
請參閱圖4,本發明預燒測試結構1中電子載板11可更具有線路層111,線路層111位於第一表面11a上,複數導電柱143電性連接線路層111。於一實施例中,複數導電柱143與線路層111之間可採焊接固定。
Please refer to FIG. 4 . The
綜上所述,本發明預燒測試結構中以承載元件承載導電元件,使導電元件可設計成能夠便於大電流傳輸的規格,大電流不經由電子載板內的銅層長距離傳輸,故可有效解決先前技術中電壓降之問題,因而電子載板內的銅層厚度及層數亦可減少,可進一步降低電子載板的製作成本。再者,導電元件未對應位於測試單元的正下方,故不妨礙電子載板的散熱功能。 In summary, the pre-burn test structure of the present invention uses a carrier element to carry a conductive element, so that the conductive element can be designed to facilitate large current transmission. The large current does not pass through the copper layer in the electronic substrate for long-distance transmission, so it can effectively solve the problem of voltage drop in the previous technology. Therefore, the thickness and number of copper layers in the electronic substrate can also be reduced, which can further reduce the manufacturing cost of the electronic substrate. In addition, the conductive element is not located directly below the test unit, so it does not hinder the heat dissipation function of the electronic substrate.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.
1:預燒測試結構 1: Pre-burn test structure
11:電子載板 11: Electronic carrier
11a:第一表面 11a: First surface
11b:第二表面 11b: Second surface
12:測試單元 12: Test unit
13:承載元件 13: Carrying components
131:凹槽 131: Groove
141:本體 141:Entity
142:連接部 142:Connection part
143:導電柱 143:Conductive pillar
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW113101407A TWI885697B (en) | 2024-01-12 | 2024-01-12 | Burn-in test structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW113101407A TWI885697B (en) | 2024-01-12 | 2024-01-12 | Burn-in test structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI885697B true TWI885697B (en) | 2025-06-01 |
| TW202528759A TW202528759A (en) | 2025-07-16 |
Family
ID=97225008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW113101407A TWI885697B (en) | 2024-01-12 | 2024-01-12 | Burn-in test structure |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI885697B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6072322A (en) * | 1997-12-30 | 2000-06-06 | Intel Corporation | Thermally enhanced test socket |
| JP3645095B2 (en) * | 1998-07-17 | 2005-05-11 | Hoya株式会社 | Burn-in board, bumped membrane ring and manufacturing method thereof |
| TW200710412A (en) * | 2005-04-27 | 2007-03-16 | Aehr Test Systems | Apparatus for testing electronic devices |
| US7199598B2 (en) * | 2003-11-27 | 2007-04-03 | Espec Corp. | Burn-in substrate for semiconductor devices |
| CN1957259A (en) * | 2004-04-27 | 2007-05-02 | Jsr株式会社 | Sheetlike probe, its manufacturing method and its application |
| US7271605B2 (en) * | 2005-02-15 | 2007-09-18 | Advantest Corporation | Burn-in apparatus |
| CN101625375A (en) * | 2008-03-07 | 2010-01-13 | 台湾积体电路制造股份有限公司 | Probe card and assembling method thereof |
| CN101971037A (en) * | 2008-03-14 | 2011-02-09 | 富士胶片株式会社 | probe card |
| CN110865292A (en) * | 2019-12-20 | 2020-03-06 | 无锡市新丝路测控技术有限公司 | Burn-in board |
-
2024
- 2024-01-12 TW TW113101407A patent/TWI885697B/en active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6072322A (en) * | 1997-12-30 | 2000-06-06 | Intel Corporation | Thermally enhanced test socket |
| JP3645095B2 (en) * | 1998-07-17 | 2005-05-11 | Hoya株式会社 | Burn-in board, bumped membrane ring and manufacturing method thereof |
| US7199598B2 (en) * | 2003-11-27 | 2007-04-03 | Espec Corp. | Burn-in substrate for semiconductor devices |
| CN1957259A (en) * | 2004-04-27 | 2007-05-02 | Jsr株式会社 | Sheetlike probe, its manufacturing method and its application |
| US7271605B2 (en) * | 2005-02-15 | 2007-09-18 | Advantest Corporation | Burn-in apparatus |
| TW200710412A (en) * | 2005-04-27 | 2007-03-16 | Aehr Test Systems | Apparatus for testing electronic devices |
| CN101625375A (en) * | 2008-03-07 | 2010-01-13 | 台湾积体电路制造股份有限公司 | Probe card and assembling method thereof |
| CN101971037A (en) * | 2008-03-14 | 2011-02-09 | 富士胶片株式会社 | probe card |
| CN110865292A (en) * | 2019-12-20 | 2020-03-06 | 无锡市新丝路测控技术有限公司 | Burn-in board |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202528759A (en) | 2025-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7872876B2 (en) | Multi-layered printed circuit board | |
| KR100252731B1 (en) | Semiconductor Devices and Packages for Semiconductor Devices | |
| US7928543B2 (en) | Tape wiring substrate and tape package using the same | |
| TW201944148A (en) | Display device | |
| US8022313B2 (en) | Circuit board with electromagnetic bandgap adjacent or overlapping differential signals | |
| TWI404938B (en) | Probe card | |
| US6225687B1 (en) | Chip package with degassing holes | |
| CN111653551A (en) | A BGA chip package structure with high anti-electromagnetic pulse interference capability | |
| CN113506518B (en) | Display panel and display device | |
| CN114980478A (en) | Flexible circuit board, preparation method of flexible circuit board and display device | |
| TWI885697B (en) | Burn-in test structure | |
| US7259336B2 (en) | Technique for improving power and ground flooding | |
| US7170361B1 (en) | Method and apparatus of interposing voltage reference traces between signal traces in semiconductor devices | |
| US11849608B2 (en) | Flexible display substrate and method for preparing the same, and display device | |
| TWI897355B (en) | Display panel, manufacturing method thereof, and display device | |
| CN101031995A (en) | Split thin film capacitor for multiple voltages | |
| WO2025016102A1 (en) | Array substrate and manufacturing method therefor, and display device | |
| JP2004158777A (en) | Printed board | |
| KR100350424B1 (en) | Semiconductor device | |
| JP2000223799A (en) | Wiring board and manufacturing method thereof | |
| CN221466575U (en) | Electronic device | |
| US20260011632A1 (en) | Substrate structure | |
| WO2025016103A9 (en) | Display panel and display apparatus | |
| US20230309233A1 (en) | Electronic device | |
| CN210609854U (en) | Structure for detecting temperature of peripheral environment of PCB |