TWI885279B - Methods, die bonders, and plasma treatment apparatuses for microelectronic component assembly and processing - Google Patents

Abstract

The disclosure relates to methods and apparatus for, in combination, treating dielectric material surfaces of singulated microelectronic components with an atmospheric plasma after retrieval from a carrier structure before placement on am atmospheric plasma treated dielectric material surface of another microelectronic component.

Description

Method, die bonder and plasma processing device for assembly and processing of microelectronic components

The present invention relates to plasma treatment of microelectronic components and their selective bonding and assembly. More specifically, the present invention relates to a method and apparatus for atmospheric plasma treatment of microelectronic components, wherein the atmospheric plasma treatment can be integrated with the hybrid bonding and assembly of microelectronic components.

As the performance of electronic devices and systems increases, there is an associated need to improve the performance of microelectronic components (e.g., semiconductor dies) of such devices and systems while maintaining or even reducing the form factor (e.g., length, width, and height) of a microelectronic component assembly. Such requirements are typically, but not exclusively, associated with mobile devices and high-performance systems. In order to maintain or reduce the footprint and height of an assembly of microelectronic components, three-dimensional (3D) assemblies of stacked components equipped with conductive so-called through-silicon vias (TSVs) for vertical electrical (e.g., signal, power, ground/bias) communication between stacked components have become more common.

As the thickness of the bonded components decreases, preformed dielectric materials can be used in the bond wires (i.e., the spaces between stacked components) to reduce the bond wire thickness while increasing bond wire uniformity. Such preformed dielectric materials include, for example, so-called non-conductive films (NCFs) and wafer-level underfills (WLUFs), which are often used interchangeably. While more effective in achieving thinner and more uniform bond wires, these dielectric materials still have a measurable thickness and therefore contribute significantly to the thickness of the stacked multi-component (i.e., 4, 8, 12, 16, etc.) assembly. Additionally, these assemblies traditionally employ solder capped conductive (i.e., copper) posts that are tightly mated to conductive (i.e., copper) terminal pads of adjacent components, or less commonly, employ conductive posts that are diffusion bonded directly to conductive terminal pads. In either instance, the presence of preformed dielectric material in the bond wires, alone or in combination with component warping, can promote open joints (i.e., open electrical connections) or, in the case of solder capped posts, stretched joints (insufficient solder between the surface of the post and the surface of the pad) or shorts between laterally adjacent conductive structures due to lateral solder leakage during reflow.

25℃)溫度下相互接合，其中組件之導電元件相互對準。根據一堆疊中之預期數目之組件之需要重複該程序。導電元件之鄰近表面之相互接觸可透過在其等接合期間吸引經活化氧化矽層來達成，且接觸之導電元件表面之擴散接合可藉由在約400℃或較低(例如，在約150℃至約300℃之一範圍內)之一 溫度下在一基底基板(例如，安裝至一載體晶圓之一未經單切半導體晶圓)上對數個組件堆疊進行一後續分批退火達約十分鐘至約六個小時或更久(取決於退火溫度)之一時段來實施。在環境溫度下進行混合接合及在相對低溫度下進行分批退火之優點包含將組件之間之接合線減少至近零厚度，以及將鄰近導電元件之間距按比例縮小至約1μm之能力。包含多個堆疊之薄微電子組件之微電子組件總成之非限制性實例包含半導體記憶體晶粒之總成，其等單獨或結合其他晶粒功能性(例如邏輯)包含所謂的高頻寬記憶體(HBMx)以及其他晶片至晶圓(C2W)及晶圓至晶圓(W2W)總成。 A further development in the interconnection of stacked microelectronic components includes so-called hybrid bonding, also known as direct bond interconnect (DBI), which uses in-situ formed dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride or extremely thin polymers, to interconnect the stacked microelectronic components. However, the use of such dielectric materials requires contamination-free planar dielectric surfaces for effective and uniform bonding of closely mating dielectric surfaces of the microelectronic components. In addition, instead of conductive pillars and pads protruding from the component surface, the ends of the conductive element surfaces, such as TSVs or conductive (e.g., copper) pads, can be substantially flush with the exposed oxide surface or slightly recessed from the exposed oxide surface. These conductive elements should also be contamination-free to implement robust diffusion bonding of mating conductive surfaces of aligned conductive elements. In a hybrid bonding process using silicon oxide (e.g., SiO ₂ ) as an example dielectric, the silicon oxide and conductive component surfaces of the components to be bonded are cleaned, the silicon oxide is activated using a plasma to increase hydrophilicity and reactivity, and the activated silicon oxide surfaces are placed together in an environment (e.g.,

The stack of components is bonded to each other at a temperature of about 25° C., wherein the conductive elements of the components are aligned with each other. The process is repeated as needed for the desired number of components in the stack. Contact of adjacent surfaces of the conductive elements can be achieved by attracting the activated silicon oxide layer during such bonding, and diffusion bonding of the contacting conductive element surfaces can be implemented by performing a subsequent batch annealing of several component stacks on a base substrate (e.g., an unsingulated semiconductor wafer mounted to a carrier wafer) at a temperature of about 400° C. or lower (e.g., in a range of about 150° C. to about 300° C.) for a period of about ten minutes to about six hours or longer (depending on the annealing temperature). Advantages of hybrid bonding at ambient temperature and batch annealing at relatively low temperatures include the ability to reduce bond wires between components to near zero thickness and to scale pitches of adjacent conductive elements down to about 1 μm. Non-limiting examples of microelectronic component assemblies comprising multiple stacked thin microelectronic components include assemblies of semiconductor memory dies, which alone or in combination with other die functionalities (e.g., logic) include so-called high bandwidth memory (HBMx), and other chip-to-wafer (C2W) and wafer-to-wafer (W2W) assemblies.

An embodiment of the present invention includes a method of forming a microelectronic component assembly, the method comprising: picking up a microelectronic component from a carrier structure; applying an atmospheric plasma to a dielectric material on a lower side of the microelectronic component; applying an atmospheric plasma to a dielectric material on an exposed upper surface of another microelectronic component; and placing the lower side of the microelectronic component in contact with a location on the exposed upper surface of the other microelectronic component to which the atmospheric plasma has been applied to form a hybrid bond between the dielectric materials.

Embodiments of the invention include an apparatus comprising: a support for a carrier structure of microelectronic components; a device for receiving individual microelectronic components from the carrier structure; and an atmospheric plasma discharge configured and having a nozzle positionable to treat an underside of each microelectronic component received by the device and then place the microelectronic component on an upper surface of another microelectronic component.

An embodiment of the present invention includes a die bonder comprising: a support member for a carrier structure of a microelectronic component; a bonding head having a bonding tip configured to capture a microelectronic component supported by the carrier structure; and an atmospheric plasma release member configured and having a nozzle positionable to perform plasma treatment on a surface of a microelectronic component captured by the bonding tip.

An embodiment of the present invention includes a method for processing a microelectronic component, the method comprising: extracting a microelectronic component from a carrier structure; treating an exposed surface of the extracted microelectronic component with an atmospheric plasma; and placing the exposed treated surface in contact with a surface of another microelectronic component.

100:Semiconductor grains

100’: Grain position

100t: Target semiconductor grain

102: Silicon oxide/silicon oxide surface

104: Arrow

106: Pickup arm

108: Pickup arm surface

110: Oriented Surface

112:Joint tip

114:Joint head

116: Engagement tip surface

118: Mixed joint

120: Contact element

122:Relative surface

124: Installation film

130: Nozzle

132: Plasma release part

132’: Plasma release part

134: Plasma

136: Lower side

138: Exposed surface

140: Base wafer

140’: Reconstructing the base wafer

140s: Wafer/single-cut wafer

142: First level

144: Upper surface

200: Removal and placement device

200’: Removal and placement device

202: Wafer loading area

204: Chamber

206: Arrow

208: Grain picking position

220: Pickup head

222: Pickup arm

C: Channel

D: Discontinuity

FIG. 1 is a schematic process flow diagram of a known process for picking up and bonding a semiconductor die for hybrid bonding with another semiconductor component; FIG. 1A is a side cross-sectional schematic diagram of an example hybrid bonding process flow diagram; FIG. 2 is a bottom view of a pick-up head of a pick-up arm showing a vacuum channel opening on a pick-up surface; FIG. 2A and FIG. 2B are micrographs of a portion of a semiconductor die surface, which show where the location of the vacuum channel opening damages the activated silicon oxide dielectric on a die surface; FIG. 3A to FIG. 3F schematically illustrate an example process flow diagram of dielectric material processing by atmospheric plasma according to an embodiment of the present invention; FIG. 4A schematically illustrates a process flow diagram of a semiconductor die surface according to an embodiment of the present invention; An apparatus according to an embodiment of the present invention is used to pick up a semiconductor die and treat a dielectric material surface of the die with an atmospheric plasma without inverting the die, and then place the treated dielectric material surface of the die on a treated dielectric surface of a non-singulated die position of a semiconductor wafer; and FIG. 4B schematically illustrates an apparatus according to an embodiment of the present invention, which is used to pick up a semiconductor die, invert the die, transfer the inverted die to a bonding head, treat a dielectric surface thereof with an atmospheric plasma and place the activated dielectric surface of the die on a plasma-treated dielectric surface of a non-singulated die position of a semiconductor wafer.

Priority claim

This application claims the benefit of U.S. Provisional Patent Application No. 63/229,769, filed on August 5, 2021, entitled "Method and Apparatus for Microelectronic Component Processing With Integrated Atmospheric Plasma Treatment," the disclosure of which is hereby incorporated herein by reference in its entirety.

Apparatus and methods for microelectronic component processing using atmospheric plasma processing to clean microelectronic component surfaces and, as a non-limiting example, activate dielectric materials for hybrid bonding of microelectronic components are described.

Conventionally, plasma processing for cleaning and activation of silicon oxide and ultrathin polymer dielectrics on microelectronic component surfaces prior to hybrid bonding has been performed in a vacuum environment (i.e., in a vacuum chamber). This requirement complicates the manufacturing process of hybrid bonded multi-component assemblies. Furthermore, throughput requirements require large-scale activation of the dielectric of singulated components of a bulk substrate (e.g., a semiconductor wafer) within a vacuum chamber, and removal of all components from the chamber before any component (e.g., a semiconductor die) can be picked up. Additionally, the use of a conventional pick and place device to pick up microelectronic components can immediately damage the previously activated dielectric surface due to contact with the surface of a pick head of a pick arm (sometimes also referred to as a "flipper") of the device. More specifically, the inventors have determined herein that vacuum drawn through vacuum channel openings on the surface of a pick arm used to pick up a target component substantially deactivates those portions of the silicon oxide. As a result, each microelectronic component that is picked up and stacked on another component after activation of the silicon oxide inherently exhibits a discontinuous (i.e., perforated) activated oxide surface, which causes the component to delaminate along the dielectric joint, and the conductive elements of the component cannot establish a robust diffusion bond, resulting in an open circuit. The inventors also believe herein that the activation of the silicon oxide can be degraded by contact with the pick arm surface alone.

Figures 1 and 1A of the drawings schematically illustrate a known pick-and-place process for a microelectronic component (e.g., semiconductor die) employed in the context of hybrid bonding. As shown in Figure 1, after a vacuum plasma treatment is performed to activate silicon oxide 102 on a back-end-of-line (BEOL) structure (Figure 1A) on a surface of a singulated semiconductor die 100 (i.e., to increase the hydrophilicity of silicon oxide 102), the semiconductor die 100 is ejected from a carrier structure (i.e., a mounting tape supported on a film frame) as shown by arrow 104 and picked up by a pick arm 106 of a pick-up device using a vacuum applied to the activated silicon oxide surface 102 through channel C in an opening of the pick arm 106 (Figure 2) onto a pick arm surface 108. Next, the pick arm 106 inverts the semiconductor die 100 to orient the surface 110 of the semiconductor die 100 upward and is transferred to the bond tip 112 of the bond head 114 by releasing the pick arm vacuum (and optionally, a reversal to a positive pressure) and applying a vacuum to the bond tip surface 116 through the opening of channel C (see FIG. 2 ). As shown in FIG1A , the bonding head 114 then moves the semiconductor die 100 with the activated silicon oxide 102 facing downward to a location of a microelectronic component (e.g., a substrate wafer with unsingulated semiconductor die locations or previously placed semiconductor die) with the activated silicon oxide 102 facing upward, and places the semiconductor die 100 on the activated silicon oxide 102 of a target die 100 or on the die location 100 ′ in the case of a substrate wafer ( FIG1 and FIG1A ). In the example of SiO ₂ bonding, plasma activation reduces the thermal requirements for bond formation by creating a high density of surface hydroxyls that form a strong covalent bond when the two activated SiO ₂ surfaces are brought into contact. In theory, contacting the activated silicon oxide 102 should form a strong hybrid joint 118 at ambient temperature and pull the opposing surfaces 122 of the aligned and slightly recessed (e.g., recessed by about 5 to about 25 nm) conductive (e.g., copper) contact elements 120 of the assembly into contact, after which a metallurgical bond between the aligned contact elements 120 is implemented as previously noted herein by performing a subsequent batch anneal at a temperature of about 400° C. or lower (e.g., about 150° C. to about 300° C.) for a period of about 10 minutes to about six hours or longer (depending on the annealing temperature and metal conditions) to expand and diffuse the bonded contact elements and enhance the dielectric bond strength.

However, as noted above and as shown in FIGS. 2A and 2B , the vacuum channels C, and specifically the vacuum drawn therethrough, deactivate the activated silicon oxide 102 exposed at the channel opening locations, thereby compromising the strength and continuity of the hybrid bond 118 ( FIGS. 1 and 1A ), resulting in potential delamination of the microelectronic assembly due to insufficient contact due to the lack of adjacent bonding of the activated silicon oxide 102 pulling the opposing surfaces 122 of the conductive contact elements 120 towards each other and potential open circuits between aligned conductive contact elements 120 . FIGS. 2A and 2B illustrate discontinuities D of such compromised activated silicon oxide 102 .

The following description provides specific details such as size, shape, material composition, and orientation to provide a detailed description of an embodiment of the present invention. However, those skilled in the art should understand and appreciate that embodiments of the present invention may be practiced without employing such specific details, as embodiments of the present invention may be practiced in conjunction with known manufacturing techniques employed in the industry. In addition, the description provided below may not form a complete process flow for hybrid bonding, an apparatus for implementing hybrid bonding, or a hybrid bonded microelectronic component assembly according to the present invention. Only those process actions and structures required to understand embodiments of the present invention are described in detail below. Additional actions to form a complete microelectronic component assembly described herein may be performed by known manufacturing processes.

The figures presented herein are for illustration purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Variations in the shapes depicted in the figures due to, for example, manufacturing techniques and/or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or regions depicted, but rather include shape deviations due to, for example, manufacturing. For example, an area depicted or described as a square may have roughness and/or nonlinear features, and an area depicted or described as a circle may include some roughness and/or linear features. In addition, sharp angles between depicted surfaces may be rounded, and vice versa. Therefore, the areas depicted in the figures are schematic, and their shapes are not intended to depict the exact shape of the areas and do not limit the scope of the patent application scope of the present invention. The drawings are not necessarily drawn to scale.

In the description and for convenience, the same or similar reference element symbols may be used to identify common features and elements between the various figure numbers.

As mentioned above, silicon oxide, nitride, oxynitride and carbonitride can be used as dielectric materials for hybrid bonding as well as ultra-thin polymers, which can also be cleaned, activated and bonded. Such polymers can include (without limitation) benzocyclobutene (BCB) polymers, polyimide (PI) or polybenzoxazole (PBO).

Referring now to Figures 3A to 3F of the drawings, an example process flow for cleaning and activating dielectric materials by atmospheric plasma treatment according to an embodiment of the present invention is illustrated. It should be noted at the outset that the entire process flow illustrated can be implemented under environmental conditions in a clean room environment (e.g., Class 10), including plasma treatment for cleaning semiconductor die surfaces (e.g., conductive element surfaces) and activating dielectric materials (e.g., silicon oxide) on the die surfaces prior to hybrid bonding. Thus, unlike the known technique of simultaneously treating a batch (i.e., wafer) of singulated semiconductor die in a vacuum chamber with plasma and then transferring from the chamber to a position in a handling device for picking up the singulated die and transferring to a target location, embodiments of the present invention are performed at the handling location using, as examples, an ambient air, _N2 , _O2 , Ar, _H2 /Ar, or mixed _N2 : _O2 plasma treatment in atmosphere. Suitable atmospheric plasma treatment equipment is commercially available from Surfx Technologies of Redondo Beach, LL, California. Other suppliers of atmospheric plasma apparatus that may be used to implement embodiments of the present invention include Enercon Industries Corporation of Menomonee Falls, Wisconsin; Theirry Corporation of Royal Oak, Michigan; Ahlbrandt Systems GmbH of Lauterbach, Germany; and Hennifer Plasma of Runcorn, Washington.

Referring now to FIG. 3A , a group (i.e., wafer batch) of singulated semiconductor dies 100 (only some dies are shown for clarity) are positioned in a spaced relationship on a mounting film 124 supported on a film frame (not shown). The bonding tip 112 of the bonding head 114 picks up a target semiconductor die 100t ejected from the mounting film 124.

As shown in FIG. 3B , the bonding head 114 then moves the target semiconductor die 100t to a position on the upward-facing nozzle 130 of a plasma discharger 132 (this term includes, as an example, a torch, a sprayer, or a fluorescent plasma device), which generates a plasma 134 to clean the lower side 136 of the target semiconductor die 100t and activate the dielectric material on the lower side 136 to form activated silicon oxide 102.

3C illustrates a plasma discharge 132′ in which the nozzle 130 is reversed to generate plasma to clean an exposed upper surface 138 of another microelectronic component (e.g., a base wafer 140 having unsingulated semiconductor die sites 100′, a reconstructed base wafer 140′ having singulated semiconductor die 100) and activate a dielectric material (e.g., silicon oxide) on the exposed surface 138 to form an activated dielectric material 102. It is noted that the plasma discharge 132′ may be the same or a different plasma discharge as the plasma discharge 132, and since the plasma processing is performed at the placement device, it may be desirable to use the same plasma discharge 132 configured to translate and rotate about a horizontal axis to reverse and process the exposed surface 138. Additionally, it is contemplated that the entire upper surface 138 of a base wafer 140 or all singulated semiconductor dies 100 of a reconstructed base wafer 140' may be processed simultaneously or prior to stacking target semiconductor dies 100t to facilitate throughput. Alternatively, only one die site 100' or die 100 may be processed at a time. In some embodiments, a plasma discharge 132' may employ a nozzle configured to produce a linear plasma discharge, thereby allowing multiple die sites 100' to be processed simultaneously. Similarly, when semiconductor die 100 is stacked to form a plurality of die stacks each including a plurality of (e.g., 4, 8, 12, 16, 32) die, a whole level of singulated and stacked target semiconductor die 100t can have its top surface cleaned and the dielectric material activated substantially simultaneously, and then a subsequent layer of the die stack target semiconductor die 100t is placed.

3D depicts the bond head 114 placing a target semiconductor die 100t having an activated dielectric material 102 on the bottom side 136 (FIG. 3B) onto a semiconductor die site 100' of a base wafer 140 or onto the activated dielectric material 102 facing upward of a singulated semiconductor die 100 of a reconstructed base wafer 140' to form a hybrid bond. It is noteworthy that the pressure (i.e., downward force) applied by the bond head can be fine-tuned to perform die placement while maintaining alignment accuracy between the stacked dies, and no heat (which can reduce alignment accuracy) is applied to the target semiconductor die 100t by the bond tip 112 during and after placement. FIG. 3E depicts an assembly of a portion of an entire first layer 142 of a target semiconductor die 100t after being placed on a base wafer 140 or a reconstructed base wafer 140' and hybrid bonded to the base wafer 140 or the reconstructed base wafer 140'. Next, FIG. 3F shows a plasma release 132' used to clean an exposed upper surface 144 of the first layer 142 of the target semiconductor die 100t and activate the dielectric material 102 on the upper surface 144 to provide activated dielectric material 102 on the upper surface to place and hybrid bond another layer of the target semiconductor die 100t having activated dielectric material on its lower side 136.

An embodiment of the present invention includes a method of forming a microelectronic component assembly, the method comprising: picking up a microelectronic component from a carrier structure; applying an atmospheric plasma to a dielectric material on a lower side of the microelectronic component; applying an atmospheric plasma to a dielectric material on an exposed upper surface of another microelectronic component; and placing the lower side of the microelectronic component in contact with a location on the exposed upper surface of the other microelectronic component to which the atmospheric plasma has been applied to form a hybrid bond between the dielectric materials.

FIG4A is a schematic illustration of an example embodiment of an apparatus suitable for implementing methods according to the present invention. The handling apparatus 200 includes a support in the form of a wafer loading area 202, including one or more singulated wafers 140s of a plurality of singulated semiconductor dies 100 supported on and adhered to a carrier structure in the form of a mounting film 124 and loaded into a chamber 204, and transferred from the support to a die pick-up position 208 as shown by arrow 206, wherein the singulated semiconductor dies 100 are ejected at 210, as is known in the art. It is also contemplated that the singulated wafers 140s may be singulated on a carrier structure in the form of a carrier wafer (e.g., glass, silicon) and the singulated semiconductor dies may be picked up from the carrier wafer. However, instead of using a known pick-up arm as described with respect to FIG1 , as shown at the right-hand side of FIG4A , a bond head 114 is used to pick up each semiconductor die 100 in coordination with the ejection of the self-mounting film 124. Next, the bond head 114 holding the semiconductor die 100 moves over and aligns with the plasma release 132 having the nozzle 130 facing upward, at which time plasma 134 is generated to clean the lower side 136 of the semiconductor die 100 and form activated silicon oxide 102 on the lower side 136 (see FIG3B ). 4A , the plasma discharge 132 may be reversed and may generate plasma 134 to clean one or more die sites 100′ of the base wafer 140 to clean the exposed upper surface and activate the dielectric material 102 thereon, either before or after applying plasma 134 to the semiconductor die 100. For such an embodiment, the bond head 114 and plasma discharge 132 may be mounted to a common carrier for translation in the X, Y, and Z directions, and in the case of the plasma discharge 132, for rotation about a horizontal axis to alternately orient the nozzle 130 upward and downward. Alternatively, a different plasma discharge member 132' having a nozzle 130 facing downward can be used to process one or more target semiconductor die sites 100' on the base wafer 140 simultaneously with the processing of a semiconductor die 100 held by the bond head 114. In either example, after plasma treatment of the semiconductor die 100 held by the bonding head 114 and plasma treatment of a target semiconductor die site 100' of the die on the base wafer 140, the bonding head 114 places the semiconductor die 100 on a target semiconductor die site 100', in response to which a hybrid bonding is performed between the activated dielectric material 102 of the semiconductor die 100 and the activated dielectric material 102 of the target semiconductor die site 100', as previously described, followed by a relatively low temperature (e.g., between about 150°C and about 300°C, such as about 250°C) batch annealing to perform permanent diffusion bonding between opposing surfaces of conductive contact elements of adjacent components.

It should be noted that the above-described one-pick-and-place operation method without the need to invert a picked semiconductor die before transfer from a pick arm to a bond head allows stacking components using a different assembly technology for hybrid bonding. As shown in FIG. 1A , microelectronic components and specifically semiconductor dies fabricated for hybrid bonding lack conventional conductive elements (e.g., solder bumps, solder-capped copper pillars, copper pillars) protruding from an active surface. Instead, conductive (e.g., copper) contact elements having exposed outer surfaces that are flush with or recessed from dielectric material on the component surface are employed. Thus, a base wafer configured for hybrid bonding and having an active surface facing upward and without TSVs can have multiple stacks of semiconductor dies stacked on the base wafer with the active surface facing upward and TSVs to form a multi-die assembly with the topmost die in each stack to be filled with discrete conductive elements (e.g., solder bumps, solder capped copper pillars, copper pillars) for connection to a higher level package after encapsulating the die stack with a dielectric molding compound between the stacks and before singulating the stacks. In a more known method, while eliminating the use of a pick arm, an array of singulated semiconductor die with active surfaces facing upward on an initial mounting film may have another mounting film disposed over the array and adhered to the other mounting film, after which the initial mounting film's adhesion may be released (e.g., by extreme ultraviolet (UV)) exposure, after which the other mounting film with the die adhered may be reversed to be ejected from the other mounting film as described above and picked up by a bond head to be placed on a base wafer in a known orientation with a known active surface facing downward. As another method, a carrier wafer may be positioned over the array of semiconductor die, the die may adhere to the carrier wafer and released from the mounting film, and then the carrier wafer may be reversed. The semiconductor die can then be released from the carrier wafer for pick-up by directed exposure to a beam of electromagnetic radiation (either to infrared to heat a heat-release adhesive or to ultraviolet to degrade a UV-sensitive adhesive).

FIG4B is a schematic illustration of another example embodiment of an apparatus suitable for implementing methods according to the present invention. The placement apparatus 200′ includes a wafer loading area 202, and a singulated wafer 140s including a plurality of singulated semiconductor dies 100 supported on and adhered to a carrier structure in the form of a mounting film 124 is presented from a wafer loading area 202 for subsequent ejection of the singulated semiconductor dies 100 for pickup by a pick head 220 of a pick arm 222. It is also contemplated that the singulated wafer 140s may be singulated on a carrier structure in the form of a carrier wafer (e.g., glass, silicon) and the singulated microelectronic components may be picked up from the carrier wafer. Next, the pick arm 222 inverts the semiconductor die 100 and transfers it to the bond head 114 with a known active surface oriented downward. The semiconductor die 100 is then moved by the bond head 114 over and aligned with the plasma discharge member 132 having the nozzle 130 facing upward, at which time plasma 134 is generated to clean the lower side 136 of the semiconductor die 100 and form the activated dielectric material 102 on the lower side 136. 4B , the plasma discharge 132 may be reversed and may generate plasma 134 to clean one or more die sites 100′ of the base wafer 140 to clean the exposed upper surface 138 and activate the dielectric material 102 thereon, either before or after applying the plasma 134 to the semiconductor die 100. For such an embodiment, the bond head 114 and the plasma discharge 132 may be mounted to a common carrier for translation in the X, Y, and Z directions, and in the case of the plasma discharge 132, for rotation about a horizontal axis to alternately orient the nozzle 130 upward and downward. Alternatively, a different plasma discharge member 132' having a nozzle 130 facing downward can be used to process one or more target semiconductor die sites 100' on the base wafer 140 simultaneously with the processing of a semiconductor die 100 held by the bond head 114. In any of the above examples, after plasma treatment of the semiconductor die 100 held by the bonding head 114 and plasma treatment of one of the target semiconductor die locations 100' of the die on the base wafer 140, the bonding head 114 places the semiconductor die 100 on a target semiconductor die location 100', in response to which a hybrid bonding is performed between the activated dielectric material 102 of the semiconductor die 100 and the activated dielectric material 102 of the target semiconductor die location 100', as previously described, followed by a relatively low temperature batch annealing to perform permanent diffusion bonding between opposing surfaces of conductive contact elements of adjacent components.

Embodiments of the invention include an apparatus comprising: a support for a carrier structure of microelectronic components; a device for receiving individual microelectronic components from the carrier structure; and an atmospheric plasma discharge configured and having a nozzle positionable to treat an underside of each microelectronic component received by the device and then place the microelectronic component on an upper surface of another microelectronic component.

Embodiments of the present invention include a die bonder comprising: a support member for a carrier structure of a microelectronic component; a bonding head having a bonding tip configured to capture a microelectronic component supported by the carrier structure; and an atmospheric plasma release member configured and having a nozzle positionable to perform plasma treatment on a surface of a microelectronic component captured by the bonding tip.

An embodiment of the present invention includes a method for processing a microelectronic component, the method comprising: extracting a microelectronic component from a carrier structure; treating an exposed surface of the extracted microelectronic component with an atmospheric plasma; and placing the exposed treated surface in contact with a surface of another microelectronic component.

Those skilled in the art will appreciate that implementation of embodiments of the present invention enhances the integrity and repeatability of hybrid bonding processes while eliminating the need for dielectric plasma activation in a vacuum environment. Pickup, cleaning, dielectric activation, and stacking of components (e.g., semiconductor die) may be performed with a single integrated device without compromising throughput. In some embodiments that eliminate the use of a pickup device, throughput may be increased.

As used herein, the terms "include", "comprising", "containing", "characterized by", and their grammatical equivalents are inclusive or open terms that do not exclude additional, unlisted elements or method actions, and also include the more restrictive terms "consisting of" and "consisting essentially of", and their grammatical equivalents. As used herein, the term "may" with respect to a material, structure, feature, or method action indicates that it is contemplated for use in practicing an embodiment of the invention, and such term is used in preference to the more restrictive term "is" to avoid any implication that other compatible materials, structures, features, and methods that may be used in combination therewith should or must be excluded.

As used herein, the terms "longitudinal", "vertical", "transverse" and "horizontal" refer to a principal plane of a substrate (e.g., substrate material, substrate structure, substrate configuration, etc.) in or on which one or more structures and/or features are formed and are not necessarily defined by the earth's gravitational field. A "transverse" or "horizontal" direction is a direction substantially parallel to the principal plane of the substrate, and a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the principal plane of the substrate. The principal plane of a substrate is defined by a surface of the substrate having an area relatively larger than other surfaces of the substrate.

As used herein, for ease of description, spatially relative terms (such as "below," "beneath," "lower," "bottom," "above," "upper," "top," "front," "back," "left," "right," and the like) may be used to describe the relationship of one element or feature to another element or feature, as depicted in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the figures. For example, if the material in the figures were reversed, elements described as "below" or "above" or "on" or "on top" of other elements or features would be oriented "below" or "beneath" or "below" or "on the bottom" of the other elements or features. Thus, one skilled in the art will appreciate that the term "above" can encompass both above and below orientations, depending on the context in which the term is used. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the singular forms "a/an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, the terms "configured" and "configuration" refer to a size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates the operation of the at least one structure and at least one device in a predetermined manner.

Any reference to an element herein using a designation such as "first," "second," etc. does not limit the number or order of those elements unless such limitation is expressly stated. Rather, such designations may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, a reference to a first and a second element does not mean that only two elements may be used therein, or that the first element must precede the second element in some manner. Additionally, unless otherwise stated, a set of elements may include one or more elements.

As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the degree to which the given parameter, property, or condition is satisfied within a certain degree of variation (such as within acceptable manufacturing tolerances) as understood by those skilled in the art. As an example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied by at least 90.0%, by at least 95.0%, by at least 99.0%, or even by at least 99.9%.

As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes a numerical value and the degree of variation relative to the numerical value within an acceptable tolerance for a particular parameter as understood by those skilled in the art. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values within a range of 90.0% to 110.0% of the numerical value, such as within a range of 95.0% to 105.0% of the numerical value, within a range of 97.5% to 102.5% of the numerical value, within a range of 99.0% to 101.0% of the numerical value, within a range of 99.5% to 100.5% of the numerical value, or within a range of 99.9% to 100.1% of the numerical value.

As used herein, the terms "layer" and "film" mean and include a layer, sheet or coating of material residing on a structure, which layer or coating may be continuous or discontinuous between portions of the material, and which may be conformal or non-conformal unless otherwise indicated.

As used herein, the term "substrate" means and includes a base material or structure on which additional materials are formed. The substrate may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode, or a semiconductor substrate on which one or more materials, layers, structures or regions are formed. The materials on the semiconductor substrate may include (but are not limited to) semiconductor materials, insulating materials, conductive materials, etc. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates (such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates), epitaxial silicon layers on a base semiconductor foundation, and other semiconductor or optoelectronic materials (such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide). The substrate may be doped or undoped.

As used herein, the term "may" with respect to a material, structure, feature, or method action indicates that it is contemplated for use in practicing an embodiment of the invention, and such term is used in preference to the more restrictive term "are" to avoid any implication that other compatible materials, structures, features, and methods that may be used in combination therewith should or must be excluded.

As used herein, the term "microelectronic component" means and includes, by way of non-limiting example, semiconductor dies, dies that exhibit functionality through non-semiconducting activity, micro-electromechanical systems (MEM) devices, substrates including multiple dies of known wafers and other bulk substrates and portions of wafers as described above, and substrates containing more than one die location.

As used herein, in connection with contacting one or more surfaces of a microelectronic component with atmospheric plasma, the term "treatment" includes surface cleaning, modification of surface properties (e.g., increasing reactivity, hydrophilicity, adhesive tendency), or both, as dictated by the material properties of a treated surface.

Although certain illustrative embodiments have been described in conjunction with the figures, those skilled in the art should recognize and understand that the embodiments covered by the present invention are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications may be made to the embodiments described herein without departing from the scope of the embodiments covered by the present invention (such as the scope of the attached invention application, including legal equivalents). In addition, features from one disclosed embodiment may be combined with features from another disclosed embodiment while still being covered within the scope of the present invention.

100t: Target semiconductor grain

102: Silicon oxide/silicon oxide surface

112:Joint tip

114:Joint head

130: Nozzle

132: Plasma release part

134: Plasma

136: Lower side

Claims (33)

A method for forming a microelectronic component assembly includes: picking up a microelectronic component from a carrier structure; The invention relates to a method for applying an atmospheric plasma to a dielectric material on a lower side of a microelectronic component by applying an atmospheric plasma to the dielectric material on a lower side of the microelectronic component, wherein the atmospheric plasma release is mounted to a bracket and configured to translate in the X, Y and Z directions and the atmospheric plasma release is configured to rotate about a horizontal axis thereof; applying the atmospheric plasma or another atmospheric plasma to the dielectric material on an exposed upper surface of another microelectronic component; and placing the lower side of the microelectronic component in contact with a location on the exposed upper surface of the other microelectronic component to which the atmospheric plasma or the another atmospheric plasma has been applied to form a hybrid bond between the dielectric materials. The method of claim 1, wherein picking up the microelectronic component from the carrier structure includes picking up the microelectronic component from a plurality of microelectronic components supported on a mounting film. The method of claim 2, wherein picking up the microelectronic component from the plurality of microelectronic components includes ejecting the microelectronic component from the mounting film and substantially simultaneously receiving the microelectronic component with a pick-up head of a pick-up arm, the method further including: before applying the atmospheric plasma to activate the dielectric material on the lower side of the microelectronic component: inverting the microelectronic component with the pick-up arm; and transferring the inverted microelectronic component to a bonding tip of a bonding head. The method of claim 2, wherein picking up the microelectronic component from the plurality of microelectronic components includes ejecting the microelectronic component from the mounting film and substantially simultaneously receiving the microelectronic component with a bonding tip of a bonding head. A method as in any one of claims 1 to 4, wherein applying the atmospheric plasma or the other atmospheric plasma to the dielectric material on the exposed upper surface of the other microelectronic component comprises applying the atmospheric plasma or the other atmospheric plasma to at least a portion of a base substrate including a plurality of unsingulated microelectronic component locations. The method of claim 5, wherein applying the atmospheric plasma or the other atmospheric plasma to at least the portion of the base substrate including the plurality of unsingulated microelectronic component locations comprises applying the atmospheric plasma or the other atmospheric plasma to at least the location on the other microelectronic component, the location on the other microelectronic component being configured as a separate unsingulated microelectronic component location. The method of claim 6, wherein applying the atmospheric plasma or the other atmospheric plasma to at least the portion of the base substrate containing the plurality of unsingulated microelectronic component locations comprises applying the atmospheric plasma or the other atmospheric plasma to substantially all of the exposed upper surface. The method of claim 6, further comprising sequentially picking up a plurality of additional microelectronic components from the carrier structure, applying the atmospheric plasma to a lower side of each additional microelectronic component, and then placing the lower side of an additional microelectronic component in contact with one of the individual non-singulated microelectronic component locations on the exposed upper surface of the other microelectronic component to which the atmospheric plasma or the other atmospheric plasma has been applied to form the hybrid bond between the activated dielectric materials. The method of claim 8, further comprising repeating the process of claim 8 until a predetermined number of individual unsingulated microelectronic component locations are each contacted by one of the additional microelectronic components. A method as claimed in any one of claims 1 to 4, wherein applying the atmospheric plasma or the other atmospheric plasma to the dielectric material on the exposed upper surface of the other microelectronic component is performed shortly before or immediately after applying the atmospheric plasma to the dielectric material on the lower side of the microelectronic component. The method of any one of claims 1 to 4, further comprising heating the assembly to a temperature of about 400°C or less to cause diffusion bonding of the mutually aligned conductive contact elements of the microelectronic component and the other microelectronic component. The method of claim 11, wherein heating the assembly to a temperature of about 400°C or less comprises heating the assembly to a temperature in a range of about 150°C to about 300°C over a period of about ten minutes to about six hours. A method as claimed in any one of claims 1 to 4, wherein applying the atmospheric plasma to the dielectric material on the lower side of the microelectronic component and applying the atmospheric plasma or the other atmospheric plasma to the dielectric material on the exposed upper surface of the other microelectronic component are performed using the same atmospheric plasma release member. A plasma treatment apparatus includes: a support for a carrier structure of a plurality of microelectronic components; a device for receiving individual microelectronic components from the carrier structure; and an atmospheric plasma discharge configured and having a nozzle positionable to perform plasma treatment on the underside of the individual microelectronic components received by the device for receiving the individual microelectronic components. The nozzle can be further positioned to perform plasma treatment on the exposed upper surface of another microelectronic component and then place one of the individual microelectronic components on the exposed upper surface of one of the other microelectronic components, wherein the atmospheric plasma release is mounted to a bracket and configured to translate in the X, Y and Z directions and the atmospheric plasma release is configured to rotate about one of its horizontal axes. A plasma processing apparatus as claimed in claim 14, wherein the device for receiving the individual microelectronic components is configured as a bonding head having a bonding tip for contacting one of the individual microelectronic components, the bonding head being positionable to place the one of the individual microelectronic components received by the bonding tip on the atmospheric plasma release and to transfer and place the received microelectronic component on one of the individual microelectronic components. A plasma processing device as claimed in claim 14, wherein the device for receiving the individual microelectronic components is configured to have a pick-up arm for contacting a pick-up head with one of the individual microelectronic components and operable to reverse the one of the individual microelectronic components carried by the pick-up head, and the plasma processing device further includes a bonding head having a bonding tip operable to receive the one of the individual microelectronic components from the pick-up head, the bonding head being positionable to place the one of the individual microelectronic components received by the bonding tip on the atmospheric plasma release and to transfer and place the received one of the individual microelectronic components on one of the individual microelectronic components. A plasma treatment device as claimed in any one of claims 14 to 16, further comprising a platform configured to support a plurality of singulated or unsingulated microelectronic components, the atmospheric plasma discharge nozzle being positionable to perform plasma treatment on the exposed upper surfaces of the singulated or unsingulated microelectronic components, the plasma treatment device further comprising a device for placing each microelectronic component after the lower side thereof has been treated on one of the singulated or unsingulated microelectronic components after the upper surface thereof has been treated. The plasma processing apparatus of claim 17, wherein the device for receiving the individual microelectronic components also includes the device for placing each received individual microelectronic component on one of the singulated or non-singulated microelectronic components. A plasma treatment device as claimed in any one of claims 14 to 16, further comprising a platform configured to support a plurality of singulated or unsingulated microelectronic components, and further comprising another atmospheric plasma discharge member having another nozzle, the other nozzle being positionable to perform plasma treatment on the exposed upper surfaces of the singulated or unsingulated microelectronic components on the platform, the plasma treatment device further comprising a device for placing each microelectronic component after the lower side thereof has been treated on a singulated or unsingulated microelectronic component after the upper surface thereof has been plasma treated. The plasma processing apparatus of claim 19, wherein the device for receiving the individual microelectronic components also includes the device for placing each received microelectronic component on one of the singulated or non-singulated microelectronic components. A plasma processing device as claimed in any one of claims 14 to 16, wherein the carrier structure comprises a mounting membrane supported on a membrane frame. The plasma processing device of claim 21 further comprises an ejection device configured to eject individual microelectronic components upward from the mounting film toward the device for receiving the individual microelectronic components from the mounting film. A plasma processing device as claimed in any one of claims 14 to 16, wherein the carrier structure comprises a carrier wafer. A die bonder includes: a support member for a carrier structure of a plurality of microelectronic components; a bonding head having a bonding tip mounted to a common bracket and configured to translate in the X, Y and Z directions, the bonding tip being configured to capture a microelectronic component supported by the carrier structure; and an atmospheric plasma release member configured and having a nozzle that can be positioned to perform plasma treatment on a surface of the microelectronic component captured by the bonding tip, wherein the atmospheric plasma release member is mounted to the common bracket and configured to translate in the X, Y and Z directions and the atmospheric plasma release member is configured to rotate about a horizontal axis thereof. A die bonder as claimed in claim 24, wherein the bonding head is positionable to place the microelectronic component captured by the bonding tip onto the atmospheric plasma release and to transfer and place the captured microelectronic component onto another microelectronic component. A die bonder as claimed in claim 24 or 25, further comprising a platform configured to support a plurality of singulated or non-singulated microelectronic components, the atmospheric plasma discharge nozzle being positionable to perform plasma treatment on exposed upper surfaces of the singulated or non-singulated microelectronic components. A die bonder as claimed in claim 26, wherein the bonding head is configured to place the captured microelectronic component after plasma treatment onto one of the plasma treated singulated or non-singulated microelectronic components. A die bonder as claimed in claim 26, further comprising another atmospheric plasma discharge member having another nozzle, the other nozzle being positionable to process the exposed top surfaces of the singulated or non-singulated microelectronic components. A die bonder as claimed in claim 28, wherein the bonding head is configured to place each captured microelectronic component after plasma treatment onto one of the plasma treated singulated or non-singulated microelectronic components. A method for processing a microelectronic component, the method comprising: extracting a microelectronic component from a carrier structure; treating an exposed surface of the extracted microelectronic component with an atmospheric plasma by an atmospheric plasma release member, wherein the atmospheric plasma release member is mounted to a bracket and configured to translate in the X, Y and Z directions and the atmospheric plasma release member is configured to rotate about a horizontal axis thereof; repositioning the atmospheric plasma release member adjacent to another exposed surface of another microelectronic component and treating the other exposed surface of the other microelectronic component with the atmospheric plasma; and placing the exposed treated surface in contact with the other exposed surface of the other microelectronic component. The method of claim 30, wherein treating the exposed surface of the captured microelectronic component includes cleaning the exposed surface. The method of claim 30 or 31, wherein processing the exposed surface of the captured microelectronic component comprises processing a silicon-based dielectric material or a polymer dielectric material. The method of claim 32, wherein processing the silicon-based dielectric material or the polymer dielectric material includes cleaning and activating the silicon-based dielectric material or the polymer dielectric material.