TWI884704B - Three-dimensional memory device - Google Patents

Abstract

A three-dimensional memory device is provided in the present disclosure. The three-dimensional memory device comprises a plurality of word lines, a plurality of bit lines, a three-dimensional memory array, a plurality of encoding circuits and a plurality of sensing circuits. The three-dimensional memory array comprises a plurality of two-dimensional memory arrays and is configured to store a first neural network data, a second neural network data, a third neural network data and a fourth neural network data related to at least one neural network model. Each of the plurality of two-dimensional memory arrays is coupled to the plurality of word lines and the plurality of bit lines, configured to receive a first input voltage and output a first output current, and configured to receive a second input voltage and output a second output current. The plurality of encoding circuits are respectively coupled to the plurality of two-dimensional memory arrays, and are configured to generate the first input voltage and the second input voltage based on the first neural network data and the second neural network data respectively. The plurality of sensing circuits are respectively coupled to the plurality of two-dimensional memory arrays, and are configured to generate the third neural network data and the fourth neural network data based on the first output current and the second output current respectively.

Description

Three-dimensional memory device

This disclosure relates to data storage techniques in three-dimensional memory devices, and more particularly to three-dimensional memory devices that store twice as much data by transmitting signals via two different signal paths.

With the evolution of memory technology, three-dimensional memory devices with lower bit cost have gradually replaced traditional planar memory and are applied in many fields. In addition, in order to improve the phenomenon that the processor needs to spend a lot of time and energy to read data from the memory, the technology of in-memory computing (IMC) has also gradually received attention. With the in-memory computing technology, operations can be performed directly in the memory, thereby improving the speed and efficiency of reading data.

The three-dimensional memory device contains a memory array with a large number of memory units, and each memory unit has a corresponding impedance. By adjusting the impedance of each memory unit, the three-dimensional memory device can realize the storage of data (i.e. neurons) in the neural network model for use in artificial intelligence technology.

However, with the development of artificial intelligence technology, the amount of data required to be stored in the computing process is getting larger and larger. Therefore, how to increase the storage capacity of three-dimensional memory devices for data in neural network models is one of the topics in this field.

One aspect of the present disclosure provides a three-dimensional memory device, comprising a plurality of word lines, a plurality of bit lines, a three-dimensional memory array, a plurality of encoding circuits, and a plurality of sensing circuits. The three-dimensional memory array comprises a plurality of two-dimensional memory arrays for storing first neural network data, second neural network data, third neural network data, and fourth neural network data associated with at least one neural network model. Each two-dimensional memory array is coupled to a plurality of word lines and a plurality of bit lines, for receiving a first input voltage and outputting a first output current, and for receiving a second input voltage and outputting a second output current. Multiple encoding circuits are respectively coupled to multiple two-dimensional memory arrays to generate a first input voltage and a second input voltage according to the first neural network data and the second neural network data. Multiple sensing circuits are respectively coupled to multiple two-dimensional memory arrays to generate a third neural network data and a fourth neural network data according to the first output current and the second output current.

In some embodiments of the three-dimensional memory device of this state, the first neural network data is associated with the Kth neural network layer in the first neural network model of the at least one neural network model, and the third neural network data is associated with the (K+1)th neural network layer in the first neural network model; and the second neural network data is associated with the Mth neural network layer in the second neural network model of the at least one neural network model, and the fourth neural network data is associated with the (M+1)th neural network layer in the second neural network model. The first neural network model is different from the second neural network model, and M and K are positive integers.

In some embodiments of the three-dimensional memory device storing data related to different neural network models, a first two-dimensional memory array among the plurality of two-dimensional memory arrays is coupled to two of the plurality of sensing circuits, a second two-dimensional memory array among the plurality of two-dimensional memory arrays is coupled to two of the plurality of encoding circuits, and the two of the plurality of sensing circuits are respectively coupled to The two of the multiple encoding circuits are respectively used to: input the third neural network data of the first two-dimensional memory array to the second two-dimensional memory array to serve as the first neural network data of the second two-dimensional memory array; and input the fourth neural network data of the first two-dimensional memory array to the second two-dimensional memory array to serve as the second neural network data of the second two-dimensional memory array.

In some embodiments of the three-dimensional memory device storing data related to different neural network models, multiple two-dimensional memory arrays receive first neural network data via multiple word lines, receive second neural network data via multiple bit lines, and multiple two-dimensional memory arrays transmit third neural network data via multiple bit lines and transmit fourth neural network data via multiple word lines.

In some embodiments of the three-dimensional memory device storing data related to different neural network models of this state, a portion of the multiple two-dimensional memory arrays receives the first neural network data via multiple word lines, receives the second neural network data via multiple bit lines, transmits the third neural network data via multiple bit lines, and transmits the fourth neural network data via multiple word lines, and another portion of the multiple two-dimensional memory arrays receives the first neural network data via multiple bit lines, receives the second neural network data via multiple word lines, transmits the third neural network data via multiple word lines, and transmits the fourth neural network data via multiple bit lines.

In some embodiments of the three-dimensional memory device of this aspect, the first neural network data is associated with the Kth neural network layer in the first neural network model of the at least one neural network model, the second neural network data is the same as the third neural network data and is associated with the (K+1)th neural network layer in the first neural network model, and the fourth neural network data is associated with the (K+2)th neural network layer in the first neural network model. K is a positive integer.

In some embodiments of the three-dimensional memory device storing data related to the same neural network model of the aspect, a first two-dimensional memory array among a plurality of two-dimensional memory arrays is coupled to a first sensing circuit and a second sensing circuit among a plurality of sensing circuits, and is coupled to a first encoding circuit and a second encoding circuit among a plurality of encoding circuits. The first encoding circuit is used to receive the first neural network data, the first sensing circuit is coupled to the second encoding circuit, and is used to transmit the third neural network data as the second neural network data to the first two-dimensional memory array, and the second sensing circuit is used to transmit the fourth neural network data to the second two-dimensional memory array among the plurality of two-dimensional memory arrays, and is used as the first neural network data of the second two-dimensional memory array.

In some embodiments of the three-dimensional memory device storing data related to the same neural network model, multiple two-dimensional memory arrays receive first neural network data via multiple word lines, receive second neural network data via multiple bit lines, and multiple two-dimensional memory arrays transmit third neural network data via multiple bit lines and transmit fourth neural network data via multiple word lines.

In some embodiments of the three-dimensional memory device storing data related to the same neural network model, a portion of the multiple two-dimensional memory arrays receives the first neural network data via multiple word lines, transmits the third neural network data via multiple bit lines and receives the second neural network data, and then transmits the fourth neural network data via multiple word lines, and another portion of the multiple two-dimensional memory arrays receives the first neural network data via multiple bit lines, transmits the third neural network data via multiple word lines and receives the second neural network data, and then transmits the fourth neural network data via multiple bit lines.

Another aspect of the present disclosure provides a three-dimensional memory device, comprising a plurality of word lines, a plurality of bit lines, a three-dimensional memory array, a plurality of encoding circuits, and a plurality of sensing circuits. The three-dimensional memory array comprises a plurality of two-dimensional memory arrays. The plurality of two-dimensional memory arrays each comprises a plurality of sub-arrays of the same size, for storing first neural network data, second neural network data, third neural network data, and fourth neural network data associated with at least one neural network model. The plurality of sub-arrays are coupled to the plurality of word lines and the plurality of bit lines, for receiving a plurality of first input voltages and outputting a plurality of first output currents, and for receiving a plurality of second input voltages and outputting a plurality of second output currents. Multiple encoding circuits are coupled to multiple sub-arrays respectively, and are used to generate multiple first input voltages and multiple second input voltages according to the first neural network data and the second neural network data respectively. Multiple sensing circuits are coupled to multiple sub-arrays respectively, and are used to generate third neural network data and fourth neural network data according to the sum of multiple first output currents and the sum of multiple second output currents respectively.

In some embodiments of the three-dimensional memory device of the other aspect, the first neural network data is associated with the Kth neural network layer in the first neural network model of the at least one neural network model, and the third neural network data is associated with the (K+1)th neural network layer in the first neural network model; and the second neural network data is associated with the Mth neural network layer in the second neural network model of the at least one neural network model, and the fourth neural network data is associated with the (M+1)th neural network layer in the second neural network model. The first neural network model is different from the second neural network model, and M and K are positive integers.

In some embodiments of the three-dimensional memory device storing data related to different neural network models in another aspect, multiple first sub-arrays in the multiple sub-arrays are each coupled to two of the multiple sensing circuits, multiple second sub-arrays in the multiple sub-arrays are each coupled to two of the multiple encoding circuits, and the multiple sensing circuits coupled to the multiple first sub-arrays are coupled to the multiple encoding circuits coupled to the multiple second sub-arrays, so as to: input the third neural network data of the multiple first sub-arrays to the multiple second sub-arrays as the first neural network data of the multiple second sub-arrays; and input the fourth neural network data of the multiple first sub-arrays to the multiple second sub-arrays as the second neural network data of the multiple second sub-arrays.

In some embodiments of the three-dimensional memory device storing data related to different neural network models in another aspect, multiple sub-arrays receive first neural network data via multiple word lines, receive second neural network data via multiple bit lines, and multiple sub-arrays transmit third neural network data via multiple bit lines, and transmit fourth neural network data via multiple word lines.

In some embodiments of the three-dimensional memory device storing data related to different neural network models in another aspect, a portion of the plurality of sub-arrays receives first neural network data via a plurality of word lines, receives second neural network data via a plurality of bit lines, transmits third neural network data via a plurality of bit lines, and transmits fourth neural network data via a plurality of word lines, and another portion of the plurality of sub-arrays receives first neural network data via a plurality of bit lines, receives second neural network data via a plurality of word lines, transmits third neural network data via a plurality of word lines, and transmits fourth neural network data via a plurality of bit lines.

In some embodiments of the three-dimensional memory device of the other aspect, the first neural network data is associated with the Kth neural network layer in the first neural network model of the at least one neural network model, the second neural network data is the same as the third neural network data and is associated with the (K+1)th neural network layer in the first neural network model, and the fourth neural network data is associated with the (K+2)th neural network layer in the first neural network model. K is a positive integer.

In some embodiments of the three-dimensional memory device storing data related to the same neural network model in another aspect, multiple first sub-arrays in the multiple sub-arrays are coupled to multiple first sensing circuits and multiple second sensing circuits in the multiple sensing circuits, and coupled to multiple first encoding circuits and multiple second encoding circuits in the multiple encoding circuits. The multiple first encoding circuits are used to receive the first neural network data, the multiple first sensing circuits are coupled to the multiple second encoding circuits, and are used to transmit the third neural network data as the second neural network data to the multiple first sub-arrays, and the multiple second sensing circuits are used to transmit the fourth neural network data to the multiple second sub-arrays in the multiple sub-arrays as the first neural network data of the multiple second sub-arrays.

In some embodiments of the three-dimensional memory device storing data related to the same neural network model in another aspect, multiple sub-arrays receive first neural network data via multiple word lines, receive second neural network data via multiple bit lines, and multiple sub-arrays transmit third neural network data via multiple bit lines, and transmit fourth neural network data via multiple word lines.

In some embodiments of the three-dimensional memory device storing data related to the same neural network model in another aspect, a portion of the plurality of sub-arrays receives the first neural network data via a plurality of word lines, transmits the third neural network data via a plurality of bit lines and receives the second neural network data, and then transmits the fourth neural network data via a plurality of word lines, and another portion of the plurality of sub-arrays receives the first neural network data via a plurality of bit lines, transmits the third neural network data via a plurality of word lines and receives the second neural network data, and then transmits the fourth neural network data via a plurality of bit lines.

In some embodiments of the three-dimensional memory device of the other aspect, the first neural network data, the second neural network data, the third neural network data, and the fourth neural network data are different from each other and are all related to a neural network layer in one of the at least one neural network model.

In some embodiments of the three-dimensional memory device for storing data of the same neural network layer related to the same neural network model in another aspect, multiple sub-arrays receive first neural network data via multiple word lines, receive second neural network data via multiple bit lines, and multiple sub-arrays transmit third neural network data via multiple bit lines, and transmit fourth neural network data via multiple word lines.

Through the two types of three-dimensional memory devices disclosed in this document, signals can be transmitted in different directions in the memory array to realize the function of storing two types of neural network data, thereby improving the storage capacity of the three-dimensional memory device.

100: Three-dimensional memory device

110: Three-dimensional memory array

111_1~111_p: two-dimensional memory array

111_1A~111_1J: subarray

120: Encoding circuit

130: Sensing circuit

140: Processing circuit

V, V1~Vn: Input voltage

I,I1~Im: output current

A1~An,B1~Bm: neural network data

C1~Cm,D1~Dn: neural network data

G11~G1m,G21~G2m: memory unit

Gn1~Gnm: memory unit

W11~W1m,W21~W2m: Impedance/weight

Wn1~Wnm: Impedance/weight

WL1~WLn: character line

BL1~BLm: bit line

X,Y,Z: Direction

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understandable, the attached drawings are described as follows: FIG. 1 is a three-dimensional schematic diagram of a three-dimensional memory device according to some embodiments of the present disclosure; FIG. 2A is a schematic diagram of an encoding circuit, a sensing circuit and a two-dimensional memory array according to some embodiments; FIG. 2B is a schematic diagram of the internal structure and current path of a two-dimensional memory array according to some embodiments of the present disclosure; FIG. 2C is a schematic diagram of a memory device according to some embodiments of the present disclosure; FIG2D is a schematic diagram of the internal structure and current path of a two-dimensional memory array according to some embodiments of the present disclosure document; FIG3A is a circuit diagram of a two-dimensional memory array according to some embodiments of the present disclosure document; FIG3B is a circuit diagram of a two-dimensional memory array according to other embodiments of the present disclosure document; FIG3C is a circuit diagram of a two-dimensional memory array according to still other embodiments of the present disclosure document. FIG. 4A is a schematic diagram of a two-dimensional memory array storing neural network data according to some embodiments of the present disclosure; FIG. 4B is a schematic diagram of a two-dimensional memory array storing neural network data according to other embodiments of the present disclosure; FIG. 4C is a schematic diagram of a two-dimensional memory array storing neural network data according to still other embodiments of the present disclosure; FIG. 5 is a schematic diagram of a two-dimensional memory array and a sub-array according to some embodiments of the present disclosure. 6A is a schematic diagram of a sub-array storing neural network data according to some embodiments of the present disclosure; 6B is a schematic diagram of a sub-array storing neural network data according to other embodiments of the present disclosure; 6C is a schematic diagram of a sub-array storing neural network data according to still other embodiments of the present disclosure; and 6D is a schematic diagram of a sub-array storing neural network data according to still other embodiments of the present disclosure.

The following will be used in conjunction with the relevant figures to illustrate the embodiments of the present disclosure document. In the figures, the same reference numerals represent the same or similar elements or method flows.

In this disclosure document, when an element is referred to as "connected", it may refer to "electrical connection" or "optical connection", and when an element is referred to as "coupled", it may refer to "electrical coupling" or "optical coupling". "Connected" or "coupled" can also be used to indicate the coordinated operation or interaction between two or more elements. Unless the text specifically limits the article, "one" and "the" can refer to one or more. It will be further understood that the "include", "include", "have" and similar terms used in this article indicate the characteristics, regions, integers, steps, operations, elements and/or components recorded therein, but do not exclude one or more other characteristics, regions, integers, steps, operations, elements, components and/or groups thereof described therein or in addition.

FIG. 1 is a three-dimensional schematic diagram of a three-dimensional memory device 100 according to some embodiments of the present disclosure. In some embodiments, the three-dimensional memory device 100 includes a three-dimensional memory array 110, a plurality of encoding circuits 120, a plurality of sensing circuits 130, a plurality of processing circuits 140, word lines WL1~WLn and bit lines BL1~BLm. It should be noted that for the sake of simplicity of the diagram, word lines WL1~WLn and bit lines BL1~BLm are omitted in FIG. 1 (to be described in subsequent paragraphs and diagrams), and only one encoding circuit 120, one sensing circuit 130 and one processing circuit 140 are shown.

The three-dimensional memory array 110 is coupled between the encoding circuit 120 and the sensing circuit 130 to receive the input voltage V from the encoding circuit 120 and transmit the output current I to the sensing circuit 130. In some embodiments, the three-dimensional memory array 110 includes two-dimensional memory arrays 111_1~111_p, where p is a positive integer. The planes of the two-dimensional memory arrays 111_1~111_p extend along a plane direction (for example, the plane direction formed by the directions X and Z in Figure 1) and are arranged along another specific direction (for example, the direction Y in Figure 1) to form a three-dimensional structure together.

In some embodiments, the three-dimensional memory array 110 can be implemented by volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM)), or a combination thereof.

In some embodiments, the two-dimensional memory arrays 111_1~111_p each include a plurality of memory cells (e.g., a plurality of transistors shown in FIG. 1). The internal structure of the memory cell will be described in detail in the following paragraphs.

The encoding circuit 120 is coupled to the two-dimensional memory arrays 111_1~111_p and the processing circuit 140 in the three-dimensional memory array 110, and is used to receive the neural network data A1~An, B1~Bm from the processing circuit 140, and transmit the corresponding input voltage V to the two-dimensional memory arrays 111_1~111_p according to the neural network data A1~An, B1~Bm.

The sensing circuit 130 is coupled to the two-dimensional memory arrays 111_1~111_p in the three-dimensional memory array 110 and the processing circuit 140, and is used to receive the output current I from the two-dimensional memory arrays 111_1~111_p, and calculate the corresponding neural network data C1~Cm, D1~Dn according to the current I, and then transmit the neural network data C1~Cm, D1~Dn to the processing circuit 140.

The processing circuit 140 is coupled to the encoding circuit 120 and the sensing circuit 130 to transmit the neural network data A1~An, B1~Bm to the encoding circuit 120 and receive the neural network data C1~Cm, D1~Dn from the sensing circuit 130.

Since the two-dimensional memory arrays 111_1 to 111_p are coupled to each encoding circuit 120 and each sensing circuit 130 in a similar manner, for the sake of simplicity, FIG. 2A only illustrates the connection relationship between the two-dimensional memory array 111_1 and the encoding circuit 120 and the sensing circuit 130. FIG. 2A is a schematic diagram of the encoding circuit 120, the sensing circuit 130 and the two-dimensional memory array 111_1 according to some examples. In some embodiments, the two-dimensional memory array 111_1 includes memory cells G11~G1m, G21~G2m, ..., Gn1~Gnm, and the memory cells G11~G1m, G21~G2m, ..., Gn1~Gnm are arranged in a square array with m rows and n columns, where m and n are positive integers.

As shown in Figure 2A, after receiving the neural network data A1~An, the encoding circuit 120 will generate corresponding input voltages V1~Vn to the two-dimensional memory array 111_1 according to the neural network data A1~An. Then, the two-dimensional memory array 111_1 will generate output currents I1~Im to the sensing circuit 130. After receiving the output currents I1~Im, the sensing circuit 130 will generate corresponding neural network data C1~Cm according to the output currents I1~Im.

For the internal structure and current path of the two-dimensional memory array 111_1, please refer to FIG. 2B. FIG. 2B is a schematic diagram of the internal structure and current path of the two-dimensional memory array 111_1 according to some embodiments of the present disclosure.

In some embodiments, the memory cells G11-G1m, G21-G2m, ..., Gn1-Gnm have impedances W11-W1m, W21-W2m, ..., Wn1-Wnm, respectively. In operation, when the input voltages V1~Vn are respectively input from the word lines WL1~WLn to the two-dimensional memory array 111_1, the two-dimensional memory array 111_1 will generate a part of the output current I1 on the bit line BL1 according to the input voltage V1 (corresponding to the neural network data A1) and the impedance W11 of the memory cell G11, and will generate another part of the output current I1 on the bit line BL1 according to the input voltage V2 (corresponding to the neural network data A2) and the impedance W21 of the memory cell G21, and so on. Therefore, the input voltage V1~Vn (corresponding to the neural network data A1~An) will generate n parts of the output current I1 on the bit line BL1, and the sum of these n parts is the output current I1 (corresponding to the neural network data C1).

Similarly, the two-dimensional memory array 111_1 generates a portion of the output current I2 on the bit line BL2 according to the input voltage V1 (corresponding to the neural network data A1) and the impedance W12 of the memory cell G12, and generates another portion of the output current I2 on the bit line BL2 according to the input voltage V2 (corresponding to the neural network data A2) and the impedance W22 of the memory cell G22, and so on. Therefore, the input of the input voltage V1~Vn (corresponding to the neural network data A1~An) will generate n portions of the output current I2 on the bit line BL2, and the sum of these n portions is the output current I2 (corresponding to the neural network data C2). The generation method of output currents I3~Im (corresponding to neural network data C3~Cm) is similar to that of output currents I1 and I2. For the sake of brevity, they will not be repeated here.

The correspondence between input voltage V1~Vn, impedance W11~W1m, W21~W2m, ..., Wn1~Wnm and output current I1~Im can be used to implement the calculation between two adjacent neural network layers in the neural network model. Please refer to Figure 2B and Figure 2C together. Figure 2C is a schematic diagram of a neural network drawn according to some embodiments of this disclosure document.

In the embodiment of FIG. 2C , neural network data A1-An are stored in neurons of the Kth neural network layer, and neural network data C1-Cm are stored in neurons of the (K+1)th neural network layer. The neural network data of a neuron in the current layer is the sum of the neural network data of all neurons in the previous layer multiplied by the corresponding weights. For example, in the embodiment of FIG. 2C, the neural network data C1 is the sum of the neural network data A1~An multiplied by weights W11, W21, ..., Wn1 respectively; the neural network data C2 is the sum of the neural network data A1~An multiplied by weights W12, W22, ..., Wn2 (not shown for simplicity), and so on. Therefore, the calculation of the neural network data C1~Cm can be expressed by the following <Formula 1>:

Since the calculation method for the neural network data C1~Cm in Figure 2B and Figure 2C is the same, the impedances W11, W21, ..., Wn1 in Figure 2B can be regarded as realizing the weights W11, W21, ..., Wn1 in the neural network model of Figure 2C, thereby realizing the function of storing the neural network data in the Kth neural network layer.

In some embodiments, the two-dimensional memory array 111_1 can receive neural network data through word lines WL1~WLn and output neural network data through bit lines BL1~BLm, and can also receive neural network data through bit lines BL1~BLm and output neural network data through word lines WL1~WLn. Please refer to Figure 2D, which is a schematic diagram of the internal structure and current path of the two-dimensional memory array 111_1 according to some embodiments of the present disclosure document.

In the embodiment of FIG. 2D, the two-dimensional memory array 111_1 receives neural network data B1 from bit line BL1, and generates a portion of neural network data D1 on word line WL1 according to the neural network data B1 and the impedance W11 of memory cell G11; receives neural network data B2 from bit line BL2, and generates another portion of neural network data D1 on word line WL1 according to the neural network data B2 and the impedance W12 of memory cell G12, and so on. Therefore, the input of neural network data B1~Bm generates m portions of neural network data D1 on word line WL1, and the sum of these m portions is neural network data D1, and so on. Therefore, the neural network data Dn can be calculated based on the neural network data B1~Bm received by the bit lines BL1~BLm and the impedance of each neural network data on the path of the word line WLn (as shown in Figure 2D).

Therefore, similar to the embodiment of FIG. 2B, the correspondence between the neural network data B1-Bm, impedances W11-W1m, W21-W2m, ..., Wn1-Wnm and neural network data D1-Dn in FIG. 2D can also be used to implement the calculation between two adjacent neural network layers in the neural network model (for example, the neural network model in FIG. 2C), so the calculation of the neural network data D1-Dn can be expressed by the following <Formula 2>:

In summary, the two-dimensional memory array 111_1 can store two different data in the same two-dimensional memory array by receiving/outputting neural network data using word lines/bit lines respectively, and receiving/outputting neural network data using bit lines/word lines respectively.

For the implementation of memory units G11~G1m, G21~G2m, ..., Gn1~Gnm, please refer to Figures 3A~3C. Figures 3A~3C are circuit diagrams of a two-dimensional memory array 111_1 according to some different embodiments of this disclosure document.

In some embodiments, memory cells G11~G1m, G21~G2m, ..., Gn1~Gnm can be connected by horizontal and vertical wires (e.g., word lines and bit lines) to form a cross-point type array. For example, in the embodiment of FIG. 3A, memory cells G11~G13 and memory cells G21~G23, G31~G33 (not labeled for simplicity) are coupled to adjacent memory cells through horizontal and vertical wires, respectively, and each memory cell (i.e., each intersection of the cross-point array) is implemented as a circuit including a resistor.

In other embodiments, memory cells G11~G1m, G21~G2m, ..., Gn1~Gnm can also be connected by horizontal and vertical wires, and their conduction states can be controlled by additional wires to form a logical NOR type array. For example, in the embodiment of FIG. 3B, memory cells G11~G13 and memory cells G21~G23, G31~G33 (not labeled for simplicity) are coupled to adjacent memory cells through horizontal and vertical wires, and each memory cell is implemented as a circuit including a resistor and a capacitor. In addition, the control terminals of the memory cells on the same column of the memory array are connected to an additional wire to control whether they are turned on or off.

Similar to FIG. 3B, in the embodiment of FIG. 3C, memory cells G11-G13 and memory cells G21-G23, G31-G33 also form a logical anti-OR array. The difference is that each memory cell in FIG. 3C is implemented as a circuit including an inductor and a capacitor.

It should be noted that the implementation methods of the memory cells G11-G13, G21-G23 and G31-G33 in Figures 3A-3C are only examples and are not intended to limit the present disclosure. As long as the circuit structure of the memory cell meets the conditions of the crosspoint array or the logical inverse array, the implementation methods of other memory cells are within the scope of the present disclosure.

FIG. 4A is a schematic diagram of two-dimensional memory arrays 111_1 and 111_2 storing neural network data according to some embodiments of the present disclosure. It should be noted that for the sake of simplicity of the diagrams, word lines and bit lines connected to each two-dimensional memory array are omitted in FIGS. 4A to 4C and 6A to 6D. When the encoding circuit 120 is connected to the left or right side of the two-dimensional memory array, it means that the two-dimensional memory array receives the neural network data via the word line. When the encoding circuit 120 is connected to the top or bottom side of the two-dimensional memory array, it means that the two-dimensional memory array receives the neural network data via the bit line. When the sensing circuit 130 is connected to the left or right side of the two-dimensional memory array, it means that the two-dimensional memory array transmits the neural network data via the word line. When the sensing circuit 130 is connected to the top or bottom side of the two-dimensional memory array, it means that the two-dimensional memory array transmits the neural network data via the bit line.

In the embodiment of FIG. 4A , the two-dimensional memory array 111_1 is coupled to the two-dimensional memory array 111_2 via a set of encoding circuits 120 , sensing circuits 130 , and processing circuits 140 to store neural network data associated with the Kth neural network layer of the first neural network model. In detail, after the encoding circuit 120 inputs the neural network data related to the Kth neural network layer of the first neural network model into the two-dimensional memory array 111_1, the sensing circuit 130 can calculate the neural network data related to the (K+1)th neural network layer of the first neural network model through weighting and summing of the two-dimensional memory array 111_1, and use it as neural network data input to the two-dimensional memory array 111_2 through the processing circuit 140 for subsequent calculations.

Similarly, the two-dimensional memory array 111_2 is also coupled to the two-dimensional memory array 111_3 through a set of encoding circuits 120, sensing circuits 130 and processing circuits 140, and calculates the neural network data related to the (K+2)th neural network layer of the first neural network model in a manner similar to the two-dimensional memory array 111_1, thereby storing the neural network data related to the (K+1)th neural network layer of the first neural network model.

In addition, the two-dimensional memory array 111_1 is coupled to the two-dimensional memory array 111_2 through another set of encoding circuits 120, sensing circuits 130 and processing circuits 140 to store neural network data related to the Kth neural network layer of the second neural network model; the two-dimensional memory array 111_2 is coupled to the two-dimensional memory array 111_3 through another set of encoding circuits 120, sensing circuits 130 and processing circuits 140 to store neural network data related to the (K+1)th neural network layer of the second neural network model.

Therefore, each two-dimensional memory array can store two sets of data through two connection methods. The connection method and data transmission method of the two-dimensional memory arrays 111_3~111_p are similar to those of the two-dimensional memory arrays 111_1 and 111_2, and will not be repeated here.

In some embodiments, the two-dimensional memory arrays 111_1 to 111_p receive neural network data related to the first neural network model via word lines, and transmit the neural network data related to the first neural network model via bit lines (as shown in the upper half of FIG. 4A ) to store the first set of data. In addition, the two-dimensional memory arrays 111_1 to 111_p further receive neural network data related to the second neural network model via bit lines, and transmit the neural network data related to the second neural network model via word lines (as shown in the lower half of FIG. 4A ) to store the second set of data.

FIG. 4B is a schematic diagram of two-dimensional memory arrays 111_1 and 111_2 storing neural network data according to other embodiments of the present disclosure. Similar to FIG. 4A, the two-dimensional memory array 111_1 in FIG. 4B is also used to store neural network data associated with the Kth neural network layer of the first neural network model and neural network data associated with the Kth neural network layer of the second neural network model, and the two-dimensional memory array 111_2 is also used to store neural network data associated with the (K+1)th neural network layer of the first neural network model and neural network data associated with the (K+1)th neural network layer of the second neural network model.

Different from FIG. 4A, in the embodiment of FIG. 4B, a portion of the two-dimensional memory arrays 111_1~111_p can receive neural network data related to the first neural network model via word lines and then transmit the neural network data related to the first neural network model via bit lines, while another portion can receive neural network data related to the first neural network model via bit lines and then transmit the neural network data related to the first neural network model via word lines to store the first set of data.

For example, as shown in the upper half of FIG. 4B, the two-dimensional memory array 111_1 receives the neural network data of the Kth neural network layer associated with the first neural network model via the word line, and then transmits the neural network data associated with the (K+1)th neural network layer of the first neural network model via the bit line, while the two-dimensional memory array 111_2 receives the neural network data associated with the (K+1)th neural network layer of the first neural network model via the bit line, and then transmits the neural network data associated with the (K+2)th neural network layer of the first neural network model via the word line.

Therefore, when the two-dimensional memory arrays 111_1~111_p store the neural network data (i.e., the second set of data) related to the second neural network model, a part of the two-dimensional memory array can receive the neural network data via the bit line and then transmit the neural network data via the word line, and another part of the two-dimensional memory array can receive the neural network data via the word line and then transmit the neural network data via the bit line.

Continuing with the embodiment shown in FIG. 4B, the two-dimensional memory array 111_1 receives neural network data related to the Kth neural network layer of the second neural network model via the bit line, and then transmits neural network data related to the (K+1)th neural network layer of the second neural network model via the word line, while the two-dimensional memory array 111_2 receives neural network data related to the (K+1)th neural network layer of the second neural network model via the word line, and then transmits neural network data related to the (K+2)th neural network layer of the second neural network model via the bit line.

It should be noted that although the two-dimensional memory arrays 111_1~111_p described in FIG. 4A, FIG. 4B and above are used to store neural network data associated with the same neural network layer in two neural network models, the present disclosure is not limited thereto. In some embodiments, the two-dimensional memory arrays 111_1~111_p can store neural network data associated with different neural network layers in two neural network models. For example, the two-dimensional memory array 111_1 can store neural network data associated with the first neural network layer of the first neural network model and the fifth neural network layer of the second neural network model.

In addition, the two-dimensional memory arrays 111_1~111_p in the present disclosure are not limited to being used to store neural network data associated with two neural network models. In some embodiments, each two-dimensional memory array is used to store neural network data associated with two adjacent neural network layers in a neural network model.

Please refer to Figure 4C, which is a schematic diagram of a two-dimensional memory array 111_1 storing neural network data according to some other embodiments of this disclosure document.

In the embodiment of FIG. 4C , first, the two-dimensional memory array 111_1 receives the neural network data associated with the Kth neural network layer of the first neural network model through the word line by means of the first set of encoding circuits 120 and sensing circuits 130, and then transmits the neural network data associated with the (K+1)th neural network layer through the bit line. Next, the processing circuit 140 transmits the neural network data associated with the (K+1)th neural network layer to the second set of encoding circuits 120 and sensing circuits 130 of the two-dimensional memory array 111_1, so that the two-dimensional memory array 111_1 receives the neural network data associated with the (K+1)th neural network layer via the bit line, and then transmits the neural network data associated with the (K+2)th neural network layer to the two-dimensional memory array 111_2 via the word line. In this way, this configuration enables a two-dimensional memory array to realize the function of storing neural network data associated with two adjacent neural network layers of a neural network model.

It should be noted that although the two-dimensional memory array 111_1 in FIG. 4C is illustrated as first receiving the neural network data with word lines and transmitting the neural network data (i.e., the first set of data) with bit lines, and then receiving the neural network data with bit lines and transmitting the neural network data (i.e., the second set of data) with word lines, the present disclosure document is not limited to this. In some embodiments, a portion of the two-dimensional memory arrays 111_1~111_p may first receive/transmit the first set of neural network data using word lines/bit lines, and then receive/transmit the second set of neural network data using bit lines/word lines, and another portion may first receive/transmit the first set of neural network data using bit lines/word lines, and then receive/transmit the second set of neural network data using word lines/bit lines.

FIG. 5 is a schematic diagram showing the relationship between the two-dimensional memory array 111_1 and the sub-arrays 111_1A~111_1J according to some embodiments of the present disclosure. In some embodiments, the two-dimensional memory array 111_1 (and other two-dimensional memory arrays in the three-dimensional memory array 110) can be divided into multiple sub-arrays of the same size to store neural network data.

In some embodiments, the sum of the sizes of the sub-arrays divided out may be equal to the size of the divided two-dimensional memory array. For example, sub-arrays 111_1A to 111_1D are all 4x4 arrays, and their sum is the same as the 8x8 two-dimensional memory array 111_1.

In other embodiments, the sum of the sizes of the sub-arrays divided out can be larger than the size of the two-dimensional memory array being divided. For example, sub-arrays 111_1E~111_1J are all 3x5 arrays, and their sum is larger than the 8x8 two-dimensional memory array 111_1. In this case, the voltages received by the extra rows and columns in the array will be set to 0.

FIG. 6A is a schematic diagram of sub-arrays 111_1A~111_1C storing neural network data according to some embodiments of the present disclosure. In some embodiments, the sub-arrays 111_1A~111_1C in FIG. 6A are used to jointly implement the two-dimensional memory array 111_1 in FIG. 2A.

In detail, each of the sub-arrays 111_1A~111_1C is connected to a set of encoding circuits 120 and sensing circuits 130, and the three sensing circuits 130 are connected to a processing circuit 140 to sum up the neural network data output by the three sensing circuits 130 to obtain neural network data related to the Kth neural network layer of the first neural network model. In addition, each of the sub-arrays 111_1A~111_1C is further connected to another set of encoding circuits 120 and sensing circuits 130, and the three sensing circuits 130 are connected to a processing circuit 140 to sum up the neural network data output by the three sensing circuits 130 to obtain neural network data related to the Kth neural network layer of the second neural network model.

Similar to the two-dimensional memory arrays 111_1~111_p in FIG. 2A, the sub-arrays 111_1A~111_1C in FIG. 6A receive neural network data related to the first neural network model through word lines, and transmit the neural network data related to the first neural network model through bit lines (as shown in the upper half of FIG. 6A) to store the first set of data. In addition, the sub-arrays 111_1A~111_1C further receive neural network data related to the second neural network model through bit lines, and transmit the neural network data related to the second neural network model through word lines (as shown in the lower half of FIG. 4A) to store the second set of data.

FIG. 6B is a schematic diagram of sub-arrays 111_1A~111_1C storing neural network data according to other embodiments of the present disclosure. In some embodiments, the sub-arrays 111_1A~111_1C in FIG. 6B are used to jointly implement the two-dimensional memory array 111_1 in FIG. 2B.

In detail, similar to FIG. 4B, a portion of the sub-arrays 111_1A~111_1C can receive neural network data related to the first neural network model via word lines, and then transmit the neural network data related to the first neural network model via bit lines, while another portion of the sub-arrays 111_1A~111_1C can receive neural network data related to the first neural network model via bit lines, and then transmit the neural network data related to the first neural network model via word lines, so as to jointly store the first set of data (as shown in the upper half of FIG. 6B). The way in which the sub-arrays 111_1A~111_1C store the second set of data is also similar to FIG. 4B, and will not be repeated here.

FIG. 6C is a schematic diagram of sub-arrays 111_1A~111_1C storing neural network data according to other embodiments of the present disclosure. In some embodiments, the sub-arrays 111_1A~111_1C in FIG. 6C are used to jointly implement the two-dimensional memory array 111_1 in FIG. 2C.

In detail, similar to FIG. 4C , sub-arrays 111_1A to 111_1C are used to store neural network data associated with two adjacent neural network layers of a neural network model. First, sub-arrays 111_1A to 111_1C receive neural network data associated with the Kth neural network layer through three encoding circuits 120 and three sensing circuits 130 via word lines, and then transmit output data through bit lines. Then, the processing circuit 140 sums up the outputs of the three sensing circuits 130 to obtain the neural network data associated with the (K+1)th neural network layer, and transmits it to the other three encoding circuits 120 and the other three sensing circuits 130. Therefore, the sub-arrays 111_1A~111_1C can receive the neural network data associated with the (K+1)th neural network layer via the bit line, and transmit the output data to another processing circuit 140 via the word line to sum up the neural network data associated with the (K+2)th neural network layer.

In addition, similar to FIG. 4C , in some embodiments, a portion of the sub-arrays 111_1A~111_1C may first receive/transmit the first set of neural network data using word lines/bit lines, and then receive/transmit the second set of neural network data using bit lines/word lines, and another portion may first receive/transmit the first set of neural network data using bit lines/word lines, and then receive/transmit the second set of neural network data using word lines/bit lines.

FIG. 6D is a schematic diagram of sub-arrays 111_1A-111_1C storing neural network data according to some further embodiments of the present disclosure. FIG. 6D is similar to FIG. 6C, except that the sub-arrays 111_1A-111_1C in FIG. 6D can be used to store neural network data associated with two parts of a neural network layer of a neural network model. In other words, the sub-arrays 111_1A~111_1C in FIG. 6D use the location [a, b, c] of the Kth neural network layer as the first set of neural network data, and use the location [d, e, f] of the Kth neural network layer as the second set of neural network data to jointly store the neural network data related to the Kth neural network layer.

Through the configuration of the three-dimensional memory device 100 proposed in this disclosure document, the function of storing two sets of neural network data can be realized by inputting two sets of data through word lines/bit lines and outputting them through bit lines/word lines, thereby improving the storage capacity of the three-dimensional memory device 100.

The above is only the preferred embodiment of this disclosure document. Without departing from the scope or spirit of this disclosure document, the structure of this disclosure document can be modified and equivalently changed in various ways. In summary, all modifications and equivalent changes made to this disclosure document within the scope of the following claims are covered by this disclosure document.

111_1,111_2: Two-dimensional memory array

120: Encoding circuit

130: Sensing circuit

140: Processing circuit

Claims (20)

A three-dimensional memory device, comprising: a plurality of word lines; a plurality of bit lines; a three-dimensional memory array, comprising a plurality of two-dimensional memory arrays, for storing a first neural network data, a second neural network data, a third neural network data and a fourth neural network data associated with at least one neural network model, wherein each two-dimensional memory array is coupled to the plurality of word lines and the plurality of bit lines, for receiving a first input voltage and outputting a first output current, and for receiving a second input voltage and outputting a second output current; A plurality of encoding circuits are coupled to the plurality of two-dimensional memory arrays, respectively, for generating the first input voltage and the second input voltage according to the first neural network data and the second neural network data; and a plurality of sensing circuits are coupled to the plurality of two-dimensional memory arrays, respectively, for generating the third neural network data and the fourth neural network data according to the first output current and the second output current. A three-dimensional memory device as described in claim 1, wherein the first neural network data is associated with a Kth neural network layer in a first neural network model of the at least one neural network model, the third neural network data is associated with a (K+1)th neural network layer in the first neural network model, and the second neural network data is associated with an Mth neural network layer in a second neural network model of the at least one neural network model, and the fourth neural network data is associated with a (M+1)th neural network layer in the second neural network model, wherein the first neural network model is different from the second neural network model, and M and K are positive integers. A three-dimensional memory device as described in claim 2, wherein a first two-dimensional memory array among the plurality of two-dimensional memory arrays is coupled to two of the plurality of sensing circuits, a second two-dimensional memory array among the plurality of two-dimensional memory arrays is coupled to two of the plurality of encoding circuits, and the two of the plurality of sensing circuits are respectively coupled to the two of the plurality of encoding circuits, respectively used to: input the third neural network data of the first two-dimensional memory array to the second two-dimensional memory array as the first neural network data of the second two-dimensional memory array; and The fourth neural network data of the first two-dimensional memory array is input into the second two-dimensional memory array to serve as the second neural network data of the second two-dimensional memory array. A three-dimensional memory device as described in claim 3, wherein the multiple two-dimensional memory arrays all receive the first neural network data via the multiple word lines, receive the second neural network data via the multiple bit lines, and the multiple two-dimensional memory arrays all transmit the third neural network data via the multiple bit lines, and transmit the fourth neural network data via the multiple word lines. A three-dimensional memory device as described in claim 3, wherein a portion of the multiple two-dimensional memory arrays receives the first neural network data via the multiple word lines, receives the second neural network data via the multiple bit lines, transmits the third neural network data via the multiple bit lines, and transmits the fourth neural network data via the multiple word lines, and another portion of the multiple two-dimensional memory arrays receives the first neural network data via the multiple bit lines, receives the second neural network data via the multiple word lines, transmits the third neural network data via the multiple word lines, and transmits the fourth neural network data via the multiple bit lines. A three-dimensional memory device as described in claim 1, wherein the first neural network data is associated with a K-th neural network layer in a first neural network model of the at least one neural network model, the second neural network data is the same as the third neural network data and is associated with a (K+1)-th neural network layer in the first neural network model, and the fourth neural network data is associated with a (K+2)-th neural network layer in the first neural network model, wherein K is a positive integer. A three-dimensional memory device as described in claim 6, wherein a first two-dimensional memory array among the plurality of two-dimensional memory arrays is coupled to a first sensing circuit and a second sensing circuit among the plurality of sensing circuits, and is coupled to a first encoding circuit and a second encoding circuit among the plurality of encoding circuits, wherein the first encoding circuit is used to receive the first neural network data, the first sensing circuit is coupled to the second encoding circuit to transmit the third neural network data as the second neural network data to the first two-dimensional memory array, and The second sensing circuit is used to transmit the fourth neural network data to a second two-dimensional memory array among the multiple two-dimensional memory arrays to be used as the first neural network data of the second two-dimensional memory array. A three-dimensional memory device as described in claim 7, wherein the multiple two-dimensional memory arrays all receive the first neural network data via the multiple word lines, receive the second neural network data via the multiple bit lines, and the multiple two-dimensional memory arrays all transmit the third neural network data via the multiple bit lines, and transmit the fourth neural network data via the multiple word lines. A three-dimensional memory device as described in claim 7, wherein a portion of the multiple two-dimensional memory arrays receives the first neural network data via the multiple word lines, transmits the third neural network data via the multiple bit lines and receives the second neural network data, and then transmits the fourth neural network data via the multiple word lines, and another portion of the multiple two-dimensional memory arrays receives the first neural network data via the multiple bit lines, transmits the third neural network data via the multiple word lines and receives the second neural network data, and then transmits the fourth neural network data via the multiple bit lines. A three-dimensional memory device, comprising: a plurality of word lines; a plurality of bit lines; a three-dimensional memory array, comprising a plurality of two-dimensional memory arrays, wherein the plurality of two-dimensional memory arrays each comprise a plurality of sub-arrays of the same size, for storing a first neural network data, a second neural network data, a third neural network data and a fourth neural network data associated with at least one neural network model, wherein the plurality of sub-arrays are coupled to the plurality of word lines and the plurality of bit lines, for receiving a plurality of first input voltages and outputting a plurality of first output currents, and for receiving a plurality of second input voltages and outputting a plurality of second output currents; A plurality of encoding circuits, respectively coupled to the plurality of sub-arrays, for generating the plurality of first input voltages and the plurality of second input voltages according to the first neural network data and the second neural network data; and a plurality of sensing circuits, respectively coupled to the plurality of sub-arrays, for generating the third neural network data and the fourth neural network data according to the sum of the plurality of first output currents and the sum of the plurality of second output currents. A three-dimensional memory device as described in claim 10, wherein the first neural network data is associated with a K-th neural network layer in a first neural network model of the at least one neural network model, and the third neural network data is associated with a (K+1)-th neural network layer in the first neural network model; and the second neural network data is associated with an M-th neural network layer in a second neural network model of the at least one neural network model, and the fourth neural network data is associated with a (M+1)-th neural network layer in the second neural network model, wherein the first neural network model is different from the second neural network model, and M and K are positive integers. A three-dimensional memory device as described in claim 11, wherein the first sub-arrays of the plurality of sub-arrays are each coupled to two of the plurality of sensing circuits, the second sub-arrays of the plurality of sub-arrays are each coupled to two of the plurality of encoding circuits, and the sensing circuits coupled to the first sub-arrays are coupled to the encoding circuits coupled to the second sub-arrays, for: inputting the third neural network data of the first sub-arrays to the second sub-arrays as the first neural network data of the second sub-arrays; and inputting the fourth neural network data of the first sub-arrays to the second sub-arrays as the second neural network data of the second sub-arrays. A three-dimensional memory device as described in claim 12, wherein the plurality of sub-arrays receive the first neural network data via the plurality of word lines, receive the second neural network data via the plurality of bit lines, and the plurality of sub-arrays transmit the third neural network data via the plurality of bit lines, and transmit the fourth neural network data via the plurality of word lines. A three-dimensional memory device as described in claim 12, wherein a portion of the plurality of sub-arrays receives the first neural network data via the plurality of word lines, receives the second neural network data via the plurality of bit lines, transmits the third neural network data via the plurality of bit lines, and transmits the fourth neural network data via the plurality of word lines, and another portion of the plurality of sub-arrays receives the first neural network data via the plurality of bit lines, receives the second neural network data via the plurality of word lines, transmits the third neural network data via the plurality of word lines, and transmits the fourth neural network data via the plurality of bit lines. A three-dimensional memory device as described in claim 10, wherein the first neural network data is associated with a K-th neural network layer in a first neural network model of the at least one neural network model, the second neural network data is the same as the third neural network data and is associated with a (K+1)-th neural network layer in the first neural network model, and the fourth neural network data is associated with a (K+2)-th neural network layer in the first neural network model, wherein K is a positive integer. A three-dimensional memory device as described in claim 15, wherein the first sub-arrays of the plurality of sub-arrays are coupled to the first sensing circuits and the second sensing circuits of the plurality of sensing circuits, and coupled to the first encoding circuits and the second encoding circuits of the plurality of encoding circuits, wherein the first encoding circuits are used to receive the first neural network data, the first sensing circuits are coupled to the second encoding circuits to transmit the third neural network data as the second neural network data to the first sub-arrays, and the second sensing circuits are used to transmit the fourth neural network data to the second sub-arrays of the plurality of sub-arrays as the first neural network data of the second sub-arrays. A three-dimensional memory device as described in claim 16, wherein the plurality of sub-arrays receive the first neural network data via the plurality of word lines, receive the second neural network data via the plurality of bit lines, and the plurality of sub-arrays transmit the third neural network data via the plurality of bit lines, and transmit the fourth neural network data via the plurality of word lines. A three-dimensional memory device as described in claim 16, wherein a portion of the plurality of sub-arrays receives the first neural network data via the plurality of word lines, transmits the third neural network data via the plurality of bit lines and receives the second neural network data, and then transmits the fourth neural network data via the plurality of word lines, and another portion of the plurality of sub-arrays receives the first neural network data via the plurality of bit lines, transmits the third neural network data via the plurality of word lines and receives the second neural network data, and then transmits the fourth neural network data via the plurality of bit lines. A three-dimensional memory device as described in claim 10, wherein the first neural network data, the second neural network data, the third neural network data and the fourth neural network data are different from each other and are all related to a neural network layer in one of the at least one neural network model. A three-dimensional memory device as described in claim 19, wherein the plurality of sub-arrays receive the first neural network data via the plurality of word lines, receive the second neural network data via the plurality of bit lines, and the plurality of sub-arrays transmit the third neural network data via the plurality of bit lines, and transmit the fourth neural network data via the plurality of word lines.

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