TWI883829B - Memory device and method of fabricating the same - Google Patents

Abstract

A memory device includes a stacked structure, a second conductive layer, channel pillars, and a string selection line cut slit. The stacked structure includes first insulating layers and first conductive layers stacked alternately. The second conductive layer is above the stacked structure. The channel pillars extend through the second conductive layer and the stacked structure. Each channel pillar includes a first portion and a second portion. The first portion extends through the stacked structure. The second portion is located on the first portion and extends through the second conductive layer. A diameter of the first portion is greater than a diameter of the second portion. The string selection line cut slit extends through the second conductive layer and is disposed between the second portions of two adjacent channel pillars. The memory device can be applied to 3D NAND flash memory to create memory devices with high capacity and performance.

Description

Memory device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a memory device and a manufacturing method thereof.

Non-volatile memory has the advantage that the stored data will not disappear after power failure, so it is widely used in personal computers and other electronic devices. The three-dimensional memory commonly used in the industry currently includes NOR memory and NAND memory. In addition, another type of three-dimensional memory is AND memory, which can be applied to multi-dimensional memory arrays and has high integration and high area utilization, and has the advantages of fast operation speed. Therefore, the development of three-dimensional memory components has gradually become the current trend.

The present invention provides a memory element and a manufacturing method thereof, which can reduce the distance between elements to reduce the chip area occupied.

An embodiment of the present invention proposes a memory element, including: a stacking structure, a second conductive layer, a plurality of channel pillars, a plurality of charge storage structures, and a string selection line cutting wall. The stacking structure includes a plurality of first insulating layers and a plurality of first conductive layers stacked alternately. The second conductive layer is above the stacking structure. A plurality of channel pillars extend through the second conductive layer and the stacking structure. Each channel pillar includes a first portion and a second portion. The first portion extends through the stacking structure. The second portion is located on the first portion and extends through the second conductive layer. The diameter of the first portion is greater than the diameter of the second portion. A plurality of charge storage structures surround the plurality of channel pillars and are in contact with the second conductive layer. The string selection line cutting wall extends through the second conductive layer and is disposed between the second portions of two adjacent channel pillars among the plurality of channel pillars.

An embodiment of the present invention proposes a memory element, including: a stacking structure, a second conductor layer, a string selection line cutting wall, a plurality of first channel columns, and a plurality of second channel columns. The stacking structure includes a plurality of insulating layers and a plurality of first conductor layers stacked alternately. The second conductor layer is located between the stacking structure and an internal connection layer having a plurality of conductor plugs. The string selection line cutting wall has a wavy shape from a top view, and the string selection line cutting wall extends through the second conductor layer and divides the second conductor layer into a first sub-region and a second sub-region. A plurality of first channel columns extend through the second conductor layer in the first sub-region and the stacking structure. A plurality of second channel columns extend through the second conductor layer in the second sub-region and the stacking structure.

An embodiment of the present invention provides a method for manufacturing a memory element, comprising the following steps. A plurality of first openings are formed in a stacked structure. The stacked structure includes a plurality of first insulating layers and a plurality of intermediate layers alternately stacked above a substrate. The plurality of first openings are filled with a sacrificial material. A conductive layer is formed above the stacked structure. The conductive layer is patterned to form a plurality of second openings and trenches between the plurality of second openings, wherein the width of the trenches is less than the plurality of diameters of the plurality of second openings. The sacrificial material is removed to expose the plurality of first openings located below the plurality of second openings. A plurality of channel pillars are formed in the plurality of first openings and the plurality of second openings. A string selection line cutting wall is formed in the trench.

Based on the above, the memory device and the manufacturing method thereof of the embodiment of the present invention can reduce the distance between devices to reduce the chip area occupied.

As device sizes continue to shrink, the distance between devices must also be reduced to reduce the chip area occupied. The present invention changes the structure of the drain-side select gate, the channel column, and the string select wire cutting wall to reduce the distance between the string select wire cutting wall and the channel column, thereby saving chip area.

1A to 1J are cross-sectional schematic diagrams of a manufacturing process of a memory device according to an embodiment of the present invention.

Referring to FIG. 1A , a substrate 100 is provided. The substrate 100 includes an array region (not shown) and a step region (not shown). The substrate 100 is, for example, a semiconductor substrate. A stacking structure SK1 is formed on the substrate 100. The stacking structure SK1 can also be referred to as an insulating stacking structure SK1. In this embodiment, the stacking structure SK1 includes an insulating layer 102 and an intermediate layer 104 stacked sequentially and alternately on the substrate 100. The insulating layer 102 is, for example, a silicon oxide layer. The intermediate layer 104 is, for example, a silicon nitride layer. The intermediate layer 104 can be used as a sacrificial layer and partially removed in a subsequent process. 4 , in one embodiment, a device 60, an interconnect structure 70, and a source line SL may be formed between the substrate 100 and the stacked structure SK1. The device layer 60 may include a complementary metal oxide semiconductor device. In other embodiments, the stacked structure SK1 is formed on the substrate 100.

Next, the stacked structure SK1 is patterned to form a step structure (not shown) in the step region. Thereafter, a dielectric layer (not shown) is formed on the step structure. The material of the dielectric layer (not shown) is, for example, silicon oxide. The dielectric layer (not shown) can be planarized by a planarization process, such as a chemical mechanical polishing process.

Next, referring to FIG1B , a plurality of openings OP1 are formed in the array region of the stacking structure SK1 . The openings OP1 pass through the stacking structure SK1 and further extend to the lower layer (not shown). In the present embodiment, the openings OP1 have a circular outline (not shown) from the top view, but the present invention is not limited thereto.

Referring to FIG. 1C , a sacrificial material is formed on the stacked structure SK1 and in the opening OP1, and then an etching back or chemical mechanical polishing process is performed to remove the excess sacrificial material on the stacked structure SK1 to form a plurality of sacrificial columns 106 in the plurality of openings OP1. The material of the sacrificial column 106 is different from that of the insulating layer 102 and the intermediate layer 104. The sacrificial column 106 is, for example, amorphous silicon, tungsten or a carbon-containing organic material. The carbon-containing organic material may be a polymer, such as a photoresist. The photoresist may be a positive photoresist or a negative photoresist. The material of the sacrificial column 106 is not limited thereto, and other materials may also be used. The sacrificial column 106 has a circular profile (not shown).

1C , a stacked structure SK2 is formed on the stacked structure SK1. In the present embodiment, the stacked structure SK2 may include an insulating layer 202, a conductive layer 204 (or referred to as a drain select gate or SGD), and an insulating layer 206. The materials of the insulating layers 202 and 206 may be the same or similar to the insulating layer 102, respectively. The material of the conductive layer 204 may be a semiconductor, a metal, a metal silicide, or a combination thereof. The semiconductor may be, for example, polycrystalline silicon. The metal may be, for example, tungsten. The metal silicide may be, for example, titanium silicide. The conductive layer 204 may be a single layer or multiple layers.

Referring to FIG. 1D , lithography and etching processes are then performed to pattern the stacked structure SK2 to form a plurality of openings OP2 and a cutting trench ST1. The openings OP2 expose the sacrificial pillars 106 respectively. The cutting trench ST1 exposes the topmost intermediate layer 104. The width W0 of the cutting trench ST1 is smaller than the width W2 of the opening OP2. The cutting trench ST1 has a strip shape (not shown).

Referring to FIG. 1E , the plurality of sacrificial pillars 106 exposed by the plurality of openings OP2 are removed to form a plurality of openings OP1. When the plurality of sacrificial pillars 106 are carbon-containing organic materials, a dry removal method, such as an oxygen plasma ashing method, can be used to remove them without problems such as over-etching or insufficient etching depth of the opening OP1. The width W1 of the opening OP1 is greater than the width W2 of the opening OP2.

Then, referring to FIG. 1F , a charge storage structure 108 and a channel column CP are formed in the openings OP2 and OP1 , and a string selection line cutting wall SSLC is formed in the cutting trench ST1 . For clarity, FIG. 2A shows an enlarged schematic diagram of the region 200 of FIG. 1F . The formation method of the charge storage structure 108 and the channel column CP can be described in detail later with reference to FIG. 2A .

1F and 2A, a charge storage structure 108 is formed in the openings OP2 and OP1 (shown in FIG. 1F). The charge storage structure 108 may include a blocking layer 124, a charge storage layer 123, and a tunneling layer 122. The tunneling layer 122 is, for example, silicon oxide. The charge storage layer 123 is, for example, silicon nitride. The blocking _layer 124 is, for example, silicon oxide or a material with a high dielectric constant greater than or equal to 7, such as _aluminum oxide ( _Al2O3 ), helium oxide ( _HfO2 ), ruthenium oxide ( _La2O5 ), transition metal oxide, ruthenium oxide, or a combination thereof. In an embodiment of the present invention, the charge storage structure 108 is also filled into the cleaving trench ST1. The width W0 of the cleaving trench ST1 is less than twice the thickness T3 of the charge storage structure 108. Therefore, at this stage, the cleaving trench ST1 will be filled with the charge storage structure 108 to form the string selection line cutting wall SSLC. The width W2 of the opening OP2 and the width W1 of the opening OP1 are greater than the width W0 of the cleaving trench ST1 and greater than twice the thickness T3 of the charge storage structure 108. That is, W0＜2T3＜W2＜W1. Therefore, the charge storage structure 108 cannot fill the openings OP2 and OP1.

Referring to FIG. 1F and FIG. 2A , a channel column CP is formed in the remaining space of the openings OP2 and OP1 (shown in FIG. 1F ). First, a channel layer 110 is formed on the charge storage structure 108. In one embodiment, the material of the channel layer 110 includes polysilicon. In one embodiment, the channel layer 110 covers the charge storage structure 108 on the sidewalls of the openings OP2 and OP1, and also covers the channel layer 110 on the bottom surface of the opening OP1 (not shown). Next, an insulating layer 112 is formed in the openings OP2 and OP1. In one embodiment, the material of the insulating layer 112 includes silicon oxide. In this embodiment, since the width W2 of the opening OP2 is smaller than the width W1 of the opening OP1, the insulating layer 112 will fill the remaining space of the opening OP2 and seal the opening OP2. The width W1 of the opening OP1 is larger, and the insulating layer 112 is on the inner surface of the channel layer 110. The remaining space cannot be filled by the insulating layer 112, so an air gap AG covered by the insulating layer 112 is formed in the opening OP1.

Afterwards, the insulating layer 112 and the channel layer 110 in the opening OP2 are etched back to form a groove (not shown), and then a conductive cap 114 is formed in the groove. In one embodiment, the material of the conductive cap 114 includes polysilicon. Afterwards, a chemical mechanical planarization process is performed to remove the excess charge storage structure 108, the insulating layer 112, and the channel layer 110 on the insulating layer 206. The channel layer 110, the insulating layer 112, and the conductive cap 114 can be collectively referred to as a channel column CP. The charge storage structure 108 surrounds the vertical outer surface of the channel column CP.

1G, a capping insulating layer 128 is formed on the insulating layer 206. The capping insulating layer 128 includes silicon oxide, silicon nitride or a combination thereof. The capping insulating layer 128 can be a single layer or multiple layers. Thereafter, a patterning process is performed to form a plurality of separation trenches ST2. The separation trenches ST2 extend through the stacked structures SK2 and SK1.

Referring to FIG. 1H , an etching process, such as a wet etching process, is performed to remove the multi-layer intermediate layer 104 around the separation trench ST2 to form a plurality of horizontal openings (not shown). Afterwards, a barrier layer 125 and a gate layer (or conductor layer) 126 are formed in the horizontal openings. The material of the barrier layer 125 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The gate layer 126 can also be referred to as a word line WL. The gate layer 126 is, for example, tungsten, cobalt, or ruthenium. The barrier layer 125 and the gate layer 126 are formed by, for example, sequentially forming a barrier material and a conductive material in the separation trench ST2 and the horizontal opening, and then performing an etching back process to form the barrier layer 125 and the gate layer 126 in the plurality of horizontal openings. Thus, the stacked structure GSK is formed. The stacked structure GSK has a memory array composed of a plurality of memory cells MC formed by the gate layer 126, the channel pillar CP and the charge storage structure 108.

Referring to FIG. 1I , a separation wall SLT is formed in the separation trench ST2. The method for forming the separation wall SLT includes filling an insulating liner material and a conductive material on the top insulating layer 128 and in the separation trench ST2. The insulating liner material is, for example, silicon oxide. The conductive material is, for example, polycrystalline silicon, titanium/titanium nitride, tungsten or a combination thereof. Then, the excess insulating liner material and conductive material on the top insulating layer 128 are removed by an etching back process or a planarization process to form a liner 142 and a conductive layer 144. The liner 142 and the conductive layer 144 are collectively referred to as the separation wall SLT. In some other embodiments, the conductive layer 144 of the partition wall SLT may further cover the air gap. In other embodiments, the partition wall SLT may be completely filled with insulating material without any conductive layer. In other embodiments, the partition wall SLT may also be a liner 142, and the liner 142 covers the air gap AG without any conductive layer.

Referring to FIG. 1J , a dielectric layer 130 is formed on the top insulating layer 128. The dielectric layer 130 is, for example, silicon oxide. Thereafter, a conductive plug COA is formed in the dielectric layer 130. The conductive plug COA is formed, for example, by forming a contact hole (not shown) in the dielectric layer 130. The contact hole exposes the top surface and upper sidewall of the conductive cap layer 114. Then, a barrier layer 132 and a conductive layer 134 are formed in the contact hole. The material of the barrier layer 132 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The conductive layer 134 is, for example, tungsten. The barrier layer 132 and the conductive layer 134 are formed by, for example, sequentially forming a barrier material and a conductive material on the dielectric layer 130 and in the contact hole, and then performing an etch back process or a chemical mechanical polishing process to form a conductive plug COA in the contact hole. Referring to FIG. 4 , before, after, or at the same time as the conductive plug COA is formed, a conductive plug COA1 connected to the conductive layer 204 and a conductive plug COA2 connected to the gate layer 126 may be formed. Thereafter, subsequent processes are performed, such as forming a via 136, a bit line BL, an internal connection structure 138, and a protective layer 140.

Fig. 2A and Fig. 2B are enlarged schematic diagrams of the local area 200 of Fig. 1F and Fig. 1J, respectively. Fig. 3A is a top view of the line A-A' of Fig. 1J. Fig. 3B is a top view of the line B-B' of Fig. 1J.

2A , in an embodiment of the present invention, each of the channel pillars CP includes a first portion P1 and a second portion P2. The first portion P1, below the second portion P2, extends through the stack structure GSK. The first portion P1 includes a channel pillar 110 and an insulating layer 112 and an air gap AG surrounded by the insulating layer 112. The second portion P2 is located on the first portion P1 and extends through the insulating layer 202, the conductive layer 204 (SGD), and the insulating layer 206. The second portion P2 is above the first portion P1 and connected to the first portion P1. The second portion P2 includes a conductive cap 114, an insulating layer 112, and a channel layer 110. The insulating layer 112 is located below the conductive cap 114. The channel layer 110 is located below the conductive cap 114 and between the charge storage structure 108 and the insulating layer 112. There is no air gap AG in the second portion P2.

2A, 3A and 3B, the diameter D1 of the first portion P1 is greater than the diameter D2 of the second portion P2. In two adjacent channel columns CP, the distance d2 between the two second portions P2 is greater than the distance d1 between the two first portions P1.

2B , in an embodiment of the present invention, the charge storage structure 108 surrounds the outer surface of the channel column CP. More specifically, the charge storage structure 108 surrounds the conductive cap 114, the channel layer 110, and the insulating layer 112. In this embodiment, the top surfaces of the charge storage layer 123 and the tunneling layer 122 of the charge storage structure 108 also contact the bottom surface of the conductive plug COA. The blocking layer 124 of the charge storage layer 123 also extends upward to cover the lower sidewall of the conductive plug COA. In this embodiment, the charge storage structure 108 contacts the insulating layer 206 , the conductive layer 204 , the insulating layer 202 , the gate layer 126 , and the sidewall of the insulating layer 102 .

Referring to FIG. 2B , in an example of the present invention, the conductive layer 204 (SGD) can be used as a drain-end select gate. The conductive layer 204 is above the topmost gate layer 126 of the stacked structure GSK. The thickness T2 of the conductive layer 204 is greater than the thickness T1 of the gate layer 126. In some embodiments, the thickness T2 of the conductive layer 204 is 1.5 to 15 times the thickness T1 of the gate layer 126. The top view of the conductive layer 204 is shown in FIG. 3B .

Referring to Figure 3B, the partition wall SLT and the string selection line cutting wall SSLC extend in the same direction, for example, along direction X. The string selection line cutting wall SSLC is located between the partition walls SLT. The shape of the string selection line cutting wall SSLC is different from the shape of the partition wall SLT. In the present embodiment, in the top view, the partition wall SLT has a strip shape, and the string selection line cutting wall SSLC has a wavy shape. The string selection line cutting wall SSLC is conformal with part of the side walls of multiple channel columns CP1 and part of the side walls of multiple channel columns CP2.

Referring to Figures 1J and 3B, the separation wall SLT divides the conductor layer 204 and the stacking structure GSK thereunder (shown in Figure 2B) into a plurality of blocks B. The string selection line cutting wall SSLC passes through the conductor layer 204 and divides the conductor layer 204 into a plurality of sub-regions SB1 and SB2. In other words, the string selection line cutting wall SSLC is between the sub-regions SB1 and SB2, so the area around the string selection line cutting wall SSLC can also be referred to as the interface region IR. The channel column CP1 extends through the conductor layer 204 and the stacking structure GSK of the sub-region SB1, respectively. The channel column CP2 extends through the conductor layer 204 and the stacking structure GSK of the sub-region SB2, respectively. The string selection line cutting wall SSLC is disposed between the channel columns CP1 and CP2, as shown in Figures 1I and 3B.

Referring to FIG. 2A and FIG. 3B , in the present embodiment, the string selection line cutting wall SSLC also does not pass through the dummy column. There is no dummy column in the area (also called the interface area) IR surrounding the string selection line cutting wall SSLC, so the string selection line cutting wall SSLC is very close to the adjacent channel column CP1 or CP2. Since there is no need to set up a dummy column in the interface area IR, the area of the chip can be saved. The dummy column described herein can have a similar structure to the channel column CP and the charge storage structure 108, but does not provide a data storage function.

2B and 3A, in the present embodiment, the distance d3 between the string selection line cutting wall SSLC and the second portion P2 of the adjacent channel column CP is very small. The distance d3 may be smaller than the distance d4 between the separation wall SLT and the second portion P2 of the adjacent channel column CP. The distance d3 is also smaller than the distance d2 between the second portions P2 of the adjacent channel columns CP.

2A and 3A , the string selection wire cutting wall SSLC passes through the insulating layer 206, the conductive layer 204, and the insulating layer 202, and lands on the top conductive layer 126 of the stacked structure GSK without extending beyond the top conductive layer 126. In other words, the string selection wire cutting wall SSLC passes through the single thick conductive layer 204 (SGD) above the stacked structure GSK, and does not pass through any thin conductive layer 126 of the stacked structure GSK. The side walls SW1 and SW2 of the string selection wire cutting wall SSLC are in contact with the conductive layer 204 (SGD).

The size of the string selection line cutting wall SSLC is quite small. Referring to Figure 2A, the width W0 of the string selection line cutting wall SSLC is smaller than the combined width W2 of the second part P2 of the channel column CP and the charge storage structure 108 surrounding it. The width W0 of the string selection line cutting wall SSLC is greater than the thickness T3 of the charge storage structure 108 and less than twice the thickness T3 of the charge storage structure 108. The string selection line cutting wall SSLC includes the tunneling layer 122, the charge storage layer 123 and the blocking layer 124 of the charge storage structure 108. The string selection line cutting wall SSLC does not include the channel layer 110.

2B , the conductive plug COA extends through the dielectric layer 228 and is electrically connected to the conductive cap 114 of the channel column CP. The conductive plug COA has an inverted U-shape. The main body MP of the conductive plug COA contacts the top surface and upper sidewall of the conductive cap 114. The bottom surface and lower sidewall of the extended portion EP of the conductive plug COA contacts the charge storage structure 108.

Referring to FIG. 4 , in at least one embodiment, as described in the previous paragraph, the stacked structure (having a memory array) of the present invention may have a device layer 60, an internal connection structure 70, and a source line layer SL below the GSK and above the substrate 100. The device layer 60 may include complementary metal oxide semiconductor devices. In some embodiments, these complementary metal oxide semiconductor devices and the internal connection structure 70 may be formed before the stacked structure GSK is formed, and thus are located below the memory array. This type of memory is also called a complementary metal oxide semiconductor device below the memory array (CMOS under Array, CuA) structure memory. Referring to FIG. 5 , in some other embodiments, before forming the stacking structure GSK, a source line layer SL is first formed on the substrate 100 (shown in FIG. 1J ). After that, after forming the stacking structure GSK, the stacking structure SK2, the conductive plugs COA, COA1, COA2 and the bit line BL on the substrate 100 according to the method of the aforementioned embodiment, a bonding layer 80A is first formed. Then, a substrate 50 having the component layer 60 and the internal connection structure 70 and the bonding layer 80B as described in the previous paragraph is provided. Then, the substrate 100 is turned over. The bonding layer 80A and the bonding layer 80B are bonded to each other to form the bonding structure 80. The substrate 100 can be ground to be completely removed or thinned (not shown), and then the internal connection structure 138 and the protective layer 140 are formed on the stacking structure GSK. The substrate 50, the device layer 60, the interconnect structure 70 and the bonding layer 80 are located below the stacked structure GSK. The second portion P2 of the channel column CP is close to the substrate 50. The first portion P1 of the channel column CP is away from the substrate 50. This complementary metal oxide semiconductor device is formed below the memory array by bonding, and this type is also called a complementary metal oxide semiconductor device bonding memory array (CMOS bonding Array, CbA) structure.

Based on the above, the memory device and its manufacturing method of the embodiment of the present invention can reduce the size of the string selection line cutting wall and reduce the distance between the string selection line cutting wall and the channel pillar to reduce the chip area occupied. Furthermore, the present invention can simplify the process and can be integrated with the existing process to increase the integration degree, increase the process yield, and reduce the manufacturing cost.

100, 50: substrate 60: device layer 70, 138: interconnect structure 80A, 80B: junction layer 80: junction structure 102, 202; 206: insulating layer 104: intermediate layer 106: sacrificial pillar 108: charge storage structure 110: channel layer 112: insulating layer 114: conductive cap 122: tunneling layer 123: charge storage layer 124: blocking layer 125, 132: barrier layer 126: conductive layer/gate layer 134, 204, SGD: conductive layer 136: via 140: protective layer 142: liner 144: conductor layer 200: local area A-A’, B-B’: line AG: air gap B: block BL: bit line CP, CP1, CP2: channel pillar d1, d2, d3, d4: distance D1, D2: diameter COA, COA1, COA2: conductor plug EP: extension IR: interface region MP: main body OP1, OP2: opening P1: first part P2: second part B: block SB1, SB2: sub-area SK1, SK2, GSK: stacking structure ST1: cutting trench ST2: separation trench SSLC: string select line cutting wall SL: source line SLT: separator wall SW1, SW2: side wall T1, T2, T3: thickness W0, W1, W2: width W0, W1, W2: width WL: word line X, Y: direction

Figures 1A to 1J are cross-sectional schematic diagrams of a manufacturing process of a memory element according to an embodiment of the present invention. Figures 2A and 2B are enlarged schematic diagrams of local areas of Figures 1F and 1J, respectively. Figure 3A is a top view of line A-A' of Figure 1J. Figure 3B is a top view of line B-B' of Figure 1J. Figure 4 is a cross-sectional schematic diagram of a complementary metal oxide semiconductor element under a memory array (CMOS under Array, CuA) structured memory element according to an embodiment of the present invention. Figure 5 is a cross-sectional schematic diagram of a complementary metal oxide semiconductor element bonded to a memory array (CMOS bonding Array, CbA) structured memory element according to an embodiment of the present invention.

SLT:Separation wall

SB1, SB2: sub-areas

B: Block

142: Lining

144: Conductor layer

204: Conductor layer

CP, CP1, CP2: channel column

P2: Part 2

SSLC: String Select Wire Cutting Wall

108: Charge storage structure

122: Tunneling layer

123: Charge storage layer

124: barrier layer

X, Y: direction

IR: Interface region

d2, d3, d4: distance

D2: Diameter

Claims (18)

A memory element comprises: A stacking structure comprising a plurality of first insulating layers and a plurality of first conductive layers stacked alternately; A second conductive layer, located above the stacking structure; A plurality of channel pillars, extending through the second conductive layer and the stacking structure, wherein each of the plurality of channel pillars comprises: A first portion, extending through the stacking structure; and A second portion, located on the first portion and extending through the second conductive layer, wherein the diameter of the first portion is greater than the diameter of the second portion; A plurality of charge storage structures, surrounding the plurality of channel pillars and contacting the outer wall of the second conductive layer; and A string selection line cutting wall, extending through the second conductive layer and disposed between the second portions of two adjacent channel pillars among the plurality of channel pillars, The bottom surface of the string selection line cutting wall contacts the top surface of the first conductive layer at the top of the stacked structure. The memory device as described in claim 1 further includes a substrate located below the stacking structure. A memory element as described in claim 1, wherein a second distance between the multiple second portions of two adjacent channel pillars is greater than a first distance between the multiple first portions of the two adjacent channel pillars. A memory device as described in claim 3, wherein a third distance between the string select line cutting wall and a second portion of an adjacent channel column is smaller than the second distance. A memory device as described in claim 1, wherein the area between the string select line cutting wall and the second portion of the adjacent channel pillar is free of dummy pillars. The memory device as described in claim 3 further includes a partition wall extending through the second conductive layer and the stack structure, wherein a fourth distance between the partition wall and the second portion of another channel column is greater than the third distance. A memory device as described in claim 1, wherein a side wall of the string selection line cutting wall is in contact with the second conductive layer. A memory element as described in claim 1, wherein the thickness of the second conductive layer is thicker than the thickness of each of the multiple first conductive layers. A memory element as described in claim 1, wherein the second portion includes: a conductive cap; a second insulating layer located below the conductive cap; and a channel layer located between the charge storage structure and the second insulating layer, wherein the charge storage structure surrounds the channel layer, the second insulating layer and the conductive cap, and contacts the second conductive layer. A memory device as described in claim 9, wherein the width of the string select line cutting wall is less than twice the thickness of the charge storage structure. A memory device as described in claim 9, wherein the string select line cutting wall includes the charge storage structure but without a channel layer. A memory element as described in claim 9, wherein the first portion includes an air gap surrounded by the second insulating layer, and the second portion does not have an air gap. A memory element as described in claim 1, wherein the string selection line cutting wall has a wavy shape when viewed from a top view. A memory element, comprising: A stacking structure, comprising a plurality of insulating layers and a plurality of first conductive layers stacked alternately; A second conductive layer, located between the stacking structure and an internal connection layer having a plurality of conductive plugs; A string selection line cutting wall, extending through the second conductive layer; A plurality of first channel pillars, extending through the second conductive layer and the stacking structure in a first sub-region; and A plurality of second channel pillars, extending through the second conductive layer and the stacking structure in a second sub-region, wherein the string selection line cutting wall is disposed between the plurality of first channel pillars and the plurality of second channel pillars, and has a wavy shape in a top view and divides the second conductive layer into a first sub-region and a second sub-region, The bottom surface of the string selection line cutting wall contacts the top surface of the first conductive layer at the top of the stacked structure. The memory device as described in claim 14 further includes a separation wall extending through the second conductive layer and the stacking structure, wherein the separation wall has a strip shape which is different from the wavy shape of the string selection line cutting wall. A memory element as described in claim 14, wherein there is no dummy pillar in the interface area between the first sub-region and the second sub-region. A memory device as described in claim 14, wherein the string selection line cutting wall is conformal with a portion of the sidewalls of the plurality of first channel pillars and a portion of the sidewalls of the plurality of second channel pillars. A method for manufacturing a memory element, comprising: forming a plurality of first openings in a stacked structure, wherein the stacked structure comprises a plurality of first insulating layers and a plurality of intermediate layers stacked alternately; filling the plurality of first openings with a sacrificial material; forming a conductive layer on the stacked structure; patterning the conductive layer to form a plurality of second openings and trenches between the plurality of second openings, wherein the width of the trenches is smaller than the widths of the plurality of second openings; removing the sacrificial material to expose the plurality of first openings located below the plurality of second openings; forming a plurality of channel pillars in the plurality of first openings and the plurality of second openings; and forming a string selection line cutting wall in the trenches.