TWI883767B - Trench type semiconductor device - Google Patents

Abstract

A trench type semiconductor device includes: a substrate, a plurality of first conductive electrodes, a plurality of second conductive electrodes, a plurality of heavily-doped regions, and a plurality of source contacts. The substrate has a plurality of trenches, the first conductor electrode is disposed at the bottom of each trench, and the second conductor electrode is disposed in each trench above the first conductor electrode. The heavily-doped regions are disposed on the surface of the substrate between the trenches. The source contacts are respectively connected to the heavily-doped regions and a first part of the plurality of second conductive electrodes, so that the first part and the heavily-doped regions are equipotential.

Description

Trench semiconductor components

The present invention relates to a trench semiconductor device, and more particularly to a trench semiconductor device with improved figure of merit (FOM).

The quality factor (FOM) of a transistor component is determined by the product of the on-resistance (Ron) and the gate-to-drain capacitance (Qgd). Currently, in order to improve the energy conversion efficiency of transistor components and suppress power loss, the quality factor (FOM) of transistor components must be reduced. Therefore, how to effectively reduce the quality factor of transistor components is the current goal of continuous efforts.

The present invention provides a trench semiconductor device that can improve the quality factor (FOM) by reducing Qgd without changing the process or device design.

The trench semiconductor element of the present invention comprises a substrate, a plurality of first conductor electrodes, a plurality of second conductor electrodes, a plurality of heavily doped regions and a plurality of source contact windows. The substrate has a plurality of trenches, the first conductor electrodes are arranged at the bottom of each trench, and the second conductor electrodes are arranged in each trench above the first conductor electrodes. The heavily doped regions are arranged on the surface of the substrate between the trenches. The source contact windows are respectively connected to the heavily doped regions and the first part of the plurality of second conductor electrodes, so that the aforementioned first part and the heavily doped regions have the same potential.

In one embodiment of the present invention, a second portion of the plurality of second conductive electrodes is electrically connected to a gate potential.

In one embodiment of the present invention, the ratio of the first part to the second part is 1/99 to 99/1.

In one embodiment of the present invention, the ratio of the first part to the second part is 1/2 to 2/1.

In one embodiment of the present invention, one end of the plurality of second conductive electrodes has an extension portion, and the trench semiconductor element may further include a gate bus and a plurality of gate contact windows. The gate bus is disposed above the extension portion, and the gate contact windows are respectively connected to the gate bus and the extension portion of the second portion of the plurality of second conductive electrodes.

In an embodiment of the present invention, an extending direction of the gate busbar is perpendicular to an extending direction of the extending portion.

In one embodiment of the present invention, the trench semiconductor device may further include a source bus bar disposed on the source contact window and connected to the source contact window.

In one embodiment of the present invention, the trench semiconductor device may further include an inter-gate dielectric layer disposed between the first conductive electrode and the second conductive electrode.

In one embodiment of the present invention, the trench semiconductor device may further include a gate dielectric layer disposed between the second conductive electrode and the heavily doped region.

In one embodiment of the present invention, the trench semiconductor device may further include a bottom oxide layer disposed between the first conductive electrode and the substrate.

In one embodiment of the present invention, the trench semiconductor element may further include a plurality of well regions disposed between the trenches and surrounding the heavily doped region, and the conductivity type of the well regions is different from the conductivity type of the heavily doped region.

Based on the above, the present invention can reduce the gate-to-drain capacitance (Qgd) through layout design, thereby improving the quality factor of trench semiconductor devices without changing the original process or device design.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The following description provides a number of embodiments for implementing different features of the present invention. In addition, these embodiments are exemplary only and are not intended to limit the scope and application of the present invention. Moreover, for the sake of clarity, the relative sizes (e.g., length, thickness, spacing, etc.) and relative positions of regions or structural components may be reduced or enlarged. In addition, similar or identical element symbols used in different figures represent similar or identical components or features.

Fig. 1 is an exemplary layout diagram of a trench semiconductor device according to an embodiment of the present invention, and thus only part of the components are shown. Fig. 2 is a cross-sectional schematic diagram of the trench semiconductor device of Fig. 1 along the II-II' line segment, in which a relatively complete component is shown.

1 and 2, the trench semiconductor device of the present embodiment includes a substrate 100, a plurality of first conductive electrodes 102, a plurality of second conductive electrodes (including a first portion 104' and a second portion 104), a plurality of heavily doped regions 106, and a plurality of source contact windows 110a and 110b. The substrate 100 has a plurality of trenches T, wherein the substrate 100 may include a semiconductor material and an epitaxial layer formed thereon. The first conductor electrode 102 is disposed at the bottom of each trench T, and the second conductor electrode (including the first portion 104' and the second portion 104) is disposed in each trench T above the first conductor electrode 102, wherein the first conductor electrode 102 and the second conductor electrode (the first portion 104' and the second portion 104) are, for example, polysilicon structures. The heavily doped region 106 is disposed on the surface of the substrate 100 between the trenches T, and the heavily doped region 106 serves as the source of the trench semiconductor device. As for the drain 108 of the trench semiconductor device, it is usually disposed at the bottom of the substrate 100. In this embodiment, source contacts 110a and 110b are formed in the inner dielectric layer ILD, and the source contact 110a is connected to the heavily doped region 106, and the source contact 110b is connected to the first portion 104' in the second conductor electrode, so that the first portion 104' and the heavily doped region 106 are at the same potential. As for the first conductor electrode 102, it can be electrically connected to the heavily doped region 106 through other lines (not shown).

Please continue to refer to FIG. 1. In this embodiment, there are 6 second conductive electrodes, 3 of which (first portion 104') are at the same potential as the heavily doped region 106 through the source contact window 110b, so the ratio of the first portion 104' to the second portion 104 is 1/1. However, the present invention is not limited thereto. In one embodiment, the ratio of the first portion 104' to the second portion 104 is 1/99 to 99/1. In another embodiment, the ratio of the first portion to the second portion is 1/2 to 2/1.

As for the second portion 104 in the second conductor electrode, it is electrically connected to the gate potential. For example, one end of the second conductor electrode in FIG. 1 has an extension portion 104a, and the trench semiconductor device may further include a gate bus 112 and a plurality of gate contacts 114, wherein the gate bus 112 is disposed above the extension portion 104a, and the gate contacts 114 are respectively connected to the gate bus 112 and the extension portion 104a of the second portion 104 in the second conductor electrode. In one embodiment, the extension direction of the gate bus 112 is perpendicular to the extension direction of the extension portion 104a.

Please refer to FIG. 1 and FIG. 2 again. The trench semiconductor device may further include a source bus 116 disposed on the source contact windows 110a and 110b and connected to the source contact windows 110a and 110b. The trench semiconductor device of the present embodiment may further include a gate dielectric layer, such as an inter-polysilicon oxide layer IPO, disposed between the first conductor electrode 102 and the second conductor electrode (including the first portion 104' and the second portion 104). The trench semiconductor device of the present embodiment may further include a gate dielectric layer 118, such as a gate oxide layer, disposed between the second conductor electrode (including the first portion 104' and the second portion 104) and the heavily doped region 106. The trench semiconductor device of the present embodiment may further include a bottom oxide layer 120 disposed between the first conductor electrode 102 and the substrate 100, and the bottom oxide layer 120 is thicker to withstand a high breakdown voltage. The trench semiconductor device of the present embodiment may further include a plurality of well regions 122 disposed between the trenches T and surrounding the heavily doped region 106, and the conductivity type of the well region 122 is different from the conductivity type of the heavily doped region 106. In one embodiment, the well region 122 is a P-type well and the heavily doped region 106 is an N+ region; in another embodiment, the well region 122 is an N-type well and the heavily doped region 106 is a P+ region.

The improved characteristics of the trench semiconductor device of the present invention will be described with reference to FIG3. FIG3 is a schematic diagram showing a circuit in the trench semiconductor device of FIG2.

In FIG3 , when current passes through the trench semiconductor device, the on-resistance Rsdon is composed of the epitaxial resistance R_EPI and the unilateral channel resistance R_channel because the first portion 104' and the heavily doped region 106 are at the same potential. In other words, compared with the conventional structure (the first portion 104' and the second portion 104 are both electrically connected to the gate potential), the channel resistance R_channel is doubled. However, since the path from the gate to the drain is reduced, the area 300 of the gate to drain capacitance (Qgd) is also reduced, so the quality factor (FOM) is improved. Furthermore, the size design and manufacturing process of the entire device do not need to be changed. It is only necessary to form the source contact window 110b connected to the first portion 104' at the same time as the source contact window 110a is formed.

If a general high voltage (120V) component is used as an example, the epitaxial resistance R_EPI accounts for about 85% of the on resistance Rsdon, the channel resistance R_channel accounts for about 15% of the on resistance Rsdon, and the area of the gate-to-drain capacitance (Qgd) is the proportion of the entire second conductor electrode (100%), then the FOM (= Qgd × Rsdon) is 100%. In contrast, the ratio of the first part 104' to the second part 104 of the present embodiment is 1/1, so the area 300 of the gate-to-drain capacitance (Qgd) is only half (50%), and the channel resistance R_channel becomes twice (30%), so the FOM is calculated to be 50% × (85%+ 15%×2)= 57.5%. Therefore, the design of the present invention can significantly reduce FOM and achieve significant improvement (about 40% improvement).

In an experiment in which the trench semiconductor device is a 200V device, only the ratio of the first part to the second part in the second conductive electrode is changed, and the rest of the device design remains unchanged, the results shown in Table 1 below can be obtained through experimental measurement.

Table 1 The ratio of the first part to the second part 2:1 1:1 1:2 Qgd [nC] 35% 50% 70% Rdson [mohm-mm ² ] 130% 113% 106% FOM 45% 56.5% 74.2% The "%" in Table 1 refers to the percentage with the value of the general device (the second conductor electrode is fully connected to the gate potential) as 100% as the comparison standard.

From Table 1, it can be seen that the FOM can be improved by adjusting the proportion of the first portion 104' with the same potential as the heavily doped region 106. Moreover, the present invention can be applied not only to high voltage components but also to medium voltage or low voltage components to improve the FOM of these components.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100: substrate 102: first conductor electrode 104: second part 104’: first part 104a: extension 106: heavily doped region 108: drain 110a, 110b: source contact window 112: gate busbar 114: gate contact window 116: source busbar 118: gate dielectric layer 120: bottom oxide layer 122: well area 300: region ILD: internal dielectric layer IPO: inter-polysilicon oxide layer R_EPI: epitaxial resistor R_channel: channel resistor T: trench

FIG. 1 is an exemplary layout diagram of a trench semiconductor element according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional diagram of a trench semiconductor element according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing a circuit in the trench semiconductor element of FIG. 2.

104: Part 2

104’: Part 1

104a: Extension

110a, 110b: source contact window

112: Gate busbar

114: Gate contact window

116: Source bus

Claims (9)

A trench semiconductor element comprises: A substrate having a plurality of trenches; A plurality of first conductor electrodes disposed at the bottom of each of the trenches; A plurality of second conductor electrodes disposed in each of the trenches above the plurality of first conductor electrodes, wherein one end of each of the second conductor electrodes has an extension portion; A plurality of heavily doped regions disposed on the surface of the substrate between the plurality of trenches; A plurality of source contact windows respectively connected to the plurality of heavily doped regions and the first portion of the plurality of second conductor electrodes, so that the first portion and the plurality of heavily doped regions have the same potential; A gate bus disposed above the extension portion; and A plurality of gate contact windows respectively connect the gate bus and the extension of the second portion of the plurality of second conductor electrodes, so that the second portion is electrically connected to the gate potential. A trench semiconductor device as described in claim 1, wherein the ratio of the first part to the second part is 1/99 to 99/1. A trench semiconductor device as described in claim 1, wherein the ratio of the first part to the second part is 1/2 to 2/1. A trench semiconductor device as described in claim 1, wherein the extension direction of the gate busbar is perpendicular to the extension direction of the extension portion. The trench semiconductor device as described in claim 1 further includes a source bus bar disposed on the plurality of source contact windows and connected to the plurality of source contact windows. The trench semiconductor device as described in claim 1 further includes a gate dielectric layer disposed between the plurality of first conductive electrodes and the plurality of second conductive electrodes. The trench semiconductor device as described in claim 1 further includes a gate dielectric layer disposed between the plurality of second conductive electrodes and the plurality of heavily doped regions. The trench semiconductor device as described in claim 1 further includes a bottom oxide layer disposed between the plurality of first conductive electrodes and the substrate. The trench semiconductor device as described in claim 1 further includes a plurality of well regions disposed between the plurality of trenches and surrounding the plurality of heavily doped regions, and the conductivity type of the plurality of well regions is different from the conductivity type of the plurality of heavily doped regions.

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