TWI883755B - Active gate driver - Google Patents

Abstract

An active gate driver comprises a gate voltage control terminal, a two-stage Miller plateau detector, a logic circuit, a feedback control circuit, and a second-order inverting buffer. The two-stage Miller plateau detector is used to detect whether the gate voltage at the gate voltage control terminal is on the Miller plateau. The logic circuit controls the driving force provided by the second-order inverting buffer to reduce the switching losses of power components and improve the overall efficiency of the circuit.

Description

Active Gate Actuator

The present invention relates to an active gate driver, and in particular to an active gate driver used in power devices.

The power components of the third generation semiconductors have the advantages of low on-resistance, high switching speed and high temperature resistance. They are currently widely used in the fields of renewable energy and automotive power. However, because the power components of the third generation semiconductors have high voltage and large current, they have large power consumption. In order to further reduce their power consumption, the development of appropriate gate drive circuits has become one of the development focuses. Gate driver circuits can be roughly divided into passive gate drivers (PGD) and active gate drivers (AGD). PGD has a simpler structure and lower cost, but its disadvantages are inflexible switching and high power consumption. AGD can be adjusted according to the feedback signal of the feedback circuit and has controllable driving force and better efficiency, but it also requires an additional control unit and has a more complex structure and higher manufacturing cost.

The main purpose of the present invention is to provide an active gate driver based on two-stage Miller plateau detection. The two-stage Miller plateau detector detects whether the gate voltage is at the Miller plateau and adjusts the control signal of the second-stage inverter buffer. When the gate voltage is at the Miller plateau, the driving force can be reduced to reduce power consumption.

An active gate driver of the present invention comprises a gate voltage control terminal, a two-stage Miller platform detector, a logic circuit, a feedback control circuit and a two-stage inverting buffer. The gate voltage control terminal is used to output a gate voltage. The two-stage Miller platform detector receives a high reference potential, a low reference potential and the gate voltage. The two-stage Miller platform detector is used to output a gate voltage. The high reference potential and the low reference potential determine whether the gate voltage is at the Miller platform, and the two-stage Miller platform detector outputs a Miller platform detection voltage. The logic circuit is electrically connected to the two-stage Miller platform detector, and the logic circuit receives the Miller platform detection voltage and a control signal. The logic circuit outputs a P-type The feedback control circuit receives the control signal and outputs a non-overlapping P-type control signal and a non-overlapping N-type control signal. The second-stage inverting buffer has a first-stage inverting buffer circuit and a second-stage inverting buffer circuit. The first-stage inverting buffer circuit is electrically connected to the logic circuit to receive the P-type control signal. and the N-type control signal, and a first-stage output node of the first-stage inverting buffer circuit is electrically connected to the gate voltage control end, the second-stage inverting buffer circuit is electrically connected to the feedback control circuit to receive the non-overlapping P-type control signal and the non-overlapping N-type control signal, and a second-stage output node of the second-stage inverting buffer circuit is electrically connected to the gate voltage control end.

The present invention detects whether the gate voltage is at the Miller platform through the two-stage Miller platform detector, and controls the first-stage inverter buffer circuit of the second-stage inverter buffer through the P-type control signal and the N-type control signal V _NS output by the logic circuit to adjust the driving force provided by the second-stage inverter buffer when the gate voltage is at the Miller platform, thereby reducing the power consumption of the entire circuit.

Please refer to FIG. 1 , which is a circuit diagram of an active gate driver 100 according to an embodiment of the present invention. The active gate driver 100 has a gate voltage control terminal N _g , a two-stage Miller platform detector 110 , a logic circuit 120 , a feedback control circuit 130 and a two-stage inverting buffer 140 .

The gate voltage control terminal _Ng is electrically connected to a power element (not shown), and is used to output a gate voltage _Vg to the power element to provide driving force. The power element can be a third generation semiconductor made of silicon carbide or gallium nitride material, but the present invention is not limited _thereto .

Referring to FIGS. 1 and 2 , the two-stage Miller platform detector 110 receives a high reference potential V _H , a low reference potential V _L and the gate voltage V _g , and the two-stage Miller platform detector 110 determines whether the gate voltage V _g is located at a Miller plateau by the high reference potential V _H and the low reference potential V _L , and the two-stage Miller platform detector 110 outputs a Miller platform detection voltage V _m . Referring to FIG. 2 , in this embodiment, the two-stage Miller platform detector 110 has a first comparator 111 , a second comparator 112 , a logic gate set 113 and a latch 114 . The first comparator 111 is electrically connected to the gate voltage control terminal _Ng , receives the high reference potential _VH and the gate voltage _Vg and outputs a first comparison signal C1, and the second comparator 112 is electrically connected to the gate voltage control terminal _Ng , receives the low reference potential _VL and the gate voltage V _g and outputs a second comparison signal C2. The logic gate group 113 is electrically connected to the first comparator 111 and the second comparator 112 to receive the first comparison signal C1 and the second comparison signal C2 and outputs a first logic signal L1 and a second logic signal L2. The latch 114 is electrically connected to the logic gate group 113 to receive the first logic signal L1 and the second logic signal L2, and the latch 114 outputs the Miller platform detection voltage _Vm .

Please refer to FIG. 2 . In this embodiment, the logic gate group 113 has an exclusive OR gate 113 a and an anti-exclusive OR gate 113 b. The exclusive OR gate 113 a is electrically connected to the first comparator 111 and the second comparator 112 to receive the first comparison signal C1 and the second comparison signal C2 and output the first logic signal L1. The anti-exclusive OR gate 113 b is electrically connected to the first comparator 111 and the second comparator 112 to receive the first comparison signal C1 and the second comparison signal C2 and output the second logic signal L2. The latch 114 is electrically connected to the exclusive OR gate 113a and the anti-exclusive OR gate 113b to receive the first logic signal L1 and the second logic signal L2. In this embodiment, the latch 114 is an SR latch. The first logic signal L1 is transmitted to the S value input terminal of the latch 114, and the second logic signal L2 is transmitted to the R value input terminal of the latch 114. The latch 114 outputs the Miller platform detection voltage _Vm from the Q value output terminal.

When the gate voltage _Vg is greater than the low reference potential _VL and less than the high reference potential _VH, it indicates that the gate voltage _Vg has entered the Miller platform, and the Miller platform detection voltage _Vm output by the two-stage Miller platform detector 110 rises to a high potential. When the gate voltage _Vg is greater than the high reference potential _VH or less than the low reference potential _VL , it indicates that the gate voltage _Vg is not located at the Miller platform, and the Miller platform detection voltage _Vm output by the two-stage Miller platform detector 110 drops to a low potential. The potentials of the high reference potential V _H and the low reference potential V _L are determined by transistors made of different materials. Generally speaking, the high reference potential V _H is 0.5 times the power voltage V _DD of the active gate driver 100, and the low reference potential V _L is 0.3 times the power voltage V _DD of the active gate driver 100, but the present invention is not limited thereto.

Please refer to Figures 1 and 3. The logic circuit 120 is electrically connected to the two-stage Miller platform detector 110. The logic circuit 120 receives the Miller platform detection voltage _Vm and a control signal _VPWM . The logic circuit 120 outputs a P-type control signal _VPS and an N-type control signal _VNS according to the Miller platform detection voltage _Vm and the control signal _VPWM . The control signal _VPWM is a driving logic signal of the overall circuit of the active gate driver 100.

Referring to FIG. 3 , in this embodiment, the logic circuit 120 has a first gate 121 , a first NAND gate 122 , a second gate 123 , a third gate 124 , a second NAND gate 125 , an NOR gate 126 , a fourth gate 127 , and a fifth gate 128 . The first gate 121 is electrically connected to the two-stage Miller platform detector 110 to receive the Miller platform detection voltage _Vm and output a first inverted signal I1. The first NAND gate 122 is electrically connected to the two-stage Miller platform detector 110. The first NAND gate 122 receives the Miller platform detection voltage _Vm and the control signal _VPWM and outputs a first NAND signal IA1. The second gate 123 receives the control signal V _PWM and output a second inverted signal I2, the third gate 124 is electrically connected to the first gate 122 to receive the first inverted signal IA1 and output a third inverted signal I3, the second gate 125 is electrically connected to the first gate 121 and the second gate 123 to receive the first inverted signal I1 and the second inverted signal I2 and output a second inverted signal IA2, the NOR gate 126 is electrically connected to the first gate 121 and the third gate 124 to receive the first inverted signal I1 and the third inverted signal I3 and output an NOR signal IO, the fourth gate 127 is electrically connected to the NOR gate 126 to receive the NOR signal IO and output the P-type control signal V _PS The fifth gate 128 is electrically connected to the second NAND gate 125 to receive the second NAND signal IA2 and output the N-type control signal V _NS .

In this embodiment, by means of the logic design of the logic circuit 120, when the Miller platform detection voltage _Vm and the control signal _VPWM are both low, the P-type control signal _VPS and the N-type control signal _VNS output by the logic circuit 120 are both high; when the Miller platform detection voltage _Vm is high and the control signal _VPWM is low, the P-type control signal _VPS output by the logic circuit 120 is high, and the N-type control signal _VNS output is low; when the Miller platform detection voltage _Vm is low and the control signal _VPWM is high, the P-type control signal _VPS and the N-type control signal VNS output by the logic circuit 120 are high. _NS are both low; when the Miller platform detection voltage _Vm and the control signal _VPWM are both high, the P-type control signal _VPS output by the logic circuit 120 is high, and the N-type control signal _VNS output is low.

The feedback control circuit 130 receives the control signal V _PWM , and the feedback control circuit 130 outputs a non-overlapping P-type control signal V _PW and a non-overlapping N-type control signal V _NW . Please refer to FIG. 4 . The feedback control circuit 130 is composed of an NAND gate, an NOR gate and a plurality of inverters. The feedback control circuit 130 is used to generate a small phase difference between the non-overlapping P-type control signal V _PW and the non-overlapping N-type control signal V _NW to create a dead zone between the triggering points of the two signals, so as to avoid the problem of the transistors in the two-stage Miller platform detector 110 being turned on at the same time.

Referring to FIG. 1 , the second-stage inverting buffer 140 has a first-stage inverting buffer circuit 141 and a second-stage inverting buffer circuit 142. The first-stage inverting buffer circuit 141 is electrically connected to the logic circuit 120 to receive the P-type control signal V _PS and the N-type control signal V _NS , and a first-stage output node N ₁ of the first-stage inverting buffer circuit 141 is electrically connected to the gate voltage control terminal N _g . The second-stage inverter buffer circuit 142 is electrically connected to the feedback control circuit 130 to receive the non-overlapping P-type control signal V _PW and the non-overlapping N-type control signal V _NW , and a second-stage output node N ₂ of the second-stage inverter buffer circuit 142 is electrically connected to the gate voltage control terminal N _g .

The first-stage inverting buffer circuit 141 has a first-stage PMOS transistor _MPS and a first-stage NMOS transistor _MNS . The source of the first-stage PMOS transistor _MPS receives the power voltage _VDD , the gate of the first-stage PMOS transistor _MPS receives the P-type control signal _VPS , the drain of the first-stage PMOS transistor _MPS is electrically connected to the first-stage output node _N1 , the drain of the first-stage NMOS transistor _MNS is electrically connected to the first-stage output node _N1 , the gate of the first-stage NMOS transistor _MNS receives the N-type control signal _VNS , and the source of the first-stage NMOS transistor _MNS is grounded.

The second-stage inverting buffer circuit 142 has a second-stage PMOS transistor _MPW and a second-stage NMOS transistor _MNW . The source of the second-stage PMOS transistor _MPW receives the power voltage _VDD , the gate of the second-stage PMOS transistor _MPW receives the non-overlapping P-type control signal _VPW , the drain of the second-stage PMOS transistor _MPW is electrically connected to the second-stage output node _N2 , the drain of the second-stage NMOS transistor _MNW is electrically connected to the second-stage output node _N2 , the gate of the second-stage NMOS transistor _MNW receives the non-overlapping N-type control signal _VNW , and the source of the second-stage NMOS transistor _MNW is grounded. The width of the first-order PMOS transistor _MPS is greater than the width of the second-order PMOS transistor _MPW , and the width of the first-order NMOS transistor _MNS is greater than the width of the second-order NMOS transistor _MNW , so that the driving force provided by the first-order inverting buffer circuit 141 is greater than the driving force provided by the second-order NMOS transistor _MNW .

Preferably, in this embodiment, the width of the first-order PMOS transistor _MPS is three times the width of the second-order PMOS transistor _MPW , and the width of the first-order NMOS transistor _MNS is three times the width of the second-order NMOS transistor _MNW , so that the driving force of the first-order inverting buffer circuit 141 is three times the driving force of the second-order NMOS transistor _MNW .

Referring to FIG. 1 , the circuit operation of the active gate driver 100 when the power element is turned on is as follows: the control signal V _PWM rises to a high level, the non-overlapping P-type control signal _VPW and the non-overlapping N-type control signal V _NW output by the feedback control circuit 130 drop to a low level to turn on the second-stage PMOS transistor _MPW and turn off the second-stage NMOS transistor _MNW , and because the gate voltage V _g just starts to rise and is less than the low reference potential V _L , the Miller platform detection voltage V _m output by the two-stage Miller platform detector 110 is a low level, so the P-type control signal V _PS and the N-type control signal V NW output by the logic circuit 120 are low. _NS are both at low level to turn on the first-stage PMOS transistor _MPS and turn off the first-stage NMOS transistor _MNS . At this time, the power supply voltage _VDD charges the gate voltage control terminal _Ng through the first-stage PMOS transistor _MPS and the second-stage PMOS transistor _MPW . The second-stage inverter buffer 140 in this section provides a strong driving force. Then, when the gate voltage _Vg rises to be greater than the low reference potential _VL and enters the Miller platform, the Miller platform detection voltage _Vm turns to a high level, the P-type control signal _VPS output by the logic circuit 120 turns to a high level, and the N-type control signal _VNS is maintained at a low level to turn off the first-stage PMOS transistor _MPS and the first-stage NMOS transistor _MNS , and the potentials of the non-overlapping P-type control signal _VPW and the non-overlapping N-type control signal _VNW output by the feedback control circuit 130 remain unchanged. Since the voltage rise rate of the gate voltage _Vg slows down when it enters the Miller platform, the power supply voltage _VDD can maintain the rise of the gate voltage _Vg only by charging the gate voltage control terminal _Ng through the second-stage PMOS transistor _MPW . The second-stage inverting buffer 140 in this section provides a weak driving force. Finally, when the gate voltage _Vg rises to a level greater than the high reference potential _VH and leaves the Miller platform, the Miller platform detection voltage _Vm turns to a low level, the P-type control signal _VPS and the N-type control signal _VNS output by the logic circuit 120 are both low levels, turning on the first-order PMOS transistor _MPS and turning off the first-order NMOS transistor _MNS , and the potentials of the non-overlapping P-type control signal _VPW and the non-overlapping N-type control signal _VNW output by the feedback control circuit 130 remain unchanged, and the power supply voltage _VDD is controlled by the first-order PMOS transistor _MPS and the second-order PMOS transistor _MPW to the gate voltage control terminal N _g is charged until the power element is fully turned on. The second-stage inverter buffer 140 in this section provides a strong driving force.

The circuit operation of the active gate driver 100 when the power element is turned off is as follows: the control signal V _PWM drops to a low level, the non-overlapping P-type control signal V _PW and the non-overlapping N-type control signal V _NW output by the feedback control circuit 130 rise to a high level to turn off the second-stage PMOS transistor _MPW and turn on the second-stage NMOS transistor M _NW . At this time, the gate voltage V _g is still greater than the high reference potential V _H and is not at the Miller platform. The Miller platform detection voltage V _m output by the two-stage Miller platform detector 110 is a low level, and the P-type control signal V _PS and the N-type control signal V NW output by the logic circuit 120 are both low. _NS are both at high level to turn off the first-stage PMOS transistor _MPS and turn on the first-stage NMOS transistor _MNS . The gate voltage _Vg is discharged through the first-stage NMOS transistor _MNS and the second-stage NMOS transistor _MNW . The second-stage inverting buffer 140 in this section provides a strong driving force. Then, when the gate voltage _Vg drops to less than the high reference potential _VH and enters the Miller platform, the Miller platform detection voltage _Vm turns to a high potential, the P-type control signal _VPS output by the logic circuit 120 maintains a high potential, and the N-type control signal _VNS output turns to a low potential, and the first-stage PMOS transistor _MPS and the first-stage NMOS transistor _MNS are turned off, and the potentials of the non-overlapping P-type control signal _VPW and the non-overlapping N-type control signal _VNW output by the feedback control circuit 130 remain unchanged. Since the voltage drop of the gate voltage _Vg slows down when entering the Miller platform, the gate voltage V The gate voltage _Vg can be maintained to decrease only by discharging through the second-stage NMOS transistor _{MNW .} The second-stage inverting buffer 140 in this section provides a weak driving force. Finally, when the gate voltage _Vg drops to less than the low reference potential _VL and leaves the Miller platform, the Miller platform detection voltage _Vm turns to a low potential, the P-type control signal _VPS and the N-type control signal _VNS output by the logic circuit 120 are both high potentials, turning off the first-order PMOS transistor _MPS and turning on the first-order NMOS transistor _MNS , and the potentials of the non-overlapping P-type control signal _VPW and the non-overlapping N-type control signal _VNW output by the feedback control circuit 130 remain unchanged. At this time, the gate voltage _Vg is connected to the first-order NMOS transistor _MNS and the second-order NMOS transistor MNS. _NW is discharged until the power element is completely turned off. The second-stage inverter buffer 140 in this section provides a strong driving force.

The present invention detects whether the gate voltage _Vg is at the Miller platform through the two-stage Miller platform detector 110, and controls the first-stage inverter buffer circuit 141 of the second-stage inverter buffer 140 through the P-type control signal _VPS and the N-type control signal _VNS output by the logic circuit 120 to adjust the driving force provided by the second-stage inverter buffer 140 when the gate voltage _Vg is at the Miller platform, thereby reducing the power consumption of the entire circuit.

The scope of protection of the present invention shall be determined by the scope of the attached patent application. Any changes and modifications made by anyone familiar with this technology without departing from the spirit and scope of the present invention shall fall within the scope of protection of the present invention.

100: Active gate actuator

V _DD : Power supply voltage

N _g : Gate voltage control terminal

V _g : Gate voltage

110: Two-stage Miller platform detector

111: First comparator

112: Second comparator

113: Logical Gate Group

113a: Mutex or Gate

113b: Anti-mutex or gate

114:Latch

C1: First comparison signal

C2: Second comparison signal

L1: First logic signal

L2: Second logic signal

V _H : High reference potential

V _L : Low reference potential

V _m : Miller platform detection voltage

120:Logic Circuit

121: First anti-gate

122: First Reverse and Gate

123: Second anti-gate

124: The third anti-gate

125: Second Anti-Gate

126: Anti-OR Gate

127: The fourth anti-gate

128: Fifth Anti-Gate

I1: First inverted signal

I2: Second inverted signal

IA1: First feedback signal

I3: The third inverted signal

IA2: Second feedback signal

IO: Anti-OR signal

V _PWM : control signal

V _PS :P type control signal

V _NS :N-type control signal

130: Feedback control circuit

V _PW : Non-overlapping P-type control signal

V _NW : Non-overlapping N-type control signal

140: Second-order inverting buffer

141: First-stage inverting buffer circuit

M _PS : First-order PMOS transistor

M _NS : First-order NMOS transistor

142: Second-order inverting buffer circuit

M _PW : Second-order PMOS transistor

M _NW : Second-order NMOS transistor

N ₁ : First-order output node

N ₂ : Second-order output node

FIG. 1: A circuit diagram of an active gate driver according to an embodiment of the present invention. FIG. 2: A circuit diagram of a two-stage Miller platform detector according to an embodiment of the present invention. FIG. 3: A circuit diagram of a logic circuit according to an embodiment of the present invention. FIG. 4: A circuit diagram of a feedback control circuit according to an embodiment of the present invention.

100: Active gate actuator

110: Two-stage Miller platform detector

120:Logic circuit

130: Feedback control circuit

140: Second-order inverting buffer

141: First-stage inverting buffer circuit

142: Second-stage inverting buffer circuit

V _H : High reference potential

V _L : Low reference potential

V _PWM : control signal

V _m : Miller platform detection voltage

V _PS :P type control signal

V _NS :N-type control signal

V _PW : Non-overlapping P-type control signal

V _NW : Non-overlapping N-type control signal

V _DD : Power supply voltage

M _PS : First-order PMOS transistor

M _NS : First-order NMOS transistor

M _PW : Second-order PMOS transistor

M _NW : Second-order NMOS transistor

N ₁ : First-order output node

N ₂ : Second-order output node

N _g : Gate voltage control terminal

V _g : Gate voltage

Claims (10)

An active gate driver includes: a gate voltage control terminal for outputting a gate voltage; a two-stage Miller platform detector for receiving a high reference potential, a low reference potential and the gate voltage, the two-stage Miller platform detector determines whether the gate voltage is located at the Miller platform by the high reference potential and the low reference potential, and the two-stage Miller platform detector detects whether the gate voltage is located at the Miller platform by the high reference potential and the low reference potential. The Miller platform detector outputs a Miller platform detection voltage; a logic circuit electrically connected to the two-stage Miller platform detector, the logic circuit receives the Miller platform detection voltage and a control signal, and the logic circuit outputs a P-type control signal and an N-type control signal according to the Miller platform detection voltage and the control signal; a feedback control circuit connected to the The control signal is received, and the feedback control circuit outputs a non-overlapping P-type control signal and a non-overlapping N-type control signal; and a two-stage inverting buffer having a first-stage inverting buffer circuit and a second-stage inverting buffer circuit, the first-stage inverting buffer circuit is electrically connected to the logic circuit to receive the P-type control signal and the N-type control signal, A first-stage output node of the first-stage inverting buffer circuit is electrically connected to the gate voltage control end, the second-stage inverting buffer circuit is electrically connected to the feedback control circuit to receive the non-overlapping P-type control signal and the non-overlapping N-type control signal, and a second-stage output node of the second-stage inverting buffer circuit is electrically connected to the gate voltage control end. The active gate driver of claim 1, wherein the two-stage Miller platform detector has a first comparator, a second comparator, a logic gate set and a latch, the first comparator is electrically connected to the gate voltage control end, the first comparator receives the high reference potential and the gate voltage and outputs a first comparison signal, the second comparator is electrically connected to the gate voltage control end, the second comparator receives The low reference potential and the gate voltage output a second comparison signal, the logic gate group is electrically connected to the first comparator and the second comparator to receive the first comparison signal and the second comparison signal and output a first logic signal and a second logic signal, the latch is electrically connected to the logic gate group to receive the first logic signal and the second logic signal, and the latch outputs the Miller platform detection voltage. An active gate driver as claimed in claim 2, wherein the logic gate set has a mutual exclusion gate and an anti-mutual exclusion gate, the mutual exclusion gate electrically connects the first comparator and the second comparator to receive the first comparison signal and the second comparison signal and outputs the first logic signal, and the anti-mutual exclusion gate electrically connects the first comparator and the second comparator to receive the first comparison signal and the second comparison signal and outputs the second logic signal. An active gate driver as claimed in claim 1, wherein the logic circuit has a first flop gate, a first NAND gate, a second flop gate, a third flop gate, a second NAND gate, an NOR gate, a fourth flop gate and a fifth flop gate, wherein the first flop gate is electrically connected to the two-stage Miller platform detector to receive the Miller platform detection voltage and output a first inverted signal, the first NAND gate is electrically connected to the two-stage Miller platform detector, the first NAND gate receives the Miller platform detection voltage and the control signal and outputs a first NAND signal, the second flop gate receives the control signal and outputs a second inverted signal, and the third The gate is electrically connected to the first NAND gate to receive the first NAND signal and output a third inverted signal, the second NAND gate is electrically connected to the first NAND gate and the second NAND gate to receive the first inverted signal and the second inverted signal and output a second NAND signal, the NOR gate is electrically connected to the first NAND gate and the third NAND gate to receive the first inverted signal and the third inverted signal and output an NOR signal, the fourth NAND gate is electrically connected to the NOR gate to receive the NOR signal and output the P-type control signal, and the fifth NAND gate is electrically connected to the second NAND gate to receive the second NAND signal and output the N-type control signal. The active gate driver of claim 1 or 4, wherein when the Miller platform detection voltage and the control signal are both low, the P-type control signal and the N-type control signal output by the logic circuit are both high; when the Miller platform detection voltage is high and the control signal is low, the P-type control signal output by the logic circuit is high, and the N-type control signal output is high. When the Miller platform detection voltage is low and the control signal is high, the P-type control signal and the N-type control signal output by the logic circuit are both low; when the Miller platform detection voltage and the control signal are both high, the P-type control signal output by the logic circuit is high and the N-type control signal output is low. An active gate driver as in claim 1, wherein the first-order inverting buffer circuit has a first-order PMOS transistor and a first-order NMOS transistor, the source of the first-order PMOS transistor receives a power voltage, the gate of the first-order PMOS transistor receives the P-type control signal, the drain of the first-order PMOS transistor is electrically connected to the first-order output node, the drain of the first-order NMOS transistor is electrically connected to the first-order output node, the gate of the first-order NMOS transistor receives the N-type control signal, and the source of the first-order NMOS transistor is grounded. As the active gate driver of claim 6, the second-stage inverting buffer circuit has a second-stage PMOS transistor and a second-stage NMOS transistor, the source of the second-stage PMOS transistor receives the power voltage, the gate of the second-stage PMOS transistor receives a non-overlapping P-type control signal, the drain of the second-stage PMOS transistor is electrically connected to the second-stage output node, the drain of the second-stage NMOS transistor is electrically connected to the second-stage output node, the gate of the second-stage NMOS transistor receives the non-overlapping N-type control signal, and the source of the second-stage NMOS transistor is grounded. An active gate driver as claimed in claim 7, wherein the width of the first-order PMOS transistor is greater than the width of the second-order PMOS transistor, and the width of the first-order NMOS transistor is greater than the width of the second-order NMOS transistor. An active gate driver as claimed in claim 8, wherein the width of the first-order PMOS transistor is three times the width of the second-order PMOS transistor, and the width of the first-order NMOS transistor is three times the width of the second-order NMOS transistor. The active gate driver of claim 8 or 9, wherein when the Miller platform detection voltage and the control signal are both low, the P-type control signal and the N-type control signal output by the logic circuit are both high; when the Miller platform detection voltage is high and the control signal is low, the P-type control signal output by the logic circuit is high, and the N-type control signal output is high. When the Miller platform detection voltage is low and the control signal is high, the P-type control signal and the N-type control signal output by the logic circuit are both low; when the Miller platform detection voltage and the control signal are both high, the P-type control signal output by the logic circuit is high and the N-type control signal output is low.

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