TWI883558B - Method using implant seed layer for manufacturing wafer and wafer structure thereof - Google Patents

Abstract

The present invention provides a method using implant seed layer for manufacturing wafer and wafer structure thereof, wherein the method comprises: providing a wafer having an activation temperature; making a seed layer formed on the wafer; and performing activation temperature treatment treated the wafer carrier and the seed layer to form a regenerated wafer substrate; and an performing annealing treatment to the regenerated wafer substrate to eliminate crystal defects. Through the implementation of the present invention, scrapped or inferior wafers can be turned into high-quality regenerated wafers.

Description

Method for manufacturing wafer carrier with seed layer implantation and wafer structure thereof

The present invention is a method for manufacturing a wafer carrier with a seed layer implanted therein and a wafer structure thereof, in particular, a method for manufacturing a wafer carrier with a seed layer implanted therein for manufacturing a regenerated wafer and a wafer structure thereof.

Wafer refers to the chip used in the manufacture of semiconductor integrated circuits. Due to its round shape, it is called a wafer. The production of wafers at least goes through purification, seeding, rotating crystal pulling, pulling out crystal rods, and cutting into wafers. These processes and equipment require huge funds, so the cost of wafers is very expensive.

After wafer production, common defects can be classified into point defects, line defects and surface defects. These defects have a significant impact on the properties of the material. Point defects are vacancy, line defects are generally called dislocation, and surface defects of metals include: double-sided, grain boundary and superposition defects.

Because these defects will seriously affect the subsequent electronic component manufacturing, when the wafer has the above defects, it will often be treated as scrapped or defective, which will result in huge losses. Therefore, how to reprocess scrapped or defective wafers at a lower cost to become high-quality recycled wafers has become an important issue.

The present invention is a method for manufacturing a wafer carrier with a seed layer implanted therein and a wafer structure thereof, which is mainly intended to solve the problem of great losses caused by waste or inferior products after wafer production.

The present invention provides a method for manufacturing a wafer carrier with a seed layer implanted therein, which includes: providing a wafer carrier, which is made of a semiconductor material and has an activation temperature; manufacturing a seed layer, which is to form a semiconductor material on a surface of the wafer carrier to form a seed layer; performing an activation temperature treatment, which is to heat and activate the wafer carrier and the seed layer at the activation temperature to form a regenerated wafer substrate with a solid solution structure; and performing an annealing treatment, which is to anneal the regenerated wafer substrate to adjust and relax the crystallization properties between the seed layer and the wafer carrier and eliminate crystal defects.

The present invention also provides a wafer structure with a seed layer implantation layer, which includes: a wafer carrier, which is made of a semiconductor material; a seed layer, which is a nano-imprint deposition structure and is bonded to a surface of the wafer carrier, and the seed layer is also formed of a semiconductor material; and a dissolution layer, which is formed by the wafer carrier and the seed layer, and the dissolution layer allows the wafer carrier and the seed to form a solid solution structure that eliminates crystal defects.

By implementing the present invention, at least the following improved effects can be achieved: 1. Wafers that were originally to be scrapped or inferior can be turned into high-quality recycled wafers. 2. Recycled wafers with high added value can be produced at a low cost.

In order to enable anyone skilled in the relevant art to understand the technical content of the present invention and implement it accordingly, and based on the content disclosed in this specification, the scope of the patent application and the drawings, any person skilled in the relevant art can easily understand the relevant purposes and advantages of the present invention. Therefore, the detailed features and advantages of the present invention will be described in detail in the implementation method.

As shown in FIG. 1 , a method S100 for manufacturing a wafer carrier with seed layer implantation according to the present embodiment includes: providing a wafer carrier S10 ; manufacturing a seed layer S20 ; performing an activation temperature treatment S30 ; and performing an annealing treatment S40 .

As shown in FIG. 2 and FIG. 3 , a wafer structure 100 with a seed layer and an implanted layer according to the present embodiment is shown, which includes: a wafer carrier 10 ; a seed layer 20 ; and a dissolving layer 30 .

A wafer carrier S10 is provided. The wafer carrier 10 of this embodiment is mainly a defective wafer that fails to meet the quality inspection after wafer production. Therefore, before providing the wafer carrier S10, a substrate treatment cleaning step can be performed first, which includes: a. Cleaning the substrate: using a surfactant to clean the substrate of the defective wafer to remove surface dirt and grease. b. Removing the oxide layer: If there is still an oxide layer on the substrate surface of the defective wafer, the oxide layer can be removed again.

The wafer carrier 10 is made of a semiconductor material and has an activation temperature. The wafer carrier 10 can be a single crystal wafer carrier 10.

A seed layer S20 is fabricated by bonding a semiconductor material of the same material as the wafer carrier 10 to a surface of the wafer carrier 10 by, for example, nanoimprint deposition or spin coating, to form a seed layer 20 of a nanoimprint deposition structure.

When making the seed layer 20, the equipment is adjusted to ensure that it is in a correct operating state and to ensure that the seed layer 20 after deposition is uniform and meets the expected thickness requirements.

The activation temperature treatment S30 is performed to heat and activate the wafer carrier 10 and the seed layer 20 at the activation temperature, and to form a dissolution layer 30 between the wafer carrier 10 and the seed layer 20. The activation temperature is selected according to the semiconductor material properties of the wafer carrier 10 and the seed layer 20, and a suitable activation temperature is selected.

The above-mentioned wafer carrier 10, seed layer 20 and dissolution layer 30 can be made of a semiconductor material of silicon carbide (SiC) or gallium nitride (GaN). In other words, the wafer carrier 10, seed layer 20 and dissolution layer 30 can be a material layer of silicon carbide (SiC) or gallium nitride (GaN), but are not limited to this.

During the activation temperature treatment S30, the wafer carrier 10 on which the seed layer S20 is made is placed in a heat treatment system, and then heated for a suitable time at the selected activation temperature to form a melted and then solidified dissolving layer 30 between the seed layer 20 and the wafer carrier 10, and finally cooled and solidified to form a regenerated wafer substrate.

The annealing process S40 is performed by placing the regenerated wafer substrate in an annealing system to adjust and relax the crystal properties of the solution layer 30 and eliminate crystal defects. After the annealing process S40, the regenerated wafer substrate becomes a wafer structure 100 having a nano-imprint seed layer and an implanted layer. In addition, the annealing process S40 can be performed using an organic metal chemical vapor deposition (MOCVD) equipment to perform the annealing step and temperature control.

After all the above processes are completed, the regenerated wafer substrate can be inspected and analyzed again, including: a. Surface morphology detection: It uses surface morphology detection instruments, such as atomic force microscopes, scanning electron microscopes, etc., to detect the surface morphology and uniformity of the seed layer 20; b. Structural and composition analysis: It uses instruments such as X-ray diffraction and energy scattering spectroscopy to perform structural and composition analysis of the seed layer 20 to ensure that it meets the requirements.

The wafer structure 100 with a nano-imprinted seed layer implantation layer of the present embodiment can become a regenerated wafer after the inspection is completed. Since the regenerated wafer has overcome the original defect problem under the action of the seed layer 20, epitaxial growth is performed on the seed layer 20. The new epitaxial layer will be able to be arranged along the excellent lattice of the seed layer 20, continue to grow upward, and form an excellent regenerated epitaxial layer 40.

However, the above-mentioned embodiments are used to illustrate the features of the present invention, and their purpose is to enable those familiar with the technology to understand the content of the present invention and implement it accordingly, rather than to limit the patent scope of the present invention. Therefore, any other equivalent modifications or amendments that are completed without departing from the spirit disclosed by the present invention should still be included in the scope of the patent application described below.

S100: Method for manufacturing a wafer carrier with seed layer implantation S10: Providing a wafer carrier S20: Producing a seed layer S30: Performing activation temperature treatment S40: Performing annealing treatment 100: Wafer structure with seed layer implantation layer 10: Wafer carrier 20: Seed layer 30: Solvent layer 40: Regenerated epitaxial layer

[Figure 1] is a flow diagram of a wafer carrier manufacturing method for seed layer implantation; [Figure 2] is a three-dimensional embodiment of a wafer structure with a seed layer implantation layer; [Figure 3] is a cross-sectional embodiment diagram of Figure 2; and [Figure 4] is an application embodiment diagram of using Figure 2 to continue to form a regenerated epitaxial layer.

S100: Method for manufacturing wafer carrier with seed layer implantation

S10: Provide a wafer carrier

S20: Make a seed layer

S30: Activation temperature treatment

S40: Annealing treatment

Claims (6)

A method for manufacturing a wafer carrier with seed layer implantation, comprising: Providing a wafer carrier, the wafer carrier is made of a semiconductor material and has an activation temperature; Making a seed layer, which is to form the semiconductor material on a surface of the wafer carrier and form a seed layer; Performing an activation temperature treatment, which is to heat and activate the wafer carrier and the seed layer at the activation temperature and form a regenerated wafer substrate with a solid solution structure; and Performing an annealing treatment, which is to anneal the regenerated wafer substrate to adjust and relax the crystallization properties between the seed layer and the wafer carrier and eliminate crystal defects; Wherein the wafer carrier is a single crystal wafer carrier; The process of making a seed layer is to form the semiconductor material on the surface of the wafer carrier by nanoimprint deposition or spin coating to form the seed layer. The manufacturing method as described in item 1 of the patent application scope, wherein the semiconductor material is a semiconductor material of silicon carbide (SiC) or gallium nitride (GaN). As described in the manufacturing method of claim 1, the annealing step is controlled by a metal organic chemical vapor deposition (MOCVD) device. A wafer structure with a seed layer implantation layer, comprising: a wafer carrier, which is made of a semiconductor material; a seed layer, which is a nano-imprint deposition structure and is bonded to a surface of the wafer carrier, and the seed layer is also formed of the semiconductor material; and a dissolving layer, which is formed by the wafer carrier and the seed layer, and the dissolving layer enables the wafer carrier and the seed to form a solid solution structure that eliminates crystal defects. The wafer structure as described in item 4 of the patent application scope, wherein the wafer carrier is a single crystal wafer carrier. The wafer structure as described in item 4 of the patent application scope, wherein the wafer carrier, the seed layer and the dissolution layer are made of a material layer of silicon carbide (SiC) or gallium nitride (GaN).

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