TWI881773B - Microprocessor for display control, display device and information processing device - Google Patents

Abstract

A display control microprocessor includes a decoding unit to support an instruction set, and is characterized in that: the instruction set includes a register write instruction, the register write instruction includes an address offset and a value to be written, and is used to write the value to be written into a target register of a timing controller, wherein the address of the target register is equal to the sum of a base address stored in a base register and the address offset; and the display control microprocessor is used to execute an operation mode setting program, which includes: writing a base address into the base register; and continuously executing the register write instruction multiple times to write multiple planning data into multiple target registers correspondingly, so as to set an operation mode of the timing controller, thereby determining a screen scanning mode of a display panel.

Description

Microprocessor for display control, display device and information processing device

The present invention relates to display driving, and more particularly to a display driving scheme capable of planning driving modes.

A general display device includes a display control circuit, a drive circuit and a display panel, wherein the display control circuit includes a timing controller to transmit display data and a scanning signal to the drive circuit, and the drive circuit generates a voltage signal according to the display data and the scanning signal to drive the display panel.

However, generally speaking, the timing controller is a chip with limited processing power, which can only work in a fixed mode, and therefore cannot provide a variable screen scanning mode for the display panel, and cannot monitor the operation of the driver circuit.

In order to solve the above problems, this field urgently needs a novel display control circuit.

The main purpose of the present invention is to provide a display control microprocessor that can continuously execute multiple register write instructions to write multiple planning data into multiple target registers to set an operation mode of a timing controller, thereby determining a screen scanning mode of a display panel.

Another object of the present invention is to provide a display control microprocessor that can read a frame count value register of the timing controller to obtain the frame number of the display data that has been transmitted.

Another object of the present invention is to provide a display control microprocessor that can read a row count register of the timing controller to obtain the number of completed row scans in the current frame.

Another object of the present invention is to provide a display control microprocessor that can generate an interrupt signal to force the execution of a predetermined program when the count value of a counter reaches a preset value.

To achieve the above-mentioned purpose, a display control microprocessor is proposed, which includes a decoding unit to support an instruction set, and is characterized in that: the instruction set includes a register write instruction, the register write instruction includes an address offset and a value to be written, and is used to write the value to be written into a target register of a timing controller, wherein the address of the target register is equal to the sum of a base address stored in a base register and the address offset; and the display control microprocessor is used to execute an operation mode setting program, which includes: writing a base address into the base register; and continuously executing the register write instruction multiple times to write multiple planning data into multiple target registers correspondingly, so as to set an operation mode of the timing controller, thereby determining a screen scanning mode of a display panel.

In one embodiment, the instruction set includes a system register read instruction for reading a frame count value register of the timing controller to obtain the frame number of the display data that has been transmitted.

In one embodiment, the instruction set includes a system register read instruction for reading a row count value register of the timing controller to obtain the number of completed row scans in a current frame.

In one embodiment, the instruction set includes a register write instruction for writing a preset value into a counting threshold register, wherein when the count value of a counter in the display control microprocessor reaches the preset value stored in the counting threshold register, an interrupt signal is generated to drive the display control microprocessor to execute a predetermined program.

In one embodiment, the instruction set includes a conditional jump instruction, and the display control microprocessor executes the conditional jump instruction when powered on to stay at the original instruction capture address when the content of a flash memory is all 0 or 1, wherein the flash memory is used to store the program code of the display control microprocessor.

To achieve the above-mentioned object, the present invention further proposes a display device, which has a microprocessor, a timing controller, a driving circuit and a display panel, wherein the microprocessor is coupled to the timing controller, the timing controller is coupled to the driving circuit, the driving circuit is used to drive the display panel, and the microprocessor includes a decoding unit to support an instruction set, and its characteristics are: the instruction set includes a register write instruction, the register write instruction includes an address offset and a value to be written, and is used to write the value to the register. A write value is written into a target register of a timing controller, wherein the address of the target register is equal to the sum of a base address stored in a base register and the address offset; and the microprocessor is used to execute an operation mode setting program, which includes: writing a base address into the base register; and continuously executing the register write instruction multiple times to write multiple planning data into multiple target registers to set an operation mode of the timing controller, thereby determining the screen scanning mode of the display panel.

In one embodiment, the instruction set includes a system register read instruction for reading a frame count value register of the timing controller to obtain the frame number of the display data that has been transmitted.

In one embodiment, the instruction set includes a system register read instruction for reading a row count value register of the timing controller to obtain the number of completed row scans in a current frame.

In one embodiment, the instruction set includes a register write instruction for writing a preset value into a count threshold register, wherein when the count value of a counter in the microprocessor reaches the preset value stored in the count threshold register, an interrupt signal is generated to drive the microprocessor to execute a predetermined program.

In one embodiment, the instruction set includes a conditional jump instruction, and the microprocessor executes the conditional jump instruction when powered on to stay at the original instruction capture address when the content of a flash memory is all 0 or 1, wherein the flash memory is used to store the program code of the microprocessor.

To achieve the above-mentioned purpose, the present invention further proposes an information processing device having a central processing unit and a display device as described above, wherein the central processing unit is used to communicate with the display device.

In a possible embodiment, the display device may be a liquid crystal display device, a millimeter diode light-emitting display device, a micrometer diode light-emitting display device, a quantum dot diode light-emitting display device or an organic light-emitting diode display device.

In a possible embodiment, the information processing device may be a portable computer, a car computer, a smart watch, a smart bracelet or a smart phone.

In order to enable the review committee to further understand the structure, features, purpose, and advantages of the present invention, the detailed description of the drawings and preferred specific embodiments is attached as follows.

10: Bus

100: Display control circuit

110: Microprocessor

111: Static random access memory

120: Flash memory

130: Timing controller

131: Frame count value register

132: Row count value register

133: Display data output unit

134: Scanning signal output unit

135: Target register module

200: Display device

210: Display control circuit

220:Drive circuit

230: Display panel

300: Information processing device

310: Central Processing Unit

320: Display device

FIG. 1 is a block diagram of an embodiment of the display control circuit of the present invention; FIG. 2 is a block diagram of an embodiment of the display device of the present invention; and FIG. 3 is a block diagram of an embodiment of the information processing device of the present invention.

Please refer to Figure 1, which shows a block diagram of an embodiment of the display control circuit of the present invention.

As shown in FIG. 1 , a display control circuit 100 includes a microprocessor 110, a flash memory 120, and a timing controller 130. The microprocessor 110, the flash memory 120, and the timing controller 130 are all coupled to a bus 10. The timing controller 130 includes a frame count value register 131, a row count value register 132, a display data output unit 133, a scan signal output unit 134, and a target register module 135. The microprocessor 110 includes a static random access memory 111 to load a program code from the flash memory 120 when powered on. The frame count value register 131 is used to store the display data D that has been transmitted. _IN frame number, the row count value register 132 is used to store the number of completed row scans in the current frame, the display data output unit 133 is used to output the display data signal S _DATA to a source driver (or a column driver), the scan signal output unit 134 is used to output the scan signal S _SCAN to a gate driver (or a row driver), and the target register module 135 includes multiple target registers.

The principle of the present invention is to use the microprocessor 110 to plan the timing controller 130 to set an operation mode of the timing controller 130, thereby determining a screen scanning mode of a display panel, for example, sequential scanning or skip scanning, or its scanning frequency. In detail, the microprocessor 110 includes a decoding unit to support an instruction set, and its characteristics are:

(I) The instruction set includes a register write instruction, which includes an address offset and a value to be written, and is used to write the value to be written into a target register of a target register module 135 of a timing controller, wherein the address of the target register is equal to the sum of a base address stored in a base register and the address offset. For example, assuming that the register write instruction is a 16-bit instruction, the first two bits represent its operator, the middle 4 bits represent the address offset, and the lower 10 bits represent the value to be written, then the register write instruction can write the 10-bit value to be written into 16 different target registers of the target register module 135.

(ii) The microprocessor 110 is used to execute an operation mode setting program, which includes: 1. writing a base address into the base register; and 2. continuously executing the register write instruction multiple times to write a plurality of planning data into a plurality of target registers of the target register module 135 to set an operation mode of the timing controller 130, thereby determining the screen scanning mode of the display panel.

In addition, the instruction set may include a system register read instruction for reading the frame count value register 131 of the timing controller 130 to obtain the frame number of the display data that has been transmitted.

In addition, the instruction set may include a system register read instruction for reading the row count value register 132 of the timing controller 130 to obtain the number of completed row scans in the current frame. In this way, the present invention can support accurate monitoring of the row scan width within a frame to determine whether the system status is abnormal.

In addition, the instruction set may include a register write instruction for writing a preset value into a count threshold register (not shown in the figure), wherein when the count value of a counter (not shown in the figure) in the microprocessor 110 reaches the preset value stored in the count threshold register, an interrupt signal is generated to drive the microprocessor 110 to execute a predetermined program. In this way, the present invention can provide more accurate event response capabilities than software polling.

In addition, the instruction set may include a conditional jump instruction, and the microprocessor 110 executes the conditional jump instruction when powered on to stay at the original instruction fetch address when the contents of the flash memory 120 are all 0 or 1, wherein the flash memory 120 is used to store the program code of the microprocessor 110.

According to the above description, the present invention further proposes a display device. Please refer to Figure 2, which shows a block diagram of an embodiment of the display device of the present invention.

As shown in FIG. 2 , a display device 200 includes a display control circuit 210, a driving circuit 220 and a display panel 230, wherein the display control circuit 210 is coupled to the driving circuit 220, the driving circuit 220 is used to drive the display panel 230, and the display control circuit 210 is implemented by the display control circuit 100.

In addition, according to the above description, the present invention further proposes an information processing device. Please refer to FIG. 3, which shows a block diagram of an embodiment of the information processing device of the present invention. As shown in FIG. 3, an information processing device 300 has a central processing unit 310 and a display device 320, wherein the display device 320 is implemented by the display device 200 and the central processing unit 310 is used to communicate with the display device 320.

In addition, the display device 320 can be a liquid crystal display device, a millimeter diode light-emitting display device, a micrometer diode light-emitting display device, a quantum dot diode light-emitting display device or an organic light-emitting diode display device.

In addition, the information processing device 300 may be a portable computer, a car computer, a smart watch, a smart bracelet, or a smart phone.

According to the above design, the present invention has the following advantages:

1. The display control microprocessor of the present invention can continuously execute multiple register write instructions to write multiple planning data into multiple target registers to set an operation mode of a timing controller, thereby determining a screen scanning mode of a display panel; 2. The display control microprocessor of the present invention can read a frame count value register of the timing controller to obtain the number of frames of the display data that have been transmitted; 3. The display control microprocessor of the present invention can read a row count value register of the timing controller to obtain the number of row scans completed in a current frame; and 4. The display control microprocessor of the present invention can generate an interrupt signal when the count value of a counter reaches a preset value to force the execution of a predetermined program.

What is disclosed in this case is a better embodiment. Any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by people familiar with the art do not deviate from the scope of the patent rights of this case.

In summary, this case shows that its purpose, means and effects are different from the known technology, and it is the first invention that is practical and meets the patent requirements for invention. We sincerely ask the review committee to examine it and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

10: Bus

100: Display control circuit

110: Microprocessor

111: Static random access memory

120: Flash memory

130: Timing controller

131: Frame count value register

132: Row count value register

133: Display data output unit

134: Scanning signal output unit

135: Target register module

Claims (13)

A display control microprocessor includes a decoding unit to support an instruction set, and is characterized in that: The instruction set includes a register write instruction, the register write instruction includes an address offset and a value to be written, and is used to write the value to be written into a target register of a timing controller, wherein the address of the target register is equal to the sum of a base address stored in a base register and the address offset; and The display control microprocessor is used to execute an operation mode setting program, which includes: Writing a base address into the base register; and Continuously executing the register write instruction multiple times to write multiple planning data into multiple target registers correspondingly, so as to set an operation mode of the timing controller, thereby determining a screen scanning mode of a display panel. A display control microprocessor as described in claim 1, wherein the instruction set includes a system register read instruction for reading a frame count value register of the timing controller to obtain the frame number of the display data that has been transmitted. A display control microprocessor as described in claim 1, wherein the instruction set includes a system register read instruction for reading a row count value register of the timing controller to obtain the number of completed row scans in a current frame. A display control microprocessor as described in claim 1, wherein the instruction set includes a register write instruction for writing a preset value into a counting threshold register, wherein when the count value of a counter in the display control microprocessor reaches the preset value stored in the counting threshold register, an interrupt signal is generated to drive the display control microprocessor to execute a predetermined program. A display control microprocessor as described in claim 1, wherein the instruction set includes a conditional jump instruction, and the display control microprocessor executes the conditional jump instruction when powered on to stay at the original instruction capture address when the contents of a flash memory are all 0 or 1, wherein the flash memory is used to store the program code of the display control microprocessor. A display device has a microprocessor, a timing controller, a drive circuit and a display panel, wherein the microprocessor is coupled to the timing controller, the timing controller is coupled to the drive circuit, the drive circuit is used to drive the display panel, and the microprocessor includes a decoding unit to support an instruction set, and its characteristics are: The instruction set includes a register write instruction, the register write instruction includes an address offset and a value to be written, and is used to write the value to be written into a target register of a timing controller, wherein the address of the target register is equal to the sum of a base address stored in a base register and the address offset; and The microprocessor is used to execute an operation mode setting program, which includes: Writing the base address into the base register; and Continuously execute the register write instruction multiple times to write multiple planning data into multiple target registers to set an operation mode of the timing controller, thereby determining the screen scanning mode of the display panel. A display device as described in claim 6, wherein the instruction set includes a system register read instruction for reading a frame count value register of the timing controller to obtain the frame number of the display data that has been transmitted. A display device as described in claim 6, wherein the instruction set includes a system register read instruction for reading a row count value register of the timing controller to obtain the number of completed row scans in a current frame. A display device as described in claim 6, wherein the instruction set includes a register write instruction for writing a preset value into a counting threshold register, wherein when the count value of a counter in the microprocessor reaches the preset value stored in the counting threshold register, an interrupt signal is generated to drive the microprocessor to execute a predetermined program. A display device as described in claim 6, wherein the instruction set includes a conditional jump instruction, and the microprocessor executes the conditional jump instruction when powered on to stay at the original instruction capture address when the contents of a flash memory are all 0 or 1, wherein the flash memory is used to store the program code of the microprocessor. An information processing device having a central processing unit and a display device as described in any one of claims 6 to 10, wherein the central processing unit is used to communicate with the display device. An information processing device as described in claim 11, wherein the display device is selected from the group consisting of a liquid crystal display device, a millimeter diode light-emitting display device, a micrometer diode light-emitting display device, a quantum dot diode light-emitting display device and an organic light-emitting diode display device. The information processing device as described in claim 11 is selected from the group consisting of a portable computer, a car computer, a smart watch, a smart bracelet and a smart phone.

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