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TWI880886B - Display device and electronic device - Google Patents

Display device and electronic device Download PDF

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Publication number
TWI880886B
TWI880886B TW106133312A TW106133312A TWI880886B TW I880886 B TWI880886 B TW I880886B TW 106133312 A TW106133312 A TW 106133312A TW 106133312 A TW106133312 A TW 106133312A TW I880886 B TWI880886 B TW I880886B
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TW
Taiwan
Prior art keywords
film
conductive film
metal oxide
insulating film
transistor
Prior art date
Application number
TW106133312A
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Chinese (zh)
Other versions
TW201817014A (en
Inventor
片山雅博
黑崎大輔
岡崎健一
肥純一
Original Assignee
日商半導體能源研究所股份有限公司
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Publication of TW201817014A publication Critical patent/TW201817014A/en
Application granted granted Critical
Publication of TWI880886B publication Critical patent/TWI880886B/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756—Amorphous oxide semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The number of lithography processes is reduced and a high-definition display device is provided. The display device includes a pixel portion and a driver circuit for driving the pixel portion. The pixel portion includes a first transistor and a pixel electrode electrically connected to the first transistor. The driver circuit includes a second transistor and a connection portion. The second transistor includes a metal oxide film, first and second gate electrodes that face each other with the metal oxide film positioned therebetween, source and drain electrodes over and in contact with the metal oxide film, and a first wiring connecting the first and second gate electrodes. The connection portion includes a second wiring on the same surface as the first gate electrode, a third wiring on the same surface as the source electrode and the drain electrode, and a fourth wiring connecting the second wiring and the third wiring. The pixel electrode, the first wiring, and the fourth wiring are formed using the same layer.

Description

顯示裝置及電子裝置Display devices and electronic devices

[0001] 本發明的一個實施方式係關於一種顯示裝置及電子裝置。 [0002] 注意，本發明的一個實施方式不侷限於上述技術領域。本說明書等所公開的發明的一個實施方式的技術領域係關於一種物體、方法或製造方法。另外，本發明的一個實施方式係關於一種製程(process)、機器(machine)、產品(manufacture)或組合物(composition of matter)。本發明的一個實施方式尤其係關於一種半導體裝置、顯示裝置、發光裝置、蓄電裝置、記憶體裝置、其驅動方法或其製造方法。 [0003] 注意，本說明書等中的半導體裝置是指藉由利用半導體特性而能夠工作的所有裝置。除了電晶體等半導體元件之外，半導體電路、運算裝置或記憶體裝置也是半導體裝置的一個實施方式。攝像裝置、顯示裝置、液晶顯示裝置、發光裝置、電光裝置、發電裝置(包括薄膜太陽能電池或有機薄膜太陽能電池等)及電子裝置有時包括半導體裝置。[0001] An embodiment of the present invention relates to a display device and an electronic device. [0002] Note that an embodiment of the present invention is not limited to the above-mentioned technical fields. The technical field of an embodiment of the invention disclosed in this specification, etc. is related to an object, a method or a manufacturing method. In addition, an embodiment of the present invention is related to a process, a machine, a product or a composition of matter. In particular, an embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof or a manufacturing method thereof. [0003] Note that the semiconductor device in this specification, etc. refers to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, or memory devices are also an embodiment of semiconductor devices. Camera devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells or organic thin-film solar cells, etc.) and electronic devices sometimes include semiconductor devices.

[0004] 作為可用於電晶體的半導體材料，氧化物半導體受到矚目。例如，已公開了如下半導體裝置：層疊有多個氧化物半導體層，在該多個氧化物半導體層中，被用作通道的氧化物半導體層包含銦及鎵，並且使銦的比率比鎵的比率高，由此提高場效移動率(有時，簡單地稱為移動率或mFE)的半導體裝置(參照專利文獻1)。 [0005] 另外，將氧化物半導體電晶體用於液晶顯示器或有機EL(Electroluminescence：電致發光)顯示器等顯示裝置的技術受到注目。氧化物半導體電晶體的關態電流(off-state current)非常低。已公開了藉由利用該特性降低顯示靜態影像時的更新頻率，來降低液晶顯示器或有機EL顯示器的功耗的技術(參照專利文獻2及專利文獻3)。注意，在本說明書中，將上述降低顯示裝置的功耗的驅動方法稱為IDS(idling stop：空轉停止)驅動。 [0006] 此外，近年來，隨著顯示裝置的大螢幕化及高清晰化，電晶體被要求微型化。 [0007] [專利文獻1]日本專利申請公開第2014-7399號公報 [專利文獻2]日本專利申請公開第2011-141522號公報 [專利文獻3]日本專利申請公開第2011-141524號公報[0004] Oxide semiconductors have attracted attention as semiconductor materials that can be used for transistors. For example, a semiconductor device has been disclosed in which a plurality of oxide semiconductor layers are stacked, in which an oxide semiconductor layer used as a channel contains indium and gallium, and the ratio of indium is higher than the ratio of gallium, thereby improving field effect mobility (sometimes simply referred to as mobility or mFE) (see Patent Document 1). [0005] In addition, technology for using oxide semiconductor transistors in display devices such as liquid crystal displays or organic EL (Electroluminescence) displays has attracted attention. The off-state current of oxide semiconductor transistors is very low. A technology has been disclosed for reducing the power consumption of a liquid crystal display or an organic EL display by utilizing this characteristic to reduce the refresh frequency when displaying a static image (see Patent Document 2 and Patent Document 3). Note that in this specification, the above-mentioned driving method for reducing the power consumption of the display device is referred to as IDS (idling stop) driving. [0006] In addition, in recent years, with the large-screen and high-definition display devices, transistors have been required to be miniaturized. [0007] [Patent Document 1] Japanese Patent Application Publication No. 2014-7399 [Patent Document 2] Japanese Patent Application Publication No. 2011-141522 [Patent Document 3] Japanese Patent Application Publication No. 2011-141524

[0008] 為了實現電晶體的微型化，在光微影製程中需要高精確度的遮罩位置對準。此外，需要考慮遮罩位置對準的偏差量而使電晶體的各圖案的配置具有餘地，因此難以實現電晶體的微型化。此外，當光微影製程的次數多時，製程變得複雜，導致良率下降。此外，遮罩具有微細形狀且被要求高精確度的形狀，所以其價格非常昂貴。此外，隨著顯示裝置的大螢幕化，閘極佈線及源極佈線等變長，因此佈線電阻增大，功耗變高。 [0009] 鑒於上述問題，本發明的一個實施方式的目的之一是提供一種高解析度的顯示裝置。此外，本發明的一個實施方式的目的之一是提供一種顯示品質高的顯示裝置。此外，本發明的一個實施方式的目的之一是提供一種功耗低的顯示裝置。此外，本發明的一個實施方式的目的之一是提供一種新穎的顯示裝置。此外，本發明的一個實施方式的目的之一是提供一種新穎的電子裝置。 [0010] 注意，上述目的的記載不妨礙其他目的的存在。本發明的一個實施方式並不需要實現所有上述目的。上述目的以外的目的從說明書等的記載看來是顯而易見的，並可以從說明書等中抽取上述目的以外的目的。 [0011] 本發明的一個實施方式是一種顯示裝置，該顯示裝置包括像素部及驅動像素部的驅動電路，其中，像素部包括第一電晶體及與第一電晶體電連接的像素電極，驅動電路包括第二電晶體及連接部，第二電晶體包括金屬氧化物膜、以隔著金屬氧化物膜彼此相對的方式配置的第一閘極電極及第二閘極電極、在金屬氧化物膜上並與其接觸的源極電極及汲極電極以及使第一閘極電極和第二閘極電極連接的第一佈線，連接部包括形成在與第一閘極電極相同的表面上的第二佈線、形成在與源極電極及汲極電極相同的表面上的第三佈線以及使第二佈線和第三佈線連接的第四佈線，並且，像素電極、第一佈線及第四佈線形成在相同的層中。 [0012] 在本發明的一個實施方式的上述顯示裝置中，較佳的是，在第一電晶體與像素電極之間包括具有平坦頂面的第一絕緣膜，在第二電晶體與第一佈線之間包括具有平坦頂面的第二絕緣膜，在第二佈線及第三佈線與第四佈線之間包括具有平坦頂面的第三絕緣膜。 [0013] 本發明的一個實施方式是一種顯示裝置，該顯示裝置包括像素部及驅動像素部的驅動電路，其中，像素部包括第一電晶體及與第一電晶體電連接的像素電極，驅動電路包括第二電晶體及連接部，第二電晶體包括金屬氧化物膜、配置在與金屬氧化物膜重疊的區域的閘極電極以及在金屬氧化物膜上並與其接觸的源極電極及汲極電極，連接部包括形成在與閘極電極相同的表面上的第一佈線、形成在與源極電極及汲極電極相同的表面上的第二佈線以及使第一佈線和第二佈線連接的第三佈線，並且，像素電極及第三佈線形成在相同的層中。 [0014] 在本發明的一個實施方式的上述顯示裝置中，較佳的是，在第一電晶體與像素電極之間包括具有平坦頂面的第一絕緣膜，在第一佈線及第二佈線與第三佈線之間包括具有平坦頂面的第三絕緣膜。 [0015] 本發明的一個實施方式是一種顯示裝置，該顯示裝置包括像素部及驅動像素部的驅動電路，其中，像素部包括第一電晶體及與第一電晶體電連接的像素電極，驅動電路包括第二電晶體及連接部，第二電晶體包括金屬氧化物膜、以隔著金屬氧化物膜彼此相對的方式配置的第一閘極電極及第二閘極電極以及在金屬氧化物膜上並與其接觸的源極電極及汲極電極，連接部包括第一佈線及形成在第一佈線上的第二佈線，第一閘極電極與第二閘極電極電連接，第一佈線形成在與第一閘極電極相同的表面上，第二佈線形成在與源極電極及汲極電極相同的表面上，並且，像素電極及第二閘極電極形成在相同的層中。 [0016] 在本發明的一個實施方式的上述顯示裝置中，較佳的是，在第一電晶體與像素電極之間包括具有平坦頂面的第一絕緣膜，在金屬氧化物膜與第二閘極電極之間包括具有平坦頂面的第二絕緣膜。 [0017] 本發明的一個實施方式是一種顯示裝置，該顯示裝置包括像素部及驅動像素部的驅動電路，其中，像素部包括第一電晶體及與第一電晶體電連接的像素電極，驅動電路包括第二電晶體及連接部，第二電晶體包括金屬氧化物膜、配置在與金屬氧化物膜重疊的區域的閘極電極以及在金屬氧化物膜上並與其接觸的源極電極及汲極電極，連接部包括第一佈線及形成在第一佈線上的第二佈線，第一佈線形成在與閘極電極相同的表面上，並且，第二佈線形成在與源極電極及汲極電極相同的表面上。 [0018] 在本發明的一個實施方式的上述顯示裝置中，較佳的是，在第一電晶體與像素電極之間包括具有平坦頂面的第一絕緣膜。 [0019] 在本發明的一個實施方式中，源極電極及汲極電極的端部也可以位於金屬氧化物膜的端部的內側。 [0020] 在本發明的一個實施方式中，金屬氧化物膜也可以包含銦、鋅及氧。 [0021] 在本發明的一個實施方式中，上述金屬氧化物膜也可以還包含元素M，該元素M為選自鎵、鋁、矽、硼、釔、錫、銅、釩、鈹、鈦、鐵、鎳、鍺、鋯、鉬、鑭、鈰、釹、鉿、鉭、鎢和鎂中的一種或多種。 [0022] 另外，在本發明的一個實施方式中，上述金屬氧化物膜也可以包括在銦、元素M及鋅原子的總和中銦的含量為40%以上且50%以下的區域及元素M的含量為5%以上且30%以下的區域。 [0023] 另外，在本發明的一個實施方式中，在上述金屬氧化物膜中，在銦、元素M及鋅的原子數比為In：M：Zn=4：x：y的情況下，x也可以為1.5以上且2.5以下且y也可以為2以上且4以下。 [0024] 另外，本發明的一個實施方式是一種電子裝置，該電子裝置包括上述顯示裝置中的任一個及接收器。 [0025] 藉由減少光微影製程，可以縮減圖案配置的餘地，並可以實現電晶體的微型化、顯示裝置的高清晰化。此外，藉由減少光微影製程，可以實現製程的簡化、良率的提高。此外，藉由減少光微影製程，可以降低遮罩成本。此外，藉由在接觸部使佈線直接連接，可以實現良好的接觸，而可以降低接觸電阻。 [0026] 藉由本發明的一個實施方式，可以提供一種高解析度的顯示裝置。此外，藉由本發明的一個實施方式，可以提供一種顯示品質高的顯示裝置。此外，藉由本發明的一個實施方式，可以提供一種功耗低的顯示裝置。此外，藉由本發明的一個實施方式，可以提供一種新穎的顯示裝置。此外，藉由本發明的一個實施方式，可以提供一種新穎的電子裝置。 [0027] 注意，上述效果的記載不妨礙其他效果的存在。本發明的一個實施方式並不需要實現所有上述效果。另外，從說明書、圖式、申請專利範圍等的記載中可明顯得知上述以外的效果，而可以從說明書、圖式、申請專利範圍等的記載中衍生上述以外的效果。[0008] In order to achieve miniaturization of transistors, high-precision mask position alignment is required in the photolithography process. In addition, it is necessary to consider the deviation of the mask position alignment so that the configuration of each pattern of the transistor has room, so it is difficult to achieve miniaturization of the transistor. In addition, when the number of photolithography processes is large, the process becomes complicated, resulting in a decrease in yield. In addition, the mask has a fine shape and is required to have a high-precision shape, so it is very expensive. In addition, with the large-screen display device, the gate wiring and the source wiring become longer, so the wiring resistance increases and the power consumption increases. [0009] In view of the above problems, one of the purposes of an embodiment of the present invention is to provide a high-resolution display device. In addition, one of the purposes of an embodiment of the present invention is to provide a display device with high display quality. In addition, one of the purposes of an embodiment of the present invention is to provide a display device with low power consumption. In addition, one of the purposes of an embodiment of the present invention is to provide a novel display device. In addition, one of the purposes of an embodiment of the present invention is to provide a novel electronic device. [0010] Note that the description of the above purposes does not hinder the existence of other purposes. An embodiment of the present invention does not need to achieve all of the above purposes. Purposes other than the above purposes are obvious from the description in the specification, etc., and purposes other than the above purposes can be extracted from the specification, etc. [0011] One embodiment of the present invention is a display device, which includes a pixel portion and a driving circuit for driving the pixel portion, wherein the pixel portion includes a first transistor and a pixel electrode electrically connected to the first transistor, the driving circuit includes a second transistor and a connecting portion, the second transistor includes a metal oxide film, a first gate electrode and a second gate electrode arranged in a manner opposite to each other with the metal oxide film interposed therebetween, A source electrode and a drain electrode are formed on and in contact with the film, and a first wiring connecting the first gate electrode and the second gate electrode, the connecting portion includes a second wiring formed on the same surface as the first gate electrode, a third wiring formed on the same surface as the source electrode and the drain electrode, and a fourth wiring connecting the second wiring and the third wiring, and the pixel electrode, the first wiring and the fourth wiring are formed in the same layer. [0012] In the above display device of an embodiment of the present invention, preferably, a first insulating film having a flat top surface is included between the first transistor and the pixel electrode, a second insulating film having a flat top surface is included between the second transistor and the first wiring, and a third insulating film having a flat top surface is included between the second wiring and the third wiring and the fourth wiring. [0013] One embodiment of the present invention is a display device, which includes a pixel portion and a driving circuit for driving the pixel portion, wherein the pixel portion includes a first transistor and a pixel electrode electrically connected to the first transistor, the driving circuit includes a second transistor and a connecting portion, the second transistor includes a metal oxide film, a gate electrode arranged in a region overlapping the metal oxide film, and a source electrode and a drain electrode on the metal oxide film and in contact with the metal oxide film, the connecting portion includes a first wiring formed on the same surface as the gate electrode, a second wiring formed on the same surface as the source electrode and the drain electrode, and a third wiring connecting the first wiring and the second wiring, and the pixel electrode and the third wiring are formed in the same layer. [0014] In the above-mentioned display device of one embodiment of the present invention, preferably, a first insulating film having a flat top surface is included between the first transistor and the pixel electrode, and a third insulating film having a flat top surface is included between the first wiring and the second wiring and the third wiring. [0015] One embodiment of the present invention is a display device, which includes a pixel portion and a driving circuit for driving the pixel portion, wherein the pixel portion includes a first transistor and a pixel electrode electrically connected to the first transistor, the driving circuit includes a second transistor and a connecting portion, the second transistor includes a metal oxide film, a first gate electrode and a second gate electrode arranged in a manner opposite to each other with the metal oxide film interposed therebetween, and A source electrode and a drain electrode are on and in contact with the metal oxide film, the connection portion includes a first wiring and a second wiring formed on the first wiring, the first gate electrode is electrically connected to the second gate electrode, the first wiring is formed on the same surface as the first gate electrode, the second wiring is formed on the same surface as the source electrode and the drain electrode, and the pixel electrode and the second gate electrode are formed in the same layer. [0016] In the above-mentioned display device of an embodiment of the present invention, preferably, a first insulating film having a flat top surface is included between the first transistor and the pixel electrode, and a second insulating film having a flat top surface is included between the metal oxide film and the second gate electrode. [0017] An embodiment of the present invention is a display device, which includes a pixel portion and a driving circuit for driving the pixel portion, wherein the pixel portion includes a first transistor and a pixel electrode electrically connected to the first transistor, the driving circuit includes a second transistor and a connecting portion, the second transistor includes a metal oxide film, a gate electrode arranged in a region overlapping the metal oxide film, and a source electrode and a drain electrode on and in contact with the metal oxide film, the connecting portion includes a first wiring and a second wiring formed on the first wiring, the first wiring is formed on the same surface as the gate electrode, and the second wiring is formed on the same surface as the source electrode and the drain electrode. [0018] In the above-mentioned display device of an embodiment of the present invention, preferably, a first insulating film having a flat top surface is included between the first transistor and the pixel electrode. [0019] In an embodiment of the present invention, the end portions of the source electrode and the drain electrode may also be located inside the end portions of the metal oxide film. [0020] In an embodiment of the present invention, the metal oxide film may also contain indium, zinc and oxygen. [0021] In one embodiment of the present invention, the metal oxide film may further include an element M, and the element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, curium, titanium, iron, nickel, germanium, zirconium, molybdenum, tungsten, and magnesium. [0022] In addition, in one embodiment of the present invention, the metal oxide film may also include a region where the content of indium in the total of indium, element M, and zinc atoms is 40% or more and 50% or less, and a region where the content of element M is 5% or more and 30% or less. [0023] In addition, in one embodiment of the present invention, in the above-mentioned metal oxide film, when the atomic ratio of indium, element M and zinc is In:M:Zn=4:x:y, x can also be greater than 1.5 and less than 2.5 and y can also be greater than 2 and less than 4. [0024] In addition, an embodiment of the present invention is an electronic device, which includes any one of the above-mentioned display devices and a receiver. [0025] By reducing the photolithography process, the margin for pattern configuration can be reduced, and the miniaturization of transistors and the high definition of display devices can be achieved. In addition, by reducing the photolithography process, the process can be simplified and the yield can be improved. In addition, by reducing the photolithography process, the mask cost can be reduced. In addition, by directly connecting the wiring at the contact portion, good contact can be achieved, and the contact resistance can be reduced. [0026] According to an embodiment of the present invention, a high-resolution display device can be provided. According to an embodiment of the present invention, a display device with high display quality can be provided. According to an embodiment of the present invention, a display device with low power consumption can be provided. According to an embodiment of the present invention, a novel display device can be provided. According to an embodiment of the present invention, a novel electronic device can be provided. [0027] Note that the description of the above-mentioned effects does not hinder the existence of other effects. An embodiment of the present invention does not need to achieve all of the above-mentioned effects. In addition, effects other than the above are clearly apparent from the description in the specification, drawings, claims, etc., and effects other than the above can be derived from the description in the specification, drawings, claims, etc.

[0029] 下面，參照圖式對實施方式進行說明。注意，所屬技術領域的通常知識者可以很容易地理解一個事實，就是實施方式可以以多個不同形式來實施，其方式和詳細內容可以在不脫離本發明的精神及其範圍的條件下被變換為各種各樣的形式。因此，本發明不應該被解釋為僅限定在下面的實施方式所記載的內容中。 [0030] 在圖式中，為便於清楚地說明，有時誇大表示大小、層的厚度或區域。因此，本發明並不一定限定於上述尺寸。此外，在圖式中，示意性地示出理想的例子，因此本發明不侷限於圖式所示的形狀或數值等。 [0031] 在本說明書中使用的“第一”、“第二”、“第三”等序數詞是為了避免組件的混淆而附加的，而不是為了在數目方面上進行限定的。 [0032] 在本說明書中，為方便起見，使用“上”、“下”等表示配置的詞句，以參照圖式說明組件的位置關係。另外，組件的位置關係根據描述各組件的方向適當地改變。因此，不侷限於本說明書中所說明的詞句，可以根據情況適當地更換。 [0033] 在本說明書等中，電晶體是指至少包括閘極、汲極以及源極這三個端子的元件。電晶體在汲極(汲極端子、汲極區域或汲極電極)與源極(源極端子、源極區域或源極電極)之間具有通道區，並且電流能夠藉由通道區流過源極與汲極之間。注意，在本說明書等中，通道區是指電流主要流過的區域。 [0034] 另外，在使用極性不同的電晶體的情況或電路工作中的電流方向變化的情況等下，源極及汲極的功能有時相互調換。因此，在本說明書等中，源極和汲極可以相互調換。 [0035] 在本說明書等中，“電連接”包括藉由“具有某種電作用的元件”連接的情況。在此，“具有某種電作用的元件”只要可以進行連接目標間的電信號的授收，就對其沒有特別的限制。例如，“具有某種電作用的元件”不僅包括電極和佈線，而且還包括電晶體等的切換元件、電阻器、電感器、電容器、其他具有各種功能的元件等。 [0036] 在本說明書等中，“平行”是指兩條直線形成的角度為-10°以上且10°以下的狀態。因此，也包括該角度為-5°以上且5°以下的狀態。另外，“垂直”是指兩條直線形成的角度為80°以上且100°以下的狀態。因此也包括該角度為85°以上且95°以下的角度的狀態。 [0037] 另外，在本說明書等中，可以將“膜”和“層”相互調換。例如，有時可以將“導電層”變換為“導電膜”。此外，例如，有時可以將“絕緣膜”變換為“絕緣層”。 [0038] 在本說明書等中，在沒有特別的說明的情況下，關態電流(off-state current)是指電晶體處於關閉狀態(也稱為非導通狀態、遮斷狀態)的汲極電流。在沒有特別的說明的情況下，在n通道電晶體中，關閉狀態是指閘極與源極間的電壓Vgs低於臨界電壓Vth的狀態，在p通道電晶體中，關閉狀態是指閘極與源極間的電壓Vgs高於臨界電壓Vth的狀態。例如，n通道電晶體的關態電流有時是指閘極與源極間的電壓Vgs低於臨界電壓Vth時的汲極電流。 [0039] 電晶體的關態電流有時取決於Vgs。因此，“電晶體的關態電流為I以下”有時是指存在使電晶體的關態電流成為I以下的Vgs的值。電晶體的關態電流有時是指：當Vgs為預定的值時的關閉狀態；當Vgs為預定的範圍內的值時的關閉狀態；或者當Vgs為能夠獲得充分低的關態電流的值時的關閉狀態等。 [0040] 作為一個例子，設想一種n通道電晶體，該n通道電晶體的臨界電壓Vth為0.5V，Vgs為0.5V時的汲極電流為1´10-9 A，Vgs為0.1V時的汲極電流為1´10-13 A，Vgs為-0.5V時的汲極電流為1´10-19 A，Vgs為-0.8V時的汲極電流為1´10-22 A。在Vgs為-0.5V時或在Vgs為-0.5V至-0.8V的範圍內，該電晶體的汲極電流為1´10-19 A以下，所以有時稱該電晶體的關態電流為1´10-19 A以下。由於存在使該電晶體的汲極電流成為1´10-22 A以下的Vgs，因此有時稱該電晶體的關態電流為1´10-22 A以下。 [0041] 在本說明書等中，有時以每通道寬度W的電流值表示具有通道寬度W的電晶體的關態電流。另外，有時以每預定的通道寬度(例如1mm)的電流值表示具有通道寬度W的電晶體的關態電流。在為後者時，關態電流的單位有時以具有電流/長度的次元的單位(例如，A/mm)表示。 [0042] 電晶體的關態電流有時取決於溫度。在本說明書中，在沒有特別的說明的情況下，關態電流有時表示在室溫、60℃、85℃、95℃或125℃下的關態電流。或者，有時表示在保證包括該電晶體的半導體裝置等的可靠性的溫度下或者在包括該電晶體的半導體裝置等被使用的溫度(例如，5℃至35℃中的任一溫度)下的關態電流。“電晶體的關態電流為I以下”有時是指在室溫、60℃、85℃、95℃、125℃、保證包括該電晶體的半導體裝置的可靠性的溫度下或者在包括該電晶體的半導體裝置等被使用的溫度(例如，5℃至35℃中的任一溫度)下存在使電晶體的關態電流成為I以下的Vgs的值。 [0043] 電晶體的關態電流有時取決於汲極與源極間的電壓Vds。在本說明書中，在沒有特別的說明的情況下，關態電流有時表示Vds為0.1V、0.8V、1V、1.2V、1.8V、2.5V、3V、3.3V、10V、12V、16V或20V時的關態電流。或者，有時表示保證包括該電晶體的半導體裝置等的可靠性的Vds時或者包括該電晶體的半導體裝置等所使用的Vds時的關態電流。“電晶體的關態電流為I以下”有時是指：在Vds為0.1V、0.8V、1V、1.2V、1.8V、2.5V、3V、3.3V、10V、12V、16V、20V、保證包括該電晶體的半導體裝置的可靠性的Vds或包括該電晶體的半導體裝置等被使用的Vds下存在使電晶體的關態電流成為I以下的Vgs的值。 [0044] 在上述關態電流的說明中，可以將汲極換稱為源極。也就是說，關態電流有時指電晶體處於關閉狀態時流過源極的電流。 [0045] 在本說明書等中，有時將關態電流記作洩漏電流。在本說明書等中，關態電流例如有時指在電晶體處於關閉狀態時流在源極與汲極間的電流。 [0046] 在本說明書等中，電晶體的臨界電壓是指在電晶體中形成通道時的閘極電壓(Vg)。明確而言，電晶體的臨界電壓有時是指：在以橫軸表示閘極電壓(Vg)且以縱軸表示汲極電流(Id)的平方根，而標繪出的曲線(Vg-ÖId特性)中，在將具有最大傾斜度的切線外推時的直線與汲極電流(Id)的平方根為0(Id為0A)處的交叉點的閘極電壓(Vg)。或者，電晶體的臨界電壓有時是指在以L為通道長度且以W為通道寬度，Id[A]´L[mm]/W[mm]的值為1´10-9 [A]時的閘極電壓(Vg)。 [0047] 注意，在本說明書等中，例如在導電性充分低時，有時即便在表示為“半導體”時也具有“絕緣體”的特性。此外，“半導體”與“絕緣體”的邊境不清楚，因此有時不能精確地區別。由此，有時可以將本說明書等所記載的“半導體”換稱為“絕緣體”。同樣地，有時可以將本說明書等所記載的“絕緣體”換稱為“半導體”。或者，有時可以將本說明書等所記載的“絕緣體”換稱為“半絕緣體”。 [0048] 另外，在本說明書等中，例如在導電性充分高時，有時即便在表示為“半導體”時也具有“導電體”的特性。此外，“半導體”和“導電體”的邊境不清楚，因此有時不能精確地區別。由此，有時可以將本說明書所記載的“半導體”換稱為“導電體”。同樣地，有時可以將本說明書所記載的“導電體”換稱為“半導體”。 [0049] 注意，在本說明書等中，半導體的雜質是指構成半導體膜的主要成分之外的元素。例如，濃度低於0.1atomic%的元素是雜質。當包含雜質時，有可能在半導體中形成DOS(Density of States：態密度)，載子移動率有可能降低或結晶性有可能降低。在半導體包含氧化物半導體時，作為改變半導體特性的雜質，例如有第1族元素、第2族元素、第13族元素、第14族元素、第15族元素或主要成分之外的過渡金屬等，尤其是，有氫(包含於水中)、鋰、鈉、矽、硼、磷、碳、氮等。在是氧化物半導體的情況下，有時例如由於氫等雜質的混入導致氧缺陷的產生。此外，當半導體是矽時，作為改變半導體特性的雜質，例如有氧、除氫之外的第1族元素、第2族元素、第13族元素、第15族元素等。 [0050] 在本說明書等中，金屬氧化物(metal oxide)是指廣義上的金屬的氧化物。金屬氧化物被分類為氧化物絕緣體、氧化物導電體(包括透明氧化物導電體)和氧化物半導體(Oxide Semiconductor，也可以簡稱為OS)等。例如，在將金屬氧化物用於電晶體的活性層的情況下，有時將該金屬氧化物稱為氧化物半導體。換言之，在金屬氧化物具有放大作用、整流作用和開關作用中的至少一個的情況下，可以將該金屬氧化物稱為金屬氧化物半導體(metal oxide semiconductor)，或者可以將其簡稱為OS。另外，可以將OS FET稱為包含金屬氧化物或氧化物半導體的電晶體。 [0051] 在本說明書等中，有時將包含氮的金屬氧化物稱為金屬氧化物(metal oxide)。另外，也可以將包含氮的金屬氧化物稱為金屬氧氮化物(metal oxynitride)。 [0052] 實施方式1 在本實施方式中，參照圖1A至圖46D說明本發明的一個實施方式的顯示裝置及其製造方法。 [0053] á1-1.顯示裝置的結構實例1ñ 圖1A、圖1B和圖1C示出本發明的一個實施方式的顯示裝置所包括的像素部及驅動電路中的電晶體的剖面圖，圖2A和圖2B示出其俯視圖。 [0054] 本發明的一個實施方式的顯示裝置包括電晶體100A、電晶體200A、電容器250A及連接部150A。 [0055] 圖1A是包括在像素部中的電晶體200A及電容器250A的剖面圖，且相當於沿著圖2A的點劃線X1-X2的剖面圖。圖1B是包括在驅動電路中的電晶體100A及連接部150A的剖面圖，且相當於沿著圖2B的點劃線X3-X4的剖面圖。圖1C是包括在驅動電路中的電晶體100A的剖面圖，且相當於沿著圖2B的點劃線Y1-Y2的剖面圖。注意，在圖2A和圖2B中，為了方便起見，省略電晶體100A、電晶體200A及電容器250A的組件的一部分(被用作閘極絕緣膜的絕緣膜等)。此外，有時在各電晶體中將點劃線X1-X2方向稱為通道長度方向，將點劃線Y1-Y2方向稱為通道寬度方向。注意，有時在後面的電晶體的俯視圖中也與圖2A和圖2B同樣地省略組件的一部分。 [0056] 如圖1A所示，像素部包括電晶體200A、被用作像素電極的導電膜220及電容器250A。被用作像素電極的導電膜220與電晶體200A電連接。 [0057] 電晶體200A包括：基板102上的導電膜204；基板102及導電膜204上的絕緣膜106；絕緣膜106上的金屬氧化物膜208；金屬氧化物膜208上的導電膜212a；以及金屬氧化物膜208上的導電膜212b。 [0058] 在電晶體200A中，絕緣膜106被用作閘極絕緣膜。此外，在電晶體200A中，導電膜204被用作閘極電極，導電膜212a被用作源極電極，導電膜212b被用作汲極電極。 [0059] 在電晶體200A中，導電膜212a及導電膜212b的端部位於金屬氧化物膜208的端部的內側。 [0060] 在電晶體200A上，明確而言，在金屬氧化物膜208、導電膜212a及導電膜212b上形成有絕緣膜114、絕緣膜114上的絕緣膜116、絕緣膜116上的絕緣膜118以及絕緣膜118上的絕緣膜119。在電晶體200A中，絕緣膜114、絕緣膜116及絕緣膜118被用作電晶體200A的保護絕緣膜。此外，絕緣膜119被用作平坦化膜。 [0061] 絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119在與導電膜212b重疊的區域具有開口242a。被用作像素電極的導電膜220藉由開口242a與導電膜212b電連接。 [0062] 電晶體200A為所謂的通道蝕刻型電晶體，具有單閘極結構。 [0063] 由導電膜213、絕緣膜106、金屬氧化物膜228和導電膜215a形成電容器250A。被用作電容佈線的導電膜213與導電膜204、104、113在同一製程中形成在同一平面上。導電膜215a與導電膜212a、212b、112a、112b、115a在同一製程中形成在同一平面上。 [0064] 在電容器250A中，導電膜215a的端部位於金屬氧化物膜228的端部的內側。 [0065] 被用作像素電極的導電膜220形成在絕緣膜119上。設置在被用作平坦化膜的絕緣膜119上的導電膜220也具有高平坦性。由於導電膜220的平坦性高，所以在顯示裝置為液晶顯示裝置的情況下，可以減少液晶層的配向不良。此外，藉由利用絕緣膜119可以擴大被用作閘極佈線的導電膜204與導電膜220的間隔以及被用作信號線的導電膜212a與導電膜220的間隔，由此可以降低佈線延遲。 [0066] 如圖1B及圖1C所示，驅動電路包括電晶體100A及連接部150A。 [0067] 在電晶體100A中，形成有：基板102上的導電膜104；基板102及導電膜104上的絕緣膜106；絕緣膜106上的金屬氧化物膜108；金屬氧化物膜108上的導電膜112a；金屬氧化物膜108上的導電膜112b；金屬氧化物膜108、導電膜112a及導電膜112b上的絕緣膜114；絕緣膜114上的絕緣膜116；絕緣膜116上的絕緣膜118；絕緣膜118上的導電膜130a。 [0068] 在電晶體100A中，絕緣膜106被用作第一閘極絕緣膜，絕緣膜114、絕緣膜116及絕緣膜118被用作第二閘極絕緣膜。此外，在電晶體100A中，導電膜104被用作第一閘極電極，導電膜130a被用作第二閘極電極。此外，在電晶體100A中，導電膜112a被用作源極電極，導電膜112b被用作汲極電極。 [0069] 在電晶體100A中，導電膜112a及導電膜112b的端部位於金屬氧化物膜108的端部的內側。 [0070] 在電晶體100A上，明確而言，在絕緣膜118及導電膜130a上形成有絕緣膜119。在電晶體100A中，絕緣膜119被用作平坦化膜。 [0071] 在電晶體100A中，絕緣膜106、絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119在與導電膜104重疊的區域包括開口146a。此外，絕緣膜119在與導電膜130a重疊的區域包括開口148a。被用作第一佈線的導電膜120b藉由開口146a及開口148a與導電膜130a及導電膜104電連接。藉由設置導電膜120b，被用作電晶體100A的第一閘極電極的導電膜104與被用作第二閘極電極的導電膜130a電連接。 [0072] 電晶體100A為所謂的通道蝕刻型電晶體，具有雙閘極結構。 [0073] 如圖1B所示，電晶體100A的金屬氧化物膜108位於與導電膜104及導電膜130a相對的位置，夾在兩個被用作閘極電極的導電膜之間。導電膜130a的通道長度方向上的長度及導電膜130a的通道寬度方向上的長度分別比金屬氧化物膜108的通道長度方向上的長度及金屬氧化物膜108的通道寬度方向上的長度長，並且導電膜130a隔著絕緣膜114、絕緣膜116及絕緣膜118覆蓋金屬氧化物膜108整體。 [0074] 換言之，導電膜104及導電膜130a藉由形成在絕緣膜106、絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119中的開口彼此連接且包括位於金屬氧化物膜108的側端部的外側的區域。 [0075] 藉由採用上述結構，可以利用導電膜104及導電膜130a的電場電圍繞電晶體100A所包括的金屬氧化物膜108。可以將如電晶體100A那樣利用第一閘極電極及第二閘極電極的電場電圍繞形成有通道區的金屬氧化物膜的電晶體的裝置結構稱為Surrounded channel(S-channel：圍繞通道)結構。 [0076] 因為電晶體100A具有S-channel結構，所以可以使用被用作第一閘極電極的導電膜104對金屬氧化物膜108有效地施加用來引起通道的電場，由此，電晶體100A的電流驅動能力得到提高，從而可以得到高通態電流特性。此外，由於可以提高通態電流，所以可以使電晶體100A微型化。另外，由於金屬氧化物膜108被用作第一閘極電極的導電膜104與用作第二閘極電極的導電膜130a圍繞，所以可以提高電晶體100A的機械強度。 [0077] 此外，在電晶體100A中，金屬氧化物膜108包括：絕緣膜106上的金屬氧化物膜108_1；以及金屬氧化物膜108_1上的金屬氧化物膜108_2。另外，在電晶體200A中，金屬氧化物膜208包括：絕緣膜106上的金屬氧化物膜208_1；以及金屬氧化物膜208_1上的金屬氧化物膜208_2。此外，金屬氧化物膜108_1、108_2、208_1、208_2都包含相同的元素。例如，金屬氧化物膜108_1、108_2、208_1、208_2較佳為獨立地包含In、M(M為鎵、鋁、矽、硼、釔、錫、銅、釩、鈹、鈦、鐵、鎳、鍺、鋯、鉬、鑭、鈰、釹、鉿、鉭、鎢或鎂)和Zn。 [0078] 此外，金屬氧化物膜108_1、108_2、208_1、208_2較佳為獨立地包括In的原子個數比大於M的原子個數比的區域。例如，較佳為將金屬氧化物膜108_1、108_2、208_1、208_2的In、M和Zn的原子個數比設定為In：M：Zn=4：2：3或其附近。在此，“附近”包括：當In為4時，M為1.5以上且2.5以下，並且Zn為2以上且4以下的情況。或者，較佳為將金屬氧化物膜108_1、108_2、208_1、208_2的In、M和Zn的原子個數比設定為In：M：Zn=5：1：6或其附近。如此，當金屬氧化物膜108_1、108_2、208_1、208_2的組成大致相同時，可以使用相同的濺射靶材，所以可以抑制製造成本。另外，在使用相同的濺射靶材的情況下，可以在同一處理室中在真空中連續地形成金屬氧化物膜108_1、108_2、208_1、208_2，所以可以抑制雜質混入金屬氧化物膜108_1與金屬氧化物膜108_2的介面和金屬氧化物膜208_1與金屬氧化物膜208_2的介面。 [0079] 金屬氧化物膜108_1、金屬氧化物膜108_2、金屬氧化物膜208_1、金屬氧化物膜208_2較佳為具有CAC(Cloud-Aligned Composite)構成的金屬氧化物。參照圖47對該金屬氧化物進行說明。 [0080] 圖47示出具有CAC構成的金屬氧化物的示意圖。注意，在本說明書中，在本發明的一個實施方式的金屬氧化物具有半導體的功能的情況下，定義為CAC-MO(Metal Oxide Semiconductor)或CAC-OS(Oxide Semiconductor)。 [0081] 例如，如圖47所示，在CAC-MO或CAC-OS中包含在金屬氧化物中的元素不均勻地分佈，以各元素為主要成分的區域001及區域002混合而成為或分散為馬賽克(mosaic)狀。換言之，CAC-OS是包含在金屬氧化物中的元素不均勻地分佈的構成，其中包含不均勻地分佈的元素的材料的尺寸為0.5nm以上且10nm以下，較佳為1nm以上且2nm以下或附近的尺寸。注意，在下面也將在金屬氧化物中一個或多個金屬元素不均勻地分佈且包含該金屬元素的區域混合的狀態稱為馬賽克狀或補丁(patch)狀，該區域的尺寸為0.5nm以上且10nm以下，較佳為1nm以上且2nm以下或附近的尺寸。 [0082] 另外，CAC-MO或CAC-OS在材料的一部分中具有導電性的功能，在材料的另一部分中具有絕緣性的功能，作為材料的整體具有半導體的功能。此外，在將CAC-MO或CAC-OS用於電晶體的通道的情況下，導電性的功能是使被用作載子的電子(或電洞)流過的功能，絕緣性的功能是不使被用作載子的電子流過的功能。藉由導電性的功能和絕緣性的功能的互補作用，可以使CAC-MO或CAC-OS具有開關功能(開啟/關閉的功能)。藉由在CAC-MO或CAC-OS中使各功能分離，可以最大限度地提高各功能。 [0083] 在本說明書等中，CAC-MO或CAC-OS包括導電性區域及絕緣性區域。例如，圖47所示的區域001及區域002中的一個可以是導電性區域，另一個可以是絕緣性區域。導電性區域具有上述導電性的功能，絕緣性區域具有上述絕緣性的功能。在材料中，導電性區域和絕緣性區域有時以奈米粒子級分離。另外，導電性區域和絕緣性區域有時在材料中不均勻地分佈。此外，有時觀察到其邊緣模糊而以雲狀連接的導電性區域。 [0084] CAC-MO或CAC-OS由具有不同能帶間隙的成分構成。例如，CAC-MO或CAC-OS由具有起因於絕緣性區域的寬隙的成分及具有起因於導電性區域的窄隙的成分構成。在該構成中，當使載子流過時，載子主要在具有窄隙的成分中流過。此外，具有窄隙的成分與具有寬隙的成分互補作用，與具有窄隙的成分聯動地在具有寬隙的成分中載子流過。因此，在將上述CAC-MO或CAC-OS用於電晶體的通道區時，在電晶體的導通狀態中可以得到高電流驅動力，亦即大通態電流及高場效移動率。 [0085] 就是說，也可以將CAC-MO或CAC-OS稱為基質複合材料(matrix composite)或金屬基質複合材料(metal matrix composite)。關於CAC-MO或CAC-OS，將在實施方式2中進行詳細的說明。 [0086] 藉由使金屬氧化物膜108_1、108_2、208_1、208_2獨立地包括其In的原子個數比大於M的原子個數比的區域且具有CAC構成，可以提高電晶體100A、200A的場效移動率。明確而言，電晶體100A、200A的場效移動率可以超過40cm2 /Vs，較佳為超過50cm2 /Vs，更佳為超過100cm2 /Vs。 [0087] 具有S-Channel結構的電晶體100A具有高場效移動率及高驅動能力，因此藉由將電晶體100A用於驅動電路，典型的是用於生成閘極信號的閘極驅動器，可以提供一種邊框寬度窄(也稱為窄邊框)的顯示裝置。此外，藉由將電晶體100A用於顯示裝置所包括的供應來自信號線的信號的源極驅動器(尤其是，與源極驅動器所包括的移位暫存器的輸出端子連接的解多工器)，可以提供一種與顯示裝置連接的佈線數較少的顯示裝置。 [0088] 另外，由於電晶體100A、電晶體200A為通道蝕刻結構的電晶體，因此與頂閘極結構的電晶體相比，製程數較少。另外，由於電晶體100A、電晶體200A的通道使用金屬氧化物膜，因此電晶體100A、200A不需要使用低溫多晶矽的電晶體所需要的雷射晶化製程。因此，即使是使用大面積基板的顯示裝置，也可以降低製造成本。再者，藉由在Ultra High Definition(“4K解析度”、“4K2K”、“4K”)和Super High Definition(“8K解析度”、“8K4K”、“8K”)等高解析度的大型顯示裝置中將如電晶體100A、200A那樣場效移動率高的電晶體用於驅動電路及顯示部，可以實現短時間的寫入及顯示不良的降低，所以是較佳的。 [0089] 連接部150A包括：基板102上的被用作第二佈線的導電膜113；設置在被用作第二佈線的導電膜113上的絕緣膜106、絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119中的開口142a；金屬氧化物膜128上的被用作第三佈線的導電膜115a；設置在被用作第三佈線的導電膜115a上的絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119中的開口144a；以及被用作第四佈線的導電膜120a，該導電膜120a以覆蓋開口142a及開口144a的方式形成且使被用作第二佈線的導電膜113與被用作第三佈線的導電膜115a連接。在圖1B中，開口142a及開口144a為具有一個步階的形狀，但也可以為具有兩個以上的步階的形狀。 [0090] 在連接部150A中，導電膜115a的端部位於金屬氧化物膜128的端部的內側。 [0091] 被用作第二佈線的導電膜113與被用作電晶體100A的第一閘極電極的導電膜104在同一製程中形成在同一平面上。被用作第三佈線的導電膜115a與被用作電晶體100A的源極電極的導電膜112a及被用作汲極電極的導電膜112b在同一製程中形成在同一平面上。被用作第四佈線的導電膜120a與被用作像素電極的導電膜220在同一製程中形成在同一平面上。 [0092] 換言之，被用作第二佈線的導電膜113與被用作電晶體100A的第一閘極電極的導電膜104使用相同的層形成。被用作第三佈線的導電膜115a與被用作電晶體100A的源極電極的導電膜112a及被用作汲極電極的導電膜112b使用相同的層形成。被用作第四佈線的導電膜120a與被用作像素電極的導電膜220使用相同的層形成。 [0093] 被用作像素電極的導電膜220、被用作第一佈線的導電膜120b及被用作第四佈線的導電膜120a在同一製程中形成。換言之，被用作像素電極的導電膜220、被用作第一佈線的導電膜120b及被用作第四佈線的導電膜120a使用相同的層形成。此外，被用作像素電極的導電膜220、被用作第一佈線的導電膜120b及被用作第四佈線的導電膜120a接觸於被用作平坦化膜的絕緣膜119的頂面。 [0094] á1-2.顯示裝置的組件ñ 接著，對本實施方式的顯示裝置所包括的組件進行詳細的說明。 [0095] [基板] 雖然對基板102的材料等沒有特別的限制，但是至少需要能夠承受後續的加熱處理的耐熱性。例如，作為基板102，可以使用玻璃基板、陶瓷基板、石英基板、藍寶石基板等。另外，還可以使用以矽或碳化矽為材料的單晶半導體基板或多晶半導體基板、以矽鍺等為材料的化合物半導體基板、SOI(Silicon On Insulator：絕緣層上覆矽)基板等，並且也可以將設置有半導體元件的上述基板用作基板102。當作為基板102使用玻璃基板時，藉由使用第六代(1500mm´1850mm)、第七代(1870mm´2200mm)、第八代(2200mm´2400mm)、第九代(2400mm´2800mm)、第十代(2950mm´3400mm)等的大面積基板，可以製造大型顯示裝置。 [0096] 作為基板102，也可以使用撓性基板，並且在撓性基板上直接形成電晶體100A、200A。或者，也可以在基板102與電晶體100A、200A之間設置剝離層。剝離層可以在如下情況下使用，亦即在剝離層上製造半導體裝置的一部分或全部，然後將其從基板102分離並轉置到其他基板上的情況。此時，也可以將電晶體100A、200A轉置到耐熱性低的基板或撓性基板上。 [0097] [導電膜] 被用作閘極電極的導電膜104、204、被用作源極電極的導電膜112a、212a及被用作汲極電極的導電膜112b、212b可以使用選自鉻(Cr)、銅(Cu)、鋁(Al)、金(Au)、銀(Ag)、鋅(Zn)、鉬(Mo)、鉭(Ta)、鈦(Ti)、鎢(W)、錳(Mn)、鎳(Ni)、鐵(Fe)、鈷(Co)中的金屬元素、以上述金屬元素為成分的合金或者組合上述金屬元素的合金等形成。 [0098] 另外，作為導電膜104、112a、112b、204、212a、212b，可以使用包含銦和錫的氧化物(In-Sn氧化物)、包含銦和鎢的氧化物(In-W氧化物)、包含銦、鎢及鋅的氧化物(In-W-Zn氧化物)、包含銦和鈦的氧化物(In-Ti氧化物)、包含銦、鈦及錫的氧化物(In-Ti-Sn氧化物)、包含銦和鋅的氧化物(In-Zn氧化物)、包含銦、錫及矽的氧化物(In-Sn-Si氧化物)、包含銦、鎵及鋅的氧化物(In-Ga-Zn氧化物)等氧化物導電體或氧化物半導體。 [0099] 在此，說明氧化物導電體。在本說明書等中，也可以將氧化物導電體稱為OC(Oxide Conductor)。例如，在氧化物半導體中形成氧缺陷，對該氧缺陷添加氫而在導帶附近形成施體能階。其結果是，氧化物半導體的導電性增高，而成為導電體。可以將成為導電體的氧化物半導體稱為氧化物導電體。一般而言，由於金屬氧化物的能隙大，因此對可見光具有透光性。另一方面，氧化物導電體是在導帶附近具有施體能階的氧化物半導體。因此，在氧化物導電體中，起因於施體能階的吸收的影響小，而對可見光具有與金屬氧化物大致相同的透光性。 [0100] 氧化物導電體的氫濃度比被用作通道的金屬氧化物(例如，氧化物半導體)高，典型的是8´1019 atoms/cm3 以上，較佳為1´1020 atoms/cm3 以上，較佳為5´1020 atoms/cm3 以上。 [0101] 氧化物導電體在具有缺陷且包含雜質時具有導電性。包含氧化物導電體的導電膜的電阻率為1´10-3 Wcm以上且低於1´104 Wcm，進一步較佳為1´10-3 Wcm以上且低於1´10-1 Wcm。 [0102] 另外，較佳為包含氧化物導電體的導電膜的導電率典型的是1´10-2 S/m以上且1´105 S/m以下，或者1´103 S/m以上且1´105 S/m以下。 [0103] 氧化物導電體包含雜質及缺陷。典型的是，包含氧化物導電體的導電膜是藉由稀有氣體的添加而生成缺陷的膜。或者，藉由電漿的暴露而生成缺陷的膜。 [0104] 另外，作為導電膜104、112a、112b、204、212a、212b，也可以應用Cu-X合金膜(X為Mn、Ni、Cr、Fe、Co、Mo、Ta或Ti)。藉由使用Cu-X合金膜，可以以濕蝕刻製程進行加工，從而可以抑制製造成本。由於Cu-X合金膜的電阻低，所以藉由使用Cu-X合金膜形成導電膜104、112a、112b、204、212a、212b，可以抑制佈線延遲。因此，在製造大型顯示裝置時使用Cu-X合金膜作為佈線是較佳的。 [0105] 此外，導電膜112a、112b、212a、212b尤其較佳為包含上述金屬元素中的銅、鈦、鎢、鉭和鉬中的一個或多個。尤其是，作為導電膜112a、112b、212a、212b，較佳為使用氮化鉭膜。該氮化鉭膜具有導電性且對銅或氫具有高阻擋性。此外，因為氮化鉭膜的氫的釋放量少，所以氮化鉭膜最適合用於與金屬氧化物膜108、208接觸的導電膜或金屬氧化物膜108、208附近的導電膜。此外，當作為導電膜112a、112b、212a、212b使用銅膜時，可以降低導電膜112a、112b、212a、212b的電阻，所以是較佳的。 [0106] 可以藉由無電鍍法形成導電膜112a、112b、212a、212b。作為藉由該無電鍍法可形成的材料，例如可以使用選自Cu、Ni、Al、Au、Sn、Co、Ag和Pd中的一個或多個。尤其是，由於在使用Cu或Ag時，可以降低導電膜的電阻，所以是較佳的。 [0107] [被用作閘極絕緣膜的絕緣膜] 作為被用作電晶體100A、200A的閘極絕緣膜的絕緣膜106，可以藉由電漿增強化學氣相沉積(PECVD：Plasma Enhanced Chemical Vapor Deposition)法、濺射法等形成包括氧化矽膜、氧氮化矽膜、氮氧化矽膜、氮化矽膜、氧化鋁膜、氧化鉿膜、氧化釔膜、氧化鋯膜、氧化鎵膜、氧化鉭膜、氧化鎂膜、氧化鑭膜、氧化鈰膜和氧化釹膜中的一種以上的絕緣層。注意，絕緣膜106也可以具有兩層或三層以上的疊層結構。 [0108] 此外，較佳的是，與被用作電晶體100A、200A的通道區的金屬氧化物膜108、208接觸的絕緣膜106為氧化物絕緣膜，更佳的是，該氧化物絕緣膜具有氧含量超過化學計量組成的區域(過量氧區域)。換言之，絕緣膜106能夠釋放氧。為了在絕緣膜106中形成過量氧區域，例如可以在氧氛圍下形成絕緣膜106或者在氧氛圍下對成膜之後的絕緣膜106進行加熱處理。 [0109] 此外，當絕緣膜106使用氧化鉿時發揮如下效果。氧化鉿的相對介電常數比氧化矽或氧氮化矽高。因此，藉由使用氧化鉿，與使用氧化矽的情況相比，可以使絕緣膜106的厚度變大，由此，可以減少穿隧電流引起的洩漏電流。亦即，可以實現關態電流小的電晶體。再者，與具有非晶結構的氧化鉿相比，具有結晶結構的氧化鉿具有高相對介電常數。因此，為了形成關態電流小的電晶體，較佳為使用具有結晶結構的氧化鉿。作為結晶結構的例子，可以舉出單斜晶系或立方晶系等。注意，本發明的一個實施方式不侷限於此。 [0110] 注意，不侷限於上述結構，作為接觸於金屬氧化物膜108、208的絕緣膜也可以使用氮化物絕緣膜。例如，可以舉出藉由形成氮化矽膜並對該氮化矽膜的表面進行氧電漿處理等來使氮化矽膜的表面氧化的結構。注意，在對氮化矽膜的表面進行氧電漿處理等的情況下，氮化矽膜的表面有可能在原子級上被氧化，因此有時藉由電晶體的剖面觀察等觀察不到氧化膜。換言之，當觀察電晶體的剖面時，有時觀察到氮化矽膜接觸於金屬氧化物。 [0111] 與氧化矽膜相比，氮化矽膜的相對介電常數較高且為了得到與氧化矽膜相等的靜電容量所需要的厚度較大，因此，藉由使電晶體的閘極絕緣膜包括氮化矽膜，可以增加絕緣膜的厚度。因此，可以藉由抑制電晶體的絕緣耐壓的下降並提高絕緣耐壓來抑制電晶體的靜電破壞。 [0112] 在本實施方式中，作為絕緣膜106形成氮化矽膜與氧化矽膜的疊層膜。 [0113] [金屬氧化物膜] 作為金屬氧化物膜108、208可以使用上述材料。 [0114] 當金屬氧化物膜108、208為In-M-Zn氧化物時，用來形成In-M-Zn氧化物的濺射靶材的金屬元素的原子個數比較佳為滿足In＞M。作為這種濺射靶材的金屬元素的原子個數比，可以舉出In：M：Zn=2：1：3、In：M：Zn=3：1：2、In：M：Zn=4：2：4.1、In：M：Zn=5：1：6、In：M：Zn=5：1：7、In：M：Zn=5：1：8、In：M：Zn=6：1：6、In：M：Zn=5：2：5等。 [0115] 另外，當使用In-M-Zn氧化物形成金屬氧化物膜108、208時，作為濺射靶材較佳為使用包含多晶的In-M-Zn氧化物的靶材。藉由使用包含多晶的In-M-Zn氧化物的靶材，容易形成具有結晶性的金屬氧化物膜108、208。注意，所形成的金屬氧化物膜108、208的原子個數比分別包含上述濺射靶材中的金屬元素的原子個數比的±40%的範圍內。例如，在被用於金屬氧化物膜108、208的濺射靶材的組成為In：Ga：Zn=4：2：4.1[原子個數比]時，所形成的金屬氧化物膜108、208的組成有時為In：Ga：Zn=4：2：3[原子個數比]或其附近。 [0116] 金屬氧化物膜108、208的能隙為2eV以上，較佳為2.5eV以上。如此，藉由使用能隙較寬的氧化物半導體，可以降低電晶體100A、200A的關態電流。 [0117] 金屬氧化物膜108、208較佳為具有非單晶結構。非單晶結構例如包括下述CAAC-OS(C Axis Aligned Crystalline Oxide Semiconductor：c軸配向結晶氧化物半導體)、多晶結構、微晶結構或非晶結構。在非單晶結構中，非晶結構的缺陷態密度最高，而CAAC-OS的缺陷態密度最低。 [0118] 即使金屬氧化物膜108_1、108_2、208_1、208_2獨立地包含In的原子個數比比M的原子個數比多的區域，如果金屬氧化物膜108_1、108_2、208_1、208_2的結晶性高，場效移動率則有可能降低。 [0119] 因此，金屬氧化物膜108_1可以包含其結晶性比金屬氧化物膜108_2低的區域。金屬氧化物膜208_1可以包含其結晶性比金屬氧化物膜208_2低的區域。例如可以使用X射線繞射(XRD：X-Ray Diffraction)或穿透式電子顯微鏡(TEM：Transmission Electron Microscope)對金屬氧化物膜108_1、108_2、208_1、208_2的結晶性進行分析。 [0120] 在金屬氧化物膜108_1、208_1包括結晶性低的區域的情況下，發揮如下優異的效果。 [0121] 首先，對在金屬氧化物膜108中可能形成的氧缺陷進行說明。 [0122] 另外，形成在金屬氧化物膜108中的氧缺陷對電晶體特性造成負面影響而引起問題。例如，當在金屬氧化物膜108中形成有氧缺陷時，該氧缺陷與氫鍵合，而成為載子供應源。當在金屬氧化物膜108中產生載子供應源時，具有金屬氧化物膜108的電晶體100A的電特性發生變動，典型為臨界電壓的漂移。因此，在金屬氧化物膜108中，氧缺陷越少越好。 [0123] 於是，在本發明的一個實施方式中，位於金屬氧化物膜108附近的絕緣膜，明確而言，形成在金屬氧化物膜108上方的絕緣膜114、116包含過量氧。藉由使氧或過量氧從絕緣膜114、116移動到金屬氧化物膜108，能夠減少金屬氧化物膜中的氧缺陷。 [0124] 在此，參照圖45A和圖45B對擴散到金屬氧化物膜108中的氧或過量氧的路徑進行說明。圖45A和圖45B是表示擴散到金屬氧化物膜108中的氧或過量氧的擴散路徑的示意圖，圖45A是通道長度方向上的示意圖，圖45B是通道寬度方向上的示意圖。在此，使用金屬氧化物膜108進行說明，但是在金屬氧化物膜208中氧也與金屬氧化物膜108同樣地擴散。 [0125] 絕緣膜114、116所包含的氧或過量氧從上方，亦即經過金屬氧化物膜108_2而擴散到金屬氧化物膜108_1中(圖45A和圖45B所示的Route 1)。 [0126] 或者，絕緣膜114、116所包含的氧或過量氧從金屬氧化物膜108_1及金屬氧化物膜108_2的側面擴散到金屬氧化物膜108中(圖45B所示的Route 2)。 [0127] 例如，在圖45A和圖45B所示的Route 1中，在金屬氧化物膜108_2的結晶性高時，有時妨礙氧或過量氧的擴散。另一方面，在圖45B所示的Route 2中，可以將氧或過量氧從金屬氧化物膜108_1及金屬氧化物膜108_2的側面擴散到金屬氧化物膜108_1及金屬氧化物膜108_2中。 [0128] 此外，在圖45B所示的Route 2中，當金屬氧化物膜108_1包括其結晶性比金屬氧化物膜108_2低的區域時，該區域成為過量氧的擴散路徑，可以將過量氧擴散到其結晶性高於金屬氧化物膜108_1的金屬氧化物膜108_2中。此外，雖然圖45A和圖45B未圖示，但是在絕緣膜106包含氧或過量氧的情況下，氧或過量氧有可能從絕緣膜106還擴散到金屬氧化物膜108中。 [0129] 如此，採用結晶性不同的金屬氧化物膜的疊層結構，將結晶性低的區域用作過量氧的擴散路徑，由此可以提供一種可靠性高的電晶體。 [0130] 此外，在只使用結晶性低的金屬氧化物膜構成金屬氧化物膜108的情況下，雜質(例如，氫或水分等)附著於或者混入到背後通道一側，亦即相當於金屬氧化物膜108_2的區域中，有時導致可靠性的下降。 [0131] 混入到金屬氧化物膜108中的氫或水分等雜質對電晶體特性造成負面影響，所以成為問題。因此，在金屬氧化物膜108中，氫或水分等雜質越少越好。 [0132] 於是，藉由提高金屬氧化物膜108的上層的金屬氧化物膜的結晶性，可以抑制可能混入到金屬氧化物膜108中的雜質。尤其是，藉由提高金屬氧化物膜108_2的結晶性，可以抑制對導電膜112a、112b進行加工時的損傷。當對導電膜112a、112b進行加工時，金屬氧化物膜108的表面，亦即金屬氧化物膜108_2的表面暴露於蝕刻劑或蝕刻氣體。當金屬氧化物膜108_2包括結晶性高的區域時，其蝕刻耐性高於結晶性低的金屬氧化物膜108_1。因此，金屬氧化物膜108_2被用作蝕刻停止膜。 [0133] 藉由作為金屬氧化物膜108使用雜質濃度低且缺陷態密度低的金屬氧化物膜，可以製造具有優良的電特性的電晶體，所以是較佳的。這裡，將雜質濃度低且缺陷態密度低(氧缺陷少)的狀態稱為“高純度本質”或“實質上高純度本質”。作為金屬氧化物膜中的雜質，典型地可以舉出水、氫等。在本說明書等中，有時將降低或去除金屬氧化物膜中的水及氫的處理稱為脫水化、脫氫化。另外，有時將對金屬氧化物膜或氧化物絕緣膜添加氧的處理稱為加氧化，有時將被加氧化且包含超過化學計量組成的氧的狀態稱為過氧化狀態。 [0134] 因為高純度本質或實質上高純度本質的金屬氧化物膜的載子發生源較少，所以可以降低載子密度。因此，在該金屬氧化物膜中形成有通道區的電晶體很少具有負臨界電壓的電特性(也稱為常開啟特性)。因為高純度本質或實質上高純度本質的金屬氧化物膜具有較低的缺陷態密度，所以有可能具有較低的陷阱態密度。高純度本質或實質上高純度本質的金屬氧化物膜的關態電流顯著小，即便是通道寬度為1´106 mm、通道長度L為10mm的元件，當源極電極與汲極電極間的電壓(汲極電壓)在1V至10V的範圍時，關態電流也可以為半導體參數分析儀的測量極限以下，亦即1´10-13 A以下。 [0135] 此外，在金屬氧化物膜108_1具有其結晶性低於金屬氧化物膜108_2的區域時，載子密度有時得到提高。 [0136] 此外，當金屬氧化物膜108_1的載子密度較高時，費米能階有時相對地高於金屬氧化物膜108_1的導帶。由此，金屬氧化物膜108_1的導帶底變低，金屬氧化物膜108_1的導帶底與可能形成在閘極絕緣膜(在此，絕緣膜106)中的陷阱能階的能量差有時變大。當該能量差變大時，在閘極絕緣膜中被俘獲的電荷變少，有時可以減少電晶體的臨界電壓變動。此外，當金屬氧化物膜108_1的載子密度得到提高時，可以提高金屬氧化物膜108的場效移動率。 [0137] [被用作保護絕緣膜的絕緣膜 1] 絕緣膜114、116被用作電晶體100A、200A的保護絕緣膜。另外，絕緣膜114、116具有對金屬氧化物膜108、208供應氧的功能。亦即，絕緣膜114、116包含氧。另外，絕緣膜114是能夠使氧透過的絕緣膜。注意，絕緣膜114還被用作在後面形成絕緣膜116時緩解對金屬氧化物膜108、208造成的損傷的膜。 [0138] 作為絕緣膜114，可以使用厚度為5nm以上且150nm以下，較佳為5nm以上且50nm以下的氧化矽膜、氧氮化矽膜等。 [0139] 此外，較佳為使絕緣膜114中的缺陷量較少，典型的是，藉由電子自旋共振(ESR：Electron Spin Resonance)測得的起因於矽懸空鍵且在g=2.001處出現的信號的自旋密度較佳為3´1017 spins/cm3 以下。若絕緣膜114的缺陷密度高，氧則與該缺陷鍵合，而使絕緣膜114中的氧的透過性減少。 [0140] 在絕緣膜114中，有時從外部進入絕緣膜114的氧不是全部移動到絕緣膜114的外部，而是其一部分殘留在絕緣膜114內部。另外，有時在氧從外部進入絕緣膜114的同時，絕緣膜114所含有的氧移動到絕緣膜114的外部，由此在絕緣膜114中發生氧的移動。在形成能夠使氧透過的氧化物絕緣膜作為絕緣膜114時，可以使從設置在絕緣膜114上的絕緣膜116脫離的氧經過絕緣膜114而移動到金屬氧化物膜108、208中。 [0141] 此外，絕緣膜114可以使用起因於氮氧化物的態密度低的氧化物絕緣膜形成。注意，該起因於氮氧化物的態密度有時會形成在金屬氧化物膜的價帶頂的能量(EV _OS )與金屬氧化物膜的導帶底的能量(EC _OS )之間。作為上述氧化物絕緣膜，可以使用氮氧化物的釋放量少的氧氮化矽膜或氮氧化物的釋放量少的氧氮化鋁膜等。 [0142] 此外，在熱脫附譜分析法(TDS：Thermal Desorption Spectroscopy)中，氮氧化物的釋放量少的氧氮化矽膜是氨釋放量比氮氧化物的釋放量多的膜，典型的是氨的釋放量為1´1018 分子/cm3 以上且5´1019 分子/cm3 以下。注意，該氨釋放量是在進行膜表面溫度為50℃以上且650℃以下，較佳為50℃以上且550℃以下的加熱處理時的釋放量。 [0143] 氮氧化物(NOx ，x大於0且為2以下，較佳為1以上且2以下)，典型的是NO2 或NO在絕緣膜114等中形成能階。該能階位於金屬氧化物膜108、208的能隙中。由此，當氮氧化物擴散到絕緣膜114與金屬氧化物膜108、208的介面時，有時該能階在絕緣膜114一側俘獲電子。其結果是，被俘獲的電子留在絕緣膜114與金屬氧化物膜108、208的介面附近，由此使電晶體的臨界電壓向正方向漂移。 [0144] 另外，當進行加熱處理時，氮氧化物與氨及氧起反應。當進行加熱處理時，絕緣膜114所包含的氮氧化物與絕緣膜116所包含的氨起反應，由此絕緣膜114所包含的氮氧化物減少。因此，在絕緣膜114與金屬氧化物膜108、208的介面處不容易俘獲電子。 [0145] 藉由作為絕緣膜114使用上述氧化物絕緣膜，可以降低電晶體的臨界電壓的漂移，從而可以降低電晶體的電特性變動。 [0146] 另外，上述氧化物絕緣膜的利用SIMS測得的氮濃度為6´1020 atoms/cm3 以下。 [0147] 藉由在基板溫度為220℃以上且350℃以下的情況下利用使用矽烷及一氧化二氮的PECVD法形成上述氧化物絕緣膜，可以形成緻密且硬度高的膜。 [0148] 絕緣膜116為氧含量超過化學計量組成的氧化物絕緣膜。上述氧化物絕緣膜由於被加熱而其一部分的氧脫離。另外，在TDS中，上述氧化物絕緣膜包括氧釋放量為1.0´1019 atoms/cm3 以上，較佳為3.0´1020 atoms/cm3 以上的區域。注意，上述氧釋放量是在TDS中的加熱處理的溫度為50℃以上且650℃以下或者50℃以上且550℃以下的範圍內被釋放的氧的總量。此外，上述氧釋放量為在TDS中換算為氧原子的總量。 [0149] 作為絕緣膜116可以使用厚度為30nm以上且500nm以下，較佳為50nm以上且400nm以下的氧化矽膜、氧氮化矽膜等。 [0150] 此外，較佳為使絕緣膜116中的缺陷量較少，典型的是，藉由ESR測得的起因於矽懸空鍵且在g=2.001處出現的信號的自旋密度低於1.5´1018 spins/cm3 ，更佳為1´1018 spins/cm3 以下。由於絕緣膜116與絕緣膜114相比離金屬氧化物膜108、208更遠，所以絕緣膜116的缺陷密度也可以高於絕緣膜114。 [0151] 另外，因為絕緣膜114、116可以使用相同種類的材料形成，所以有時無法明確地確認到絕緣膜114與絕緣膜116的介面。因此，在本實施方式中，以虛線示出絕緣膜114與絕緣膜116的介面。注意，在本實施方式中，雖然說明絕緣膜114與絕緣膜116的兩層結構，但是不侷限於此，例如，也可以採用絕緣膜114的單層結構或三層以上的疊層結構。 [0152] [被用作保護絕緣膜的絕緣膜 2] 絕緣膜118被用作電晶體100A、200A的保護絕緣膜。 [0153] 絕緣膜118包含氫和/或氮。或者，絕緣膜118包含氮及矽。絕緣膜118具有阻擋氧、氫、水、鹼金屬、鹼土金屬等的功能。藉由設置絕緣膜118，能夠防止氧從金屬氧化物膜108、208擴散到外部並能夠防止絕緣膜114、116所包含的氧擴散到外部，還能夠抑制氫、水等從外部侵入金屬氧化物膜108、208中。 [0154] 作為絕緣膜118，例如可以使用氮化物絕緣膜。作為該氮化物絕緣膜，有氮化矽膜、氮氧化矽膜、氮化鋁膜、氮氧化鋁膜等。 [0155] 雖然上述所記載的導電膜、絕緣膜、金屬氧化物膜及金屬膜等各種膜可以利用濺射法或PECVD法形成，但是例如也可以利用其它方法，例如熱CVD (Chemical Vapor Deposition：化學氣相沉積)法形成。作為熱CVD法的例子，可以舉出MOCVD(Metal Organic Chemical Vapor Deposition：有機金屬化學氣相沉積)法或ALD(Atomic Layer Deposition：原子層沉積)法等。 [0156] 由於熱CVD法是不使用電漿的成膜方法，因此具有不產生因電漿損傷引起的缺陷的優點。此外，可以以如下方法進行熱CVD法：將源氣體供應到處理室內，將處理室內的壓力設定為大氣壓或減壓而在基板上沉積膜。 [0157] 此外，可以以如下方法進行ALD法：將源氣體供應到處理室內，將處理室內的壓力設定為大氣壓或減壓而在基板上沉積膜。 [0158] á1-3.顯示裝置的結構實例2ñ 圖3A、圖3B和圖3C示出本發明的一個實施方式的顯示裝置所包括的像素部及驅動電路中的電晶體的剖面圖。圖3A、圖3B和圖3C所示的顯示裝置所包括的電晶體的結構與圖1A、圖1B和圖1C所示的顯示裝置不同。注意，其俯視圖與圖2A及圖2B所示的結構相同，因此援用圖2A及圖2B。 [0159] 本發明的一個實施方式的顯示裝置包括電晶體100B、電晶體200B、電容器250B及連接部150B。 [0160] 圖3A是包括在像素部中的電晶體200B及電容器250B的剖面圖，且相當於沿著圖2A的點劃線X1-X2的剖面圖。圖3B是包括在驅動電路中的電晶體100B及連接部150B的剖面圖，且相當於沿著圖2B的點劃線X3-X4的剖面圖。圖3C是包括在驅動電路中的電晶體100B的剖面圖，且相當於沿著圖2B的點劃線Y1-Y2的剖面圖。 [0161] 如圖3A所示，像素部包括電晶體200B、被用作像素電極的導電膜220及電容器250B。被用作像素電極的導電膜220與電晶體200B電連接。因為電晶體200B及電容器250B可以參照圖1A所示的電晶體200A及電容器250A，所以省略詳細說明。 [0162] 如圖3B及圖3C所示，驅動電路包括電晶體100B及連接部150B。 [0163] 電晶體100B包括：基板102上的導電膜104；基板102及導電膜104上的絕緣膜106；絕緣膜106上的金屬氧化物膜108；金屬氧化物膜108上的導電膜112a；金屬氧化物膜108上的導電膜112b；金屬氧化物膜108、導電膜112a、112b上的絕緣膜114；絕緣膜114上的絕緣膜116；以及絕緣膜116上的導電膜132a。 [0164] 在電晶體100B中，絕緣膜106被用作第一閘極絕緣膜，絕緣膜114及絕緣膜116被用作第二閘極絕緣膜。此外，在電晶體100B中，導電膜104被用作第一閘極電極，導電膜132a被用作第二閘極電極。此外，在電晶體100B中，導電膜112a被用作源極電極，導電膜112b被用作汲極電極。 [0165] 在電晶體100B中，導電膜112a及導電膜112b的端部位於金屬氧化物膜108的端部的內側。 [0166] 在電晶體100B上，明確而言，在絕緣膜116及導電膜132a上形成有絕緣膜118以及絕緣膜118上的絕緣膜119。在電晶體100B中，絕緣膜118被用作電晶體100B的保護絕緣膜。此外，絕緣膜119被用作平坦化膜。 [0167] 在電晶體100B中，絕緣膜106、絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119在與導電膜104重疊的區域包括開口146b。此外，絕緣膜119在與導電膜132a重疊的區域包括開口148b。被用作第一佈線的導電膜120b藉由開口146b及開口148b與導電膜132a及導電膜104電連接。藉由設置導電膜120b，被用作電晶體100B的第一閘極電極的導電膜104與被用作第二閘極電極的導電膜132a電連接。 [0168] 電晶體100B為所謂的通道蝕刻型電晶體，具有雙閘極結構。 [0169] 導電膜132a較佳為上述氧化物導電體(OC)。藉由作為導電膜132a使用氧化物導電體，可以對絕緣膜114、116中添加氧。添加到絕緣膜114、116的氧移動到金屬氧化物膜108、208中，填補金屬氧化物膜108、208中的氧缺陷。其結果是，可以提高電晶體100B、200B的可靠性。 [0170] 如圖3B所示，電晶體100B的金屬氧化物膜108位於與導電膜104及導電膜132a相對的位置，夾在兩個被用作閘極電極的導電膜之間。導電膜132a的通道長度方向上的長度及導電膜132a的通道寬度方向上的長度分別比金屬氧化物膜108的通道長度方向上的長度及金屬氧化物膜108的通道寬度方向上的長度長，並且導電膜132a隔著絕緣膜114及絕緣膜116覆蓋金屬氧化物膜108整體。 [0171] 換言之，導電膜104及導電膜132a藉由形成在絕緣膜106、絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119中的開口彼此連接且包括位於金屬氧化物膜108的側端部的外側的區域。 [0172] 藉由採用上述結構，可以利用導電膜104及導電膜132a的電場電圍繞電晶體100B所包括的金屬氧化物膜108，由此可以實現S-channel結構。關於s-channel結構，可以參照前面的說明。 [0173] 連接部150B包括：基板102上的被用作第二佈線的導電膜113；在被用作第二佈線的導電膜113上且設置在絕緣膜106、絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119中的開口142b；金屬氧化物膜128上的被用作第三佈線的導電膜115a；在被用作第三佈線的導電膜115a上且設置在絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119中的開口144b；以及被用作第四佈線的導電膜120a，該導電膜120a以覆蓋開口142b及開口144b的方式形成且連接被用作第二佈線的導電膜113與被用作第三佈線的導電膜115a。在圖3B中，開口142b及開口144b的開口形狀為一個步階狀，但也可以為兩個步階等多個步階狀。 [0174] 在連接部150B中，導電膜115a的端部位於金屬氧化物膜128的端部的內側。 [0175] 被用作第二佈線的導電膜113與被用作電晶體100B的第一閘極電極的導電膜104在同一製程中形成在同一平面上。被用作第三佈線的導電膜115a與被用作電晶體100B的源極電極的導電膜112a及被用作汲極電極的導電膜112b在同一製程中形成在同一平面上。被用作第四佈線的導電膜120a與被用作像素電極的導電膜220在同一製程中形成在同一平面上。 [0176] 換言之，被用作第二佈線的導電膜113與被用作電晶體100B的第一閘極電極的導電膜104使用相同的層形成。被用作第三佈線的導電膜115a與被用作電晶體100B的源極電極的導電膜112a及被用作汲極電極的導電膜112b使用相同的層形成。被用作第四佈線的導電膜120a與被用作像素電極的導電膜220使用相同的層形成。 [0177] 被用作像素電極的導電膜220、被用作第一佈線的導電膜120b及被用作第四佈線的導電膜120a在同一製程中形成。換言之，被用作像素電極的導電膜220、被用作第一佈線的導電膜120b及被用作第四佈線的導電膜120a使用相同的層形成。此外，被用作像素電極的導電膜220、被用作第一佈線的導電膜120b及被用作第四佈線的導電膜120a接觸於被用作平坦化膜的絕緣膜119的頂面。 [0178] á1-4.顯示裝置的結構實例3ñ 圖4A、圖4B和圖4C示出本發明的一個實施方式的顯示裝置所包括的像素部及驅動電路中的電晶體的剖面圖，圖5A和圖5B示出其俯視圖。圖4A至圖4C以及圖5A和圖5B所示的顯示裝置所包括的電晶體的結構與圖1A、圖1B和圖1C所示的顯示裝置不同。 [0179] 本發明的一個實施方式的顯示裝置包括電晶體100C、電晶體200C、電容器250C及連接部150C。 [0180] 圖4A是包括在像素部中的電晶體200C及電容器250C的剖面圖，且相當於沿著圖5A的點劃線X1-X2的剖面圖。圖4B是包括在驅動電路中的電晶體100C及連接部150C的剖面圖，且相當於沿著圖5B的點劃線X3-X4的剖面圖。圖4C是包括在驅動電路中的電晶體100C的剖面圖，且相當於沿著圖5B的點劃線Y1-Y2的剖面圖。 [0181] 如圖4A所示，像素部包括電晶體200C、被用作像素電極的導電膜220及電容器250C。被用作像素電極的導電膜220與電晶體200C電連接。因為電晶體200C及電容器250C可以參照圖1A所示的電晶體200A及電容器250A，所以省略詳細說明。 [0182] 如圖4B及圖4C所示，驅動電路包括電晶體100C及連接部150C。 [0183] 電晶體100C包括：基板102上的導電膜104；基板102及導電膜104上的絕緣膜106；絕緣膜106上的金屬氧化物膜108；金屬氧化物膜108上的導電膜112a；以及金屬氧化物膜108上的導電膜112b。 [0184] 在電晶體100C中，絕緣膜106被用作閘極絕緣膜。此外，在電晶體100C中，導電膜104被用作閘極電極，導電膜112a被用作源極電極，導電膜112b被用作汲極電極。 [0185] 在電晶體100C中，導電膜112a及導電膜112b的端部位於金屬氧化物膜208的端部的內側。 [0186] 在電晶體100C上，明確而言，在金屬氧化物膜108、導電膜112a及導電膜112b上形成有絕緣膜114、絕緣膜114上的絕緣膜116、絕緣膜116上的絕緣膜118以及絕緣膜118上的絕緣膜119。在電晶體100C中，絕緣膜114、絕緣膜116及絕緣膜118被用作電晶體100C的保護絕緣膜。此外，絕緣膜119被用作平坦化膜。 [0187] 絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119在與導電膜212b重疊的區域具有開口242c。被用作像素電極的導電膜220藉由開口242c與導電膜212b電連接。 [0188] 電晶體100C為所謂的通道蝕刻型電晶體，具有單閘極結構。 [0189] 連接部150C包括：基板102上的被用作第二佈線的導電膜113；在被用作第二佈線的導電膜113上且設置在絕緣膜106、絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119中的開口142c；金屬氧化物膜128上的被用作第三佈線的導電膜115a；在被用作第三佈線的導電膜115a上且設置在絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119中的開口144c；以及被用作第四佈線的導電膜120a，該導電膜120a以覆蓋開口142c及開口144c的方式形成且連接被用作第二佈線的導電膜113與被用作第三佈線的導電膜115a。在圖4B中，開口142b及開口144b的開口形狀為一個步階狀，但也可以為兩個步階等多個步階狀。 [0190] 在連接部150C中，導電膜115a的端部位於金屬氧化物膜128的端部的內側。 [0191] 被用作第二佈線的導電膜113與被用作電晶體100C的第一閘極電極的導電膜104在同一製程中形成在同一平面上。被用作第三佈線的導電膜115a與被用作電晶體100C的源極電極的導電膜112a及被用作汲極電極的導電膜112b在同一製程中形成在同一平面上。被用作第四佈線的導電膜120a與被用作像素電極的導電膜220在同一製程中形成在同一平面上。 [0192] 換言之，被用作第二佈線的導電膜113與被用作電晶體100C的第一閘極電極的導電膜204使用相同的層形成。被用作第三佈線的導電膜115a與被用作電晶體100C的源極電極的導電膜112a及被用作汲極電極的導電膜112b使用相同的層形成。被用作第四佈線的導電膜120a與被用作像素電極的導電膜220使用相同的層形成。 [0193] 被用作像素電極的導電膜220、被用作第一佈線的導電膜120b及被用作第四佈線的導電膜120a在同一製程中形成。換言之，被用作像素電極的導電膜220、被用作第一佈線的導電膜120b及被用作第四佈線的導電膜120a使用相同的層形成。此外，被用作像素電極的導電膜220、被用作第一佈線的導電膜120b及被用作第四佈線的導電膜120a接觸於被用作平坦化膜的絕緣膜119的頂面。 [0194] á1-5.顯示裝置的結構實例4ñ 圖6A、圖6B和圖6C示出本發明的一個實施方式的顯示裝置所包括的像素部及驅動電路中的電晶體的剖面圖，圖7A和圖7B示出其俯視圖。 [0195] 本發明的一個實施方式的顯示裝置包括電晶體100D、電晶體200D、電容器250D及連接部150D。 [0196] 圖6A是包括在像素部中的電晶體200D及電容器250D的剖面圖，且相當於沿著圖7A的點劃線X1-X2的剖面圖。圖6B是包括在驅動電路中的電晶體100D及連接部150D的剖面圖，且相當於沿著圖7B的點劃線X3-X4的剖面圖。圖6C是包括在驅動電路中的電晶體100D的剖面圖，且相當於沿著圖7B的點劃線Y1-Y2的剖面圖。注意，在圖7A和圖7B中，為了方便起見，省略電晶體100D、電晶體200D及電容器250D的組件的一部分(被用作閘極絕緣膜的絕緣膜等)。此外，有時在各電晶體中將點劃線X1-X2方向稱為通道長度方向，將點劃線Y1-Y2方向稱為通道寬度方向。注意，有時在後面的電晶體的俯視圖中也與圖7A和圖7B同樣地省略組件的一部分。 [0197] 如圖6A所示，像素部包括電晶體200D、被用作像素電極的導電膜220及電容器250D。被用作像素電極的導電膜220與電晶體200D電連接。 [0198] 電晶體200D包括：基板102上的導電膜204；基板102及導電膜204上的絕緣膜106；絕緣膜106上的金屬氧化物膜208；金屬氧化物膜208上的導電膜212a；以及金屬氧化物膜208上的導電膜212b。 [0199] 在電晶體200D中，絕緣膜106被用作閘極絕緣膜。此外，在電晶體200D中，導電膜204被用作閘極電極，導電膜212a被用作源極電極，導電膜212b被用作汲極電極。 [0200] 在電晶體200D中，導電膜212a及導電膜212b的端部位於金屬氧化物膜208的端部的內側。 [0201] 在電晶體200D上，明確而言，在金屬氧化物膜208、導電膜212a及導電膜212b上形成有絕緣膜114、絕緣膜114上的絕緣膜116、絕緣膜116上的絕緣膜118以及絕緣膜118上的絕緣膜119。在電晶體200D中，絕緣膜114、絕緣膜116及絕緣膜118被用作電晶體200D的保護絕緣膜。此外，絕緣膜119被用作平坦化膜。 [0202] 絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119在與導電膜212b重疊的區域具有開口242d。被用作像素電極的導電膜220藉由開口242d與導電膜212b電連接。 [0203] 電晶體200D為所謂的通道蝕刻型電晶體，具有單閘極結構。 [0204] 由導電膜213、絕緣膜106、金屬氧化物膜228和導電膜215a形成電容器250D。被用作電容佈線的導電膜213與導電膜204、104、113在同一製程中形成在同一平面上。導電膜215a與導電膜212a、212b、112a、112b、115d在同一製程中形成在同一平面上。 [0205] 在電容器250D中，導電膜215a的端部位於金屬氧化物膜228的端部的內側。 [0206] 被用作像素電極的導電膜220形成在絕緣膜119上。設置在被用作平坦化膜的絕緣膜119上的導電膜220也具有高平坦性。由於導電膜220的平坦性高，所以在顯示裝置為液晶顯示裝置的情況下，可以減少液晶層的配向不良。此外，藉由利用絕緣膜119可以擴大被用作閘極佈線的導電膜204與導電膜220的間隔以及被用作信號線的導電膜212a與導電膜220的間隔，由此可以降低佈線延遲。 [0207] 如圖6B及圖6C所示，驅動電路包括電晶體100D及連接部150D。 [0208] 在電晶體100D中，形成有：基板102上的導電膜104；基板102及導電膜104上的絕緣膜106；絕緣膜106上的金屬氧化物膜108；金屬氧化物膜108上的導電膜112a；金屬氧化物膜108上的導電膜112b；金屬氧化物膜108、導電膜112a及導電膜112b上的絕緣膜114；絕緣膜114上的絕緣膜116；絕緣膜116上的絕緣膜118；絕緣膜118上的絕緣膜119及導電膜130d。 [0209] 在電晶體100D中，絕緣膜119在與導電膜104及金屬氧化物膜108重疊的區域包括開口142d。此外，絕緣膜106、絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119在與導電膜104重疊且不與金屬氧化物膜108、導電膜112a及導電膜112b重疊的區域包括開口146d。 [0210] 以覆蓋開口146d及開口142d的方式設置有被用作第二閘極電極的導電膜130d。在開口142d中，被用作第二閘極電極的導電膜130d設置在被用作第一閘極電極的導電膜104上。也就是說，被用作第二閘極電極的導電膜130d與被用作第一閘極電極的導電膜104電連接。此外，在開口142d中，被用作第二閘極電極的導電膜130d設置在被用作第二閘極絕緣膜的絕緣膜118上。也就是說，被用作第二閘極電極的導電膜130d配置在與被用作第一閘極電極的導電膜104及金屬氧化物膜108重疊的區域。 [0211] 在電晶體100D中，絕緣膜106被用作第一閘極絕緣膜，絕緣膜114、絕緣膜116及絕緣膜118被用作第二閘極絕緣膜。此外，在電晶體100D中，導電膜104被用作第一閘極電極，導電膜130d被用作第二閘極電極。此外，在電晶體100D中，導電膜112a被用作源極電極，導電膜112b被用作汲極電極。 [0212] 在電晶體100D中，絕緣膜119被用作平坦化膜。 [0213] 在電晶體100D中，導電膜112a及導電膜112b的端部位於金屬氧化物膜108的端部的內側。 [0214] 電晶體100D為所謂的通道蝕刻型電晶體，具有雙閘極結構。 [0215] 如圖6B所示，電晶體100D的金屬氧化物膜108位於與導電膜104及導電膜130d相對的位置，夾在兩個被用作閘極電極的導電膜之間。導電膜130d的通道長度方向上的長度及導電膜130d的通道寬度方向上的長度分別比金屬氧化物膜108的通道長度方向上的長度及金屬氧化物膜108的通道寬度方向上的長度長，並且導電膜130d隔著絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119覆蓋金屬氧化物膜108整體。 [0216] 換言之，導電膜104及導電膜130d藉由形成在絕緣膜106、絕緣膜114、絕緣膜116、絕緣膜118及絕緣膜119中的開口彼此連接且包括位於金屬氧化物膜108的側端部的外側的區域。 [0217] 藉由採用上述結構，可以利用導電膜104及導電膜130d的電場電圍繞電晶體100D所包括的金屬氧化物膜108，由此可以實現S-channel結構。關於s-channel結構，可以參照前面的說明。 [0218] 因為電晶體100D具有S-channel結構，所以可以使用被用作第一閘極電極的導電膜104對金屬氧化物膜108有效地施加用來引起通道的電場，由此，電晶體100D的電流驅動能力得到提高，從而可以得到高通態電流特性。此外，由於可以提高通態電流，所以可以使電晶體100D微型化。另外，由於金屬氧化物膜108被用作第一閘極電極的導電膜104與用作第二閘極電極的導電膜130d圍繞，所以可以提高電晶體100D的機械強度。 [0219] 連接部150D包括：基板102上的被用作第一佈線的導電膜113；設置在被用作第一佈線的導電膜113上的絕緣膜106中的開口160；以及覆蓋開口160的被用作第二佈線的導電膜115d。在開口160中，被用作第二佈線的導電膜115d設置在被用作第一佈線的導電膜113上，並且，被用作第一佈線的導電膜113與被用作第二佈線的導電膜115d電連接。 [0220] 在開口160中，被用作第一佈線的導電膜113與被用作第二佈線的導電膜115d直接連接。因此，也可以說開口160是接觸孔。藉由使被用作第一佈線的導電膜113與被用作第二佈線的導電膜115d直接連接，可以實現良好的接觸，而可以降低接觸電阻。 [0221] 被用作第一佈線的導電膜113與被用作電晶體100D的第一閘極電極的導電膜104在同一製程中形成在同一平面上。被用作第二佈線的導電膜115d與被用作電晶體100D的源極電極的導電膜112a及被用作汲極電極的導電膜112b在同一製程中形成在同一平面上。 [0222] 換言之，被用作第一佈線的導電膜113與被用作電晶體100D的第一閘極電極的導電膜104使用相同的層形成。被用作第二佈線的導電膜115d與被用作電晶體100D的源極電極的導電膜112a及被用作汲極電極的導電膜112b使用相同的層形成。 [0223] 被用作像素電極的導電膜220與被用作第二閘極電極的導電膜130d在同一製程中形成。換言之，被用作像素電極的導電膜220與被用作第二閘極電極的導電膜130d使用相同的層形成。此外，被用作像素電極的導電膜220及被用作第二閘極電極的導電膜130d與被用作平坦化膜的絕緣膜119的頂面接觸。 [0224] á1-6.顯示裝置的結構實例5ñ 圖8A、圖8B和圖8C示出本發明的一個實施方式的顯示裝置所包括的像素部及驅動電路中的電晶體的剖面圖，圖9A和圖9B示出其俯視圖。圖8A至圖8C以及圖9A和圖9B所示的顯示裝置所包括的電晶體的結構與圖6A、圖6B和圖6C所示的顯示裝置不同。 [0225] 本發明的一個實施方式的顯示裝置包括電晶體100E、電晶體200E、電容器250E及連接部150E。 [0226] 圖8A是包括在像素部中的電晶體200E及電容器250E的剖面圖，且相當於沿著圖9A的點劃線X1-X2的剖面圖。圖8B是包括在驅動電路中的電晶體100E及連接部150E的剖面圖，且相當於沿著圖9B的點劃線X3-X4的剖面圖。圖8C是包括在驅動電路中的電晶體100E的剖面圖，且相當於沿著圖9B的點劃線Y1-Y2的剖面圖。 [0227] 如圖8A所示，像素部包括電晶體200E、被用作像素電極的導電膜220及電容器250E。被用作像素電極的導電膜220與電晶體200E電連接。因為電晶體200E及電容器250E可以參照圖6A所示的電晶體200D及電容器250D，所以省略詳細說明。 [0228] 如圖8B及圖8C所示，驅動電路包括電晶體100E及連接部150E。 [0229] 電晶體100E包括：基板102上的導電膜104；基板102及導電膜104上的絕緣膜106；絕緣膜106上的金屬氧化物膜108；金屬氧化物膜108上的導電膜112a；以及金屬氧化物膜108上的導電膜112b。 [0230] 在電晶體100E中，絕緣膜106被用作閘極絕緣膜。此外，在電晶體100E中，導電膜104被用作閘極電極，導電膜112a被用作源極電極，導電膜112b被用作汲極電極。 [0231] 在電晶體100E中，導電膜112a及導電膜112b的端部位於金屬氧化物膜108的端部的內側。 [0232] 在電晶體100E上，明確而言，在金屬氧化物膜108、導電膜112a及導電膜112b上形成有絕緣膜114、絕緣膜114上的絕緣膜116、絕緣膜116上的絕緣膜118以及絕緣膜118上的絕緣膜119。在電晶體100E中，絕緣膜114、絕緣膜116及絕緣膜118被用作電晶體100E的保護絕緣膜。此外，絕緣膜119被用作平坦化膜。 [0233] 電晶體100E為所謂的通道蝕刻型電晶體，具有單閘極結構。 [0234] 因為連接部150E可以參照圖6B所示的連接部150D，所以省略詳細說明。 [0235] á1-7.顯示裝置的製造方法1ñ 參照圖10A至圖22C對包括在圖1A、圖1B及圖1C所示的本發明的一個實施方式的顯示裝置中的電晶體100A、電晶體200A、電容器250A及連接部150A的製造方法進行說明。 [0236] 圖10A至圖22C是說明顯示裝置的製造方法的剖面圖。在圖10A至圖22C的剖面圖中，點劃線X1-X2的方向為電晶體200A的通道長度方向，點劃線X3-X4的方向為電晶體100A的通道長度方向。點劃線Y1-Y2的方向為電晶體100A的通道寬度方向。 [0237] 首先，在基板102上形成導電膜，藉由光微影製程及蝕刻製程對該導電膜進行加工，來形成被用作電晶體100A的第一閘極電極的導電膜104、被用作佈線的導電膜113、被用作電晶體200A的閘極電極的導電膜204及被用作電容佈線的導電膜213。接著，在導電膜104、導電膜113、導電膜213、導電膜204及基板102上形成被用作第一閘極絕緣膜的絕緣膜106(參照圖10A、圖10B及圖10C)。形成導電膜104、導電膜113、導電膜213及導電膜204的製程為第一光微影製程。 [0238] 在本說明書等中，光微影製程是指使用光罩形成圖案的製程。 [0239] 在本實施方式中，作為基板102使用玻璃基板。作為導電膜104、導電膜113、導電膜204及導電膜213，藉由濺射法形成厚度為50nm的鈦膜和厚度為200nm的銅膜。 [0240] 在本實施方式中，作為絕緣膜106，藉由PECVD法形成厚度為400nm的氮化矽膜和厚度為50nm的氧氮化矽膜。 [0241] 另外，上述氮化矽膜具有包括第一氮化矽膜、第二氮化矽膜及第三氮化矽膜的三層結構。該三層結構例如可以如下所示那樣形成。 [0242] 可以在如下條件下形成厚度為50nm的第一氮化矽膜：例如，作為源氣體使用流量為200sccm的矽烷、流量為2000sccm的氮以及流量為100sccm的氨氣體，向PECVD設備的反應室內供應該源氣體，將反應室內的壓力控制為100Pa，使用27.12MHz的高頻電源供應2000W的功率。 [0243] 可以在如下條件下形成厚度為300nm的第二氮化矽膜：作為源氣體使用流量為200sccm的矽烷、流量為2000sccm的氮以及流量為2000sccm的氨氣體，向PECVD設備的反應室內供應該源氣體，將反應室內的壓力控制為100Pa，使用27.12MHz的高頻電源供應2000W的功率。 [0244] 例如，可以在如下條件下形成厚度為50nm的第三氮化矽膜：作為源氣體使用流量為200sccm的矽烷、流量為2000sccm的氮以及流量為100sccm的氨氣體，向PECVD設備的反應室內供應該源氣體，將反應室內的壓力控制為100Pa，使用27.12MHz的高頻電源供應2000W的功率。 [0245] 另外，可以將形成上述第一氮化矽膜、第二氮化矽膜及第三氮化矽膜時的基板溫度設定為350℃以下。 [0246] 藉由作為氮化矽膜採用上述三層結構，例如在作為導電膜104、導電膜113、導電膜204和導電膜213中的一個以上使用包含銅的導電膜的情況下，能夠發揮如下效果。 [0247] 第一氮化矽膜可以抑制銅從導電膜104、導電膜113、導電膜204和導電膜213擴散。第二氮化矽膜具有釋放氫的功能，可以提高被用作閘極絕緣膜的絕緣膜的耐壓。第三氮化矽膜是氫的釋放量少且可以抑制從第二氮化矽膜釋放的氫擴散的膜。 [0248] 接著，在絕緣膜106上形成金屬氧化物膜108a及金屬氧化物膜108b(參照圖12A、圖12B及圖12C)。 [0249] 圖11A、圖11B及圖11C是在絕緣膜106上形成金屬氧化物膜108a及金屬氧化物膜108b時的成膜裝置內的剖面示意圖。圖11A、圖11B及圖11C示意性地示出：作為成膜裝置的濺射裝置；在該濺射裝置中設置的靶材191；形成在靶材191的下方的電漿192。 [0250] 在圖11A、圖11B及圖11C中，以虛線的箭頭示意性地表示添加到絕緣膜106的氧或過量氧。例如，在形成金屬氧化物膜108a時使用氧氣體的情況下，可以有效地對絕緣膜106添加氧。 [0251] 首先，在絕緣膜106上形成金屬氧化物膜108a。金屬氧化物膜108a的厚度可以為1nm以上且25nm以下，較佳為5nm以上且20nm以下。此外，金屬氧化物膜108a使用惰性氣體(典型的是，Ar氣體)和氧氣體中的任一個或兩個形成。此外，形成金屬氧化物膜108a時的沉積氣體整體中所佔的氧氣體的比率(以下，也稱為氧流量比)為0%以上且低於30%，較佳為5%以上且15%以下。 [0252] 藉由以上述範圍的氧流量比形成金屬氧化物膜108a，可以使金屬氧化物膜108a的結晶性低於金屬氧化物膜108b的結晶性。 [0253] 接著，在金屬氧化物膜108a上形成金屬氧化物膜108b。當形成金屬氧化物膜108b時，在包含氧氣體的氛圍下進行電漿放電。此時，對成為金屬氧化物膜108b的被形成面的金屬氧化物膜108a添加氧。形成金屬氧化物膜108b時的氧流量比為30%以上且100%以下，較佳為50%以上且100%以下，更佳為70%以上且100%以下。 [0254] 金屬氧化物膜108b的厚度為20nm以上且100nm以下，較佳為20nm以上且50nm以下。 [0255] 如上所述，用來形成金屬氧化物膜108b的氧流量比較佳為高於用來形成金屬氧化物膜108a的氧流量比。換言之，金屬氧化物膜108a較佳為在比金屬氧化物膜108b低的氧分壓下形成。 [0256] 形成金屬氧化物膜108a及金屬氧化物膜108b時的基板溫度可以為室溫(25℃)以上且200℃以下，較佳為室溫以上且130℃以下。上述範圍的基板溫度適合用於使用大面積玻璃基板(例如，上述第8世代至第10世代的玻璃基板)的情況。尤其是，藉由將金屬氧化物膜108a及金屬氧化物膜108b的成膜時的基板溫度設定為室溫，可以抑制基板的變形或彎曲。此外，在想要提高金屬氧化物膜108b的結晶性的情況下，較佳為提高形成金屬氧化物膜108b時的基板溫度。 [0257] 藉由在真空中連續地形成金屬氧化物膜108a及金屬氧化物膜108b，可以防止雜質混入各介面，所以是更佳的。 [0258] 另外，需要進行濺射氣體的高度純化。例如，作為被用作濺射氣體的氧氣體或氬氣體，使用露點為-40℃以下，較佳為-80℃以下，更佳為-100℃以下，進一步較佳為-120℃以下的高純度氣體，由此可以儘可能地防止水分等混入金屬氧化物膜。 [0259] 另外，在藉由濺射法形成金屬氧化物膜的情況下，較佳為使用低溫泵等吸附式真空抽氣泵對濺射裝置的處理室進行高真空抽氣(抽空到5´10-7 Pa至1´10-4 Pa左右)以儘可能地去除對金屬氧化物膜來說是雜質的水等。尤其是，在濺射裝置的待機時處理室內的相當於H2 O的氣體分子(相當於m/z=18的氣體分子)的分壓較佳為1´10- 4 Pa以下，更佳為5´10- 5 Pa以下。 [0260] 在本實施方式中，金屬氧化物膜108a使用In-Ga-Zn金屬氧化物靶材(In：Ga：Zn=4：2：4.1[原子個數比])並利用濺射法形成。此外，將形成金屬氧化物膜108a時的基板溫度設定為室溫，作為沉積氣體使用流量為180sccm的氬氣體及流量為20sccm的氧氣體(氧流量比為10%)。 [0261] 此外，金屬氧化物膜108b使用In-Ga-Zn金屬氧化物靶材(In：Ga：Zn=4：2：4.1[原子個數比])並利用濺射法形成。此外，將形成金屬氧化物膜108b時的基板溫度設定為室溫，作為沉積氣體使用流量為200sccm的氧氣體(氧流量比為100%)。 [0262] 藉由使金屬氧化物膜108a的成膜時的氧流量比與金屬氧化物膜108b的成膜時的氧流量比不同，可以形成結晶性不同的疊層膜。 [0263] 雖然在此說明利用濺射法的製造方法，但是不侷限於此，也可以使用脈衝雷射沉積(PLD)法、電漿增強化學氣相沉積(PECVD)法、熱CVD(Chemical Vapor Deposition)法、ALD(Atomic Layer Deposition)法、真空蒸鍍法等。作為熱CVD法的例子，可以舉出MOCVD(Metal Organic Chemical Vapor Deposition：有機金屬化學氣相沉積)法。 [0264] 在形成金屬氧化物膜108a及金屬氧化物膜108b之後，也可以將金屬氧化物膜108a及金屬氧化物膜108b暴露於包含氧的電漿。其結果是，可以對金屬氧化物膜108a及金屬氧化物膜108b的表面添加氧，而可以減少金屬氧化物膜108a及金屬氧化物膜108b的氧缺陷。尤其是，藉由減少金屬氧化物膜108a及金屬氧化物膜108b的側面的氧缺陷，可以抑制電晶體的洩漏電流的發生，所以是較佳的。 [0265] 此外，較佳的是，在形成金屬氧化物膜108a及金屬氧化物膜108b之後進行加熱處理(以下，稱為第一加熱處理)。藉由進行第一加熱處理，可以減少包含在金屬氧化物膜108a及金屬氧化物膜108b中的氫、水等。另外，以氫、水等的減少為目的的加熱處理也可以在將金屬氧化物膜108a及108b加工為島狀之後進行。注意，第一加熱處理是金屬氧化物膜的高度純化處理之一。 [0266] 第一加熱處理的溫度例如為150℃以上且低於基板的應變點，較佳為200℃以上且450℃以下，更佳為250℃以上且350℃以下。 [0267] 第一加熱處理可以使用電爐、RTA(Rapid Thermal Anneal：快速熱退火)裝置等進行。藉由使用RTA裝置，可只在短時間內以基板的應變點以上的溫度進行加熱處理。由此，可以縮短加熱時間。第一加熱處理可以在氮、氧、超乾燥空氣(含水量為20ppm以下，較佳為1ppm以下，更佳為10ppb以下的空氣)或稀有氣體(氬、氦等)的氛圍下進行。上述氮、氧、超乾燥空氣或稀有氣體較佳為不含有氫、水等。此外，在氮或稀有氣體氛圍下進行加熱處理之後，也可以在氧或超乾燥空氣氛圍下進行加熱。其結果是，在可以使金屬氧化物膜中的氫、水等脫離的同時，可以將氧供應到金屬氧化物膜中。其結果是，可以減少金屬氧化物膜中的氧缺陷。 [0268] 接著，在金屬氧化物膜108a及金屬氧化物膜108b上形成導電膜112。接著，藉由第二光微影製程，在導電膜112上形成光阻遮罩251、光阻遮罩253、光阻遮罩151及光阻遮罩153(參照圖13A、圖13B及圖13C)。形成光阻遮罩251、光阻遮罩253、光阻遮罩151及光阻遮罩153的製程為第二光微影製程。 [0269] 在本實施方式中，作為導電膜112，藉由濺射法依次形成厚度為30nm的鈦膜、厚度為200nm的銅膜、厚度為10nm的鈦膜。 [0270] 光阻遮罩253在與導電膜204重疊的區域具有光阻劑的厚度薄的區域255。區域255也可以稱為凹部。光阻遮罩151在與導電膜104重疊的區域具有光阻劑的厚度薄的區域155。區域155也可以稱為凹部。在本實施方式中，在形成光阻遮罩時，採用使用多色調(高灰階)遮罩的曝光。藉由使用多色調(高灰階)遮罩可以形成光阻劑的厚度不同的光阻遮罩。 [0271] 對使用多色調(高灰階)遮罩的曝光進行說明。 [0272] 首先，形成用來形成光阻遮罩的光阻劑。作為光阻劑，可以使用正性光阻劑或者負性光阻劑。在此，使用正性光阻劑。光阻劑既可以藉由旋塗法形成，又可以藉由噴墨法選擇性地形成。當藉由噴墨法選擇性地形成光阻劑時，可以防止在不需要的部分中形成光阻劑的情況，所以可以減少材料的浪費。 [0273] 接著，作為光罩使用多色調遮罩，對光阻劑照射光，來對光阻劑進行曝光。 [0274] 多色調遮罩指的是能夠以三個級別(曝光部分、中間曝光部分以及未曝光部分)進行曝光的遮罩，且是使透過光具有多種強度的光罩。藉由進行一次曝光及顯影製程，可以形成具有多種厚度區域的光阻遮罩。因此，藉由使用多色調遮罩，可以減少光微影製程的次數，由此可以簡化製程。 [0275] 作為多色調遮罩的典型例子，有如圖46A所示的灰色調遮罩10a以及如圖46C所示的半色調遮罩10b。 [0276] 如圖46A所示，灰色調遮罩10a包括透光基板13及設置在透光基板13上的遮光膜15。此外，灰色調遮罩10a包括設置有遮光膜的遮光部17、由遮光膜的圖案而設置的繞射光柵部18及沒有設置遮光膜的透過部19。 [0277] 作為透光基板13，可以使用石英等透光基板。遮光膜15可以使用鉻或氧化鉻等吸收光的遮光材料形成。 [0278] 圖46B示出對灰色調遮罩10a照射曝光光線時的光穿透率TR。如圖46B所示，遮光部17的光穿透率21為0%。透過部19的光穿透率21大約為100%。此外，在繞射光柵部18中，可以在10%以上且70%以下的範圍內調整光穿透率21。在繞射光柵部18中，將狹縫、點、網目等的光透過部的間隔設定為用於曝光的光的解析度限度以下的間隔。此外，藉由調整狹縫、點、網目的間隔及柵距，可以控制繞射光柵部18的光穿透率。繞射光柵部18可以使用週期性或非週期性的狹縫、點、網目。 [0279] 如圖46C所示，半色調遮罩10b包括透光基板13以及設置在透光基板13上的遮光膜25和半透過膜23。此外，半色調遮罩10b包括設置有遮光膜25和半透過膜23的遮光部27、沒有設置遮光膜25且設置有半透過膜23的半透過部28以及沒有設置遮光膜25和半透過膜23的透過部29。 [0280] 圖46D示出對半色調遮罩10b照射曝光光線時的光穿透率。如圖46D所示，遮光部27的光穿透率31為0%。透過部29的光穿透率31大約為100%。此外，在半透過部28中，可以在10%以上且70%以下的範圍內調整光穿透率31。在半透過部28中，可以根據半透過膜23的材料控制光穿透率。 [0281] 作為半透過膜23，可以使用MoSiN、MoSi、MoSiO、MoSiON、CrSi等。作為遮光膜25，可以使用鉻或氧化鉻等吸收光的遮光材料。 [0282] 藉由在使用多色調遮罩進行曝光之後進行顯影，可以形成如圖13A、圖13B及圖13C所示的具有厚度不同的區域的光阻遮罩。 [0283] 注意，雖然作為多色調遮罩示出了光阻劑的厚度為兩種的例子，但是本發明的一個實施方式不侷限於此。藉由使用具有多個光穿透率的繞射光柵部18或半透過膜23，可以形成具有三種以上的厚度的光阻劑。 [0284] 接著，以光阻遮罩251、光阻遮罩253、光阻遮罩151及光阻遮罩153為遮罩去除導電膜112、金屬氧化物膜108a及金屬氧化物膜108b的一部分，來形成導電膜215、導電膜212A、導電膜112A、導電膜115、金屬氧化物膜228、金屬氧化物膜208、金屬氧化物膜108及金屬氧化物膜128(參照圖14A、圖14B及圖14C)。 [0285] 在對導電膜112進行加工時，可以使用濕蝕刻法。但是，加工方法不侷限於此，例如也可以使用乾蝕刻法。在對金屬氧化物膜108b進行加工時，可以使用濕蝕刻法。但是，加工方法不侷限於此，例如也可以使用乾蝕刻法。 [0286] 在對導電膜112、金屬氧化物膜108a及金屬氧化物膜108b進行加工時，可以使用不同的蝕刻法。例如，可以在對導電膜112進行加工時使用乾蝕刻法，而在對金屬氧化物膜108a及金屬氧化物膜108b進行加工時使用濕蝕刻法。 [0287] 接著，去除光阻遮罩251、光阻遮罩253、光阻遮罩151及光阻遮罩153的一部分，來縮小光阻遮罩的面積。藉由縮小光阻遮罩的面積，形成光阻遮罩251a、光阻遮罩253a、光阻遮罩253b、光阻遮罩151a、光阻遮罩151b及光阻遮罩153a(參照圖15A、圖15B及圖15C)。 [0288] 在去除光阻遮罩的一部分時，可以使用灰化裝置。藉由灰化處理，在光阻遮罩的面積減小的同時，有時光阻遮罩的厚度減薄。 [0289] 例如，作為灰化處理可以利用光激發灰化處理，其中，對氧或臭氧等氣體照射紫外線等光，使氣體與有機物起化學反應，來去除有機物。此外，作為灰化處理也可以利用電漿灰化處理，其中，以高頻等使氧或臭氧等氣體電漿化，使用該電漿去除有機物。 [0290] 光阻遮罩253的厚度薄的區域255及光阻遮罩151的厚度薄的區域155的光阻劑藉由上述灰化處理被去除，由此如圖15A、圖15B及圖15C所示那樣，光阻遮罩彼此分開。藉由去除光阻遮罩的一部分，去除與導電膜204重疊的區域255a的光阻遮罩，來使區域255a的導電膜212A露出。此外，去除與導電膜104重疊的區域155a的光阻遮罩，來使區域155a的導電膜112A露出。 [0291] 光阻遮罩251a的端部位於導電膜215的端部的內側。光阻遮罩253a及光阻遮罩253b的端部位於導電膜212A的端部的內側。光阻遮罩151a及光阻遮罩151b的端部位於導電膜112A的端部的內側。光阻遮罩153a的端部位於導電膜115的端部的內側。 [0292] 接著，以光阻遮罩251a、光阻遮罩253a、光阻遮罩253b、光阻遮罩151a、光阻遮罩151b及光阻遮罩153a為遮罩去除導電膜215、導電膜212A、導電膜112A、導電膜115的一部分，來形成導電膜215a、導電膜212a、導電膜212b、導電膜112a、導電膜112b及導電膜115a(參照圖16A、圖16B及圖16C)。 [0293] 導電膜215a的端部位於金屬氧化物膜228的端部的內側。導電膜212a及導電膜212b的端部位於金屬氧化物膜208的端部的內側。導電膜112a及導電膜112b的端部位於金屬氧化物膜108的端部的內側。導電膜115a的端部位於金屬氧化物膜128的端部的內側。 [0294] 接著，去除光阻遮罩251a、光阻遮罩253a、光阻遮罩253b、光阻遮罩151a、光阻遮罩151b及光阻遮罩153a。 [0295] 在去除光阻遮罩之後，也可以洗滌金屬氧化物膜108、金屬氧化物膜128、金屬氧化物膜208及金屬氧化物膜228(更明確而言，金屬氧化物膜108_2、金屬氧化物膜128_2、金屬氧化物膜208_2及金屬氧化物膜228_2、)的表面(背後通道一側)。作為洗滌方法，例如可以舉出使用磷酸等化學溶液的洗滌。藉由使用磷酸等化學溶液進行洗滌，可以去除附著於金屬氧化物膜108_2、金屬氧化物膜128_2、金屬氧化物膜208_2及金屬氧化物膜228_2表面的雜質(例如，包含在導電膜112a、導電膜112b、導電膜212a、導電膜212b中的元素等)。注意，不一定必須進行該洗滌，根據情況可以不進行該洗滌。 [0296] 另外，在導電膜112a、導電膜112b、導電膜212a、導電膜212b的形成製程和/或上述洗滌製程中，有時金屬氧化物膜108及金屬氧化物膜208的從導電膜112a、導電膜112b、導電膜212a、導電膜212b露出的區域有時變薄。 [0297] 此外，金屬氧化物膜108及金屬氧化物膜208露出的區域，就是說，金屬氧化物膜108_2及金屬氧化物膜208_2較佳為其結晶性得到提高的金屬氧化物膜。結晶性高的金屬氧化物膜具有雜質(尤其是用於導電膜112a、導電膜112b、導電膜212a、導電膜212b的構成元素)不容易擴散到膜中的結構。因此，可以製造一種可靠性高的電晶體。 [0298] 此外，在圖16A、圖16B及圖16C中，雖然示出從導電膜112a、導電膜112b、導電膜115a、導電膜212a、導電膜212b及導電膜215a露出的金屬氧化物膜108、金屬氧化物膜128、金屬氧化物膜208、金屬氧化物膜228的表面，亦即金屬氧化物膜108_2、金屬氧化物膜128_2、金屬氧化物膜208_2、金屬氧化物膜228_2的表面具有凹部的情況，但是不侷限於此，從導電膜112a、導電膜112b、導電膜115a、導電膜212a、導電膜212b及導電膜215a露出的金屬氧化物膜108、金屬氧化物膜128、金屬氧化物膜208、金屬氧化物膜228的表面也可以不具有凹部。 [0299] 接著，在絕緣膜106、金屬氧化物膜108、金屬氧化物膜128、金屬氧化物膜208、金屬氧化物膜228、導電膜215a、導電膜212a、導電膜212b、導電膜112a、導電膜112b及導電膜115a上形成絕緣膜114、絕緣膜116及絕緣膜118(參照圖17A、圖17B及圖17C)。 [0300] 在此，較佳為在形成絕緣膜114之後以不暴露於大氣的方式連續地形成絕緣膜116。藉由在形成絕緣膜114之後以不暴露於大氣的方式調整源氣體的流量、壓力、高頻功率和基板溫度中的一個以上來連續地形成絕緣膜116，可以降低絕緣膜114與絕緣膜116的介面處的來自大氣成分的雜質濃度。 [0301] 例如，作為絕緣膜114，可以藉由PECVD法形成氧氮化矽膜。此時，作為源氣體，較佳為使用含有矽的沉積氣體及氧化性氣體。含有矽的沉積氣體的典型例子為矽烷、乙矽烷、丙矽烷、氟化矽烷等。作為氧化性氣體，有一氧化二氮、二氧化氮等。另外，在相對於上述沉積氣體流量的氧化性氣體流量為20倍以上且500倍以下，較佳為40倍以上且100倍以下。 [0302] 在本實施方式中，作為絕緣膜114，在如下條件下利用PECVD法形成氧氮化矽膜：保持基板102的溫度為220℃，作為源氣體使用流量為50sccm的矽烷及流量為2000sccm的一氧化二氮，處理室內的壓力為20Pa，並且，供應到平行板電極的高頻功率為13.56MHz、100W(功率密度為1.6´10- 2 W/cm2 )。 [0303] 作為絕緣膜116，在如下條件下形成氧化矽膜或氧氮化矽膜：將設置於進行了真空抽氣的PECVD設備的處理室內的基板溫度保持為180℃以上且350℃以下，將源氣體引入處理室中並將處理室內的壓力設定為100Pa以上且250Pa以下，較佳為100Pa以上且200Pa以下，並且，對設置於處理室內的電極供應0.17W/cm2 以上且0.5W/cm2 以下，較佳為0.25W/cm2 以上且0.35W/cm2 以下的高頻功率。 [0304] 在絕緣膜116的成膜中，對具有上述壓力的反應室供應具有上述功率密度的高頻功率，由此在電漿中源氣體的分解效率得到提高，氧自由基增加，且促進源氣體的氧化，使得絕緣膜116中的氧含量超過化學計量組成。另一方面，在以上述基板溫度形成的膜中，由於矽與氧的鍵合力較弱，因此，藉由後面製程的加熱處理而使膜中的氧的一部分脫離。其結果是，可以形成氧含量超過化學計量組成且由於被加熱而其一部分的氧脫離的氧化物絕緣膜。 [0305] 在絕緣膜116的形成製程中，絕緣膜114被用作金屬氧化物膜108、208的保護膜。因此，可以在減少對金屬氧化物膜108、208造成的損傷的同時使用功率密度高的高頻功率形成絕緣膜116。 [0306] 另外，在絕緣膜116的成膜中，藉由增加相對於氧化性氣體的包含矽的沉積氣體的流量，可以減少絕緣膜116中的缺陷量。典型的是，能夠形成缺陷量較少的氧化物絕緣膜，其中藉由ESR測得的起因於矽懸空鍵且在g=2.001處出現的信號的自旋密度低於6´1017 spins/cm3 ，較佳為3´1017 spins/cm3 以下，更佳為1.5´1017 spins/cm3 以下。其結果是，能夠提高電晶體100A、200A的可靠性。 [0307] 較佳為在形成絕緣膜114、116之後進行加熱處理(以下，稱為第二加熱處理)。藉由第二加熱處理，可以降低包含於絕緣膜114、116中的氮氧化物。藉由第二加熱處理，可以將包含於絕緣膜114、116中的氧的一部分移動到金屬氧化物膜108、208中以減少金屬氧化物膜108、208中的氧缺陷。 [0308] 將第二加熱處理的溫度典型地設定為低於400℃，較佳為低於375℃，進一步較佳為150℃以上且350℃以下。第二加熱處理可以在氮、氧、超乾燥空氣(含水量為20ppm以下，較佳為1ppm以下，較佳為10ppb以下的空氣)或稀有氣體(氬、氦等)的氛圍下進行。較佳為在上述氮、氧、超乾燥空氣或稀有氣體中不含有氫、水等。該加熱處理可以使用電爐、RTA裝置等進行。 [0309] 絕緣膜118包含氫和氮中的一者或兩者。作為絕緣膜118，例如較佳為使用氮化矽膜。絕緣膜118例如可以藉由濺射法或PECVD法形成。例如，當藉由PECVD法形成絕緣膜118時，使基板溫度低於400℃，較佳為低於375℃，進一步較佳為180℃以上且350℃以下。藉由將絕緣膜118的成膜時的基板溫度設定為上述範圍，可以形成緻密的膜，所以是較佳的。另外，藉由將絕緣膜118的成膜時的基板溫度設定為上述範圍，可以將絕緣膜114、116中的氧或者過量氧移動到金屬氧化物膜108。 [0310] 例如，當作為絕緣膜118利用PECVD法形成氮化矽膜時，作為源氣體較佳為使用包含矽的沉積氣體、氮及氨。藉由使用少於氮的氨，在電漿中氨離解而產生活性種。該活性種將包括在包含矽的沉積氣體中的矽與氫之間的鍵合及氮分子之間的三鍵切斷。其結果，可以促進矽與氮的鍵合，而可以形成矽與氫的鍵合少、缺陷少且緻密的氮化矽膜。另一方面，在氨量比氮量多時，包含矽的沉積氣體及氮的分解不進展，矽與氫的鍵合會殘留下來，而導致形成缺陷增加且不緻密的氮化矽膜。由此，在源氣體中，將相對於氨的氮流量比設定為5倍以上且50倍以下，較佳為10倍以上且50倍以下。 [0311] 在本實施方式中，作為絕緣膜118，藉由利用PECVD設備並使用矽烷、氮及氨作為源氣體，形成厚度為50nm的氮化矽膜。矽烷的流量為50sccm，氮的流量為5000sccm，氨的流量為100sccm。將處理室的壓力設定為100Pa，將基板溫度設定為350℃，用27.12MHz的高頻電源對平行板電極供應1000W的高頻功率。PECVD設備是電極面積為6000cm2 的平行板型PECVD設備，並且，將所供應的功率的換算為每單位面積的功率(功率密度)為1.7´10- 1 W/cm2 。 [0312] 在此，較佳為在形成絕緣膜116之後以不暴露於大氣的方式連續地形成絕緣膜118。藉由在形成絕緣膜116之後以不暴露於大氣的方式調整源氣體的流量、壓力、高頻功率和基板溫度中的一個以上來連續地形成絕緣膜118，可以降低絕緣膜116與絕緣膜118的介面處的來自大氣成分的雜質濃度。 [0313] 此外，也可以在形成絕緣膜118之後進行與上述第一加熱處理及第二加熱處理同等的加熱處理(以下，稱為第三加熱處理)。 [0314] 藉由進行第三加熱處理，絕緣膜116所包含的氧移動到金屬氧化物膜108、208，填補金屬氧化物膜108、208中的氧缺陷。 [0315] 接著，在絕緣膜118上形成導電膜130(參照圖18A、圖18B及圖18C)。 [0316] 導電膜130可以使用具有透光性的導電膜。具有透光性的導電膜例如可以使用氧化銦錫、銦鋅氧化物、包含氧化鎢的銦氧化物、包含氧化鎢的銦鋅氧化物、包含氧化鈦的銦氧化物、包含氧化鈦的銦錫氧化物、包含氧化矽的銦錫氧化物等導電材料而形成。 [0317] 此外，在作為導電膜130使用In-Ga-Zn金屬氧化物靶材(In：Ga：Zn=4：2：4.1[原子數比])形成導電膜的情況下，當形成絕緣膜118時，絕緣膜118所包含的氫和/或氮有時進入導電膜130。此時，氫和/或氮鍵合到導電膜130中的氧缺陷而降低導電膜130的電阻。由此可以形成低電阻的導電膜130。低電阻的導電膜是氧化物導電體膜。 [0318] 在形成導電膜130時可以使用濺射裝置。在形成導電膜130時，在包含氧氣體的氛圍下進行電漿放電。此時，對被形成導電膜130的絕緣膜118添加氧。形成導電膜130時的氛圍除了氧氣體以外還可以混有惰性氣體(例如，氦氣體、氬氣體、氙氣體等)。 [0319] 氧氣體至少包含在形成導電膜130時的沉積氣體中即可，在形成導電膜130時的沉積氣體整體中，氧氣體所佔的比率高於0%且為100%以下，較佳為10%以上且100%以下，更佳為30%以上且100%以下。 [0320] 在本實施方式中，藉由濺射法利用In-Ga-Zn金屬氧化物靶材(In：Ga：Zn=4：2：4.1[原子數比])形成導電膜130。另外，也可以使用ITO靶材且作為沉積氣體使用100%的氧氣體利用濺射法形成導電膜130。 [0321] 注意，雖然本實施方式示出在形成導電膜130時對絕緣膜116添加氧的方法，但是不侷限於此。例如，也可以在形成導電膜130之後還對絕緣膜116添加氧。 [0322] 為了對絕緣膜116添加氧，例如可以使用包含銦、錫、矽的氧化物(In-Sn-Si氧化物，也稱為ITSO)靶材(In2 O3 ：SnO2 ：SiO2 =85：10：5[重量%])形成厚度為5nm的ITSO膜。此時，當ITSO膜的厚度為1nm以上且20nm以下，或者2nm以上且10nm以下時，可以適當地透過氧且抑制氧的釋放，所以是較佳的。然後，隔著ITSO膜對絕緣膜116添加氧。作為氧的添加方法，可以舉出離子摻雜法、離子植入法、電漿處理法等。當添加氧時，藉由對基板一側施加偏壓，可以有效地將氧添加到絕緣膜116。當施加偏壓時，例如使用灰化裝置，可以將施加到該灰化裝置的基板一側的偏壓的功率密度設定為1W/cm2 以上且5W/cm2 以下。此外，藉由將添加氧時的基板溫度設定為室溫以上且300℃以下，較佳為100℃以上且250℃以下，可以高效地對絕緣膜116添加氧。 [0323] 接著，將導電膜130加工為所希望的形狀，來形成導電膜130a(參照圖19A、圖19B及圖19C)。形成導電膜130a的製程為第三光微影製程。 [0324] 在本實施方式中，使用濕蝕刻法形成導電膜130a。在形成導電膜130a時，也可以使用乾蝕刻法。 [0325] 接著，在絕緣膜118及導電膜130a上形成絕緣膜119(參照圖20A、圖20B及圖20C)。絕緣膜119在與導電膜212b重疊的區域具有開口242。絕緣膜119在與導電膜113重疊的區域具有開口142。絕緣膜119在與導電膜115a重疊的區域具有開口144。絕緣膜119在不與導電膜130a重疊且與導電膜104重疊的區域具有開口146。絕緣膜119在與導電膜130a重疊的區域具有開口148。 [0326] 在絕緣膜118及導電膜130a上塗佈感光樹脂，然後進行曝光及顯影，來可以形成絕緣膜119。或者，在絕緣膜118及導電膜130a上塗佈非感光樹脂，然後進行燒成。接著，形成光阻遮罩，使用該光阻遮罩對燒成後的非感光樹脂進行蝕刻，來可以形成絕緣膜119。形成絕緣膜119的製程為第四光微影製程。 [0327] 接著，使用絕緣膜119作為遮罩，去除絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118的一部分(參照圖21A、圖21B及圖21C)。去除與開口242重疊的區域的絕緣膜114、絕緣膜116及絕緣膜118使導電膜212b露出，來形成開口242a。去除與開口142重疊的區域的絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118使導電膜113露出，來形成開口142a。去除與開口144重疊的區域的絕緣膜114、絕緣膜116及絕緣膜118使導電膜115a露出，來形成開口144a。去除與開口146重疊的區域的絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118使導電膜104露出，來形成開口146a。不去除與開口148重疊的區域的導電膜130a，來形成開口148a。 [0328] 在形成開口242a、開口142a、開口144a、開口146a及開口148a時，可以使用乾蝕刻法。此外，也可以使用濕蝕刻法。也可以組合乾蝕刻法和濕蝕刻法。 [0329] 在形成開口242a、開口142a、開口144a、開口146a及開口148a時，較佳的是，絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118的蝕刻速率較高，而導電膜212b、導電膜113、導電膜115a及導電膜130a的蝕刻速率較低。此外，絕緣膜119的蝕刻速率較佳為較低。 [0330] 在形成開口242a、開口142a、開口144a、開口146a及開口148a時，有時絕緣膜119的厚度變薄。考慮該變薄的厚度設定形成絕緣膜119時的膜厚度即可。 [0331] 接著，在絕緣膜119、開口242a、開口142a、開口144a、開口146a及開口148a上形成導電膜，該導電膜將成為導電膜220、被用作第四佈線的導電膜120a及被用作第一佈線的導電膜120b。 [0332] 藉由使用光微影製程及蝕刻製程對上述導電膜進行加工，形成導電膜220、被用作第四佈線的導電膜120a及被用作第一佈線的導電膜120b(參照圖22A、圖22B及圖22C)。藉由設置導電膜120a，使導電膜113與導電膜115a電連接。藉由設置導電膜120b，使導電膜130a與導電膜104電連接。 [0333] 形成導電膜220、被用作第四佈線的導電膜120a及被用作第一佈線的導電膜120b的製程為第五光微影製程。 [0334] 如此，藉由進行五次的光微影製程，可以製造圖1A、圖1B及圖1C所示的顯示裝置。 [0335] 在本發明的一個實施方式中，藉由較少(五次)的光微影製程可以製造顯示裝置。藉由減少光微影製程數，可以減小配置圖案時的面積，並且可以實現電晶體的微型化及顯示裝置的高清晰化。此外，藉由減少光微影製程數，可以實現製程的簡化以及良率的提高。此外，藉由減少光微影製程數，可以降低遮罩成本。 [0336] á1-8.顯示裝置的製造方法2ñ 參照圖23A至圖29C對包括在圖3A、圖3B及圖3C所示的本發明的一個實施方式的顯示裝置中的電晶體100B、電晶體200B、電容器250B及連接部150B的製造方法進行說明。 [0337] 圖23A至圖29C是說明顯示裝置的製造方法的剖面圖。在圖23A至圖29C的剖面圖中，點劃線X1-X2的方向為電晶體200B的通道長度方向，點劃線X3-X4的方向為電晶體100B的通道長度方向。點劃線Y1-Y2的方向為電晶體100B的通道寬度方向。 [0338] 在圖3A、圖3B及圖3C所示的顯示裝置中，與圖1A、圖1B及圖1C所示的顯示裝置同樣地進行到形成導電膜215、導電膜212a、導電膜212b、導電膜112a、導電膜112b及導電膜115a為止的製程。 [0339] 接著，在導電膜215a、導電膜212a、導電膜212b、導電膜112a、導電膜112b及導電膜115a上形成絕緣膜114及絕緣膜116(參照圖23A、圖23B及圖23C)。 [0340] 接著，在絕緣膜116上形成導電膜132(參照圖25A、圖25B及圖25C)。 [0341] 作為導電膜132，可以使用In-Ga-Zn金屬氧化物靶材(In：Ga：Zn=4：2：4.1[原子數比])形成導電膜。當在導電膜132上形成絕緣膜118時，絕緣膜118所包含的氫和/或氮有時進入導電膜132。此時，氫和/或氮鍵合到導電膜132中的氧缺陷而降低導電膜132的電阻。由此可以形成低電阻的導電膜132。低電阻的導電膜是氧化物導電體膜。 [0342] 圖24A、圖24B和圖24C是在絕緣膜116上形成導電膜132時的成膜裝置內的剖面示意圖。圖24A、圖24B和圖24C示意性地示出：作為成膜裝置的濺射裝置；在該濺射裝置中設置的靶材193；在靶材193的下方形成的電漿194。 [0343] 首先，在形成導電膜132時，在包含氧氣體的氛圍下進行電漿放電。此時，對被形成導電膜132的絕緣膜116添加氧。形成導電膜132時的氛圍除了氧氣體以外還可以混有惰性氣體(例如，氦氣體、氬氣體、氙氣體等)。 [0344] 氧氣體至少包含在形成導電膜132時的沉積氣體中即可，在形成導電膜132時的沉積氣體整體中，氧氣體所佔的比率高於0%且為100%以下，較佳為10%以上且100%以下，更佳為30%以上且100%以下。 [0345] 在圖24A、圖24B及圖24C中，以虛線的箭頭示意性地表示添加到絕緣膜116的氧或過量氧。 [0346] 在本實施方式中，藉由濺射法利用In-Ga-Zn金屬氧化物靶材(In：Ga：Zn=4：2：4.1[原子數比])形成導電膜132。另外，也可以使用ITO靶材且作為沉積氣體使用100%的氧氣體利用濺射法形成導電膜132。 [0347] 注意，雖然本實施方式示出在形成導電膜132時對絕緣膜116添加氧的方法，但是不侷限於此。例如，也可以在形成導電膜132之後還對絕緣膜116添加氧。 [0348] 為了對絕緣膜116添加氧，例如可以使用包含銦、錫、矽的氧化物(In-Sn-Si氧化物，也稱為ITSO)靶材(In2 O3 ：SnO2 ：SiO2 =85：10：5[重量%])形成厚度為5nm的ITSO膜。此時，當ITSO膜的厚度為1nm以上且20nm以下，或者2nm以上且10nm以下時，可以適當地透過氧且抑制氧的釋放，所以是較佳的。然後，隔著ITSO膜對絕緣膜116添加氧。作為氧的添加方法，可以舉出離子摻雜法、離子植入法、電漿處理法等。當添加氧時，藉由對基板一側施加偏壓，可以有效地將氧添加到絕緣膜116。當施加偏壓時，例如使用灰化裝置，可以將施加到該灰化裝置的基板一側的偏壓的功率密度設定為1W/cm2 以上且5W/cm2 以下。此外，藉由將添加氧時的基板溫度設定為室溫以上且300℃以下，較佳為100℃以上且250℃以下，可以高效地對絕緣膜116添加氧。 [0349] 接著，將導電膜132加工為所希望的形狀，來形成導電膜132a(參照圖26A、圖26B及圖26C)。形成導電膜132a的製程為第三光微影製程。 [0350] 在本實施方式中，使用濕蝕刻法形成導電膜132a。在形成導電膜132a時，也可以使用乾蝕刻法。 [0351] 接著，在絕緣膜116及導電膜132a上形成絕緣膜118。 [0352] 接著，在絕緣膜118上形成絕緣膜119(參照圖27A、圖27B及圖27C)。絕緣膜119在與導電膜212b重疊的區域具有開口242。絕緣膜119在與導電膜113重疊的區域具有開口142。絕緣膜119在與導電膜115a重疊的區域具有開口144。絕緣膜119在不與導電膜132a重疊且與導電膜104重疊的區域具有開口146。絕緣膜119在與導電膜132a重疊的區域具有開口148。 [0353] 在絕緣膜118及導電膜132a上塗佈感光樹脂，然後進行曝光及顯影，來可以形成絕緣膜119。或者，在絕緣膜118及導電膜132a上塗佈非感光樹脂，然後進行燒成。接著，形成光阻遮罩，使用該光阻遮罩對燒成後的非感光樹脂進行蝕刻，來可以形成絕緣膜119。形成絕緣膜119的製程為第四光微影製程。 [0354] 接著，使用絕緣膜119作為遮罩，去除絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118的一部分(參照圖28A、圖28B及圖28C)。去除與開口242重疊的區域的絕緣膜114、絕緣膜116及絕緣膜118使導電膜212b露出，來形成開口242b。去除與開口142重疊的區域的絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118使導電膜113露出，來形成開口142b。去除與開口144重疊的區域的絕緣膜114、絕緣膜116及絕緣膜118使導電膜115a露出，來形成開口144b。去除與開口146重疊的區域的絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118使導電膜104露出，來形成開口146b。去除與開口148重疊的區域的絕緣膜118使導電膜132a露出，來形成開口148b。 [0355] 在形成開口242b、開口142b、開口144b、開口146b及開口148b時，可以使用乾蝕刻法。此外，也可以使用濕蝕刻法。也可以組合乾蝕刻法和濕蝕刻法。 [0356] 在形成開口242b、開口142b、開口144b、開口146b及開口148b時，較佳的是，絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118的蝕刻速率較高，而導電膜212b、導電膜113、導電膜115a及導電膜132a的蝕刻速率較低。此外，絕緣膜119的蝕刻速率較佳為較低。 [0357] 在形成開口242b、開口142b、開口144b、開口146b及開口148b時，有時絕緣膜119的厚度變薄。考慮該變薄的厚度設定形成絕緣膜119時的膜厚度即可。 [0358] 接著，在絕緣膜119、開口242b、開口142b、開口144b、開口146b及開口148b上形成導電膜，該導電膜將成為導電膜220、被用作第四佈線的導電膜120a及被用作第一佈線的導電膜120b。 [0359] 藉由使用光微影製程及蝕刻製程對上述導電膜進行加工，形成導電膜220、被用作第四佈線的導電膜120a及被用作第一佈線的導電膜120b(參照圖29A、圖29B及圖29C)。藉由形成導電膜120a，使導電膜113與導電膜115a電連接。藉由形成導電膜120b，使導電膜132a與導電膜104電連接。 [0360] 形成導電膜220、被用作第四佈線的導電膜120a及被用作第一佈線的導電膜120b的製程為第五光微影製程。 [0361] 如此，藉由進行五次的光微影製程，可以製造圖3A、圖3B及圖3C所示的顯示裝置。 [0362] 在本發明的一個實施方式中，藉由較少(五次)的光微影製程可以製造顯示裝置。藉由減少光微影製程數，可以減小配置圖案時的面積，並且可以實現電晶體的微型化及顯示裝置的高清晰化。此外，藉由減少光微影製程數，可以實現製程的簡化以及良率的提高。此外，藉由減少光微影製程數，可以降低遮罩成本。 [0363] á1-9.顯示裝置的製造方法3ñ 參照圖30A至圖32C對包括在圖4A、圖4B及圖4C所示的本發明的一個實施方式的顯示裝置中的電晶體100C、電晶體200C、電容器250C及連接部150C的製造方法進行說明。在圖4A、圖4B及圖4C所示的顯示裝置中，與圖1A、圖1B及圖1C所示的顯示裝置同樣地進行到形成絕緣膜118為止的製程。 [0364] 接著，在絕緣膜118上形成絕緣膜119(參照圖30A、圖30B及圖30C)。絕緣膜119在與導電膜212b重疊的區域具有開口242。絕緣膜119在與導電膜113重疊的區域具有開口142。絕緣膜119在與導電膜115a重疊的區域具有開口144。 [0365] 在絕緣膜118上塗佈感光樹脂，然後進行曝光及顯影，來可以形成絕緣膜119。或者，在絕緣膜118上塗佈非感光樹脂，然後進行燒成。接著，形成光阻遮罩，使用該光阻遮罩對燒成後的非感光樹脂進行蝕刻，來可以形成絕緣膜119。形成絕緣膜119的製程為第三光微影製程。 [0366] 接著，使用絕緣膜119作為遮罩，去除絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118的一部分(參照圖31A、圖31B及圖31C)。去除與開口242重疊的區域的絕緣膜114、絕緣膜116及絕緣膜118使導電膜212b露出，來形成開口242c。去除與開口142重疊的區域的絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118使導電膜113露出，來形成開口142c。去除與開口144重疊的區域的絕緣膜114、絕緣膜116及絕緣膜118使導電膜115a露出，來形成開口144c。 [0367] 在形成開口242c、開口142c、開口144c時，可以使用乾蝕刻法。此外，也可以使用濕蝕刻法。也可以組合乾蝕刻法和濕蝕刻法。 [0368] 在形成開口242c、開口142c、開口144c時，較佳的是，絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118的蝕刻速率較高，而導電膜212b、導電膜113、導電膜115a及導電膜132a的蝕刻速率較低。此外，絕緣膜119的蝕刻速率較佳為較低。 [0369] 在形成開口242c、開口142c、開口144c時，有時絕緣膜119的厚度變薄。考慮該變薄的厚度設定形成絕緣膜119時的膜厚度即可。 [0370] 接著，在絕緣膜119、開口242c、開口142c、開口144c上形成導電膜，該導電膜將成為導電膜220、被用作第四佈線的導電膜120a及被用作第一佈線的導電膜120b。 [0371] 藉由使用光微影製程及蝕刻製程對上述導電膜進行加工，形成導電膜220、被用作第四佈線的導電膜120a及被用作第一佈線的導電膜120b(參照圖32A、圖32B及圖32C)。藉由形成導電膜120a，使導電膜113與導電膜115a電連接。 [0372] 形成導電膜220、被用作第四佈線的導電膜120a及被用作第一佈線的導電膜120b的製程為第四光微影製程。 [0373] 如此，藉由進行四次的光微影製程，可以製造圖4A、圖4B及圖4C所示的顯示裝置。 [0374] 此外，在本實施方式中，藉由一次的光微影製程形成金屬氧化物膜228、金屬氧化物膜208、金屬氧化物膜108、金屬氧化物膜128、導電膜215a、導電膜212a、導電膜212b、導電膜112a、導電膜112b及導電膜115a。也可以藉由彼此不同的光微影製程進行金屬氧化物膜228、金屬氧化物膜208、金屬氧化物膜108和金屬氧化物膜128的形成以及導電膜215a、導電膜212a、導電膜212b、導電膜112a、導電膜112b和導電膜115a的形成。在進行不同的光微影製程形成它們的情況下，可以藉由五次的光微影製程形成圖4A、圖4B及圖4C所示的顯示裝置。 [0375] 在本發明的一個實施方式中，藉由較少(四次或五次)的光微影製程可以製造顯示裝置。藉由減少光微影製程數，可以減小配置圖案時的面積，並且可以實現電晶體的微型化及顯示裝置的高清晰化。此外，藉由減少光微影製程數，可以實現製程的簡化以及良率的提高。此外，藉由減少光微影製程數，可以降低遮罩成本。 [0376] á1-10.顯示裝置的製造方法4ñ 參照圖33A至圖41C對包括在圖6A、圖6B及圖6C所示的本發明的一個實施方式的顯示裝置中的電晶體100D、電晶體200D、電容器250D及連接部150D的製造方法進行說明。 [0377] 圖33A至圖41C是說明顯示裝置的製造方法的剖面圖。在圖33A至圖41C的剖面圖中，點劃線X1-X2的方向為電晶體200D的通道長度方向，點劃線X3-X4的方向為電晶體100D的通道長度方向。點劃線Y1-Y2的方向為電晶體100D的通道寬度方向。 [0378] 在圖6A、圖6B及圖6C所示的顯示裝置中，與圖1A、圖1B及圖1C所示的顯示裝置同樣地進行到形成金屬氧化物膜108a及金屬氧化物膜108b為止的製程。 [0379] 接著，利用光微影製程及蝕刻製程對金屬氧化物膜108及絕緣膜106進行加工，來在與導電膜113重疊的區域形成開口160(參照圖33A、圖33B及圖33C)。在開口160中，導電膜113露出。形成開口160的製程為第二光微影製程。 [0380] 接著，在金屬氧化物108上形成導電膜112。接著，藉由第三光微影製程，在導電膜112上形成光阻遮罩251、光阻遮罩253、光阻遮罩151及光阻遮罩153(參照圖34A、圖34B及圖34C)。形成光阻遮罩251、光阻遮罩253、光阻遮罩151及光阻遮罩153的製程為第三光微影製程。 [0381] 在本實施方式中，作為導電膜112，藉由濺射法依次形成厚度為30nm的鈦膜、厚度為200nm的銅膜、厚度為10nm的鈦膜。 [0382] 光阻遮罩253在與導電膜204重疊的區域具有光阻劑的厚度薄的區域255。區域255也可以稱為凹部。光阻遮罩151在與導電膜104重疊的區域具有光阻劑的厚度薄的區域155。區域155也可以稱為凹部。在本實施方式中，在形成光阻遮罩時，採用使用多色調(高灰階)遮罩的曝光。藉由使用多色調(高灰階)遮罩可以形成光阻劑的厚度不同的光阻遮罩。 [0383] 藉由在使用多色調遮罩進行曝光之後進行顯影，可以形成如圖34A、圖34B及圖34C所示的具有厚度不同的區域的光阻遮罩。 [0384] 注意，雖然作為多色調遮罩示出了光阻劑的厚度為兩種的例子，但是本發明的一個實施方式不侷限於此。藉由使用具有多個光穿透率的繞射光柵部18或半透過膜23，可以形成具有三種以上的厚度的光阻劑。 [0385] 接著，以光阻遮罩251、光阻遮罩253、光阻遮罩151及光阻遮罩153為遮罩去除導電膜112及金屬氧化物膜108的一部分，來形成導電膜215、導電膜212A、導電膜112A、導電膜115、金屬氧化物膜228、金屬氧化物膜208、金屬氧化物膜108及金屬氧化物膜128(參照圖35A、圖35B及圖35C)。 [0386] 在對導電膜112進行加工時，可以使用濕蝕刻法。但是，加工方法不侷限於此，例如也可以使用乾蝕刻法。在對金屬氧化物膜108b進行加工時，可以使用濕蝕刻法。但是，加工方法不侷限於此，例如也可以使用乾蝕刻法。 [0387] 在對導電膜112、金屬氧化物膜108a及金屬氧化物膜108b進行加工時，可以使用不同的蝕刻法。例如，可以在對導電膜112進行加工時使用乾蝕刻法，而在對金屬氧化物膜108a及金屬氧化物膜108b進行加工時使用濕蝕刻法。 [0388] 接著，去除光阻遮罩251、光阻遮罩253、光阻遮罩151及光阻遮罩153的一部分，來縮小光阻遮罩的面積。藉由縮小光阻遮罩的面積，形成光阻遮罩251a、光阻遮罩253a、光阻遮罩253b、光阻遮罩151a、光阻遮罩151b及光阻遮罩153a(參照圖36A、圖36B及圖36C)。 [0389] 在去除光阻遮罩的一部分時，可以使用灰化裝置。藉由灰化處理，在光阻遮罩的面積減小的同時，有時光阻遮罩的厚度減薄。 [0390] 例如，作為灰化處理可以利用光激發灰化處理，其中，對氧或臭氧等氣體照射紫外線等光，使氣體與有機物起化學反應，來去除有機物。此外，作為灰化處理可以利用電漿灰化處理，其中，以高頻等使氧或臭氧等氣體電漿化，使用該電漿去除有機物。 [0391] 光阻遮罩253的厚度薄的區域255及光阻遮罩151的厚度薄的區域155的光阻劑藉由上述灰化處理被去除，由此如圖36A、圖36B及圖36C所示那樣，光阻遮罩彼此分開。藉由去除光阻遮罩的一部分，去除與導電膜204重疊的區域255a的光阻遮罩，來使區域255a的導電膜212A露出。此外，去除與導電膜104重疊的區域155a的光阻遮罩，來使區域155a的導電膜112A露出。 [0392] 光阻遮罩251a的端部位於導電膜215的端部的內側。光阻遮罩253a及光阻遮罩253b的端部位於導電膜212A的端部的內側。光阻遮罩151a及光阻遮罩151b的端部位於導電膜112A的端部的內側。光阻遮罩153a的端部位於導電膜115的端部的內側。 [0393] 接著，以光阻遮罩251a、光阻遮罩253a、光阻遮罩253b、光阻遮罩151a、光阻遮罩151b及光阻遮罩153a為遮罩去除導電膜215、導電膜212A、導電膜112A、導電膜115的一部分，來形成導電膜215a、導電膜212a、導電膜212b、導電膜112a、導電膜112b及導電膜115a(參照圖37A、圖37B及圖37C)。 [0394] 導電膜215a的端部位於金屬氧化物膜228的端部的內側。導電膜212a及導電膜212b的端部位於金屬氧化物膜208的端部的內側。導電膜112a及導電膜112b的端部位於金屬氧化物膜108的端部的內側。導電膜115a的端部位於金屬氧化物膜128的端部的內側。 [0395] 接著，去除光阻遮罩251a、光阻遮罩253a、光阻遮罩253b、光阻遮罩151a、光阻遮罩151b及光阻遮罩153a。 [0396] 在去除光阻遮罩之後，也可以洗滌金屬氧化物膜108、金屬氧化物膜128、金屬氧化物膜208及金屬氧化物膜228(更明確而言，金屬氧化物膜108_2、金屬氧化物膜128_2、金屬氧化物膜208_2及金屬氧化物膜228_2)的表面(背後通道一側)。作為洗滌方法，例如可以舉出使用磷酸等化學溶液的洗滌。藉由使用磷酸等化學溶液進行洗滌，可以去除附著於金屬氧化物膜108_2、金屬氧化物膜128_2、金屬氧化物膜208_2及金屬氧化物膜228_2表面的雜質(例如，包含在導電膜112a、導電膜112b、導電膜212a、導電膜212b中的元素等)。注意，不一定必須進行該洗滌，根據情況可以不進行該洗滌。 [0397] 另外，在導電膜112a、導電膜112b、導電膜212a、導電膜212b的形成製程和/或上述洗滌製程中，有時金屬氧化物膜108及金屬氧化物膜208的從導電膜112a、導電膜112b、導電膜212a、導電膜212b露出的區域有時變薄。 [0398] 此外，金屬氧化物膜108及金屬氧化物膜208露出的區域，就是說，金屬氧化物膜108_2及金屬氧化物膜208_2較佳為其結晶性得到提高的金屬氧化物膜。結晶性高的金屬氧化物膜具有雜質(尤其是用於導電膜112a、導電膜112b、導電膜212a、導電膜212b的構成元素)不容易擴散到膜中的結構。因此，可以製造一種可靠性高的電晶體。 [0399] 此外，在圖37A、圖37B及圖37C中，雖然示出從導電膜112a、導電膜112b、導電膜115a、導電膜212a、導電膜212b及導電膜215a露出的金屬氧化物膜108、金屬氧化物膜128、金屬氧化物膜208、金屬氧化物膜228的表面，亦即金屬氧化物膜108_2、金屬氧化物膜128_2、金屬氧化物膜208_2、金屬氧化物膜228_2的表面具有凹部的情況，但是不侷限於此，從導電膜112a、導電膜112b、導電膜115a、導電膜212a、導電膜212b及導電膜215a露出的金屬氧化物膜108、金屬氧化物膜128、金屬氧化物膜208、金屬氧化物膜228的表面也可以不具有凹部。 [0400] 接著，在絕緣膜106、金屬氧化物膜108、金屬氧化物膜128、金屬氧化物膜208、金屬氧化物膜228、導電膜215a、導電膜212a、導電膜212b、導電膜112a、導電膜112b及導電膜115a上形成絕緣膜114、絕緣膜116及絕緣膜118(參照圖38A、圖38B及圖38C)。 [0401] 因為絕緣膜114、絕緣膜116及絕緣膜118的形成方法可以參照上述記載，所以省略詳細說明。 [0402] 在此，較佳為在形成絕緣膜114之後以不暴露於大氣的方式連續地形成絕緣膜116。藉由在形成絕緣膜114之後以不暴露於大氣的方式調整源氣體的流量、壓力、高頻功率和基板溫度中的一個以上來連續地形成絕緣膜116，可以降低絕緣膜114與絕緣膜116的介面處的來自大氣成分的雜質濃度。 [0403] 在此，較佳為在形成絕緣膜116之後以不暴露於大氣的方式連續地形成絕緣膜118。藉由在形成絕緣膜116之後以不暴露於大氣的方式調整源氣體的流量、壓力、高頻功率和基板溫度中的一個以上來連續地形成絕緣膜118，可以降低絕緣膜116與絕緣膜118的介面處的來自大氣成分的雜質濃度。 [0404] 此外，也可以在形成絕緣膜118之後進行與上述第一加熱處理及第二加熱處理同等的加熱處理(以下，稱為第三加熱處理)。 [0405] 藉由進行第三加熱處理，絕緣膜116所包含的氧移動到金屬氧化物膜108、208，填補金屬氧化物膜108、208中的氧缺陷。 [0406] 接著，藉由第四光微影製程，在絕緣膜118上形成絕緣膜119(參照圖39A、圖39B及圖39C)。絕緣膜119在與導電膜212b重疊的區域包括開口242。絕緣膜119在與導電膜104及金屬氧化物膜108重疊的區域包括厚度薄的區域157。區域157也可以稱為凹部。絕緣膜119在與導電膜104重疊且不與金屬氧化物膜108重疊的區域包括開口146。在本實施方式中，在形成絕緣膜119時，採用使用多色調(高灰階)遮罩的曝光。藉由使用多色調(高灰階)遮罩可以形成包括厚度不同的區域的絕緣膜119。 [0407] 在絕緣膜118上塗佈感光樹脂，然後進行曝光及顯影，來可以形成絕緣膜119。或者，在絕緣膜118上塗佈非感光樹脂，然後進行燒成。接著，形成光阻遮罩，使用該光阻遮罩對燒成後的非感光樹脂進行蝕刻，來可以形成絕緣膜119。 [0408] 接著，使用絕緣膜119作為遮罩，去除絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118的一部分(參照圖40A、圖40B及圖40C)。去除與開口242重疊的區域的絕緣膜114、絕緣膜116及絕緣膜118使導電膜212b露出，來形成開口242d。去除與開口146重疊的區域的絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118使導電膜104露出，來形成開口146d。在去除絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118的一部分時，絕緣膜119的一部分也被去除。去除區域157的絕緣膜119使絕緣膜118露出，來形成開口142d。 [0409] 在形成開口242d、開口142d、開口146d時，可以使用乾蝕刻法。此外，也可以使用濕蝕刻法。也可以組合乾蝕刻法和濕蝕刻法。 [0410] 在形成開口242d、開口142d、開口146d時，較佳的是，絕緣膜106、絕緣膜114、絕緣膜116及絕緣膜118的蝕刻速率較高，而導電膜212b、導電膜113及導電膜115a的蝕刻速率較低。 [0411] 在形成開口242d、開口142d、開口146d時，有時絕緣膜119的厚度變薄。考慮該變薄的厚度設定形成絕緣膜119時的膜厚度即可。 [0412] 在去除區域157的絕緣膜119時，可以利用灰化處理。藉由灰化處理，在絕緣膜119的面積減小的同時，有時絕緣膜119的厚度減薄。考慮該變薄的厚度設定形成絕緣膜119時的膜厚度即可。 [0413] 接著，在絕緣膜119、開口242a、開口142d及開口146d上形成導電膜。將該導電膜加工為所希望的形狀，來形成導電膜220及導電膜130d(參照圖41A、圖41B及圖41C)。形成導電膜220及導電膜130d的製程為第五光微影製程。 [0414] 導電膜220及導電膜130d可以使用具有透光性的導電膜。具有透光性的導電膜例如可以使用氧化銦錫、銦鋅氧化物、包含氧化鎢的銦氧化物、包含氧化鎢的銦鋅氧化物、包含氧化鈦的銦氧化物、包含氧化鈦的銦錫氧化物、包含氧化矽的銦錫氧化物等導電材料而形成。 [0415] 此外，在作為導電膜220及導電膜130d使用In-Ga-Zn金屬氧化物靶材(In：Ga：Zn=4：2：4.1[原子數比])形成導電膜的情況下，當形成絕緣膜118時，絕緣膜118所包含的氫和/或氮有時進入導電膜220及導電膜130d。此時，氫和/或氮鍵合到導電膜220及導電膜130d中的氧缺陷而降低導電膜220及導電膜130d的電阻。由此可以形成低電阻的導電膜220及導電膜130d。低電阻的導電膜是氧化物導電體膜。 [0416] 在形成導電膜220及導電膜130d時可以使用濺射裝置。在形成導電膜220及導電膜130d時，在包含氧氣體的氛圍下進行電漿放電。此時，對被形成導電膜220及導電膜130d的絕緣膜118添加氧。形成導電膜220及導電膜130d時的氛圍除了氧氣體以外還可以混有惰性氣體(例如，氦氣體、氬氣體、氙氣體等)。 [0417] 氧氣體至少包含在形成導電膜220及導電膜130d時的沉積氣體中即可，在形成導電膜220及導電膜130d時的沉積氣體整體中，氧氣體所佔的比率高於0%且為100%以下，較佳為10%以上且100%以下，更佳為30%以上且100%以下。 [0418] 在本實施方式中，藉由濺射法利用In-Ga-Zn金屬氧化物靶材(In：Ga：Zn=4：2：4.1[原子數比])形成導電膜220及導電膜130d。另外，也可以使用ITO靶材且作為沉積氣體使用100%的氧氣體利用濺射法形成導電膜220及導電膜130d。 [0419] 注意，雖然本實施方式示出在形成導電膜220及導電膜130d時對絕緣膜116添加氧的方法，但是不侷限於此。例如，也可以在形成導電膜220及導電膜130d之後還對絕緣膜116添加氧。 [0420] 為了對絕緣膜116添加氧，例如可以使用包含銦、錫、矽的氧化物(In-Sn-Si氧化物，也稱為ITSO)靶材(In2 O3 ：SnO2 ：SiO2 =85：10：5[重量%])形成厚度為5nm的ITSO膜。此時，當ITSO膜的厚度為1nm以上且20nm以下，或者2nm以上且10nm以下時，可以適當地透過氧且抑制氧的釋放，所以是較佳的。然後，隔著ITSO膜對絕緣膜116添加氧。作為氧的添加方法，可以舉出離子摻雜法、離子植入法、電漿處理法等。當添加氧時，藉由對基板一側施加偏壓，可以有效地將氧添加到絕緣膜116。當施加偏壓時，例如使用灰化裝置，可以將施加到該灰化裝置的基板一側的偏壓的功率密度設定為1W/cm2 以上且5W/cm2 以下。此外，藉由將添加氧時的基板溫度設定為室溫以上且300℃以下，較佳為100℃以上且250℃以下，可以高效地對絕緣膜116添加氧。 [0421] 在本實施方式中，使用濕蝕刻法形成導電膜220及導電膜130d。在形成導電膜220及導電膜130d時，也可以使用乾蝕刻法。 [0422] 如此，藉由進行五次的光微影製程，可以製造圖6A、圖6B及圖6C所示的顯示裝置。 [0423] 在本發明的一個實施方式中，藉由較少(五次)的光微影製程可以製造顯示裝置。藉由減少光微影製程數，可以減小配置圖案時的面積，並且可以實現電晶體的微型化及顯示裝置的高清晰化。此外，藉由減少光微影製程數，可以實現製程的簡化以及良率的提高。此外，藉由減少光微影製程數，可以降低遮罩成本。此外，在連接部中，藉由使被用作第一佈線的導電膜113與被用作第二佈線的導電膜115d直接連接，可以實現良好的接觸，而可以降低接觸電阻。 [0424] á1-11.顯示裝置的製造方法5ñ 參照圖42A至圖44C對包括在圖8A、圖8B及圖8C所示的本發明的一個實施方式的顯示裝置中的電晶體100E、電晶體200E、電容器250E及連接部150E的製造方法進行說明。在圖8A、圖8B及圖8C所示的顯示裝置中，與圖6A、圖6B及圖6C所示的顯示裝置同樣地進行到形成絕緣膜118為止的製程。 [0425] 接著，藉由第四光微影製程，在絕緣膜118上形成絕緣膜119(參照圖42A、圖42B及圖42C)。絕緣膜119在與導電膜212b重疊的區域包括開口242。 [0426] 在絕緣膜118上塗佈感光樹脂，然後進行曝光及顯影，來可以形成絕緣膜119。或者，在絕緣膜118上塗佈非感光樹脂，然後進行燒成。接著，形成光阻遮罩，使用該光阻遮罩對燒成後的非感光樹脂進行蝕刻，來可以形成絕緣膜119。 [0427] 接著，使用絕緣膜119作為遮罩，去除絕緣膜114、絕緣膜116及絕緣膜118的一部分(參照圖43A、圖43B及圖43C)。去除與開口242重疊的區域的絕緣膜114、絕緣膜116及絕緣膜118使導電膜212b露出，來形成開口242e。 [0428] 在形成開口242e時，可以使用乾蝕刻法。此外，也可以使用濕蝕刻法。也可以組合乾蝕刻法和濕蝕刻法。 [0429] 在形成開口242e時，較佳的是，絕緣膜114、絕緣膜116及絕緣膜118的蝕刻速率較高，而導電膜212b的蝕刻速率較低。此外，絕緣膜119的蝕刻速率較佳為較低。 [0430] 在形成開口242e時，有時絕緣膜119的厚度變薄。考慮該變薄的厚度設定形成絕緣膜119時的膜厚度即可。 [0431] 接著，在絕緣膜119及開口242e上形成導電膜。將該導電膜加工為所希望的形狀，來形成導電膜220(參照圖44A、圖44B及圖44C)。形成導電膜220的製程為第五光微影製程。 [0432] 導電膜220可以使用具有透光性的導電膜。具有透光性的導電膜例如可以使用氧化銦錫、銦鋅氧化物、包含氧化鎢的銦氧化物、包含氧化鎢的銦鋅氧化物、包含氧化鈦的銦氧化物、包含氧化鈦的銦錫氧化物、包含氧化矽的銦錫氧化物等導電材料而形成。 [0433] 在本實施方式中，使用濕蝕刻法形成導電膜220。在形成導電膜220時，也可以使用乾蝕刻法。 [0434] 如此，藉由進行五次的光微影製程，可以製造圖8A、圖8B及圖8C所示的顯示裝置。 [0435] 在本發明的一個實施方式中，藉由較少(五次)的光微影製程可以製造顯示裝置。藉由減少光微影製程數，可以減小配置圖案時的面積，並且可以實現電晶體的微型化及顯示裝置的高清晰化。此外，藉由減少光微影製程數，可以實現製程的簡化以及良率的提高。此外，藉由減少光微影製程數，可以降低遮罩成本。此外，在連接部中，藉由使被用作第一佈線的導電膜113與被用作第二佈線的導電膜115a直接連接，可以實現良好的接觸，而可以降低接觸電阻。 [0436] 本實施方式的至少一部分可以與本說明書所記載的其他實施方式適當地組合而實施。 [0437] 實施方式2 在本實施方式中，參照圖47至圖50C對本發明的一個實施方式的金屬氧化物膜進行說明。 [0438] áCAC-OS的構成ñ 以下說明可以用於本發明的一個實施方式所公開的電晶體的具有CAC構成的金屬氧化物的詳細內容。在此，作為具有CAC構成的金屬氧化物的典型例子使用CAC-OS進行說明。 [0439] 例如，如圖47所示，在CAC-OS中包含在金屬氧化物中的元素不均勻地分佈，以各元素為主要成分的區域001及區域002混合而形成為或分散為馬賽克(mosaic)狀。換言之，CAC-OS是包含在金屬氧化物中的元素不均勻地分佈的構成，其中包含不均勻地分佈的元素的材料的尺寸為0.5nm以上且10nm以下，較佳為0.5nm以上且3nm以下或近似的尺寸。 [0440] 包含不均勻地分佈的特定的元素的區域的物理特性由該元素所具有的性質決定。例如，包含不均勻地分佈的包含在金屬氧化物中的元素中更趨於成為絕緣體的元素的區域成為電介質區域。另一方面，包含不均勻地分佈的包含在金屬氧化物中的元素中更趨於成為導體的元素的區域成為導電體區域。當導電體區域及電介質區域以馬賽克狀混合時，該材料具有半導體的功能。 [0441] 換言之，本發明的一個實施方式中的金屬氧化物是物理特性不同的材料混合的基質複合材料(matrix composite)或金屬基質複合材料(metal matrix composite)的一種。 [0442] 氧化物半導體較佳為至少包含銦。尤其較佳為包含銦及鋅。除此之外，也可以還包含元素M(M是選自鎵、鋁、矽、硼、釔、銅、釩、鈹、鈦、鐵、鎳、鍺、鋯、鉬、鑭、鈰、釹、鉿、鉭、鎢和鎂等中的一種或多種)。 [0443] 例如，In-Ga-Zn氧化物中的CAC-OS(在CAC-OS中，尤其可以將In-Ga-Zn氧化物稱為CAC-IGZO)是指材料分成銦氧化物(以下，稱為InOX1 (X1為大於0的實數))或銦鋅氧化物(以下，稱為InX2 ZnY2 OZ2 (X2、Y2及Z2為大於0的實數))等以及鎵氧化物(以下，稱為GaOX3 (X3為大於0的實數))或鎵鋅氧化物(以下，稱為GaX4 ZnY4 OZ4 (X4、Y4及Z4為大於0的實數))等而成為馬賽克狀，且馬賽克狀的InOX1 或InX2 ZnY2 OZ2 均勻地分佈在膜中的構成(以下，也稱為雲狀)。 [0444] 換言之，CAC-OS是具有以GaOX3 為主要成分的區域和以InX2 ZnY2 OZ2 或InOX1 為主要成分的區域混在一起的構成的複合氧化物半導體。在本說明書中，例如，當第一區域的In與元素M的原子個數比大於第二區域的In與元素M的原子個數比時，第一區域的In濃度高於第二區域。 [0445] 注意，IGZO是通稱，有時是指包含In、Ga、Zn及O的化合物。作為典型例子，可以舉出以InGaO3 (ZnO)m1 (m1為自然數)或In(1+x0) Ga(1-x0) O3 (ZnO)m0 (-1 ≤x0≤1，m0為任意數)表示的結晶性化合物。 [0446] 上述結晶性化合物具有單晶結構、多晶結構或CAAC結構。CAAC結構是多個IGZO的奈米晶具有c軸配向性且在a-b面上以不配向的方式連接的結晶結構。 [0447] 另一方面，CAC-OS與氧化物半導體的材料構成有關。CAC-OS是指如下構成：在包含In、Ga、Zn及O的材料構成中，一部分中觀察到以Ga為主要成分的奈米粒子狀區域，一部分中觀察到以In為主要成分的奈米粒子狀區域，並且，這些區域分別以馬賽克狀無規律地分散。因此，在CAC-OS中，結晶結構是次要因素。 [0448] CAC-OS不包含組成不同的二種以上的膜的疊層結構。例如，不包含由以In為主要成分的膜與以Ga為主要成分的膜的兩層構成的結構。 [0449] 注意，有時觀察不到以GaOX3 為主要成分的區域與以InX2 ZnY2 OZ2 或InOX1 為主要成分的區域之間的明確的邊界。 [0450] 在CAC-OS中包含選自鋁、矽、硼、釔、銅、釩、鈹、鈦、鐵、鎳、鍺、鋯、鉬、鑭、鈰、釹、鉿、鉭、鎢和鎂等中的一種或多種以代替鎵的情況下，CAC-OS是指如下結構：一部分中觀察到以該元素為主要成分的奈米粒子狀區域，一部分中觀察到以In為主要成分的奈米粒子狀區域，並且，這些區域以馬賽克狀無規律地分散。 [0451] áCAC-OS的分析ñ 接著，說明使用各種測定方法對在基板上形成的氧化物半導體進行測定的結果。 [0452] áá樣本的結構及製造方法ññ 以下，對本發明的一個實施方式的九個樣本進行說明。各樣本在形成氧化物半導體時的基板溫度及氧氣體流量比上不同。各樣本包括基板及基板上的氧化物半導體。 [0453] 對各樣本的製造方法進行說明。 [0454] 作為基板使用玻璃基板。使用濺射裝置在玻璃基板上作為氧化物半導體形成厚度為100nm的In-Ga-Zn氧化物。成膜條件為如下：將處理室內的壓力設定為0.6Pa，作為靶材使用氧化物靶材(In：Ga：Zn=4：2：4.1[原子個數比])。另外，對設置在濺射裝置內的氧化物靶材供應2500W的AC功率。 [0455] 在形成氧化物時採用如下條件來製造九個樣本：將基板溫度設定為不進行意圖性的加熱時的溫度(以下，也稱為室溫或R.T.)、130℃或170℃。另外，將氧氣體對Ar和氧的混合氣體的流量比(以下，也稱為氧氣體流量比)設定為10%、30%或100%。 [0456] ááX射線繞射分析ññ 在本節中，說明對九個樣本進行X射線繞射(XRD：X-ray diffraction)測定的結果。作為XRD裝置，使用Bruker公司製造的D8 ADVANCE。測定條件為如下：利用Out-of-plane法進行q/2q掃描，掃描範圍為15deg.至50deg.，步進寬度為0.02deg.，掃描速度為3.0deg./分。 [0457] 圖48示出利用Out-of-plane法測定XRD譜的結果。在圖48中，最上行示出成膜時的基板溫度為170℃的樣本的測定結果，中間行示出成膜時的基板溫度為130℃的樣本的測定結果，最下行示出成膜時的基板溫度為R.T.的樣本的測定結果。另外，最左列示出氧氣體流量比為10%的樣本的測定結果，中間列示出氧氣體流量比為30%的樣本的測定結果，最右列示出氧氣體流量比為100%的樣本的測定結果。 [0458] 在圖48所示的XRD譜中，成膜時的基板溫度越高或成膜時的氧氣體流量比越高，2q=31°附近的峰值強度則越大。另外，已知2q=31°附近的峰值來源於在大致垂直於被形成面或頂面的方向上具有c軸配向性的結晶性IGZO化合物(也稱為CAAC(c-axis aligned crystalline)-IGZO)。 [0459] 另外，如圖48的XRD譜所示，成膜時的基板溫度越低或氧氣體流量比越低，峰值則越不明顯。因此，可知在成膜時的基板溫度低或氧氣體流量比低的樣本中，觀察不到測定區域的a-b面方向及c軸方向的配向。 [0460] áá電子顯微鏡分析ññ 在本節中，說明對在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本利用HAADF-STEM(High-Angle Annular Dark Field Scanning Transmission Electron Microscope：高角度環形暗場-掃描穿透式電子顯微鏡)進行觀察及分析的結果(以下，也將利用HAADF-STEM取得的影像稱為TEM影像)。 [0461] 說明對利用HAADF-STEM取得的平面影像(以下，也稱為平面TEM影像)及剖面影像(以下，也稱為剖面TEM影像)進行影像分析的結果。利用球面像差校正功能觀察TEM影像。在取得HAADF-STEM影像時，使用日本電子株式會社製造的原子解析度分析電子顯微鏡JEM-ARM200F，將加速電壓設定為200kV，照射直徑大致為0.1nm的電子束。 [0462] 圖49A為在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本的平面TEM影像。圖49B為在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本的剖面TEM影像。 [0463] áá電子繞射圖案的分析ññ 在本節中，說明藉由對在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本照射直徑為1nm的電子束(也稱為奈米束)，來取得電子繞射圖案的結果。 [0464] 觀察圖49A所示的在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本的平面TEM影像中的黑點a1、黑點a2、黑點a3、黑點a4及黑點a5的電子繞射圖案。電子繞射圖案的觀察以固定速度照射電子束35秒鐘的方式進行。圖49C示出黑點a1的結果，圖49D示出黑點a2的結果，圖49E示出黑點a3的結果，圖49F示出黑點a4的結果，圖49G示出黑點a5的結果。 [0465] 在圖49C、圖49D、圖49E、圖49F及圖49G中，觀察到如圓圈那樣的(環狀的)亮度高的區域。另外，在環狀區域內觀察到多個斑點。 [0466] 觀察圖49B所示的在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本的剖面TEM影像中的黑點b1、黑點b2、黑點b3、黑點b4及黑點b5的電子繞射圖案。圖49H示出黑點b1的結果，圖49I示出黑點b2的結果，圖49J示出黑點b3的結果，圖49K示出黑點b4的結果，圖49L示出黑點b5的結果。 [0467] 在圖49H、圖49I、圖49J、圖49K及圖49L中，觀察到環狀的亮度高的區域。另外，在環狀區域內觀察到多個斑點。 [0468] 例如，當對包含InGaZnO4 結晶的CAAC-OS在平行於樣本面的方向上入射直徑為300nm的電子束時，可以獲得包含起因於InGaZnO4 結晶的(009)面的斑點的繞射圖案。換言之，CAAC-OS具有c軸配向性，並且c軸朝向大致垂直於被形成面或頂面的方向。另一方面，當對相同的樣本在垂直於樣本面的方向上入射直徑為300nm的電子束時，確認到環狀繞射圖案。換言之，CAAC-OS不具有a軸配向性及b軸配向性。 [0469] 當使用大直徑(例如，50nm以上)的電子束對具有微晶的氧化物半導體(nano crystalline oxide semiconductor，以下稱為nc-OS)進行電子繞射時，觀察到類似光暈圖案的繞射圖案。另外，當使用小直徑(例如，小於50nm)的電子束對nc-OS進行奈米束電子繞射時，觀察到亮點(斑點)。另外，在nc-OS的奈米束電子繞射圖案中，有時觀察到如圓圈那樣的(環狀的)亮度高的區域。而且，有時在環狀區域內觀察到多個亮點。 [0470] 在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本的電子繞射圖案具有環狀的亮度高的區域且在該環狀區域內出現多個亮點。因此，在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本呈現與nc-OS類似的電子繞射圖案，在平面方向及剖面方向上不具有配向性。 [0471] 如上所述，成膜時的基板溫度低或氧氣體流量比低的氧化物半導體的性質與非晶結構的氧化物半導體膜及單晶結構的氧化物半導體膜都明顯不同。 [0472] áá元素分析ññ 在本節中，說明使用能量色散型X射線分析法(EDX：Energy Dispersive X-ray spectroscopy)取得EDX面分析影像且進行評價，由此進行在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本的元素分析的結果。在EDX測定中，作為元素分析裝置使用日本電子株式會社製造的能量色散型X射線分析裝置JED-2300T。在檢測從樣本發射的X射線時，使用矽漂移探測器。 [0473] 在EDX測定中，對樣本的分析目標區域的各點照射電子束，並測定此時發生的樣本的特性X射線的能量及發生次數，獲得對應於各點的EDX譜。在本實施方式中，各點的EDX譜的峰值歸屬於In原子中的向L殼層的電子躍遷、Ga原子中的向K殼層的電子躍遷、Zn原子中的向K殼層的電子躍遷及O原子中的向K殼層的電子躍遷，並算出各點的各原子的比率。藉由在樣本的分析目標區域中進行上述步驟，可以獲得示出各原子的比率分佈的EDX面分析影像。 [0474] 圖50A、圖50B及圖50C示出在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本的剖面的EDX面分析影像。圖50A示出Ga原子的EDX面分析影像(在所有的原子中Ga原子所佔的比率為1.18至18.64[atomic%])。圖50B示出In原子的EDX面分析影像(在所有的原子中In原子所佔的比率為9.28至33.74[atomic%])。圖50C示出Zn原子的EDX面分析影像(在所有的原子中Zn原子所佔的比率為6.69至24.99[atomic%])。另外，圖50A、圖50B及圖50C示出在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本的剖面中的相同區域。在EDX面分析影像中，由明暗表示元素的比率：該區域內的測定元素越多該區域越亮，測定元素越少該區域就越暗。圖50A、圖50B及圖50C所示的EDX面分析影像的倍率為720萬倍。 [0475] 在圖50A、圖50B及圖50C所示的EDX面分析影像中，確認到明暗的相對分佈，在成膜時的基板溫度為R.T.且氧氣體流量比為10%的條件下製造的樣本中確認到各原子具有分佈。在此，著眼於圖50A、圖50B及圖50C所示的由實線圍繞的區域及由虛線圍繞的區域。 [0476] 在圖50A中，在由實線圍繞的區域內相對較暗的區域較多，在由虛線圍繞的區域內相對較亮的區域較多。另外，在圖50B中，在由實線圍繞的區域內相對較亮的區域較多，在由虛線圍繞的區域內相對較暗的區域較多。 [0477] 換言之，由實線圍繞的區域為In原子相對較多的區域，由虛線圍繞的區域為In原子相對較少的區域。在圖50C中，在由實線圍繞的區域內，右側是相對較亮的區域，左側是相對較暗的區域。因此，由實線圍繞的區域為以InX2 ZnY2 OZ2 或InOX1 等為主要成分的區域。 [0478] 另外，由實線圍繞的區域為Ga原子相對較少的區域，由虛線圍繞的區域為Ga原子相對較多的區域。在圖50C中，在由虛線圍繞的區域內，左上方的區域為相對較亮的區域，右下方的區域為相對較暗的區域。因此，由虛線圍繞的區域為以GaOX3 或GaX4 ZnY4 OZ4 等為主要成分的區域。 [0479] 如圖50A、圖50B及圖50C所示，In原子的分佈與Ga原子的分佈相比更均勻，以InOX1 為主要成分的區域看起來像是藉由以InX2 ZnY2 OZ2 為主要成分的區域互相連接的。如此，以InX2 ZnY2 OZ2 或InOX1 為主要成分的區域以雲狀展開形成。 [0480] 如此，可以將具有以GaOX3 等為主要成分的區域及以InX2 ZnY2 OZ2 或InOX1 為主要成分的區域不均勻地分佈而混合的構成的In-Ga-Zn氧化物稱為CAC-OS。 [0481] CAC-OS的結晶結構具有nc結構。在具有nc結構的CAC-OS的電子繞射圖案中，除了起因於包含單晶、多晶或CAAC結構的IGZO的亮點(斑點)以外，還出現多個亮點(斑點)。或者，該結晶結構定義為除了出現多個亮點(斑點)之外，還出現環狀的亮度高的區域。 [0482] 另外，如圖50A、圖50B及圖50C所示，以GaOX3 等為主要成分的區域及以InX2 ZnY2 OZ2 或InOX1 為主要成分的區域的尺寸為0.5nm以上且10nm以下或者1nm以上且3nm以下。在EDX面分析影像中，以各元素為主要成分的區域的直徑較佳為1nm以上且2nm以下。 [0483] 如上所述，CAC-OS的結構與金屬元素均勻地分佈的IGZO化合物不同，其具有與IGZO化合物不同的性質。換言之，CAC-OS具有以GaOX3 等為主要成分的區域及以InX2 ZnY2 OZ2 或InOX1 為主要成分的區域互相分離且以各元素為主要成分的區域為馬賽克狀的構成。 [0484] 在此，以InX2 ZnY2 OZ2 或InOX1 為主要成分的區域的導電性高於以GaOX3 等為主要成分的區域。換言之，當載子流過以InX2 ZnY2 OZ2 或InOX1 為主要成分的區域時，呈現氧化物半導體的導電性。因此，當以InX2 ZnY2 OZ2 或InOX1 為主要成分的區域在氧化物半導體中以雲狀分佈時，可以實現高場效移動率(m)。 [0485] 另一方面，以GaOX3 等為主要成分的區域的絕緣性高於以InX2 ZnY2 OZ2 或InOX1 為主要成分的區域。換言之，當以GaOX3 等為主要成分的區域在氧化物半導體中分佈時，可以抑制洩漏電流而實現良好的切換工作。 [0486] 因此，當將CAC-OS用於半導體元件時，藉由起因於GaOX3 等的絕緣性及起因於InX2 ZnY2 OZ2 或InOX1 的導電性的互補作用可以實現高通態電流(Ion )及高場效移動率(m)。 [0487] 另外，使用CAC-OS的半導體元件具有高可靠性。因此，CAC-OS適用於顯示器等各種半導體裝置。 [0488] 本實施方式的至少一部分可以與本說明書所記載的其他實施方式適當地組合而實施。 [0489] á具有金屬氧化物膜的電晶體ñ 下面，說明將上述金屬氧化物膜用於電晶體的情況。 [0490] 藉由將上述金屬氧化物膜用於電晶體可以實現載子移動率高且開關特性高的電晶體。另外，可以實現可靠性高的電晶體。 [0491] 另外，較佳為將載子密度低的金屬氧化物膜用於電晶體。例如，金屬氧化物膜的載子密度可以低於8´1011 /cm3 ，較佳為低於1´1011 /cm3 ，更佳為低於1´1010 /cm3 且為1´10-9 /cm3 以上。 [0492] 在降低金屬氧化物膜的載子密度的情況下，降低金屬氧化物膜中的雜質濃度而降低缺陷態密度。在本說明書等中，將雜質濃度低且缺陷態密度低的狀態稱為“高純度本質”或“實質上高純度本質”。因為高純度本質或實質上高純度本質的金屬氧化物膜的載子發生源較少，所以有可能降低載子密度。另外，因為高純度本質或實質上高純度本質的金屬氧化物膜具有較低的缺陷態密度，所以有可能具有較低的陷阱態密度。 [0493] 此外，被金屬氧化物膜的陷阱能階俘獲的電荷到消失需要較長的時間，有時像固定電荷那樣動作。因此，有時在陷阱態密度高的氧化物半導體中形成有通道區的電晶體的電特性不穩定。 [0494] 因此，為了使電晶體的電特性穩定，降低金屬氧化物膜中的雜質濃度是有效的。為了降低金屬氧化物膜中的雜質濃度，較佳為還降低附近膜中的雜質濃度。作為雜質有氫、氮、鹼金屬、鹼土金屬、鐵、鎳、矽等。 [0495] 在此，說明金屬氧化物膜中的各雜質的影響。 [0496] 在金屬氧化物膜包含第14族元素之一的矽或碳時，氧化物半導體中形成缺陷能階。因此，氧化物半導體中或氧化物半導體的介面附近的矽或碳的濃度(藉由二次離子質譜分析法(SIMS：Secondary Ion Mass Spectrometry)測得的濃度)為2´1018 atoms/cm3 以下，較佳為2´1017 atoms/cm3 以下。 [0497] 另外，當金屬氧化物膜包含鹼金屬或鹼土金屬時，有時形成缺陷能階而形成載子。因此，使用包含鹼金屬或鹼土金屬的金屬氧化物膜的電晶體容易具有常開啟特性。由此，較佳為降低金屬氧化物膜中的鹼金屬或鹼土金屬的濃度。明確而言，利用SIMS分析測得的金屬氧化物膜中的鹼金屬或鹼土金屬的濃度為1´1018 atoms/cm3 以下，較佳為2´1016 atoms/cm3 以下。 [0498] 當金屬氧化物膜包含氮時，產生作為載子的電子，並載子密度增加，而氧化物半導體容易被n型化。其結果是，將含有氮的氧化物半導體用於半導體的電晶體容易具有常開啟型特性。因此，較佳為儘可能地減少氧化物半導體中的氮，例如，利用SIMS分析測得的氧化物半導體中的氮濃度為小於5´1019 atoms/cm3 ，較佳為5´1018 atoms/cm3 以下，更佳為1´1018 atoms/cm3 以下，進一步較佳為5´1017 atoms/cm3 以下。 [0499] 包含在金屬氧化物膜中的氫與鍵合於金屬原子的氧起反應生成水，因此有時形成氧缺陷(Vo )。當氫進入該氧缺陷(Vo )時，有時產生作為載子的電子。另外，有時由於氫的一部分與鍵合於金屬原子的氧鍵合，產生作為載子的電子。因此，使用包含氫的氧化物半導體的電晶體容易具有常開啟特性。由此，較佳為儘可能減少氧化物半導體中的氫。明確而言，利用SIMS分析測得氧化物半導體中的氫濃度為低於1´1020 atoms/cm3 ，較佳為低於1´1019 atoms/cm3 ，更佳為低於5´1018 atoms/cm3 ，進一步較佳為低於1´1018 atoms/cm3 。 [0500] 藉由將氧引入金屬氧化物膜中，可以降低金屬氧化物膜中的氧缺陷(Vo )。換言之，當金屬氧化物膜中的氧缺陷(Vo )被氧填補時，氧缺陷(Vo )消失。因此，藉由使氧擴散到金屬氧化物膜中，可以減少電晶體的氧缺陷(Vo )，從而可以提高電晶體的可靠性。 [0501] 作為將氧引入金屬氧化物膜的方法，例如，可以以與氧化物半導體接觸的方式設置包含超過化學計量組成的氧的氧化物。也就是說，較佳為在上述氧化物中形成包含超過化學計量組成的氧的區域(以下，也稱為氧過量區域)。尤其是，當將金屬氧化物膜用於電晶體時，藉由對電晶體附近的基底膜或層間膜等設置具有氧過量區域的氧化物，可以降低電晶體的氧缺陷，由此可以提高電晶體的可靠性。 [0502] 藉由將雜質被充分降低的金屬氧化物膜用於電晶體的通道形成區，可以使電晶體具有穩定的電特性。 [0503] 本實施方式的至少一部分可以與本說明書所記載的其他實施方式適當地組合而實施。 [0504] 實施方式3 在本實施方式中，使用圖51至圖63說明包括前面的實施方式中例示出的電晶體的顯示裝置的一個例子。 [0505] 圖51是示出顯示裝置的一個例子的俯視圖。圖51所示的顯示裝置700包括：設置在第一基板701上的像素部702；設置在第一基板701上的源極驅動電路部704及閘極驅動電路部706；以圍繞像素部702、源極驅動電路部704及閘極驅動電路部706的方式設置的密封劑712；以及以與第一基板701對置的方式設置的第二基板705。注意，由密封劑712密封第一基板701及第二基板705。也就是說，像素部702、源極驅動電路部704及閘極驅動電路部706被第一基板701、密封劑712及第二基板705密封。注意，雖然在圖51中未圖示，但是在第一基板701與第二基板705之間設置有顯示元件。 [0506] 另外，在顯示裝置700中，在第一基板701上的不由密封劑712圍繞的區域中設置有分別電連接於像素部702、源極驅動電路部704及閘極驅動電路部706的FPC(Flexible printed circuit：軟性印刷電路板)端子部708。另外，FPC端子部708連接於FPC716，並且藉由FPC716對像素部702、源極驅動電路部704及閘極驅動電路部706供應各種信號等。另外，像素部702、源極驅動電路部704、閘極驅動電路部706以及FPC端子部708各與信號線710連接。由FPC716供應的各種信號等是藉由信號線710供應到像素部702、源極驅動電路部704、閘極驅動電路部706以及FPC端子部708的。 [0507] 另外，也可以在顯示裝置700中設置多個閘極驅動電路部706。另外，作為顯示裝置700，雖然示出將源極驅動電路部704及閘極驅動電路部706形成在與像素部702相同的第一基板701上的例子，但是並不侷限於該結構。例如，可以只將閘極驅動電路部706形成在第一基板701上，或者可以只將源極驅動電路部704形成在第一基板701上。此時，也可以採用將形成有源極驅動電路或閘極驅動電路等的基板(例如，由單晶半導體膜、多晶半導體膜形成的驅動電路基板)形成於第一基板701的結構。另外，對另行形成的驅動電路基板的連接方法沒有特別的限制，而可以採用COG(Chip On Glass：晶粒玻璃接合)方法、打線接合方法等。 [0508] 另外，顯示裝置700所包括的像素部702、源極驅動電路部704及閘極驅動電路部706包括多個電晶體，並可以應用本發明的一個實施方式的半導體裝置的電晶體。 [0509] 另外，顯示裝置700可以包括各種元件。作為該元件，例如可以舉出電致發光(EL)元件(包含有機物及無機物的EL元件、有機EL元件、無機EL元件、LED等)、發光電晶體元件(根據電流發光的電晶體)、電子發射元件、液晶元件、電子墨水元件、電泳元件、電濕潤(electrowetting)元件、電漿顯示面板(PDP)、MEMS(微機電系統)、顯示器(例如柵光閥(GLV)、數位微鏡裝置(DMD)、數位微快門(DMS)元件)、壓電陶瓷顯示器等。 [0510] 此外，作為使用EL元件的顯示裝置的一個例子，有EL顯示器等。作為使用電子發射元件的顯示裝置的一個例子，有場致發射顯示器(FED)或SED方式平面型顯示器(SED：Surface-conduction Electron-emitter Display，表面傳導電子發射顯示器)等。作為使用液晶元件的顯示裝置的一個例子，有液晶顯示器(透射式液晶顯示器、半透射式液晶顯示器、反射式液晶顯示器、直觀式液晶顯示器、投射式液晶顯示器)等。作為使用電子墨水元件或電泳元件的顯示裝置的一個例子，有電子紙等。注意，當實現半透射式液晶顯示器或反射式液晶顯示器時，使像素電極的一部分或全部具有反射電極的功能。例如，使像素電極的一部分或全部包含鋁、銀等。並且，此時也可以將SRAM等記憶體電路設置在反射電極下。由此，可以進一步降低功耗。 [0511] 作為顯示裝置700的顯示方式，可以採用逐行掃描方式或隔行掃描方式等。另外，作為當進行彩色顯示時在像素中控制的顏色要素，不侷限於RGB(R表示紅色，G表示綠色，B表示藍色)這三種顏色。例如，可以由R像素、G像素、B像素及W(白色)像素的四個像素構成。或者，如PenTile排列，也可以由RGB中的兩個顏色構成一個顏色要素，並根據顏色要素選擇不同的兩個顏色來構成。或者可以對RGB追加黃色(yellow)、青色(cyan)、洋紅色(magenta)等中的一種以上的顏色。另外，各個顏色要素的點的顯示區域的大小可以不同。但是，所公開的發明不侷限於彩色顯示的顯示裝置，而也可以應用於黑白顯示的顯示裝置。 [0512] 另外，為了將白色光(W)用於背光(有機EL元件、無機EL元件、LED、螢光燈等)使顯示裝置進行全彩色顯示，也可以使用彩色層(也稱為濾光片)。作為彩色層，例如可以適當地組合紅色(R)、綠色(G)、藍色(B)、黃色(Y)等而使用。藉由使用彩色層，可以與不使用彩色層的情況相比進一步提高顏色再現性。此時，也可以藉由設置包括彩色層的區域和不包括彩色層的區域，將不包括彩色層的區域中的白色光直接用於顯示。藉由部分地設置不包括彩色層的區域，在顯示明亮的影像時，有時可以減少彩色層所引起的亮度降低而減少功耗兩成至三成左右。但是，在使用有機EL元件或無機EL元件等自發光元件進行全彩色顯示時，也可以從具有各發光顏色的元件發射R、G、B、Y、W。藉由使用自發光元件，有時與使用彩色層的情況相比進一步減少功耗。 [0513] 此外，作為彩色化的方式，除了經過濾色片將來自上述白色光的發光的一部分轉換為紅色、綠色及藍色的方式(濾色片方式)之外，還可以使用分別使用紅色、綠色及藍色的發光的方式(三色方式)以及將藍色光的一部分轉換為紅色或綠色的方式(顏色轉換方式或量子點方式)。 [0514] 在本實施方式中，使用圖52至圖57說明作為顯示元件使用液晶元件及EL元件的結構。圖52至圖55是沿著圖51所示的點劃線Q-R的剖面圖，作為顯示元件使用液晶元件的結構。另外，圖56及圖57是沿著圖51所示的點劃線Q-R的剖面圖，作為顯示元件使用EL元件的結構。 [0515] 下面，首先說明圖52至圖57所示的共同部分，接著說明不同的部分。 [0516] á3-1.顯示裝置的共同部分的說明ñ 圖52至圖57所示的顯示裝置700包括：引線配線部711；像素部702；源極驅動電路部704；以及FPC端子部708。另外，引線配線部711包括信號線710。另外，像素部702包括電晶體750及電容器(未圖示)。另外，源極驅動電路部704包括電晶體752。 [0517] 電晶體750具有與上述電晶體200A同樣的結構。電晶體752具有與上述電晶體100A同樣的結構。電晶體750及電晶體752也可以具有使用上述實施方式所示的其他電晶體的結構。 [0518] 在本實施方式中使用的電晶體包括高度純化且氧缺陷的形成被抑制的金屬氧化物膜。該電晶體可以降低關態電流。因此，可以延長影像信號等電信號的保持時間，在供電狀態下也可以延長寫入間隔。因此，可以降低更新工作的頻率，由此可以發揮抑制功耗的效果。 [0519] 另外，在本實施方式中使用的電晶體能夠得到較高的場效移動率，因此能夠進行高速驅動。例如，藉由將這種能夠進行高速驅動的電晶體用於液晶顯示裝置，可以在同一基板上形成像素部的切換電晶體及用於驅動電路的驅動電晶體。也就是說，因為作為驅動電路不需要另行使用由矽晶圓等形成的半導體裝置，所以可以縮減半導體裝置的構件數。另外，在像素部中也可以藉由使用能夠進行高速驅動的電晶體提供高品質的影像。 [0520] 在圖52至圖57中示出像素部702所包括的電晶體750及源極驅動電路部704所包括的電晶體752使用相同的結構的電晶體的結構，但是不侷限於此。例如，像素部702及源極驅動電路部704也可以使用不同電晶體。明確而言，可以舉出像素部702使用交錯型電晶體，且源極驅動電路部704使用實施方式1所示的反交錯型電晶體的結構，或者像素部702使用實施方式1所示的反交錯型電晶體，且源極驅動電路部704使用交錯型電晶體的結構等。此外，也可以將上述源極驅動電路部704置換為閘極驅動電路部。 [0521] 信號線710與被用作電晶體750、752的源極電極及汲極電極的導電膜在同一製程中形成。例如，當使用包含銅元素的材料形成信號線710時，起因於佈線電阻的信號延遲等較少，而可以實現大螢幕的顯示。 [0522] 另外，FPC端子部708包括連接電極760、異方性導電膜780及FPC716。連接電極760與被用作電晶體750、752的源極電極及汲極電極的導電膜在同一製程中形成。另外，連接電極760與FPC716所包括的端子藉由異方性導電膜780電連接。 [0523] 另外，作為第一基板701及第二基板705，例如可以使用玻璃基板。另外，作為第一基板701及第二基板705，也可以使用具有撓性的基板。作為該具有撓性的基板，例如可以舉出塑膠基板等。 [0524] 另外，在第一基板701與第二基板705之間設置有結構體778。結構體778是藉由選擇性地對絕緣膜進行蝕刻而得到的柱狀間隔物，用來控制第一基板701與第二基板705之間的距離(液晶盒厚(cell gap))。另外，作為結構體778，也可以使用球狀間隔物。 [0525] 另外，在第二基板705一側，設置有被用作黑矩陣的遮光膜738、被用作濾色片的彩色膜736、與遮光膜738及彩色膜736接觸的絕緣膜734。 [0526] á3-2.使用液晶元件的顯示裝置的結構實例ñ 圖52及圖53所示的顯示裝置700包括液晶元件775。液晶元件775包括導電膜772、導電膜774及液晶層776。導電膜774設置在第二基板705一側並被用作相對電極。圖52及圖53所示的顯示裝置700可以藉由由施加到導電膜772與導電膜774之間的電壓改變液晶層776的配向狀態，由此控制光的透過及非透過而顯示影像。 [0527] 導電膜772電連接到電晶體750所具有的被用作源極電極及汲極電極的導電膜。導電膜772形成在電晶體750的閘極絕緣膜上並被用作像素電極，亦即顯示元件的一個電極。此外，導電膜772被用作反射電極。圖52及圖53所示的顯示裝置700是由導電膜772反射外光並經過彩色膜736進行顯示的所謂的反射型彩色液晶顯示裝置。 [0528] 另外，作為導電膜772，可以使用對可見光具有透光性的導電膜或對可見光具有反射性的導電膜。作為對可見光具有透光性的導電膜，例如，較佳為使用包含選自銦(In)、鋅(Zn)、錫(Sn)中的一種的材料。作為對可見光具有反射性的導電膜，例如，較佳為使用包含鋁或銀的材料。在本實施方式中，作為導電膜772使用對可見光具有反射性的導電膜。 [0529] 如圖52及圖53所示，絕緣膜770被用作平坦化膜。另外，在絕緣膜770上形成有導電膜772。 [0530] 此外，圖52及圖53所示的顯示裝置700示出反射型彩色液晶顯示裝置，但是不侷限於此。例如，作為導電膜772使用對可見光具有透光性的導電膜，可以實現透射型彩色液晶顯示裝置。另外，可以實現組合反射型彩色液晶顯示裝置和透射型彩色液晶顯示裝置的所謂的半透射型彩色液晶顯示裝置。 [0531] 在此，圖54及圖55示出透射型彩色液晶顯示裝置。圖54及圖55是沿著圖51所示的點劃線Q-R的剖面圖，且圖54及圖55示出作為顯示元件使用液晶元件的結構。此外，圖54及圖55所示的顯示裝置700是作為液晶元件的驅動方式使用水平電場方式(例如，FFS(Fringe Field Switching：邊緣電場切換)模式)的結構的一個例子。在圖54及圖55所示的結構的情況下，被用作像素電極的導電膜772上設置有絕緣膜773，絕緣膜773上設置有導電膜774。此時，導電膜774具有共用電極的功能，可以由隔著絕緣膜773在導電膜772與導電膜774之間產生的電場控制液晶層776的配向狀態。 [0532] 注意，雖然在圖52至圖55中未圖示，但是也可以分別在導電膜772和/或導電膜774的與液晶層776接觸的一側設置配向膜。此外，雖然在圖52至圖55中未圖示，但是也可以適當地設置偏振構件、相位差構件、抗反射構件等光學構件(光學基板)等。例如，也可以使用利用偏振基板及相位差基板的圓偏振。此外，作為光源，也可以使用背光、側光等。 [0533] 在作為顯示元件使用液晶元件的情況下，可以使用熱致液晶、低分子液晶、高分子液晶、高分子分散型液晶、鐵電液晶、反鐵電液晶等。這些液晶材料根據條件呈現出膽固醇相、層列相、立方相、手性向列相、均質相等。 [0534] 此外，在採用橫向電場方式的情況下，也可以使用不使用配向膜的呈現藍相的液晶。藍相是液晶相的一種，是指當使膽固醇型液晶的溫度上升時即將從膽固醇相轉變到均質相之前出現的相。因為藍相只在較窄的溫度範圍內出現，所以將其中混合了幾wt%以上的手性試劑的液晶組合物用於液晶層，以擴大溫度範圍。由於包含呈現藍相的液晶和手性試劑的液晶組成物的回應速度快，並且其具有光學各向同性。由此，包含呈現藍相的液晶和手性試劑的液晶組成物不需要配向處理。另外，因不需要設置配向膜而不需要摩擦處理，因此可以防止由於摩擦處理而引起的靜電破壞，由此可以降低製程中的液晶顯示裝置的不良和破損。此外，呈現藍相的液晶材料的視角依賴性小。 [0535] 另外，當作為顯示元件使用液晶元件時，可以使用：TN(Twisted Nematic：扭曲向列)模式、IPS(In-Plane-Switching：平面內切換)模式、FFS模式、ASM(Axially Symmetric aligned Micro-cell：軸對稱排列微單元)模式、OCB(Optical Compensated Birefringence：光學補償彎曲)模式、FLC(Ferroelectric Liquid Crystal：鐵電性液晶)模式以及AFLC(AntiFerroelectric Liquid Crystal：反鐵電性液晶)模式等。 [0536] 另外，顯示裝置700也可以使用常黑型液晶顯示裝置，例如採用垂直配向(VA)模式的透射型液晶顯示裝置。作為垂直配向模式，可以舉出幾個例子，例如可以使用MVA(Multi-Domain Vertical Alignment：多域垂直配向)模式、PVA(Patterned Vertical Alignment：垂直配向構型)模式、ASV(Advanced Super View：超視覺)模式等。 [0537] á3-3.使用發光元件的顯示裝置ñ 圖56及圖57所示的顯示裝置700包括發光元件782。發光元件782包括導電膜772、EL層786及導電膜788。圖56及圖57所示的顯示裝置700藉由使發光元件782所包括的EL層786發光，可以顯示影像。此外，EL層786包含有機化合物或量子點等無機化合物。 [0538] 作為可以用於有機化合物的材料，可以舉出螢光性材料或磷光性材料等。此外，作為可以用於量子點的材料，可以舉出膠狀量子點材料、合金型量子點材料、核殼(Core Shell)型量子點材料、核型量子點材料等。另外，也可以使用包含第12族與第16族、第13族與第15族或第14族與第16族的元素群的材料。或者，可以使用包含鎘(Cd)、硒(Se)、鋅(Zn)、硫(S)、磷(P)、銦(In)、碲(Te)、鉛(Pb)、鎵(Ga)、砷(As)、鋁(Al)等元素的量子點材料。 [0539] 在圖56及圖57所示的顯示裝置700中，在電晶體750上設置有絕緣膜730。絕緣膜730覆蓋導電膜772的一部分。發光元件782採用頂部發射結構。因此，導電膜788具有透光性且使EL層786發射的光透過。注意，雖然在本實施方式中例示出頂部發射結構，但是不侷限於此。例如，也可以應用於向導電膜772一側發射光的底部發射結構或向導電膜772一側及導電膜788一側的兩者發射光的雙面發射結構。 [0540] 另外，在與發光元件782重疊的位置上設置有彩色膜736，並在與絕緣膜730重疊的位置、引線配線部711及源極驅動電路部704中設置有遮光膜738。彩色膜736及遮光膜738也可以被絕緣膜覆蓋。由密封膜732填充發光元件782與彩色膜736之間。注意，雖然例示出在圖56所示的顯示裝置700中設置彩色膜736的結構，但是並不侷限於此。例如，在藉由分別塗佈來形成EL層786時，也可以採用不設置彩色膜736的結構。 [0541] 作為絕緣膜730，可以使用聚醯亞胺樹脂、丙烯酸樹脂、聚醯亞胺醯胺樹脂、苯并環丁烯樹脂、聚醯胺樹脂、環氧樹脂等具有耐熱性的有機材料。此外，也可以藉由層疊多個使用上述材料形成的絕緣膜形成絕緣膜730。 [0542] á3-4.在顯示裝置中設置輸入輸出裝置的結構實例ñ 另外，也可以在圖52至圖57所示的顯示裝置700中設置輸入輸出裝置。作為該輸入輸出裝置例如可以舉出觸控面板等。 [0543] 圖58至圖63示出對圖52至圖57所示的顯示裝置700設置觸控面板791的結構。 [0544] 圖58至圖63是在圖52至圖57所示的顯示裝置700中設置觸控面板791的剖面圖。 [0545] 首先，以下說明圖58至圖63所示的觸控面板791。 [0546] 圖58至圖63所示的觸控面板791是設置在基板705與彩色膜736之間的所謂的In-Cell型觸控面板。觸控面板791在形成彩色膜736之前形成在基板705一側即可。 [0547] 觸控面板791包括遮光膜738、絕緣膜792、電極793、電極794、絕緣膜795、電極796、絕緣膜797。例如，當手指或觸控筆等檢測物件靠近觸控面板時，可以檢測出電極793與電極794之間的相互電容的變化。 [0548] 此外，在圖58至圖63所示的電晶體750的上方示出電極793、電極794的交叉部。電極796藉由設置在絕緣膜795中的開口與夾住電極794的兩個電極793電連接。此外，在圖58至圖63中示出設置有電極796的區域設置在像素部702中的結構，但是不侷限於此，例如也可以形成在源極驅動電路部704中。 [0549] 電極793及電極794設置在與遮光膜738重疊的區域。此外，如圖62及圖63所示，電極793較佳為以不與發光元件782重疊的方式設置。此外，如圖58至及圖61所示，電極793較佳為以不與液晶元件775重疊的方式設置。換言之，電極793在與發光元件782及液晶元件775重疊的區域具有開口。也就是說，電極793具有網格形狀。藉由採用這種結構，電極793可以具有不遮斷發光元件782所發射的光的結構。或者，電極793也可以具有不遮斷透過液晶元件775的光的結構。因此，由於因配置觸控面板791而導致的亮度下降極少，所以可以實現可見度高且功耗得到降低的顯示裝置。此外，電極794也可以具有相同的結構。 [0550] 電極793及電極794由於不與發光元件782重疊，所以電極793及電極794可以使用可見光的穿透率低的金屬材料。或者，電極793及電極794由於不與液晶元件775重疊，所以電極793及電極794可以使用可見光的穿透率低的金屬材料。 [0551] 因此，與使用可見光的穿透率高的氧化物材料的電極相比，可以降低電極793及電極794的電阻，由此可以提高觸控面板的感測器靈敏度。 [0552] 例如，電極793、794、796也可以使用導電奈米線。該奈米線的直徑平均值可以為1nm以上且100nm以下，較佳為5nm以上且50nm以下，更佳為5nm以上且25nm以下。此外，作為上述奈米線可以使用Ag奈米線、Cu奈米線、Al奈米線等金屬奈米線或碳奈米管等。例如，在作為電極793、794、796中的任一個或全部使用Ag奈米線的情況下，能夠實現89%以上的可見光穿透率及40W/平方以上且100W/平方以下的片電阻值。 [0553] 雖然在圖58至圖63中示出In-Cell型觸控面板的結構，但是不侷限於此。例如，也可以採用形成在顯示裝置700上的所謂的On-Cell型觸控面板或貼合於顯示裝置700而使用的所謂的Out-Cell型觸控面板。 [0554] 如此，本發明的一個實施方式的顯示裝置可以與各種方式的觸控面板組合而使用。 [0555] 本實施方式的至少一部分可以與本說明書所記載的其他實施方式適當地組合而實施。 [0556] 實施方式4 在本實施方式中，參照圖64A、圖64B及圖64C說明包括本發明的一個實施方式的半導體裝置的顯示裝置。 [0557] á4.顯示裝置的電路結構ñ 圖64A所示的顯示裝置包括：具有顯示元件的像素的區域(以下稱為像素部502)；配置在像素部502的外側並具有用來驅動像素的電路的電路部(以下稱為驅動電路部504)；具有保護元件的功能的電路(以下稱為保護電路506)；以及端子部507。此外，也可以不設置保護電路506。 [0558] 驅動電路部504的一部分或全部與像素部502較佳為形成在同一基板上。由此，可以減少構件的數量及端子的數量。當驅動電路部504的一部分或全部與像素部502不形成在同一基板上時，驅動電路部504的一部分或全部可以藉由COG或TAB(Tape Automated Bonding：捲帶自動接合)安裝。 [0559] 像素部502包括用來驅動配置為X行(X為2以上的自然數)Y列(Y為2以上的自然數)的多個顯示元件的電路(以下稱為像素電路501)，驅動電路部504包括輸出用來選擇像素的信號(掃描信號)的電路(以下稱為閘極驅動器504a)以及供應用來驅動像素中的顯示元件的信號(資料信號)的電路(以下稱為源極驅動器504b)等驅動電路。 [0560] 閘極驅動器504a具有移位暫存器等。閘極驅動器504a藉由端子部507接收用來驅動移位暫存器的信號並輸出信號。例如，閘極驅動器504a被輸入啟動脈衝信號、時脈信號等並輸出脈衝信號。閘極驅動器504a具有控制被供應掃描信號的佈線(以下稱為掃描線GL_1至GL_X)的電位的功能。另外，也可以設置多個閘極驅動器504a，並藉由多個閘極驅動器504a各別控制掃描線GL_1至GL_X。或者，閘極驅動器504a具有供應初始化信號的功能。但是，不侷限於此，閘極驅動器504a也可以供應其他信號。 [0561] 源極驅動器504b具有移位暫存器等。源極驅動器504b藉由端子部507接收用來驅動移位暫存器的信號和從其中得出資料信號的信號(影像信號)。源極驅動器504b具有根據影像信號生成寫入到像素電路501的資料信號的功能。另外，源極驅動器504b具有依照由於啟動脈衝信號、時脈信號等的輸入產生的脈衝信號來控制資料信號的輸出的功能。另外，源極驅動器504b具有控制被供應資料信號的佈線(以下稱為資料線DL_1至DL_Y)的電位的功能。或者，源極驅動器504b具有供應初始化信號的功能。但是，不侷限於此，源極驅動器504b可以供應其他信號。 [0562] 源極驅動器504b例如使用多個類比開關等來構成。源極驅動器504b藉由依次使多個類比開關開啟而可以輸出對影像信號進行時間分割所得到的信號作為資料信號。此外，也可以使用移位暫存器等構成源極驅動器504b。 [0563] 脈衝信號及資料信號分別藉由被供應掃描信號的多個掃描線GL之一及被供應資料信號的多個資料線DL之一被輸入到多個像素電路501的每一個。另外，閘極驅動器504a控制多個像素電路501的每一個中的資料信號的寫入及保持。例如，脈衝信號藉由掃描線GL_m(m是X以下的自然數)從閘極驅動器504a被輸入到第m行第n列的像素電路501，資料信號根據掃描線GL_m的電位藉由資料線DL_n(n是Y以下的自然數)從源極驅動器504b被輸入到第m行第n列的像素電路501。 [0564] 圖64A所示的保護電路506例如連接於作為閘極驅動器504a和像素電路501之間的佈線的掃描線GL。或者，保護電路506連接於作為源極驅動器504b和像素電路501之間的佈線的資料線DL。或者，保護電路506可以連接於閘極驅動器504a和端子部507之間的佈線。或者，保護電路506可以連接於源極驅動器504b和端子部507之間的佈線。此外，端子部507是指設置有用來從外部的電路對顯示裝置輸入電力、控制信號及影像信號的端子的部分。 [0565] 保護電路506是在對與其連接的佈線供應一定範圍之外的電位時使該佈線與其他佈線之間導通的電路。 [0566] 如圖64A所示，藉由對像素部502和驅動電路部504設置保護電路506，可以提高顯示裝置對因ESD(Electro Static Discharge：靜電放電)等而產生的過電流的耐性。但是，保護電路506的結構不侷限於此，例如，也可以採用將閘極驅動器504a與保護電路506連接的結構或將源極驅動器504b與保護電路506連接的結構。或者，也可以採用將端子部507與保護電路506連接的結構。 [0567] 另外，雖然在圖64A中示出由閘極驅動器504a和源極驅動器504b形成驅動電路部504的例子，但不侷限於此。例如，也可以只形成閘極驅動器504a並安裝形成有另外準備的源極驅動電路的基板(例如，由單晶半導體膜或多晶半導體膜形成的驅動電路基板)。 [0568] 另外，圖64A所示的多個像素電路501例如可以採用圖64B所示的結構。 [0569] 圖64B所示的像素電路501包括液晶元件570、電晶體550以及電容器560。可以將前面的實施方式所示的電晶體用於電晶體550。 [0570] 根據像素電路501的規格適當地設定液晶元件570的一對電極中的一個的電位。根據被寫入的資料設定液晶元件570的配向狀態。此外，也可以對多個像素電路501的每一個所具有的液晶元件570的一對電極中的一個供應共用電位。此外，對一個行內的像素電路501所具有的液晶元件570的一對電極之一供應的電位可以不同於對另一行內的像素電路501所具有的液晶元件570的一對電極之一供應的電位。 [0571] 例如，作為包括液晶元件570的顯示裝置的驅動方法也可以使用如下模式：TN模式；STN模式；VA模式；ASM(Axially Symmetric aligned Micro-cell：軸對稱排列微單元)模式；OCB(Optically Compensated Birefringence：光學補償彎曲)模式；FLC(Ferroelectric Liquid Crystal：鐵電性液晶)模式；AFLC(Anti Ferroelectric Liquid Crystal：反鐵電性液晶)模式；MVA模式；PVA(Patterned Vertical Alignment：垂直配向構型)模式；IPS模式；FFS模式或TBA(Transverse Bend Alignment：橫向彎曲配向)模式等。另外，作為顯示裝置的驅動方法，除了上述驅動方法之外，還有ECB(Electrically Controlled Birefringence：電控雙折射)模式、PDLC(Polymer Dispersed Liquid Crystal：聚合物分散液晶)模式、PNLC(Polymer Network Liquid Crystal：聚合物網路液晶)模式、賓主模式等。但是，不侷限於此，作為液晶元件及其驅動方式可以使用各種液晶元件及驅動方式。 [0572] 在第m行第n列的像素電路501中，電晶體550的源極電極和汲極電極中的一個與資料線DL_n電連接，源極電極和汲極電極中的另一個與液晶元件570的一對電極中的另一個電極電連接。電晶體550的閘極電極與掃描線GL_m電連接。電晶體550具有藉由成為導通狀態或關閉狀態而對資料信號的資料的寫入進行控制的功能。 [0573] 電容器560的一對電極中的一個電極與被供應電位的佈線(以下，稱為電位供應線VL)電連接，另一個電極與液晶元件570的一對電極中的另一個電極電連接。此外，根據像素電路501的規格適當地設定電位供應線VL的電位。電容器560具有儲存被寫入的資料的儲存電容器的功能。 [0574] 例如，在包括圖64B所示的像素電路501的顯示裝置中，藉由圖64A所示的閘極驅動器504a依次選擇各行的像素電路501，並使電晶體550開啟而寫入資料信號。 [0575] 當電晶體550被關閉時，被寫入資料的像素電路501成為保持狀態。藉由按行依次進行上述步驟，可以顯示影像。 [0576] 圖64A所示的多個像素電路501例如可以採用圖64C所示的結構。 [0577] 圖64C所示的像素電路501包括電晶體552、554、電容器562以及發光元件572。可以將前面的實施方式所示的電晶體應用於電晶體552和/或電晶體554。 [0578] 電晶體552的源極電極和汲極電極中的一個電連接於被供應資料信號的佈線(以下，稱為信號線DL_n)。並且，電晶體552的閘極電極電連接於被供應閘極信號的佈線(以下，稱為掃描線GL_m)。 [0579] 電晶體552具有藉由成為導通狀態或關閉狀態而對資料信號的資料的寫入進行控制的功能。 [0580] 電容器562的一對電極中的一個電極電連接於被供應電位的佈線(以下，稱為電位供應線VL_a)，另一個電極電連接於電晶體552的源極電極和汲極電極中的另一個。 [0581] 電容器562具有儲存被寫入的資料的儲存電容器的功能。 [0582] 電晶體554的源極電極和汲極電極中的一個電連接於電位供應線VL_a。並且，電晶體554的閘極電極電連接於電晶體552的源極電極和汲極電極中的另一個。 [0583] 發光元件572的陽極和陰極中的一個電連接於電位供應線VL_b，另一個電連接於電晶體554的源極電極和汲極電極中的另一個。 [0584] 作為發光元件572，例如可以使用有機電致發光元件(也稱為有機EL元件)等。注意，發光元件572並不侷限於有機EL元件，也可以使用由無機材料構成的無機EL元件。 [0585] 此外，電位供應線VL_a和電位供應線VL_b中的一個被供應高電源電位VDD，另一個被供應低電源電位VSS。 [0586] 例如，在包括圖64C所示的像素電路501的顯示裝置中，藉由圖64A所示的閘極驅動器504a依次選擇各行的像素電路501，並使電晶體552開啟而寫入資料信號。 [0587] 當電晶體552被關閉時，被寫入資料的像素電路501成為保持狀態。並且，流過電晶體554的源極電極與汲極電極之間的電流量根據寫入的資料信號的電位被控制，發光元件572以對應於流過的電流量的亮度發光。藉由按行依次進行上述步驟，可以顯示影像。 [0588] 本實施方式的至少一部分可以與本說明書所記載的其他實施方式適當地組合而實施。 [0589] 實施方式5 圖65是示出顯示裝置800的結構實例的方塊圖。顯示裝置800包括顯示單元810、觸控感測器單元820、控制器IC815及主體840。另外，根據需要，也可以在顯示裝置800中設置光感測器843及開閉感測器844。顯示單元810包括像素部502、閘極驅動器504a及源極驅動器504b。 [0590] áá控制器ICññ 在圖65中，控制器IC815包括介面850、圖框記憶體851、解碼器852、感測器控制器853、控制器854、時脈生成電路855、影像處理部860、記憶體870、時序控制器873、暫存器875及觸控感測器控制器884。 [0591] 控制器IC815與主體840的通訊藉由介面850進行。影像資料、各種控制信號等從主體840發送到控制器IC815。此外，觸控感測器控制器884所取得的觸摸位置等資訊從控制器IC815發送到主體840。此外，控制器IC815所包括的每個電路根據主體840的規格、顯示裝置800的規格等適當地取捨。 [0592] 圖框記憶體851是用來儲存輸入到控制器IC815的影像資料的記憶體。當從主體840發送被壓縮的影像資料時，圖框記憶體851能夠儲存被壓縮的影像資料。解碼器852是使被壓縮的影像資料解壓縮的電路。當不需要使影像資料解壓縮時，解碼器852不進行處理。或者，也可以將解碼器852配置於圖框記憶體851與介面850之間。 [0593] 影像處理部860具有對影像資料進行各種影像處理的功能。例如，影像處理部860包括伽瑪校正電路861、調光電路862及調色電路863。 [0594] 另外，在作為顯示裝置800的顯示元件使用有機EL或LED等利用電流的流動發光的顯示元件的情況下，影像處理部860也可以包括校正電路864。在此情況下，源極驅動器504b較佳為包括檢測流過顯示元件的電流的電路。校正電路864具有根據從源極驅動器504b發送的信號調節顯示元件的亮度的功能。 [0595] 在影像處理部860中處理的影像資料經過記憶體870輸出到源極驅動器504b。記憶體870是暫時儲存影像資料的記憶體。源極驅動器504b具有處理被輸入的影像資料，且將該影像資料寫入到像素部502的源極線的功能。注意，對源極驅動器504b的個數沒有限制，根據像素部502的像素數設置即可。 [0596] 時序控制器873具有生成在源極驅動器504b、觸控感測器控制器884、閘極驅動器504a中使用的時序信號的功能。 [0597] 觸控感測器控制器884具有控制觸控感測器單元820的驅動電路的功能。包括從觸控感測器單元820讀出的觸摸資訊的信號被觸控感測器控制器884處理，藉由介面850發送到主體840。主體840生成反映觸摸資訊的影像資料而將其發送到控制器IC815。此外，也可以採用利用控制器IC815將觸摸資訊反映到影像資料的結構。 [0598] 時脈生成電路855具有生成在控制器IC815中使用的時脈信號的功能。控制器854具有對藉由介面850從主體840發送的各種控制信號進行處理，控制控制器IC815中的各種電路的功能。此外，控制器854具有控制對控制器IC815中的各種電路供應電源的功能。以下，將暫時停止對沒有使用的電路供應電源的技術稱為電源閘控。在圖65中，省略電源供應線。 [0599] 暫存器875儲存用於控制器IC815的工作的資料。暫存器875所儲存的資料有在影像處理部860進行校正處理時使用的參數、在時序控制器873生成各種時序信號的波形時使用的參數等。暫存器875具備由多個暫存器構成的掃描器鏈暫存器。 [0600] 感測器控制器853與光感測器843電連接。光感測器843檢測出光845而生成檢測信號。感測器控制器853根據檢測信號生成控制信號。感測器控制器853所生成的控制信號例如輸出到控制器854。 [0601] 影像處理部860可以根據使用光感測器843及感測器控制器853測定的光845的亮度調節像素的亮度。換言之，在光845的亮度低的環境下，藉由降低像素的亮度來減少刺眼且降低功耗。另外，在光845的亮度高的環境下，藉由提高像素的亮度來獲得可見性高的顯示品質。可以基於使用者所設定的亮度進行上述調整。將上述調整稱為調光或調光處理。另外，將進行該處理的電路稱為調光電路。 [0602] 另外，也可以使光感測器843及感測器控制器853具有測定光845的色調的功能來對色調進行校正。例如，在黃昏時的紅色的環境下，顯示裝置800的使用者的眼睛因顏色適應而看紅色時感覺為白色。在此情況下，產生顯示裝置800的顯示的顏色蒼白的感覺，因此藉由強調顯示裝置800的R(紅色)成分，可以進行色調校正。將上述校正稱為調色或調色處理。另外，將進行該處理的電路稱為調色電路。 [0603] 影像處理部860有時根據顯示裝置800的規格包括RGB-RGBW轉換電路等其他處理電路。RGB-RGBW轉換電路是具有將RGB(紅色、綠色、藍色)影像資料轉換為RGBW(紅色、綠色、藍色、白色)影像資料的功能的電路。就是說，當顯示裝置800包括RGBW四種顏色的像素時，藉由使用W(白色)像素顯示影像資料中的W(白色)成分，可以降低功耗。注意，在顯示裝置800包括RGBY(紅色、綠色、藍色、黃色)4個顏色的像素的情況下，例如可以使用RGB-RGBY轉換電路。 [0604] á參數ñ 伽瑪校正、調光、調色等影像校正處理相當於根據輸入影像資料X生成輸出校正資料Y的處理。在影像處理部860中使用的參數是用來將影像資料X轉換為校正資料Y的參數。 [0605] 參數的設定方式有表格方式、函數近似方式。在圖66A所示的表格方式中，將對於影像資料Xn的校正資料Yn作為參數儲存於表格中。在表格方式中，需要多個儲存對應於該表格的參數的暫存器，但是校正的彈性較高。另一方面，在可以在經驗上預先決定對於影像資料X的校正資料Y時，如圖66B所示，採用函數近似方式的結構是有效的。a1、a2、b2等是參數。這裡，示出在每個區域進行線性近似的方法，但是也可以採用以非線性函數近似的方法。在函數近似方式中，校正的彈性較低，但是儲存定義函數的參數的暫存器較少。 [0606] 在時序控制器873中使用的參數例如表示如圖66C所示那樣時序控制器873的生成信號對於基準信號成為“L”(或“H”)的時序。參數Ra(或Rb)表示對於基準信號成為“L”(或“H”)的時序相當於幾個時脈週期。 [0607] 上述用於校正的參數可以儲存於暫存器875中。此外，作為上述以外的能夠儲存於暫存器875中的參數有顯示裝置800的亮度、色調、節省能量設定(到顯示變暗或關閉顯示的時間)、觸控感測器控制器884的靈敏度等。 [0608] á電源閘控ñ 當從主體840發送的影像資料沒有變化時，控制器854可以對控制器IC815中的一部分的電路進行電源閘控。明確而言，例如，可以暫時停止區域890中的電路(圖框記憶體851、解碼器852、影像處理部860、記憶體870、時序控制器873、暫存器875)。此外，可以採用將示出影像資料沒有變化的控制信號從主體840發送到控制器IC815且在控制器854檢測出該控制信號時進行電源閘控的結構。 [0609] 當影像資料沒有變化時，例如，也可以藉由在控制器854中組裝計時器功能，根據使用計時器測量的時間決定再次開始對區域890中的電路供電的時序。 [0610] 除了區域890內的電路以外，還可以對源極驅動器504b進行上述電源閘控。 [0611] 在圖65的結構中，也可以將源極驅動器504b包括在控制器IC815中。換言之，也可以將源極驅動器504b及控制器IC815設置在同一晶片上。 [0612] 下面，對圖框記憶體851及暫存器875的具體電路結構實例進行說明。 [0613] á圖框記憶體851ñ 在圖67A中示出圖框記憶體851的結構實例。圖框記憶體851包括控制部902、單元陣列903、週邊電路908。週邊電路908包括感測放大器電路904、驅動器905、主放大器906、輸入輸出電路907。 [0614] 控制部902具有控制圖框記憶體851的功能。例如，控制部902控制驅動器905、主放大器906及輸入輸出電路907。 [0615] 驅動器905與多個佈線WL、CSEL電連接。驅動器905生成輸出到多個佈線WL、CSEL的信號。 [0616] 單元陣列903包括多個記憶單元909。記憶單元909與佈線WL、LBL(或LBLB)、BGL電連接。佈線WL是字線，佈線LBL、LBLB是局部位元線。在圖67A的例子中，單元陣列903的結構是折疊位元線方式，也可以是開放位元線方式。 [0617] 在圖67B中示出記憶單元909的結構實例。記憶單元909包括電晶體NW1、電容器CS1。記憶單元909具有與DRAM(動態隨機存取記憶體)的記憶單元相同的電路結構。這裡，電晶體NW1是包括背閘極的電晶體。電晶體NW1的背閘極與佈線BGL電連接。佈線BGL被輸入電壓Vbg_w1。 [0618] 電晶體NW1是OS電晶體。由於OS電晶體的關態電流極小，藉由由OS電晶體構成記憶單元909，可以抑制從電容器CS1洩漏電荷，所以可以降低圖框記憶體851的更新工作的頻率。此外，即使停止電源供應，圖框記憶體851也能夠長時間保持影像資料。此外，藉由使電壓Vbg_w1為負電壓，可以使電晶體NW1的臨界電壓向正電位一側漂移，且可以延長記憶單元909的保持時間。 [0619] 在此，“關態電流”是指在電晶體處於關閉狀態時流在源極和汲極之間的電流。在電晶體為n通道型的情況下，例如當臨界電壓為0V至2V左右時，可以將對於源極的閘極的電壓為負電壓時流在源極和汲極之間的電流稱為關態電流。另外，“關態電流極小”意味著例如每通道寬度1mm的關態電流為100zA(z：介，10-21 )以下的情況。由於關態電流越小越好，所以該標準化關態電流較佳為10zA/mm以下或者1zA/mm以下，更佳為10yA/mm(y：攸，10-24 )以下。 [0620] 由於單元陣列903所包括的多個記憶單元909的電晶體NW1是OS電晶體，所以其他電路的電晶體例如可以是形成在矽晶圓上的Si電晶體。由此，可以將單元陣列903層疊在感測放大器電路904上。因此，可以縮小圖框記憶體851的電路面積，由此實現控制器IC815的小型化。 [0621] 單元陣列903層疊在感測放大器電路904上。感測放大器電路904包括多個感測放大器SA。感測放大器SA與相鄰的佈線LBL、LBLB(局部位元線對)、佈線GBL、GBLB(全域位元線對)、多個佈線CSEL電連接。感測放大器SA具有放大佈線LBL與佈線LBLB的電位差的功能。 [0622] 在感測放大器電路904中，對四個佈線LBL設置有一個佈線GBL，對四個佈線LBLB設置有一個佈線GBLB，但是感測放大器電路904的結構不侷限於圖67A的結構實例。 [0623] 主放大器906與感測放大器電路904及輸入輸出電路907連接。主放大器906具有放大佈線GBL與佈線GBLB的電位差的功能。此外，可以省略主放大器906。 [0624] 輸入輸出電路907具有如下功能：將對應於寫入資料的電位輸出到佈線GBL及佈線GBLB或主放大器906；以及讀出佈線GBL及佈線GBLB的電位或主放大器906的輸出電位，將該電位作為資料輸出到外部。可以根據佈線CSEL的信號選擇讀出資料的感測放大器SA及寫入資料的感測放大器SA。因此，由於輸入輸出電路907不需要多工器等選擇電路，所以可以使電路結構簡化，可以縮小佔有面積。 [0625] á暫存器875ñ 圖68是示出暫存器875的結構實例的方塊圖。暫存器875包括掃描器鏈暫存器部875A及暫存器部875B。掃描器鏈暫存器部875A包括多個暫存器930。由多個暫存器930構成掃描器鏈暫存器。暫存器部875B包括多個暫存器931。 [0626] 暫存器930是即使停止供電，資料也不消失的非揮發性暫存器。由於暫存器930是非揮發性暫存器，所以暫存器930包括使用OS電晶體的保持電路。 [0627] 另一方面，暫存器931是揮發性暫存器。對暫存器931的電路結構沒有特別的限制，是能夠儲存資料的電路即可，也可以由閂鎖電路、正反器電路等構成。影像處理部860及時序控制器873存取暫存器部875B，從對應的暫存器931提取資料。或者，影像處理部860及時序控制器873根據從暫存器部875B供應的資料控制處理內容。 [0628] 當使儲存於暫存器875中的資料更新時，首先改變掃描器鏈暫存器部875A的資料。在改寫掃描器鏈暫存器部875A的各暫存器930的資料之後，將掃描器鏈暫存器部875A的各暫存器930的資料同時載入到暫存器部875B的各暫存器931中。 [0629] 由此，影像處理部860及時序控制器873等可以使用同時更新的資料進行各種處理。由於資料的更新保持同時性，可以實現控制器IC815的穩定工作。藉由設置掃描器鏈暫存器部875A及暫存器部875B，在影像處理部860及時序控制器873工作中也可以更新掃描器鏈暫存器部875A的資料。 [0630] 當進行控制器IC815的電源閘控時，在暫存器930中，在保持電路中儲存(保存)資料之後停止供電。在再次開始供電之後，將暫存器930的資料恢復(載入)到暫存器931中再次開始正常工作。此外，當儲存於暫存器930中的資料及儲存於暫存器931中的資料不一致時，較佳為在將暫存器931的資料儲存於暫存器930中之後，重新在暫存器930的保持電路中儲存資料。例如，在掃描器鏈暫存器部875A中插入更新資料時，產生資料不匹配。 [0631] 圖69示出暫存器930、暫存器931的電路結構實例。在圖69中示出掃描器鏈暫存器部875A的兩級暫存器930及對應於這些暫存器930的兩個暫存器931。暫存器930被輸入信號Scan In且輸出信號Scan Out。 [0632] 暫存器930包括保持電路947、選擇器948、正反器電路949。由選擇器948及正反器電路949構成掃描正反器電路。選擇器948被輸入信號SAVE1。 [0633] 保持電路947被輸入信號SAVE2、LOAD2。保持電路947包括電晶體T1至T6、電容器C4、C6。電晶體T1、T2是OS電晶體。電晶體T1、T2也可以是與記憶單元909的電晶體NW1(參照圖67B)同樣的包括背閘極的OS電晶體。 [0634] 由電晶體T1、T3、T4及電容器C4構成3電晶體型增益單元。同樣地，由電晶體T2、T5、T6及電容器C6構成3電晶體型增益單元。兩個增益單元儲存正反器電路949所保持的互補資料。由於電晶體T1、T2是OS電晶體，保持電路947即使停止供電也可以在長時間保持資料。在暫存器930中，電晶體T1、T2以外的電晶體可以由Si電晶體構成。 [0635] 保持電路947根據信號SAVE2儲存正反器電路949所保持的互補資料，根據信號LOAD2將所保持的資料載入到正反器電路949中。 [0636] 正反器電路949的輸入端子與選擇器948的輸出端子電連接，資料輸出端子與暫存器931的輸入端子電連接。正反器電路949包括反相器950至955、類比開關957、958。類比開關957、958的導通狀態被掃描時脈(記為Scan Clock)信號控制。正反器電路949不侷限於圖69的電路結構，可以使用各種正反器電路949。 [0637] 選擇器948的兩個輸入端子的一個與暫存器931的輸出端子電連接，另一個與上一級正反器電路949的輸出端子電連接。此外，對掃描器鏈暫存器部875A的第一級的選擇器948的輸入端子從暫存器875的外部輸入資料。 [0638] 暫存器931包括反相器961至963、時脈反相器964、類比開關965、緩衝器966。暫存器931根據信號LOAD1載入正反器電路949的資料。暫存器931的電晶體可以由Si電晶體構成。 [0639] áá工作例子ññ 關於顯示裝置800的控制器IC815及暫存器875的工作例子，分類為出貨前、包括顯示裝置800的電子裝置的啟動時以及正常工作時而進行說明。 [0640] á出貨前ñ 在出貨前，將有關顯示裝置800的規格等的參數儲存於暫存器875中。這些參數例如有像素數、觸控感測器數、時序控制器873用來生成各種時序信號波形的參數等。在影像處理部860包括校正電路864的情況下，將該校正資料作為參數儲存於暫存器875中。這些參數除了存儲在暫存器875中以外，也可以存儲在專用ROM中。 [0641] á啟動時ñ 在包括顯示裝置800的電子裝置的啟動時，將從主體840發送的使用者設定等的參數儲存於暫存器875中。這些參數例如有顯示的亮度或色調、觸控感測器的靈敏度、節省能量設定(到顯示變暗或關閉顯示的時間)、伽瑪校正的曲線或表格等。此外，在將該參數儲存於暫存器875中時，從控制器854對暫存器875發送掃描時脈信號及與該掃描時脈信號同步的相當於該參數的資料。 [0642] á正常工作ñ 正常工作可以分為顯示動態影像等的狀態、顯示靜態影像的狀態(能夠進行IDS驅動的狀態)及不進行顯示的狀態等。在顯示動態影像等的狀態下，影像處理部860及時序控制器873等工作，但是暫存器875的資料改變對掃描器鏈暫存器部875A進行，所以不影響到影像處理部860等。在改變掃描器鏈暫存器部875A的資料之後，藉由將掃描器鏈暫存器部875A的資料同時載入到暫存器部875B中，暫存器875的資料改變結束。此外，影像處理部860等的工作切換為對應於該資料的工作。 [0643] 在顯示靜態影像且能夠進行IDS驅動的狀態中，例如可以與區域890中的其他電路同樣地對暫存器875進行電源閘控。此時，在進行電源閘控之前，在掃描器鏈暫存器部875A所包括的暫存器930中根據信號SAVE2將正反器電路949所保持的互補資料儲存於保持電路947。 [0644] 在從電源閘控恢復時，根據信號LOAD2將保持電路947所保持的資料載入到正反器電路949中，根據信號LOAD1將正反器電路949的資料載入到暫存器931中。如此，與在電源閘控之前相同的狀態下暫存器875的資料是有效的。此外，即使處於電源閘控的狀態，在主體840要求暫存器875的參數改變時，可以解除暫存器875的電源閘控，改變參數。 [0645] 在不進行顯示的狀態下，例如，可以對區域890中的電路(包括暫存器875)進行電源閘控。此時，有時主體840也停止工作，但是由於圖框記憶體851及暫存器875是非揮發性，所以在從電源閘控恢復時，可以進行電源閘控之前的顯示(靜態影像)而不需要等待主體840的恢復。 [0646] 例如，在對折疊式資訊終端的顯示部使用顯示裝置800時，在藉由開閉感測器844的信號檢測出資訊終端被折疊且顯示裝置800的顯示面不被使用時，除了區域890中的電路以外可以對感測器控制器853及觸控感測器控制器884等進行電源閘控。 [0647] 在使資訊終端折疊時，有時根據主體840的規格，主體840停止工作。在主體840停止工作的狀態下，再次使資訊終端展開，由於圖框記憶體851及暫存器875是非揮發性，所以可以在從主體840發送影像資料、各種控制信號等之前顯示圖框記憶體851中的影像資料。 [0648] 如此，藉由在暫存器875中設置掃描器鏈暫存器部875A及暫存器部875B，對掃描器鏈暫存器部875A進行資料改變，可以順利地進行資料改變而不影響到影像處理部860及時序控制器873等。此外，掃描器鏈暫存器部875A的各暫存器930包括保持電路947，因此可以順利地轉移到電源閘控狀態以及從電源閘控狀態恢復。 [0649] 本實施方式可以與其他實施方式適當地組合而實施。 [0650] 實施方式6 在本實施方式中，參照圖70A至圖76D對包括本發明的一個實施方式的半導體裝置的顯示模組及電子裝置進行說明。 [0651] á6-1.顯示模組ñ 對可以使用本發明的一個實施方式製造的顯示模組進行說明。 [0652] 圖70A所示的顯示模組6000在上蓋6001與下蓋6002之間包括連接到FPC6005的顯示面板6006、框架6009、印刷電路板6010及電池6011。 [0653] 例如，可以將使用本發明的一個實施方式製造的顯示裝置用於顯示面板6006。由此，可以以高良率製造顯示模組。 [0654] 上蓋6001及下蓋6002可以根據顯示面板6006的尺寸適當地改變其形狀或尺寸。 [0655] 此外，也可以以與顯示面板6006重疊的方式設置觸控面板。觸控面板可以是電阻膜式觸控面板或靜電容量式觸控面板，並且能夠以與顯示面板6006重疊的方式被形成。此外，也可以使顯示面板6006具有觸控面板的功能而不設置觸控面板。 [0656] 框架6009除了具有保護顯示面板6006的功能以外還具有用來遮斷因印刷電路板6010的工作而產生的電磁波的電磁屏蔽的功能。此外，框架6009也可以具有散熱板的功能。 [0657] 印刷電路板6010具有電源電路以及用來輸出視訊信號及時脈信號的信號處理電路。作為對電源電路供應電力的電源，既可以採用外部的商業電源，又可以採用利用另行設置的電池6011的電源。當使用商業電源時，可以省略電池6011。 [0658] 此外，在顯示模組6000中還可以設置偏光板、相位差板、稜鏡片等構件。 [0659] 圖70B是具備光學觸控感測器的顯示模組6000的剖面示意圖。 [0660] 顯示模組6000包括設置在印刷電路板6010上的發光部6015及受光部6016。另外，由上蓋6001與下蓋6002圍繞的區域設置有一對導光部(導光部6017a、導光部6017b)。 [0661] 作為上蓋6001和下蓋6002例如可以使用塑膠。上蓋6001和下蓋6002的厚度可以為薄(例如0.5mm以上且5mm以下)。因此，可以使顯示模組6000的重量極輕。另外，可以用很少的材料製造上蓋6001和下蓋6002，因此可以降低製造成本。 [0662] 顯示面板6006隔著框架6009與印刷電路板6010、電池6011重疊。顯示面板6006及框架6009固定在導光部6017a、導光部6017b。 [0663] 從發光部6015發射的光6018經過導光部6017a、顯示面板6006的頂部及導光部6017b到達受光部6016。例如，當光6018被指頭或觸控筆等被檢測體阻擋時，可以檢測觸摸操作。 [0664] 例如，多個發光部6015沿著顯示面板6006的相鄰的兩個邊設置。多個受光部6016配置在與發光部6015對置的位置。由此，可以取得觸摸操作的位置的資訊。 [0665] 作為發光部6015例如可以使用LED元件等光源。尤其是，作為發光部6015，較佳為使用發射不被使用者看到且對使用者無害的紅外線的光源。 [0666] 作為受光部6016可以使用接收發光部6015所發射的光且將其轉換為電信號的光電元件。較佳為使用能夠接收紅外線的光電二極體。 [0667] 作為導光部6017a、導光部6017b可以使用至少透過光6018的構件。藉由使用導光部6017a及導光部6017b，可以將發光部6015及受光部6016配置在顯示面板6006中的下側，可以抑制外光到達受光部6016而導致觸控感測器的錯誤工作。尤其較佳為使用吸收可見光且透過紅外線的樹脂。由此，更有效地抑制觸控感測器的錯誤工作。 [0668] á6-2.電子裝置1ñ 圖71A至圖71E示出電子裝置的一個例子。 [0669] 圖71A是安裝有取景器8100的照相機8000的外觀圖。 [0670] 照相機8000包括外殼8001、顯示部8002、操作按鈕8003、快門按鈕8004等。另外，照相機8000安裝有可裝卸的鏡頭8006。 [0671] 在此，照相機8000具有能夠從外殼8001拆卸下鏡頭8006而交換的結構，鏡頭8006和外殼也可以被形成為一體。 [0672] 藉由按下快門按鈕8004，照相機8000可以進行成像。另外，顯示部8002被用作觸控面板，也可以藉由觸摸顯示部8002進行成像。 [0673] 照相機8000的外殼8001包括具有電極的嵌入器，除了可以與取景器8100連接以外，還可以與閃光燈裝置等連接。 [0674] 取景器8100包括外殼8101、顯示部8102以及按鈕8103等。 [0675] 外殼8101包括嵌合到照相機8000的嵌入器的嵌入器，可以將取景器8100安裝到照相機8000。另外，該嵌入器包括電極，可以將從照相機8000利用該電極接收的影像等顯示到顯示部8102上。 [0676] 按鈕8103被用作電源按鈕。藉由利用按鈕8103，可以切換顯示部8102的顯示或非顯示。 [0677] 本發明的一個實施方式的顯示裝置可以用於照相機8000的顯示部8002及取景器8100的顯示部8102。 [0678] 另外，在圖71A中，照相機8000與取景器8100是分開且可拆卸的電子裝置，但是也可以在照相機8000的外殼8001中內置有具備顯示裝置的取景器。 [0679] 圖71B是頭戴顯示器8200的外觀圖。 [0680] 頭戴顯示器8200包括安裝部8201、透鏡8202、主體8203、顯示部8204以及電纜8205等。另外，在安裝部8201中內置有電池8206。 [0681] 藉由電纜8205，將電力從電池8206供應到主體8203。主體8203具備無線接收器等，能夠將所接收的影像資料等的影像資訊顯示到顯示部8204上。另外，藉由利用設置在主體8203中的相機捕捉使用者的眼球及眼瞼的動作，並根據該資訊算出使用者的視點的座標，可以利用使用者的視點作為輸入方法。 [0682] 另外，也可以對安裝部8201的被使用者接觸的位置設置多個電極。主體8203也可以具有藉由檢測出根據使用者的眼球的動作而流過電極的電流，識別使用者的視點的功能。此外，主體8203可以具有藉由檢測出流過該電極的電流來監視使用者的脈搏的功能。安裝部8201可以具有溫度感測器、壓力感測器、加速度感測器等各種感測器，也可以具有將使用者的生物資訊顯示在顯示部8204上的功能。另外，主體8203也可以檢測出使用者的頭部的動作等，並與使用者的頭部的動作等同步地使顯示在顯示部8204上的影像變化。 [0683] 可以將本發明的一個實施方式的顯示裝置用於顯示部8204。 [0684] 圖71C、圖71D及圖71E是頭戴顯示器8300的外觀圖。頭戴顯示器8300包括外殼8301、顯示部8302、帶狀固定工具8304以及一對透鏡8305。 [0685] 使用者可以藉由透鏡8305看到顯示部8302上的顯示。較佳的是，彎曲配置顯示部8302。藉由彎曲配置顯示部8302，使用者可以感受高真實感。注意，在本實施方式中，例示出設置一個顯示部8302的結構，但是不侷限於此，例如也可以採用設置兩個顯示部8302的結構。此時，在將每個顯示部配置在使用者的每個眼睛一側時，可以進行利用視差的三維顯示等。 [0686] 可以將本發明的一個實施方式的顯示裝置用於顯示部8302。因為本發明的一個實施方式的顯示裝置具有極高的解析度，所以即使如圖71E那樣地使用透鏡8305放大，也可以不使使用者看到像素而可以顯示現實感更高的影像。 [0687] á6-3.電子裝置2ñ 接著，圖72A至圖72G示出與圖71A至圖71E所示的電子裝置不同的電子裝置的例子。 [0688] 圖72A至圖72G所示的電子裝置包括外殼9000、顯示部9001、揚聲器9003、操作鍵9005(包括電源開關或操作開關)、連接端子9006、感測器9007(該感測器具有測量如下因素的功能：力、位移、位置、速度、加速度、角速度、轉速、距離、光、液、磁、溫度、化學物質、聲音、時間、硬度、電場、電流、電壓、電力、輻射線、流量、濕度、傾斜度、振動、氣味或紅外線)、麥克風9008等。 [0689] 圖72A至圖72G所示的電子裝置具有各種功能。例如，可以具有如下功能：將各種資訊(靜態影像、動態影像、文字影像等)顯示在顯示部上的功能；觸控面板的功能；顯示日曆、日期或時間等的功能；藉由利用各種軟體(程式)控制處理的功能；進行無線通訊的功能；藉由利用無線通訊功能來連接到各種電腦網路的功能；藉由利用無線通訊功能，進行各種資料的發送或接收的功能；讀出儲存在存儲介質中的程式或資料來將其顯示在顯示部上的功能；等。注意，圖72A至圖72G所示的電子裝置可具有的功能不侷限於上述功能，而可以具有各種功能。另外，雖然在圖72A至圖72G中未圖示，但是電子裝置可以包括多個顯示部。此外，也可以在該電子裝置中設置照相機等而使其具有如下功能：拍攝靜態影像的功能；拍攝動態影像的功能；將所拍攝的影像儲存在存儲介質(外部存儲介質或內置於照相機的存儲介質)中的功能；將所拍攝的影像顯示在顯示部上的功能；等。 [0690] 本實施方式的至少一部分可以與本說明書所記載的其他實施方式適當地組合而實施。 [0691] 接著，對使用電子裝置的廣播系統進行說明。在此，尤其是對發送廣播信號的系統進行說明。 [0692] á廣播系統ñ 圖73為示意性地示出廣播系統的結構實例的方塊圖。廣播系統1500包括攝影機1510、發送器1511、電子裝置系統1501。電子裝置系統1501包括接收器1512及顯示裝置1513。攝影機1510包括影像感測器1520及影像處理器1521。發送器1511包括編碼器1522及調變器1523。 [0693] 接收器1512及顯示裝置1513由電子裝置系統1501所包括的天線、解調器、解碼器、邏輯電路、影像處理器及顯示器單元構成。明確而言，例如，接收器1512包括天線、解調器、解碼器及邏輯電路。顯示裝置1513包括影像處理器及顯示器單元。另外，解碼器及邏輯電路也可以不包括在接收器1512中，而包括在顯示裝置1513中。 [0694] 在攝影機1510能夠拍攝8K視頻的情況下，影像感測器1520包括能夠拍攝8K的彩色影像的像素數。例如，在一個像素由一個紅色(R)子像素、兩個綠色(G)子像素及一個藍色(B)子像素構成的情況下，影像感測器1520至少需要7680×4320×4[R、G+G、B]個像素，而在為4K攝影機的情況下，影像感測器1520的像素數至少為3840×2160×4，在為2K攝影機的情況下，像素數至少為1920×1080×4。 [0695] 影像感測器1520生成未加工的Raw資料1540。影像處理器1521對Raw資料1540進行影像處理(雜訊去除、插補處理等)並生成視頻資料1541。視頻資料1541被輸出到發送器1511。 [0696] 發送器1511對視頻資料1541進行處理來生成適合廣播頻帶的廣播信號1543(有時將廣播信號稱為載波)。編碼器1522對視頻資料1541進行處理來生成編過碼的資料1542。編碼器1522進行將視頻資料1541編碼的處理、對視頻資料1541附加廣播控制資料(例如，認證資料)的處理、加密處理以及加擾處理(用於展頻的資料排序處理)等。 [0697] 在圖73的廣播系統1500中，可以將半導體裝置用於編碼器1522。另外，可以組合專用IC或處理器(例如，GPU、CPU)等來構成編碼器1522。另外，也可以將編碼器1522集成在一個專用IC晶片。 [0698] 調變器1523藉由對編過碼的資料1542進行IQ調變(正交調幅)來生成並輸出廣播信號1543。廣播信號1543為具有I(同相)成分和Q(正交成分)成分的資料的複合信號。TV廣播電臺取得視頻資料1541並供應廣播信號1543。 [0699] 電子裝置系統1501所包括的接收器1512接收廣播信號1543。 [0700] 圖74示出包括其他的電子裝置系統的廣播系統1500A。 [0701] 廣播系統1500A包括攝影機1510、發送器1511、電子裝置系統1501A及影像生成裝置1530。電子裝置系統1501A包括接收器1512及顯示裝置1513。攝影機1510包括影像感測器1520及影像處理器1521。發送器1511包括編碼器1522A、編碼器1522B及調變器1523。 [0702] 接收器1512及顯示裝置1513由電子裝置系統1501A所包括的天線、解調器、解碼器、影像處理器及顯示器單元構成。明確而言，例如，接收器1512包括天線、解調器及解碼器，顯示裝置1513包括影像處理器及顯示器單元。另外，解碼器也可以不包括在接收器1512中，而包括在顯示裝置1513中。 [0703] 關於攝影機1510、攝影機1510所包括的影像感測器1520及影像處理器1521，參照上述說明。影像處理器1521生成視頻資料1541A。視頻資料1541A輸出到發送器1511。 [0704] 影像生成裝置1530是生成對影像處理器1521中生成的影像資料附加的文字、圖形、圖案等的影像資料的裝置。文字、圖形或圖案等的影像資料作為視頻資料1541B發送到發送器1511。 [0705] 發送器1511對視頻資料1541A及視頻資料1541B進行處理來生成適合廣播頻帶的廣播信號1543(有時將廣播信號稱為載波)。編碼器1522A對視頻資料1541A進行處理來生成編過碼的資料1542A。另外，編碼器1522B對視頻資料1541B進行處理來生成編過碼的資料1542B。編碼器1522A及編碼器1522B進行將視頻資料1541A及視頻資料1541B編碼的處理、對視頻資料1541A及視頻資料1541B附加廣播控制資料(例如，認證資料)的處理、加密處理以及加擾處理(用於展頻的資料排序處理)等。 [0706] 另外，廣播系統1500A也可以如圖73所示的廣播系統1500那樣由一個編碼器對視頻資料1541A及視頻資料1541B進行處理。 [0707] 編過碼的資料1542A及編過碼的資料1542B發送到調變器1523。調變器1523藉由對編過碼的資料1542A及編過碼的資料1542B進行IQ調變來生成並輸出廣播信號1543。廣播信號1543為具有I成分和Q成分的資料的複合信號。TV廣播電臺取得視頻資料1541並供應廣播信號1543。 [0708] 電子裝置系統1501A所包括的接收器1512接收廣播信號1543。 [0709] 圖75示意性地示出廣播系統中的資料傳輸。圖75示出從廣播電臺1561發送的電波(廣播信號)傳送到各家庭的電視機(TV)1560的路徑。TV1560具備接收器1512及顯示裝置1513。作為人造衛星1562，例如可以舉出CS衛星和BS衛星等。作為天線1564，例如可以舉出BS/110°CS天線和CS天線等。作為天線1565，例如可以舉出特高頻(UHF：Ultra High Frequency)天線等。 [0710] 電波1566A、1566B為衛星廣播信號。人造衛星1562在接收電波1566A後向地面發送電波1566B。各家庭藉由用天線1564接收電波1566B，就可以用TV1560收看衛星TV廣播。或者，其他的廣播電臺的天線接收電波1566B並用廣播電臺內的接收器將其加工為能藉由光纜傳輸的信號。廣播電臺利用光纜網發送廣播信號至各家庭的TV1560的輸入部。電波1567A、1567B為地面廣播信號。電波塔1563放大所接收的電波1567A並發送電波1567B。各家庭藉由用天線1565接收電波1567B，就可以用TV1560收看地面TV廣播。 [0711] 本實施方式的視頻傳輸系統不侷限於TV廣播系統。此外，所發送的視頻資料可以為動態影像資料，也可以為靜態影像資料。 [0712] 圖76A、圖76B、圖76C及圖76D示出接收器的方式的例子。TV1560可以由接收器接收廣播信號而將其顯示在TV1560上。圖76A示出將接收器1571設置在TV1560的外側的情況。另外，作為其他的例子，圖76B示出天線1564、1565與TV1560之間藉由無線裝置1572及無線裝置1573進行資料傳輸的情況。在此情況下，無線裝置1572或者無線裝置1573還具有接收器的功能。另外，TV1560也可以內置有無線裝置1573(參照圖76C)。 [0713] 接收器可以做成小到可隨身攜帶的尺寸。圖76D所示的接收器1574包括連接器部1575。在顯示裝置及資訊終端(例如，個人電腦、智慧手機、行動電話、平板終端等)等電子裝置具備可連接到連接器部1575的端子的情況下，可以用這些電子裝置收看衛星廣播或地面廣播。 [0714] 本實施方式的至少一部分可以與本說明書所記載的其他實施方式適當地組合而實施。[0029] Below, the implementation method is explained with reference to the drawings. Note that a person skilled in the art can easily understand the fact that the implementation method can be implemented in a variety of different forms, and its methods and details can be transformed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following implementation method. [0030] In the drawings, in order to facilitate clear explanation, the size, thickness of the layer or the area are sometimes exaggerated. Therefore, the present invention is not necessarily limited to the above-mentioned dimensions. In addition, in the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or values shown in the drawings. [0031] The ordinal numbers such as "first", "second", and "third" used in this specification are added to avoid confusion among components, not to limit the numbers. [0032] In this specification, for convenience, words such as "upper" and "lower" are used to indicate configurations to illustrate the positional relationship of components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words are not limited to those described in this specification and may be appropriately replaced according to the circumstances. [0033] In this specification, etc., a transistor refers to a component including at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and current can flow between the source and the drain through the channel region. Note that in this specification, etc., the channel region refers to a region where current mainly flows. [0034] In addition, in the case of using transistors with different polarities or when the direction of current changes during circuit operation, the functions of the source and the drain are sometimes interchanged. Therefore, in this specification, etc., the source and the drain can be interchanged. [0035] In this specification, etc., "electrically connected" includes the case of being connected by "an element having a certain electrical function." Here, "element having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between connection targets. For example, "element having a certain electrical function" includes not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions. [0036] In the present specification, etc., "parallel" refers to a state in which the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state in which the angle is greater than -5° and less than 5° is also included. In addition, "vertical" refers to a state in which the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state in which the angle is greater than 85° and less than 95° is also included. [0037] In addition, in the present specification, etc., "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film". In addition, for example, "insulating film" may be replaced with "insulating layer". [0038] In this specification, unless otherwise specified, off-state current refers to the drain current when the transistor is in an off state (also called a non-conducting state or a blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to a state in which the voltage Vgs between the gate and the source is lower than the critical voltage Vth, and in a p-channel transistor, the off state refers to a state in which the voltage Vgs between the gate and the source is higher than the critical voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to the drain current when the voltage Vgs between the gate and the source is lower than the critical voltage Vth. [0039] The off-state current of a transistor sometimes depends on Vgs. Therefore, "the off-state current of the transistor is less than 1" sometimes means that there is a value of Vgs that makes the off-state current of the transistor less than 1. The off-state current of a transistor sometimes refers to: the off-state when Vgs is a predetermined value; the off-state when Vgs is a value within a predetermined range; or the off-state when Vgs is a value that can obtain a sufficiently low off-state current, etc. [0040] As an example, consider an n-channel transistor whose critical voltage Vth is 0.5V and whose drain current is 1´10 when Vgs is 0.5V.-9 A, the drain current when Vgs is 0.1V is 1´10-13 A, the drain current when Vgs is -0.5V is 1´10-19 A, the drain current when Vgs is -0.8V is 1´10-twenty two A. At Vgs of -0.5V or in the range of -0.5V to -0.8V, the drain current of this transistor is 1´10-19 A, so the off-state current of the transistor is sometimes called 1´10-19 A or less. Due to the existence of the transistor, the drain current becomes 1´10-twenty two Vgs below A, so the off-state current of the transistor is sometimes called 1´10-twenty two A or less. [0041] In this specification, etc., the off-state current of a transistor having a channel width W is sometimes expressed as a current value per channel width W. In addition, the off-state current of a transistor having a channel width W is sometimes expressed as a current value per a predetermined channel width (e.g., 1 mm). In the latter case, the unit of the off-state current is sometimes expressed as a unit having the dimension of current/length (e.g., A/mm). [0042] The off-state current of a transistor sometimes depends on the temperature. In this specification, unless otherwise specified, the off-state current sometimes indicates the off-state current at room temperature, 60°C, 85°C, 95°C, or 125°C. Alternatively, it may refer to the off-state current at a temperature that ensures the reliability of a semiconductor device including the transistor or at a temperature at which a semiconductor device including the transistor is used (for example, any temperature between 5°C and 35°C). “The off-state current of the transistor is 1 or less” may refer to the existence of a Vgs value that makes the off-state current of the transistor 1 or less at room temperature, 60°C, 85°C, 95°C, 125°C, a temperature that ensures the reliability of a semiconductor device including the transistor or at a temperature at which a semiconductor device including the transistor is used (for example, any temperature between 5°C and 35°C). [0043] The off-state current of a transistor may depend on the voltage Vds between the drain and the source. In this specification, unless otherwise specified, the off-state current may refer to the off-state current when Vds is 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, the off-state current may refer to the off-state current at a Vds that guarantees the reliability of a semiconductor device or the like including the transistor or at a Vds used by a semiconductor device or the like including the transistor. “The off-state current of the transistor is less than 1” sometimes means: when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, a Vds that ensures the reliability of the semiconductor device including the transistor, or a Vds at which the semiconductor device including the transistor is used, there is a Vgs value that makes the off-state current of the transistor less than 1. [0044] In the above description of the off-state current, the drain can be referred to as the source. That is, the off-state current sometimes refers to the current flowing through the source when the transistor is in the off state. [0045] In this specification, etc., the off-state current is sometimes recorded as the leakage current. In this specification, etc., the off-state current sometimes refers to, for example, the current flowing between the source and the drain when the transistor is in the off state. [0046] In this specification, etc., the critical voltage of a transistor refers to the gate voltage (Vg) when a channel is formed in the transistor. Specifically, the critical voltage of a transistor sometimes refers to: in a curve (Vg-ÖId characteristic) plotted with the gate voltage (Vg) on the horizontal axis and the square root of the drain current (Id) on the vertical axis, the gate voltage (Vg) at the intersection of the straight line when the tangent with the maximum slope is extrapolated and the square root of the drain current (Id) is 0 (Id is 0A). Alternatively, the critical voltage of a transistor is sometimes given as the value of Id[A]´L[mm]/W[mm] when L is the channel length and W is the channel width.-9[A] Gate voltage (Vg). [0047] Note that in this specification, for example, when the conductivity is sufficiently low, sometimes even when it is expressed as a "semiconductor", it has the characteristics of an "insulator". In addition, the boundary between "semiconductor" and "insulator" is unclear, so it is sometimes impossible to accurately distinguish them. Therefore, sometimes the "semiconductor" described in this specification can be replaced by "insulator". Similarly, sometimes the "insulator" described in this specification can be replaced by "semiconductor". Or, sometimes the "insulator" described in this specification can be replaced by "semi-insulator". [0048] In addition, in this specification, for example, when the conductivity is sufficiently high, sometimes even when it is expressed as a "semiconductor", it has the characteristics of a "conductor". In addition, the boundary between "semiconductor" and "conductor" is unclear, so sometimes it is not possible to accurately distinguish them. Therefore, sometimes the "semiconductor" described in this specification can be replaced by "conductor". Similarly, sometimes the "conductor" described in this specification can be replaced by "semiconductor". [0049] Note that in this specification, impurities in a semiconductor refer to elements other than the main components that constitute the semiconductor film. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are included, DOS (Density of States) may be formed in the semiconductor, the carrier mobility may be reduced, or the crystallinity may be reduced. When the semiconductor includes an oxide semiconductor, as impurities that change the semiconductor characteristics, there are, for example, transition metals other than the first group elements, second group elements, thirteenth group elements, fourteenth group elements, fifteenth group elements or main components, and in particular, hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, sometimes, for example, oxygen defects are generated due to the mixing of impurities such as hydrogen. In addition, when the semiconductor is silicon, as impurities that change the semiconductor characteristics, there are, for example, oxygen, first group elements other than hydrogen, second group elements, thirteenth group elements, fifteenth group elements, etc. [0050] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide has at least one of an amplification function, a rectification function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide semiconductor), or it can be referred to as OS. In addition, an OS FET can be referred to as a transistor containing a metal oxide or an oxide semiconductor. [0051] In this specification, etc., a metal oxide containing nitrogen is sometimes referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen can also be referred to as a metal oxynitride (metal oxynitride). [0052] Embodiment 1 In this embodiment, a display device and a manufacturing method thereof according to an embodiment of the present invention are described with reference to FIGS. 1A to 46D. [0053] FIG. 1-1. Structural Example 1 of Display Device FIGS. 1A, 1B and 1C show cross-sectional views of a pixel portion and a transistor in a driving circuit included in a display device according to an embodiment of the present invention, and FIGS. 2A and 2B show top views thereof. [0054] A display device according to an embodiment of the present invention includes a transistor 100A, a transistor 200A, a capacitor 250A and a connecting portion 150A. [0055] FIG. 1A is a cross-sectional view of a transistor 200A and a capacitor 250A included in a pixel portion, and is equivalent to a cross-sectional view along dotted line X1-X2 of FIG. 2A. FIG. 1B is a cross-sectional view of a transistor 100A and a connecting portion 150A included in a driving circuit, and is equivalent to a cross-sectional view along a dotted line X3-X4 in FIG. 2B . FIG. 1C is a cross-sectional view of a transistor 100A included in a driving circuit, and is equivalent to a cross-sectional view along a dotted line Y1-Y2 in FIG. 2B . Note that in FIG. 2A and FIG. 2B , for the sake of convenience, a portion of the components of the transistor 100A, the transistor 200A, and the capacitor 250A (such as an insulating film used as a gate insulating film) is omitted. In addition, in each transistor, the dotted line X1-X2 direction is sometimes referred to as the channel length direction, and the dotted line Y1-Y2 direction is sometimes referred to as the channel width direction. Note that sometimes a part of the components is omitted in the top view of the transistor in the following as well as in FIG. 2A and FIG. 2B. [0056] As shown in FIG. 1A, the pixel portion includes a transistor 200A, a conductive film 220 used as a pixel electrode, and a capacitor 250A. The conductive film 220 used as a pixel electrode is electrically connected to the transistor 200A. [0057] The transistor 200A includes: a conductive film 204 on a substrate 102; an insulating film 106 on the substrate 102 and the conductive film 204; a metal oxide film 208 on the insulating film 106; a conductive film 212a on the metal oxide film 208; and a conductive film 212b on the metal oxide film 208. [0058] In transistor 200A, insulating film 106 is used as a gate insulating film. In addition, in transistor 200A, conductive film 204 is used as a gate electrode, conductive film 212a is used as a source electrode, and conductive film 212b is used as a drain electrode. [0059] In transistor 200A, the ends of conductive film 212a and conductive film 212b are located on the inner side of the end of metal oxide film 208. [0060] On the transistor 200A, specifically, the insulating film 114, the insulating film 116 on the insulating film 114, the insulating film 118 on the insulating film 116, and the insulating film 119 on the insulating film 118 are formed on the metal oxide film 208, the conductive film 212a, and the conductive film 212b. In the transistor 200A, the insulating film 114, the insulating film 116, and the insulating film 118 are used as protective insulating films of the transistor 200A. In addition, the insulating film 119 is used as a planarization film. [0061] The insulating film 114, the insulating film 116, the insulating film 118 and the insulating film 119 have an opening 242a in the area overlapping with the conductive film 212b. The conductive film 220 used as a pixel electrode is electrically connected to the conductive film 212b through the opening 242a. [0062] The transistor 200A is a so-called channel etching type transistor and has a single gate structure. [0063] The capacitor 250A is formed by the conductive film 213, the insulating film 106, the metal oxide film 228 and the conductive film 215a. The conductive film 213 used as a capacitor wiring is formed on the same plane as the conductive films 204, 104, and 113 in the same process. The conductive film 215a is formed on the same plane as the conductive films 212a, 212b, 112a, 112b, and 115a in the same process. [0064] In the capacitor 250A, the end of the conductive film 215a is located on the inner side of the end of the metal oxide film 228. [0065] The conductive film 220 used as a pixel electrode is formed on the insulating film 119. The conductive film 220 provided on the insulating film 119 used as a planarizing film also has high flatness. Since the conductive film 220 has high flatness, when the display device is a liquid crystal display device, poor alignment of the liquid crystal layer can be reduced. In addition, by using the insulating film 119, the distance between the conductive film 204 used as the gate wiring and the conductive film 220 and the distance between the conductive film 212a used as the signal line and the conductive film 220 can be expanded, thereby reducing the wiring delay. [0066] As shown in Figures 1B and 1C, the driving circuit includes a transistor 100A and a connecting portion 150A. [0067] In the transistor 100A, there are formed: a conductive film 104 on the substrate 102; an insulating film 106 on the substrate 102 and the conductive film 104; a metal oxide film 108 on the insulating film 106; a conductive film 112a on the metal oxide film 108; a conductive film 112b on the metal oxide film 108; an insulating film 114 on the metal oxide film 108, the conductive film 112a, and the conductive film 112b; an insulating film 116 on the insulating film 114; an insulating film 118 on the insulating film 116; and a conductive film 130a on the insulating film 118. [0068] In transistor 100A, insulating film 106 is used as a first gate insulating film, and insulating film 114, insulating film 116 and insulating film 118 are used as a second gate insulating film. In addition, in transistor 100A, conductive film 104 is used as a first gate electrode, and conductive film 130a is used as a second gate electrode. In addition, in transistor 100A, conductive film 112a is used as a source electrode, and conductive film 112b is used as a drain electrode. [0069] In transistor 100A, the ends of conductive film 112a and conductive film 112b are located on the inner side of the end of metal oxide film 108. [0070] In transistor 100A, specifically, insulating film 119 is formed on insulating film 118 and conductive film 130a. In transistor 100A, insulating film 119 is used as a planarization film. [0071] In transistor 100A, insulating film 106, insulating film 114, insulating film 116, insulating film 118, and insulating film 119 include opening 146a in a region overlapping with conductive film 104. In addition, insulating film 119 includes opening 148a in a region overlapping with conductive film 130a. The conductive film 120b used as the first wiring is electrically connected to the conductive film 130a and the conductive film 104 through the opening 146a and the opening 148a. By providing the conductive film 120b, the conductive film 104 used as the first gate electrode of the transistor 100A is electrically connected to the conductive film 130a used as the second gate electrode. [0072] The transistor 100A is a so-called channel etching type transistor having a double gate structure. [0073] As shown in FIG. 1B, the metal oxide film 108 of the transistor 100A is located at a position opposite to the conductive film 104 and the conductive film 130a, and is sandwiched between the two conductive films used as gate electrodes. The length of the conductive film 130a in the channel length direction and the length of the conductive film 130a in the channel width direction are respectively longer than the length of the metal oxide film 108 in the channel length direction and the length of the metal oxide film 108 in the channel width direction, and the conductive film 130a covers the entire metal oxide film 108 via the insulating film 114, the insulating film 116, and the insulating film 118. [0074] In other words, the conductive film 104 and the conductive film 130a are connected to each other through the openings formed in the insulating film 106, the insulating film 114, the insulating film 116, the insulating film 118, and the insulating film 119 and include a region located outside the side end of the metal oxide film 108. [0075] By adopting the above structure, the metal oxide film 108 included in the transistor 100A can be surrounded by the electric field of the conductive film 104 and the conductive film 130a. The device structure of the transistor in which the metal oxide film forming the channel region is surrounded by the electric field of the first gate electrode and the second gate electrode as in the transistor 100A can be called a surrounded channel (S-channel) structure. [0076] Since the transistor 100A has the S-channel structure, the electric field for inducing the channel can be effectively applied to the metal oxide film 108 using the conductive film 104 used as the first gate electrode, thereby improving the current driving capability of the transistor 100A and obtaining a high on-state current characteristic. In addition, since the on-state current can be increased, the transistor 100A can be miniaturized. In addition, since the metal oxide film 108 is surrounded by the conductive film 104 used as the first gate electrode and the conductive film 130a used as the second gate electrode, the mechanical strength of the transistor 100A can be improved. [0077] In addition, in the transistor 100A, the metal oxide film 108 includes: a metal oxide film 108_1 on the insulating film 106; and a metal oxide film 108_2 on the metal oxide film 108_1. In addition, in the transistor 200A, the metal oxide film 208 includes: a metal oxide film 208_1 on the insulating film 106; and a metal oxide film 208_2 on the metal oxide film 208_1. In addition, the metal oxide films 108_1, 108_2, 208_1, 208_2 all contain the same element. For example, the metal oxide films 108_1, 108_2, 208_1, 208_2 preferably independently contain In, M (M is gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, curium, titanium, iron, nickel, germanium, zirconium, molybdenum, ruthenium, neodymium, uranium, tungsten, or magnesium) and Zn. [0078] In addition, the metal oxide films 108_1, 108_2, 208_1, 208_2 preferably independently include a region in which the atomic number ratio of In is greater than the atomic number ratio of M. For example, it is preferable to set the atomic number ratio of In, M and Zn of the metal oxide films 108_1, 108_2, 208_1, 208_2 to In:M:Zn=4:2:3 or in the vicinity thereof. Here, "nearby" includes the case where, when In is 4, M is greater than 1.5 and less than 2.5, and Zn is greater than 2 and less than 4. Alternatively, it is preferable to set the atomic number ratio of In, M and Zn of the metal oxide films 108_1, 108_2, 208_1, 208_2 to In:M:Zn=5:1:6 or in the vicinity thereof. In this way, when the compositions of the metal oxide films 108_1, 108_2, 208_1, 208_2 are substantially the same, the same sputtering target can be used, so that the manufacturing cost can be suppressed. In addition, when the same sputtering target is used, the metal oxide films 108_1, 108_2, 208_1, and 208_2 can be formed continuously in the same processing chamber in a vacuum, so that the mixing of impurities into the interface between the metal oxide film 108_1 and the metal oxide film 108_2 and the interface between the metal oxide film 208_1 and the metal oxide film 208_2 can be suppressed. [0079] The metal oxide film 108_1, the metal oxide film 108_2, the metal oxide film 208_1, and the metal oxide film 208_2 are preferably metal oxides having a CAC (Cloud-Aligned Composite) structure. The metal oxide is described with reference to FIG. 47. [0080] FIG. 47 shows a schematic diagram of a metal oxide having a CAC structure. Note that in this specification, when the metal oxide of one embodiment of the present invention has a semiconductor function, it is defined as CAC-MO (Metal Oxide Semiconductor) or CAC-OS (Oxide Semiconductor). [0081] For example, as shown in FIG. 47, in CAC-MO or CAC-OS, the elements contained in the metal oxide are unevenly distributed, and regions 001 and 002 with each element as the main component are mixed or dispersed in a mosaic shape. In other words, CAC-OS is a structure in which the elements contained in the metal oxide are unevenly distributed, and the size of the material containing the unevenly distributed elements is greater than 0.5 nm and less than 10 nm, preferably greater than 1 nm and less than 2 nm or a size close thereto. Note that in the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed is also referred to as a mosaic or patch state, and the size of the region is greater than 0.5 nm and less than 10 nm, preferably greater than 1 nm and less than 2 nm or a size in the vicinity. [0082] In addition, CAC-MO or CAC-OS has a conductive function in a part of the material, an insulating function in another part of the material, and a semiconductor function as a whole. In addition, when CAC-MO or CAC-OS is used for a channel of a transistor, the conductive function is a function of allowing electrons (or holes) used as carriers to flow, and the insulating function is a function of preventing electrons used as carriers from flowing. By complementing the conductive function and the insulating function, CAC-MO or CAC-OS can have a switch function (open/close function). By separating each function in CAC-MO or CAC-OS, each function can be maximized. [0083] In this specification, CAC-MO or CAC-OS includes a conductive region and an insulating region. For example, one of the regions 001 and 002 shown in Figure 47 can be a conductive region, and the other can be an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In the material, the conductive region and the insulating region are sometimes separated at the nanoparticle level. In addition, the conductive regions and the insulating regions are sometimes distributed unevenly in the material. In addition, conductive regions whose edges are blurred and connected in a cloud shape are sometimes observed. [0084] CAC-MO or CAC-OS is composed of components with different band gaps. For example, CAC-MO or CAC-OS is composed of a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In this structure, when carriers are allowed to flow, the carriers mainly flow in the component with the narrow gap. In addition, the component with the narrow gap complements the component with the wide gap, and the carriers flow in the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the above-mentioned CAC-MO or CAC-OS is used in the channel region of the transistor, a high current driving force, that is, a large on-state current and a high field-effect mobility can be obtained in the on-state of the transistor. [0085] That is, CAC-MO or CAC-OS can also be referred to as a matrix composite material (matrix composite) or a metal matrix composite material (metal matrix composite). CAC-MO or CAC-OS will be described in detail in Implementation Method 2. [0086] By making the metal oxide films 108_1, 108_2, 208_1, 208_2 independently include a region in which the atomic number ratio of In is greater than the atomic number ratio of M and have a CAC structure, the field-effect mobility of the transistors 100A, 200A can be improved. Specifically, the field-effect mobility of transistors 100A and 200A can exceed 40cm2 /Vs, preferably more than 50cm2 /Vs, preferably more than 100cm2 /Vs. [0087] The transistor 100A having the S-Channel structure has a high field efficiency mobility and a high driving capability, so by using the transistor 100A in a driving circuit, typically a gate driver for generating a gate signal, a display device with a narrow frame width (also referred to as a narrow frame) can be provided. In addition, by using the transistor 100A in a source driver included in a display device for supplying a signal from a signal line (in particular, a demultiplexer connected to an output terminal of a shift register included in the source driver), a display device with a small number of wirings connected to the display device can be provided. [0088] In addition, since the transistors 100A and 200A are transistors of a channel etching structure, the number of processes is less than that of a transistor of a top gate structure. In addition, since the channels of the transistors 100A and 200A use a metal oxide film, the transistors 100A and 200A do not need the laser crystallization process required for transistors using low-temperature polysilicon. Therefore, even for a display device using a large-area substrate, the manufacturing cost can be reduced. Furthermore, in large-scale display devices with high resolutions such as Ultra High Definition ("4K resolution", "4K2K", "4K") and Super High Definition ("8K resolution", "8K4K", "8K"), transistors with high field efficiency such as transistors 100A and 200A are used in the drive circuit and display unit, so that writing in a short time and reduction of display defects can be achieved, which is preferable. [0089] The connecting portion 150A includes: a conductive film 113 used as a second wiring on the substrate 102; an opening 142a in the insulating film 106, the insulating film 114, the insulating film 116, the insulating film 118, and the insulating film 119 provided on the conductive film 113 used as the second wiring; a conductive film 115a used as a third wiring on the metal oxide film 128; and an opening 142a in the insulating film 119 provided on the conductive film 113 used as the second wiring. The conductive film 115a of the embodiment of the present invention is provided with an opening 144a in the insulating film 114, the insulating film 116, the insulating film 118 and the insulating film 119 on the conductive film 115a used as the wiring; and the conductive film 120a used as the fourth wiring is formed in a manner covering the opening 142a and the opening 144a and connecting the conductive film 113 used as the second wiring with the conductive film 115a used as the third wiring. In FIG. 1B, the opening 142a and the opening 144a are in a shape having one step, but may also be in a shape having more than two steps. [0090] In the connecting portion 150A, the end of the conductive film 115a is located on the inner side of the end of the metal oxide film 128. [0091] The conductive film 113 used as the second wiring is formed on the same plane in the same process as the conductive film 104 used as the first gate electrode of the transistor 100A. The conductive film 115a used as the third wiring is formed on the same plane in the same process as the conductive film 112a used as the source electrode of the transistor 100A and the conductive film 112b used as the drain electrode. The conductive film 120a used as the fourth wiring is formed on the same plane in the same process as the conductive film 220 used as the pixel electrode. [0092] In other words, the conductive film 113 used as the second wiring is formed using the same layer as the conductive film 104 used as the first gate electrode of the transistor 100A. The conductive film 115a used as the third wiring is formed using the same layer as the conductive film 112a used as the source electrode of the transistor 100A and the conductive film 112b used as the drain electrode. The conductive film 120a used as the fourth wiring is formed using the same layer as the conductive film 220 used as the pixel electrode. [0093] The conductive film 220 used as the pixel electrode, the conductive film 120b used as the first wiring, and the conductive film 120a used as the fourth wiring are formed in the same process. In other words, the conductive film 220 used as the pixel electrode, the conductive film 120b used as the first wiring, and the conductive film 120a used as the fourth wiring are formed using the same layer. In addition, the conductive film 220 used as a pixel electrode, the conductive film 120b used as a first wiring, and the conductive film 120a used as a fourth wiring are in contact with the top surface of the insulating film 119 used as a planarization film. [0094] á1-2. Components of the display deviceñ Next, the components included in the display device of the present embodiment are described in detail. [0095] [Substrate] Although there is no particular restriction on the material of the substrate 102, it is at least required to have heat resistance that can withstand subsequent heat treatment. For example, as the substrate 102, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. In addition, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium or the like, an SOI (Silicon On Insulator: silicon on an insulating layer) substrate, etc. can also be used, and the above-mentioned substrates provided with semiconductor elements can also be used as the substrate 102. When a glass substrate is used as the substrate 102, a large display device can be manufactured by using a large-area substrate of the sixth generation (1500mm´1850mm), the seventh generation (1870mm´2200mm), the eighth generation (2200mm´2400mm), the ninth generation (2400mm´2800mm), the tenth generation (2950mm´3400mm), etc. [0096] A flexible substrate may be used as the substrate 102, and the transistors 100A and 200A may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistors 100A and 200A. The peeling layer may be used in the following case, that is, a part or all of a semiconductor device is manufactured on the peeling layer, and then it is separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100A and 200A may also be transferred to a substrate with low heat resistance or a flexible substrate. [0097] [Conductive film] The conductive films 104 and 204 used as gate electrodes, the conductive films 112a and 212a used as source electrodes, and the conductive films 112b and 212b used as drain electrodes can be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co), an alloy containing the above metal elements, or an alloy combining the above metal elements. [0098] In addition, as the conductive films 104, 112a, 112b, 204, 212a, 212b, oxide conductors or oxide semiconductors such as oxides containing indium and tin (In-Sn oxide), oxides containing indium and tungsten (In-W oxide), oxides containing indium, tungsten and zinc (In-W-Zn oxide), oxides containing indium and titanium (In-Ti oxide), oxides containing indium, titanium and tin (In-Ti-Sn oxide), oxides containing indium and zinc (In-Zn oxide), oxides containing indium, tin and silicon (In-Sn-Si oxide), and oxides containing indium, gallium and zinc (In-Ga-Zn oxide) can be used. [0099] Here, oxide conductors are described. In this specification, etc., an oxide conductor may also be referred to as an OC (Oxide Conductor). For example, an oxygen defect is formed in an oxide semiconductor, and hydrogen is added to the oxygen defect to form a donor energy step near the conduction band. As a result, the conductivity of the oxide semiconductor increases, and it becomes a conductor. An oxide semiconductor that becomes a conductor can be referred to as an oxide conductor. In general, since metal oxides have a large energy gap, they are transparent to visible light. On the other hand, an oxide conductor is an oxide semiconductor that has a donor energy step near the conduction band. Therefore, in an oxide conductor, the effect of absorption due to the donor energy step is small, and the oxide conductor has approximately the same light transmittance to visible light as a metal oxide. [0100] The hydrogen concentration of the oxide conductor is higher than that of the metal oxide used as a channel (e.g., an oxide semiconductor), typically 8´1019 atoms/cm3 Above, preferably 1´1020 atoms/cm3 Above, preferably 5'1020 atoms/cm3 Above. [0101] An oxide conductor has electrical conductivity when it has defects and contains impurities. The resistivity of a conductive film containing an oxide conductor is 1´10-3 Wcm or more and less than 1´104 Wcm, the best is 1´10-3 Wcm or more and less than 1´10-1[0102] In addition, the conductivity of the conductive film preferably comprising an oxide conductor is typically 1´10-2 S/m or above and 1´105 S/m or less, or 1´103 S/m or above and 1´105 S/m or less. [0103] The oxide conductor contains impurities and defects. Typically, the conductive film containing the oxide conductor is a film in which defects are generated by adding a rare gas. Alternatively, the film in which defects are generated by exposure to plasma. [0104] In addition, a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta or Ti) can also be applied as the conductive film 104, 112a, 112b, 204, 212a, 212b. By using the Cu-X alloy film, it can be processed by a wet etching process, thereby suppressing the manufacturing cost. Since the resistance of the Cu-X alloy film is low, by using the Cu-X alloy film to form the conductive film 104, 112a, 112b, 204, 212a, 212b, the wiring delay can be suppressed. Therefore, it is preferable to use a Cu-X alloy film as wiring when manufacturing a large display device. [0105] In addition, the conductive films 112a, 112b, 212a, 212b are particularly preferably one or more of copper, titanium, tungsten, tantalum and molybdenum among the above-mentioned metal elements. In particular, as the conductive films 112a, 112b, 212a, 212b, it is preferable to use a tantalum nitride film. The tantalum nitride film has conductivity and has high barrier properties to copper or hydrogen. In addition, because the amount of hydrogen released from the tantalum nitride film is small, the tantalum nitride film is most suitable for use as a conductive film in contact with the metal oxide film 108, 208 or a conductive film near the metal oxide film 108, 208. In addition, when a copper film is used as the conductive film 112a, 112b, 212a, 212b, the resistance of the conductive film 112a, 112b, 212a, 212b can be reduced, so it is preferred. [0106] The conductive film 112a, 112b, 212a, 212b can be formed by an electroless plating method. As a material that can be formed by the electroless plating method, for example, one or more selected from Cu, Ni, Al, Au, Sn, Co, Ag and Pd can be used. In particular, when Cu or Ag is used, the resistance of the conductive film can be reduced, so it is preferred. [0107] [Insulating film used as gate insulating film] The insulating film 106 used as the gate insulating film of the transistors 100A and 200A can be formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like to form an insulating layer including one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a tantalum oxide film, a tantalum oxide film, and a neodymium oxide film. Note that the insulating film 106 may also have a stacked structure of two or more layers. [0108] In addition, preferably, the insulating film 106 in contact with the metal oxide film 108, 208 used as the channel region of the transistor 100A, 200A is an oxide insulating film, and more preferably, the oxide insulating film has a region (excess oxygen region) in which the oxygen content exceeds the stoichiometric composition. In other words, the insulating film 106 is capable of releasing oxygen. In order to form an excess oxygen region in the insulating film 106, for example, the insulating film 106 can be formed in an oxygen atmosphere or the insulating film 106 after film formation can be heat treated in an oxygen atmosphere. [0109] In addition, when the insulating film 106 uses tantalum oxide, the following effect is exerted. The relative dielectric constant of tantalum oxide is higher than that of silicon oxide or silicon oxynitride. Therefore, by using tantalum oxide, the thickness of the insulating film 106 can be increased compared to the case of using silicon oxide, thereby reducing the leakage current caused by the tunneling current. That is, a transistor with a small off-state current can be realized. Furthermore, compared with tantalum oxide having an amorphous structure, tantalum oxide having a crystalline structure has a high relative dielectric constant. Therefore, in order to form a transistor with a small off-state current, it is better to use tantalum oxide having a crystalline structure. As examples of crystalline structures, monoclinic system or cubic system, etc. can be cited. Note that an embodiment of the present invention is not limited to this. [0110] Note that, without being limited to the above structure, a nitride insulating film may be used as an insulating film in contact with the metal oxide films 108 and 208. For example, a structure in which a silicon nitride film is formed and the surface of the silicon nitride film is subjected to oxygen plasma treatment or the like to oxidize the surface of the silicon nitride film can be cited. Note that when the surface of the silicon nitride film is subjected to oxygen plasma treatment or the like, the surface of the silicon nitride film may be oxidized at the atomic level, so that the oxide film may not be observed by observing the cross section of the transistor or the like. In other words, when observing the cross section of the transistor, the silicon nitride film may be observed to be in contact with the metal oxide. [0111] Compared with silicon oxide film, silicon nitride film has a higher relative dielectric constant and a larger thickness is required to obtain an electrostatic capacitance equal to that of silicon oxide film. Therefore, by making the gate insulating film of the transistor include a silicon nitride film, the thickness of the insulating film can be increased. Therefore, electrostatic damage of the transistor can be suppressed by suppressing the decrease in the insulation withstand voltage of the transistor and improving the insulation withstand voltage. [0112] In the present embodiment, a stacked film of a silicon nitride film and a silicon oxide film is formed as the insulating film 106. [0113] [Metal oxide film] The above-mentioned materials can be used as the metal oxide films 108 and 208. [0114] When the metal oxide films 108 and 208 are In-M-Zn oxides, the atomic number ratio of the metal element of the sputtering target used to form the In-M-Zn oxide preferably satisfies In>M. Examples of the atomic number ratio of the metal element of such a sputtering target include In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, and the like. [0115] In addition, when the metal oxide films 108 and 208 are formed using In-M-Zn oxide, it is preferable to use a target containing polycrystalline In-M-Zn oxide as a sputtering target. By using a target containing polycrystalline In-M-Zn oxide, it is easy to form a crystalline metal oxide film 108 and 208. Note that the atomic number ratio of the formed metal oxide films 108 and 208 is respectively within the range of ±40% of the atomic number ratio of the metal element in the above-mentioned sputtering target. For example, when the composition of the sputtering target used for the metal oxide films 108 and 208 is In:Ga:Zn=4:2:4.1 [atomic number ratio], the composition of the formed metal oxide films 108 and 208 is sometimes In:Ga:Zn=4:2:3 [atomic number ratio] or its vicinity. [0116] The energy gap of the metal oxide films 108 and 208 is greater than 2 eV, preferably greater than 2.5 eV. In this way, by using an oxide semiconductor with a wider energy gap, the off-state current of the transistors 100A and 200A can be reduced. [0117] The metal oxide films 108 and 208 preferably have a non-single crystal structure. The non-single crystal structure includes, for example, the following CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor: c-axis aligned crystalline oxide semiconductor), a polycrystalline structure, a microcrystalline structure or an amorphous structure. Among the non-single crystal structures, the defect state density of the amorphous structure is the highest, while the defect state density of CAAC-OS is the lowest. [0118] Even if the metal oxide films 108_1, 108_2, 208_1, 208_2 independently include a region where the atomic number ratio of In is greater than the atomic number ratio of M, if the crystallinity of the metal oxide films 108_1, 108_2, 208_1, 208_2 is high, the field effect mobility may be reduced. [0119] Therefore, the metal oxide film 108_1 may include a region whose crystallinity is lower than that of the metal oxide film 108_2. The metal oxide film 208_1 may include a region whose crystallinity is lower than that of the metal oxide film 208_2. For example, the crystallinity of the metal oxide films 108_1, 108_2, 208_1, 208_2 can be analyzed using X-ray diffraction (XRD) or a transmission electron microscope (TEM). [0120] When the metal oxide film 108_1, 208_1 includes a region with low crystallinity, the following excellent effects are exerted. [0121] First, the oxygen defects that may be formed in the metal oxide film 108 are explained. [0122] In addition, the oxygen defects formed in the metal oxide film 108 have a negative impact on the transistor characteristics and cause problems. For example, when oxygen defects are formed in the metal oxide film 108, the oxygen defects bond with hydrogen and become a carrier supply source. When a carrier supply source is generated in the metal oxide film 108, the electrical characteristics of the transistor 100A having the metal oxide film 108 change, typically as a drift of the critical voltage. Therefore, in the metal oxide film 108, the fewer oxygen defects, the better. [0123] Therefore, in one embodiment of the present invention, the insulating film located near the metal oxide film 108, specifically, the insulating films 114 and 116 formed above the metal oxide film 108, contain excess oxygen. By moving oxygen or excess oxygen from the insulating films 114 and 116 to the metal oxide film 108, oxygen defects in the metal oxide film can be reduced. [0124] Here, the path of oxygen or excess oxygen diffused into the metal oxide film 108 is described with reference to Figures 45A and 45B. Figures 45A and 45B are schematic diagrams showing the diffusion path of oxygen or excess oxygen diffused into the metal oxide film 108, Figure 45A is a schematic diagram in the channel length direction, and Figure 45B is a schematic diagram in the channel width direction. Here, the metal oxide film 108 is used for explanation, but oxygen also diffuses in the metal oxide film 208 in the same manner as the metal oxide film 108. [0125] Oxygen or excess oxygen contained in the insulating films 114 and 116 diffuses into the metal oxide film 108_1 from above, that is, through the metal oxide film 108_2 (Route 1 shown in FIGS. 45A and 45B). [0126] Alternatively, oxygen or excess oxygen contained in the insulating films 114 and 116 diffuses into the metal oxide film 108 from the side surfaces of the metal oxide film 108_1 and the metal oxide film 108_2 (Route 2 shown in FIG. 45B). [0127] For example, in Route 1 shown in FIGS. 45A and 45B, when the crystallinity of the metal oxide film 108_2 is high, the diffusion of oxygen or excess oxygen is sometimes hindered. On the other hand, in Route 2 shown in FIG. 45B, oxygen or excess oxygen can be diffused from the sides of the metal oxide film 108_1 and the metal oxide film 108_2 into the metal oxide film 108_1 and the metal oxide film 108_2. [0128] Furthermore, in Route 2 shown in FIG. 45B, when the metal oxide film 108_1 includes a region whose crystallinity is lower than that of the metal oxide film 108_2, the region becomes a diffusion path for excess oxygen, and the excess oxygen can be diffused into the metal oxide film 108_2 whose crystallinity is higher than that of the metal oxide film 108_1. In addition, although not shown in FIGS. 45A and 45B , in the case where the insulating film 106 contains oxygen or excess oxygen, the oxygen or excess oxygen may diffuse from the insulating film 106 into the metal oxide film 108. [0129] In this way, by adopting a stacked structure of metal oxide films with different crystallinities and using a region with low crystallinity as a diffusion path for excess oxygen, a transistor with high reliability can be provided. [0130] In addition, in the case where the metal oxide film 108 is constituted using only a metal oxide film with low crystallinity, impurities (e.g., hydrogen or moisture) adhere to or mix into the back channel side, that is, in a region corresponding to the metal oxide film 108_2, sometimes resulting in a decrease in reliability. [0131] Impurities such as hydrogen or water mixed into the metal oxide film 108 have a negative impact on the transistor characteristics, so they become a problem. Therefore, the less impurities such as hydrogen or water in the metal oxide film 108, the better. [0132] Therefore, by improving the crystallinity of the metal oxide film on the upper layer of the metal oxide film 108, impurities that may be mixed into the metal oxide film 108 can be suppressed. In particular, by improving the crystallinity of the metal oxide film 108_2, damage when processing the conductive films 112a and 112b can be suppressed. When processing the conductive films 112a and 112b, the surface of the metal oxide film 108, that is, the surface of the metal oxide film 108_2 is exposed to the etchant or etching gas. When the metal oxide film 108_2 includes a region with high crystallinity, its etching resistance is higher than that of the metal oxide film 108_1 with low crystallinity. Therefore, the metal oxide film 108_2 is used as an etching stop film. [0133] By using a metal oxide film with low impurity concentration and low defect state density as the metal oxide film 108, a transistor with excellent electrical characteristics can be manufactured, so it is preferred. Here, the state of low impurity concentration and low defect state density (few oxygen defects) is referred to as "high purity nature" or "substantially high purity nature". As impurities in the metal oxide film, water, hydrogen, etc. can be typically cited. In this specification, etc., the process of reducing or removing water and hydrogen in the metal oxide film is sometimes referred to as dehydration or dehydrogenation. In addition, the process of adding oxygen to a metal oxide film or an oxide insulating film is sometimes referred to as overoxidation, and the state in which the overoxidation occurs and contains oxygen exceeding the stoichiometric composition is sometimes referred to as an overoxidation state. [0134] Because the metal oxide film of a high purity nature or a substantially high purity nature has fewer carrier generation sources, the carrier density can be reduced. Therefore, a transistor having a channel region formed in the metal oxide film rarely has an electrical characteristic of a negative critical voltage (also referred to as a normally-on characteristic). Because the metal oxide film of a high purity nature or a substantially high purity nature has a lower defect state density, it is possible to have a lower trap state density. The off-state current of the metal oxide film of a high purity nature or a substantially high purity nature is significantly small, even when the channel width is 1´106 mm, and the channel length L is 10mm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, the off-state current can also be below the measurement limit of the semiconductor parameter analyzer, that is, 1´10-13 A or less. [0135] In addition, when the metal oxide film 108_1 has a region whose crystallinity is lower than that of the metal oxide film 108_2, the carrier density is sometimes improved. [0136] In addition, when the carrier density of the metal oxide film 108_1 is high, the Fermi level is sometimes relatively higher than the conduction band of the metal oxide film 108_1. As a result, the conduction band bottom of the metal oxide film 108_1 becomes lower, and the energy difference between the conduction band bottom of the metal oxide film 108_1 and the trap level that may be formed in the gate insulating film (here, the insulating film 106) sometimes becomes larger. When this energy difference becomes larger, the charge trapped in the gate insulating film becomes less, and the critical voltage variation of the transistor can sometimes be reduced. In addition, when the carrier density of the metal oxide film 108_1 is improved, the field effect mobility of the metal oxide film 108 can be improved. [0137] [Insulating film used as protective insulating film 1] The insulating films 114 and 116 are used as protective insulating films of the transistors 100A and 200A. In addition, the insulating films 114 and 116 have the function of supplying oxygen to the metal oxide films 108 and 208. That is, the insulating films 114 and 116 contain oxygen. In addition, the insulating film 114 is an insulating film that allows oxygen to pass through. Note that the insulating film 114 is also used as a film that alleviates damage to the metal oxide films 108 and 208 when the insulating film 116 is formed later. [0138] As the insulating film 114, a silicon oxide film, a silicon oxynitride film, etc. having a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm, can be used. [0139] In addition, it is preferred to reduce the amount of defects in the insulating film 114. Typically, the spin density of the signal caused by the silicon dangling bond and appearing at g=2.001 measured by electron spin resonance (ESR) is preferably 3´1017 spins/cm3 Below. If the defect density of the insulating film 114 is high, oxygen bonds with the defect, thereby reducing the oxygen permeability in the insulating film 114. [0140] In the insulating film 114, sometimes the oxygen entering the insulating film 114 from the outside does not all move to the outside of the insulating film 114, but a part of it remains inside the insulating film 114. In addition, sometimes when oxygen enters the insulating film 114 from the outside, the oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, thereby causing oxygen migration in the insulating film 114. When an oxide insulating film that allows oxygen to pass through is formed as the insulating film 114, oxygen separated from the insulating film 116 provided on the insulating film 114 can be moved to the metal oxide films 108 and 208 through the insulating film 114. [0141] In addition, the insulating film 114 can be formed using an oxide insulating film having a low state density due to nitrogen oxides. Note that the state density due to nitrogen oxides may be formed at the energy (E) at the top of the valence band of the metal oxide film.V _OS ) and the energy of the conduction band bottom of the metal oxide film (EC _OS ). As the above-mentioned oxide insulating film, an oxynitride silicon film with a small amount of nitrogen oxide release or an oxynitride aluminum film with a small amount of nitrogen oxide release can be used. [0142] In addition, in thermal desorption spectroscopy (TDS: Thermal Desorption Spectroscopy), an oxynitride silicon film with a small amount of nitrogen oxide release is a film that releases more ammonia than nitrogen oxide, and typically the amount of ammonia released is 1´1018 Molecules/cm3 Above and 5´1019 Molecules/cm3 Below. Note that the ammonia release is the release amount when the membrane surface temperature is heated to a temperature of 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. [0143] Nitrogen oxides (NOx , x is greater than 0 and less than 2, preferably greater than 1 and less than 2), typically NO2 Or NO forms an energy level in the insulating film 114, etc. This energy level is located in the energy gap of the metal oxide films 108, 208. Therefore, when the nitrogen oxide diffuses to the interface between the insulating film 114 and the metal oxide films 108, 208, this energy level sometimes captures electrons on the insulating film 114 side. As a result, the captured electrons remain near the interface between the insulating film 114 and the metal oxide films 108, 208, thereby causing the critical voltage of the transistor to drift in the positive direction. [0144] In addition, when heat treatment is performed, the nitrogen oxide reacts with ammonia and oxygen. When the heat treatment is performed, the nitrogen oxide contained in the insulating film 114 reacts with the ammonia contained in the insulating film 116, thereby reducing the nitrogen oxide contained in the insulating film 114. Therefore, it is not easy to capture electrons at the interface between the insulating film 114 and the metal oxide films 108 and 208. [0145] By using the above-mentioned oxide insulating film as the insulating film 114, the drift of the critical voltage of the transistor can be reduced, thereby reducing the variation of the electrical characteristics of the transistor. [0146] In addition, the nitrogen concentration of the above-mentioned oxide insulating film measured by SIMS is 6´1020 atoms/cm3 or less. [0147] By forming the oxide insulating film by a PECVD method using silane and nitrous oxide at a substrate temperature of 220°C or more and 350°C or less, a dense and hard film can be formed. [0148] The insulating film 116 is an oxide insulating film having an oxygen content exceeding the stoichiometric composition. The oxide insulating film is heated to release a portion of oxygen. In addition, in TDS, the oxide insulating film includes an oxygen release amount of 1.0´1019 atoms/cm3 Above, preferably 3.0´1020 atoms/cm3 or the region above. Note that the above oxygen release amount is the total amount of oxygen released within the range of 50°C to 650°C or 50°C to 550°C during the heat treatment in TDS. In addition, the above oxygen release amount is the total amount converted to oxygen atoms in TDS. [0149] As the insulating film 116, a silicon oxide film, an oxynitride silicon film, etc. with a thickness of 30nm to 500nm, preferably 50nm to 400nm, can be used. [0150] In addition, it is preferred to reduce the amount of defects in the insulating film 116. Typically, the spin density of the signal caused by silicon dangling bonds and appearing at g=2.001 measured by ESR is less than 1.5´1018 spins/cm3 , preferably 1´1018 spins/cm3 Since the insulating film 116 is farther from the metal oxide film 108, 208 than the insulating film 114, the defect density of the insulating film 116 may be higher than that of the insulating film 114. [0151] In addition, since the insulating films 114 and 116 can be formed using the same type of material, it is sometimes impossible to clearly confirm the interface between the insulating film 114 and the insulating film 116. Therefore, in this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a dotted line. Note that although the insulating film 114 and the insulating film 116 have a two-layer structure in the present embodiment, the present invention is not limited thereto, and for example, the insulating film 114 may have a single-layer structure or a stacked structure of three or more layers. [0152] [Insulating film 2 used as a protective insulating film] The insulating film 118 is used as a protective insulating film for the transistors 100A and 200A. [0153] The insulating film 118 contains hydrogen and/or nitrogen. Alternatively, the insulating film 118 contains nitrogen and silicon. The insulating film 118 has a function of blocking oxygen, hydrogen, water, alkali metals, alkali earth metals, and the like. By providing the insulating film 118, it is possible to prevent oxygen from diffusing from the metal oxide films 108 and 208 to the outside and to prevent oxygen contained in the insulating films 114 and 116 from diffusing to the outside, and it is also possible to suppress hydrogen, water, etc. from invading the metal oxide films 108 and 208 from the outside. [0154] As the insulating film 118, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride film, silicon oxynitride film, aluminum nitride film, aluminum oxynitride film, and the like. [0155] Although the various films such as the conductive film, insulating film, metal oxide film and metal film described above can be formed by a sputtering method or a PECVD method, they can also be formed by other methods, such as a thermal CVD (Chemical Vapor Deposition) method. Examples of the thermal CVD method include the MOCVD (Metal Organic Chemical Vapor Deposition) method and the ALD (Atomic Layer Deposition) method. [0156] Since the thermal CVD method is a film forming method that does not use plasma, it has the advantage of not causing defects caused by plasma damage. In addition, the thermal CVD method can be performed in the following manner: a source gas is supplied into a processing chamber, and the pressure in the processing chamber is set to atmospheric pressure or reduced pressure to deposit a film on a substrate. [0157] In addition, the ALD method can be performed in the following manner: a source gas is supplied into a processing chamber, and the pressure in the processing chamber is set to atmospheric pressure or reduced pressure to deposit a film on a substrate. [0158] á1-3. Structural example of a display device 2ñ Figures 3A, 3B, and 3C show cross-sectional views of transistors in a pixel portion and a driving circuit included in a display device of an embodiment of the present invention. The structure of the transistor included in the display device shown in Figures 3A, 3B, and 3C is different from that of the display device shown in Figures 1A, 1B, and 1C. Note that its top view is the same as the structure shown in Figures 2A and 2B, so Figures 2A and 2B are referenced. [0159] A display device according to an embodiment of the present invention includes a transistor 100B, a transistor 200B, a capacitor 250B and a connecting portion 150B. [0160] Figure 3A is a cross-sectional view of the transistor 200B and the capacitor 250B included in the pixel portion, and is equivalent to the cross-sectional view along the dotted line X1-X2 of Figure 2A. Figure 3B is a cross-sectional view of the transistor 100B and the connecting portion 150B included in the driving circuit, and is equivalent to the cross-sectional view along the dotted line X3-X4 of Figure 2B. FIG3C is a cross-sectional view of a transistor 100B included in a driving circuit, and is equivalent to a cross-sectional view along dotted line Y1-Y2 of FIG2B. [0161] As shown in FIG3A, the pixel portion includes a transistor 200B, a conductive film 220 used as a pixel electrode, and a capacitor 250B. The conductive film 220 used as a pixel electrode is electrically connected to the transistor 200B. Since the transistor 200B and the capacitor 250B can refer to the transistor 200A and the capacitor 250A shown in FIG1A, detailed description is omitted. [0162] As shown in FIG3B and FIG3C, the driving circuit includes a transistor 100B and a connecting portion 150B. [0163] The transistor 100B includes: a conductive film 104 on a substrate 102; an insulating film 106 on the substrate 102 and the conductive film 104; a metal oxide film 108 on the insulating film 106; a conductive film 112a on the metal oxide film 108; a conductive film 112b on the metal oxide film 108; an insulating film 114 on the metal oxide film 108, the conductive films 112a and 112b; an insulating film 116 on the insulating film 114; and a conductive film 132a on the insulating film 116. [0164] In transistor 100B, insulating film 106 is used as a first gate insulating film, and insulating film 114 and insulating film 116 are used as a second gate insulating film. In addition, in transistor 100B, conductive film 104 is used as a first gate electrode, and conductive film 132a is used as a second gate electrode. In addition, in transistor 100B, conductive film 112a is used as a source electrode, and conductive film 112b is used as a drain electrode. [0165] In transistor 100B, the ends of conductive film 112a and conductive film 112b are located on the inner side of the end of metal oxide film 108. [0166] On the transistor 100B, specifically, an insulating film 118 and an insulating film 119 on the insulating film 118 are formed on the insulating film 116 and the conductive film 132a. In the transistor 100B, the insulating film 118 is used as a protective insulating film of the transistor 100B. In addition, the insulating film 119 is used as a planarization film. [0167] In the transistor 100B, the insulating film 106, the insulating film 114, the insulating film 116, the insulating film 118, and the insulating film 119 include an opening 146b in a region overlapping with the conductive film 104. In addition, the insulating film 119 includes an opening 148b in the area overlapping with the conductive film 132a. The conductive film 120b used as the first wiring is electrically connected to the conductive film 132a and the conductive film 104 through the opening 146b and the opening 148b. By providing the conductive film 120b, the conductive film 104 used as the first gate electrode of the transistor 100B is electrically connected to the conductive film 132a used as the second gate electrode. [0168] The transistor 100B is a so-called channel etching type transistor having a dual gate structure. [0169] The conductive film 132a is preferably the above-mentioned oxide conductor (OC). By using an oxide conductor as the conductive film 132a, oxygen can be added to the insulating films 114 and 116. The oxygen added to the insulating films 114 and 116 moves to the metal oxide films 108 and 208 to fill the oxygen defects in the metal oxide films 108 and 208. As a result, the reliability of the transistors 100B and 200B can be improved. [0170] As shown in FIG. 3B, the metal oxide film 108 of the transistor 100B is located at a position opposite to the conductive film 104 and the conductive film 132a, and is sandwiched between the two conductive films used as gate electrodes. The length of the conductive film 132a in the channel length direction and the length of the conductive film 132a in the channel width direction are respectively longer than the length of the metal oxide film 108 in the channel length direction and the length of the metal oxide film 108 in the channel width direction, and the conductive film 132a covers the entire metal oxide film 108 via the insulating film 114 and the insulating film 116. [0171] In other words, the conductive film 104 and the conductive film 132a are connected to each other through the openings formed in the insulating film 106, the insulating film 114, the insulating film 116, the insulating film 118, and the insulating film 119 and include a region located outside the side end portion of the metal oxide film 108. [0172] By adopting the above structure, the electric field of the conductive film 104 and the conductive film 132a can be used to electrically surround the metal oxide film 108 included in the transistor 100B, thereby realizing an S-channel structure. For the s-channel structure, reference can be made to the previous description. [0173] The connecting portion 150B includes: a conductive film 113 used as a second wiring on the substrate 102; an opening 142b on the conductive film 113 used as the second wiring and provided in the insulating film 106, the insulating film 114, the insulating film 116, the insulating film 118 and the insulating film 119; a conductive film 115a used as a third wiring on the metal oxide film 128; and an opening 142b on the conductive film 113 used as the third wiring. 3B , the openings 142b and 144b are formed on the conductive film 115a and are arranged in the insulating film 114, the insulating film 116, the insulating film 118 and the insulating film 119; and the conductive film 120a used as the fourth wiring is formed in a manner covering the openings 142b and the openings 144b and connecting the conductive film 113 used as the second wiring and the conductive film 115a used as the third wiring. In FIG. 3B , the opening shapes of the openings 142b and the openings 144b are in a step shape, but may also be in a plurality of step shapes such as two steps. [0174] In the connecting portion 150B, the end of the conductive film 115a is located on the inner side of the end of the metal oxide film 128. [0175] The conductive film 113 used as the second wiring is formed on the same plane in the same process as the conductive film 104 used as the first gate electrode of the transistor 100B. The conductive film 115a used as the third wiring is formed on the same plane in the same process as the conductive film 112a used as the source electrode of the transistor 100B and the conductive film 112b used as the drain electrode. The conductive film 120a used as the fourth wiring is formed on the same plane in the same process as the conductive film 220 used as the pixel electrode. [0176] In other words, the conductive film 113 used as the second wiring is formed using the same layer as the conductive film 104 used as the first gate electrode of the transistor 100B. The conductive film 115a used as the third wiring is formed using the same layer as the conductive film 112a used as the source electrode of the transistor 100B and the conductive film 112b used as the drain electrode. The conductive film 120a used as the fourth wiring is formed using the same layer as the conductive film 220 used as the pixel electrode. [0177] The conductive film 220 used as the pixel electrode, the conductive film 120b used as the first wiring, and the conductive film 120a used as the fourth wiring are formed in the same process. In other words, the conductive film 220 used as the pixel electrode, the conductive film 120b used as the first wiring, and the conductive film 120a used as the fourth wiring are formed using the same layer. In addition, the conductive film 220 used as a pixel electrode, the conductive film 120b used as a first wiring, and the conductive film 120a used as a fourth wiring are in contact with the top surface of the insulating film 119 used as a planarization film. [0178] á1-4. Structural example of a display device 3ñ Figures 4A, 4B, and 4C show cross-sectional views of transistors in a pixel portion and a driving circuit included in a display device of an embodiment of the present invention, and Figures 5A and 5B show top views thereof. The structure of the transistor included in the display device shown in Figures 4A to 4C and Figures 5A and 5B is different from that of the display device shown in Figures 1A, 1B, and 1C. [0179] A display device according to an embodiment of the present invention includes a transistor 100C, a transistor 200C, a capacitor 250C, and a connecting portion 150C. [0180] FIG4A is a cross-sectional view of the transistor 200C and the capacitor 250C included in the pixel portion, and is equivalent to the cross-sectional view along the dotted line X1-X2 of FIG5A. FIG4B is a cross-sectional view of the transistor 100C and the connecting portion 150C included in the driving circuit, and is equivalent to the cross-sectional view along the dotted line X3-X4 of FIG5B. FIG4C is a cross-sectional view of the transistor 100C included in the driving circuit, and is equivalent to the cross-sectional view along the dotted line Y1-Y2 of FIG5B. [0181] As shown in FIG. 4A, the pixel portion includes a transistor 200C, a conductive film 220 used as a pixel electrode, and a capacitor 250C. The conductive film 220 used as a pixel electrode is electrically connected to the transistor 200C. Since the transistor 200C and the capacitor 250C can refer to the transistor 200A and the capacitor 250A shown in FIG. 1A, detailed description is omitted. [0182] As shown in FIG. 4B and FIG. 4C, the driving circuit includes a transistor 100C and a connecting portion 150C. [0183] The transistor 100C includes: a conductive film 104 on a substrate 102; an insulating film 106 on the substrate 102 and the conductive film 104; a metal oxide film 108 on the insulating film 106; a conductive film 112a on the metal oxide film 108; and a conductive film 112b on the metal oxide film 108. [0184] In the transistor 100C, the insulating film 106 is used as a gate insulating film. In addition, in the transistor 100C, the conductive film 104 is used as a gate electrode, the conductive film 112a is used as a source electrode, and the conductive film 112b is used as a drain electrode. [0185] In the transistor 100C, the ends of the conductive films 112a and 112b are located on the inner side of the ends of the metal oxide film 208. [0186] In the transistor 100C, specifically, the insulating film 114, the insulating film 116 on the insulating film 114, the insulating film 118 on the insulating film 116, and the insulating film 119 on the insulating film 118 are formed on the metal oxide film 108, the conductive films 112a, and the conductive films 112b. In the transistor 100C, the insulating film 114, the insulating film 116, and the insulating film 118 are used as a protective insulating film of the transistor 100C. In addition, the insulating film 119 is used as a planarization film. [0187] The insulating film 114, the insulating film 116, the insulating film 118, and the insulating film 119 have an opening 242c in the region overlapping with the conductive film 212b. The conductive film 220 used as a pixel electrode is electrically connected to the conductive film 212b via the opening 242c. [0188] The transistor 100C is a so-called channel etching type transistor having a single gate structure. [0189] The connection portion 150C includes: a conductive film 113 used as a second wiring on the substrate 102; an opening 142c provided in the insulating film 106, the insulating film 114, the insulating film 116, the insulating film 118, and the insulating film 119 on the conductive film 113 used as the second wiring; a conductive film 115a used as a third wiring on the metal oxide film 128; and an opening 142c provided in the insulating film 106, the insulating film 114, the insulating film 116, the insulating film 118, and the insulating film 119. 4B , the openings 142b and 144b are in the shape of a step, but may also be in the shape of two steps or more. [0190] In the connecting portion 150C, the end of the conductive film 115a is located on the inner side of the end of the metal oxide film 128. [0191] The conductive film 113 used as the second wiring is formed on the same plane in the same process as the conductive film 104 used as the first gate electrode of the transistor 100C. The conductive film 115a used as the third wiring is formed on the same plane in the same process as the conductive film 112a used as the source electrode of the transistor 100C and the conductive film 112b used as the drain electrode. The conductive film 120a used as the fourth wiring is formed on the same plane in the same process as the conductive film 220 used as the pixel electrode. [0192] In other words, the conductive film 113 used as the second wiring is formed using the same layer as the conductive film 204 used as the first gate electrode of the transistor 100C. The conductive film 115a used as the third wiring is formed using the same layer as the conductive film 112a used as the source electrode of the transistor 100C and the conductive film 112b used as the drain electrode. The conductive film 120a used as the fourth wiring is formed using the same layer as the conductive film 220 used as the pixel electrode. [0193] The conductive film 220 used as the pixel electrode, the conductive film 120b used as the first wiring, and the conductive film 120a used as the fourth wiring are formed in the same process. In other words, the conductive film 220 used as the pixel electrode, the conductive film 120b used as the first wiring, and the conductive film 120a used as the fourth wiring are formed using the same layer. In addition, the conductive film 220 used as a pixel electrode, the conductive film 120b used as a first wiring, and the conductive film 120a used as a fourth wiring are in contact with the top surface of the insulating film 119 used as a planarization film. [0194] á1-5. Structural example of a display device 4ñ Figures 6A, 6B, and 6C show cross-sectional views of a pixel portion and a transistor in a driving circuit included in a display device of an embodiment of the present invention, and Figures 7A and 7B show a top view thereof. [0195] A display device of an embodiment of the present invention includes a transistor 100D, a transistor 200D, a capacitor 250D, and a connecting portion 150D. [0196] FIG6A is a cross-sectional view of a transistor 200D and a capacitor 250D included in a pixel portion, and is equivalent to a cross-sectional view along dotted line X1-X2 of FIG7A. FIG6B is a cross-sectional view of a transistor 100D and a connecting portion 150D included in a driving circuit, and is equivalent to a cross-sectional view along dotted line X3-X4 of FIG7B. FIG6C is a cross-sectional view of a transistor 100D included in a driving circuit, and is equivalent to a cross-sectional view along dotted line Y1-Y2 of FIG7B. Note that in FIGS. 7A and 7B, for the sake of convenience, a portion of the components of the transistor 100D, the transistor 200D, and the capacitor 250D (such as an insulating film used as a gate insulating film) is omitted. In addition, in each transistor, the dotted line X1-X2 direction is sometimes referred to as the channel length direction, and the dotted line Y1-Y2 direction is sometimes referred to as the channel width direction. Note that sometimes a part of the components is omitted in the top view of the transistor in the back, as in FIG. 7A and FIG. 7B. [0197] As shown in FIG. 6A, the pixel portion includes a transistor 200D, a conductive film 220 used as a pixel electrode, and a capacitor 250D. The conductive film 220 used as a pixel electrode is electrically connected to the transistor 200D. [0198] The transistor 200D includes: a conductive film 204 on a substrate 102; an insulating film 106 on the substrate 102 and the conductive film 204; a metal oxide film 208 on the insulating film 106; a conductive film 212a on the metal oxide film 208; and a conductive film 212b on the metal oxide film 208. [0199] In the transistor 200D, the insulating film 106 is used as a gate insulating film. In addition, in the transistor 200D, the conductive film 204 is used as a gate electrode, the conductive film 212a is used as a source electrode, and the conductive film 212b is used as a drain electrode. [0200] In the transistor 200D, the ends of the conductive films 212a and 212b are located inside the ends of the metal oxide film 208. [0201] In the transistor 200D, specifically, the insulating film 114, the insulating film 116 on the insulating film 114, the insulating film 118 on the insulating film 116, and the insulating film 119 on the insulating film 118 are formed on the metal oxide film 208, the conductive films 212a, and the conductive films 212b. In the transistor 200D, the insulating film 114, the insulating film 116, and the insulating film 118 are used as protective insulating films of the transistor 200D. In addition, the insulating film 119 is used as a planarization film. [0202] The insulating film 114, the insulating film 116, the insulating film 118 and the insulating film 119 have an opening 242d in the area overlapping with the conductive film 212b. The conductive film 220 used as a pixel electrode is electrically connected to the conductive film 212b through the opening 242d. [0203] The transistor 200D is a so-called channel etching type transistor having a single gate structure. [0204] The capacitor 250D is formed by the conductive film 213, the insulating film 106, the metal oxide film 228 and the conductive film 215a. The conductive film 213 used as capacitor wiring is formed on the same plane in the same process as the conductive films 204, 104, and 113. The conductive film 215a is formed on the same plane in the same process as the conductive films 212a, 212b, 112a, 112b, and 115d. [0205] In the capacitor 250D, the end of the conductive film 215a is located on the inner side of the end of the metal oxide film 228. [0206] The conductive film 220 used as a pixel electrode is formed on the insulating film 119. The conductive film 220 provided on the insulating film 119 used as a planarization film also has high flatness. Since the conductive film 220 has high flatness, when the display device is a liquid crystal display device, poor alignment of the liquid crystal layer can be reduced. In addition, by using the insulating film 119, the distance between the conductive film 204 used as the gate wiring and the conductive film 220 and the distance between the conductive film 212a used as the signal line and the conductive film 220 can be expanded, thereby reducing the wiring delay. [0207] As shown in Figures 6B and 6C, the driving circuit includes a transistor 100D and a connecting portion 150D. [0208] In the transistor 100D, there are formed: a conductive film 104 on the substrate 102; an insulating film 106 on the substrate 102 and the conductive film 104; a metal oxide film 108 on the insulating film 106; a conductive film 112a on the metal oxide film 108; a conductive film 112b on the metal oxide film 108; an insulating film 114 on the metal oxide film 108, the conductive film 112a, and the conductive film 112b; an insulating film 116 on the insulating film 114; an insulating film 118 on the insulating film 116; an insulating film 119 on the insulating film 118 and a conductive film 130d. [0209] In the transistor 100D, the insulating film 119 includes an opening 142d in a region overlapping with the conductive film 104 and the metal oxide film 108. In addition, the insulating film 106, the insulating film 114, the insulating film 116, the insulating film 118, and the insulating film 119 include an opening 146d in a region overlapping with the conductive film 104 and not overlapping with the metal oxide film 108, the conductive film 112a, and the conductive film 112b. [0210] A conductive film 130d used as a second gate electrode is provided in a manner covering the opening 146d and the opening 142d. In the opening 142d, the conductive film 130d used as the second gate electrode is provided on the conductive film 104 used as the first gate electrode. That is, the conductive film 130d used as the second gate electrode is electrically connected to the conductive film 104 used as the first gate electrode. In addition, in the opening 142d, the conductive film 130d used as the second gate electrode is provided on the insulating film 118 used as the second gate insulating film. That is, the conductive film 130d used as the second gate electrode is arranged in a region overlapping with the conductive film 104 used as the first gate electrode and the metal oxide film 108. [0211] In transistor 100D, insulating film 106 is used as a first gate insulating film, and insulating film 114, insulating film 116 and insulating film 118 are used as a second gate insulating film. In addition, in transistor 100D, conductive film 104 is used as a first gate electrode, and conductive film 130d is used as a second gate electrode. In addition, in transistor 100D, conductive film 112a is used as a source electrode, and conductive film 112b is used as a drain electrode. [0212] In transistor 100D, insulating film 119 is used as a planarization film. [0213] In transistor 100D, the ends of conductive film 112a and conductive film 112b are located inside the ends of metal oxide film 108. [0214] Transistor 100D is a so-called channel etched transistor having a double gate structure. [0215] As shown in FIG6B, metal oxide film 108 of transistor 100D is located opposite to conductive film 104 and conductive film 130d, and is sandwiched between two conductive films used as gate electrodes. The length of the conductive film 130d in the channel length direction and the length of the conductive film 130d in the channel width direction are respectively longer than the length of the metal oxide film 108 in the channel length direction and the length of the metal oxide film 108 in the channel width direction, and the conductive film 130d covers the entire metal oxide film 108 via the insulating film 114, the insulating film 116, the insulating film 118 and the insulating film 119. [0216] In other words, the conductive film 104 and the conductive film 130d are connected to each other through openings formed in the insulating film 106, the insulating film 114, the insulating film 116, the insulating film 118, and the insulating film 119 and include a region located outside the side end portion of the metal oxide film 108. [0217] By adopting the above structure, the metal oxide film 108 included in the transistor 100D can be electrically surrounded by the electric field of the conductive film 104 and the conductive film 130d, thereby realizing an S-channel structure. For the s-channel structure, reference can be made to the previous description. [0218] Since the transistor 100D has an S-channel structure, the electric field for causing the channel can be effectively applied to the metal oxide film 108 using the conductive film 104 used as the first gate electrode, thereby improving the current driving capability of the transistor 100D, thereby obtaining a high on-state current characteristic. In addition, since the on-state current can be improved, the transistor 100D can be miniaturized. In addition, since the metal oxide film 108 is surrounded by the conductive film 104 used as the first gate electrode and the conductive film 130d used as the second gate electrode, the mechanical strength of the transistor 100D can be improved. [0219] The connecting portion 150D includes: a conductive film 113 used as a first wiring on the substrate 102; an opening 160 in the insulating film 106 provided on the conductive film 113 used as the first wiring; and a conductive film 115d used as a second wiring covering the opening 160. In the opening 160, the conductive film 115d used as the second wiring is provided on the conductive film 113 used as the first wiring, and the conductive film 113 used as the first wiring is electrically connected to the conductive film 115d used as the second wiring. [0220] In the opening 160, the conductive film 113 used as the first wiring is directly connected to the conductive film 115d used as the second wiring. Therefore, it can also be said that the opening 160 is a contact hole. By directly connecting the conductive film 113 used as the first wiring and the conductive film 115d used as the second wiring, good contact can be achieved, and the contact resistance can be reduced. [0221] The conductive film 113 used as the first wiring and the conductive film 104 used as the first gate electrode of the transistor 100D are formed on the same plane in the same process. The conductive film 115d used as the second wiring and the conductive film 112a used as the source electrode of the transistor 100D and the conductive film 112b used as the drain electrode are formed on the same plane in the same process. [0222] In other words, the conductive film 113 used as the first wiring and the conductive film 104 used as the first gate electrode of the transistor 100D are formed using the same layer. The conductive film 115d used as the second wiring is formed using the same layer as the conductive film 112a used as the source electrode of the transistor 100D and the conductive film 112b used as the drain electrode. [0223] The conductive film 220 used as the pixel electrode and the conductive film 130d used as the second gate electrode are formed in the same process. In other words, the conductive film 220 used as the pixel electrode and the conductive film 130d used as the second gate electrode are formed using the same layer. In addition, the conductive film 220 used as the pixel electrode and the conductive film 130d used as the second gate electrode are in contact with the top surface of the insulating film 119 used as a planarization film. [0224] á1-6. Structural example of a display device 5ñ Figures 8A, 8B and 8C are cross-sectional views of a pixel portion and a transistor in a driving circuit included in a display device of an embodiment of the present invention, and Figures 9A and 9B are top views thereof. The structure of the transistor included in the display device shown in Figures 8A to 8C and Figures 9A and 9B is different from that of the display device shown in Figures 6A, 6B and 6C. [0225] A display device of an embodiment of the present invention includes a transistor 100E, a transistor 200E, a capacitor 250E and a connecting portion 150E. [0226] Figure 8A is a cross-sectional view of a transistor 200E and a capacitor 250E included in a pixel portion, and is equivalent to a cross-sectional view along the dotted line X1-X2 of Figure 9A. FIG8B is a cross-sectional view of a transistor 100E and a connecting portion 150E included in a driving circuit, and is equivalent to a cross-sectional view along dotted line X3-X4 of FIG9B. FIG8C is a cross-sectional view of a transistor 100E included in a driving circuit, and is equivalent to a cross-sectional view along dotted line Y1-Y2 of FIG9B. [0227] As shown in FIG8A, a pixel portion includes a transistor 200E, a conductive film 220 used as a pixel electrode, and a capacitor 250E. The conductive film 220 used as a pixel electrode is electrically connected to the transistor 200E. Since the transistor 200E and the capacitor 250E can refer to the transistor 200D and the capacitor 250D shown in FIG6A, a detailed description is omitted. [0228] As shown in FIG. 8B and FIG. 8C , the driving circuit includes a transistor 100E and a connecting portion 150E. [0229] The transistor 100E includes: a conductive film 104 on a substrate 102; an insulating film 106 on the substrate 102 and the conductive film 104; a metal oxide film 108 on the insulating film 106; a conductive film 112a on the metal oxide film 108; and a conductive film 112b on the metal oxide film 108. [0230] In the transistor 100E, the insulating film 106 is used as a gate insulating film. In addition, in the transistor 100E, the conductive film 104 is used as a gate electrode, the conductive film 112a is used as a source electrode, and the conductive film 112b is used as a drain electrode. [0231] In the transistor 100E, the ends of the conductive film 112a and the conductive film 112b are located on the inner side of the end of the metal oxide film 108. [0232] On the transistor 100E, specifically, an insulating film 114, an insulating film 116 on the insulating film 114, an insulating film 118 on the insulating film 116, and an insulating film 119 on the insulating film 118 are formed on the metal oxide film 108, the conductive film 112a, and the conductive film 112b. In transistor 100E, insulating film 114, insulating film 116 and insulating film 118 are used as protective insulating films of transistor 100E. In addition, insulating film 119 is used as a planarization film. [0233] Transistor 100E is a so-called channel etching type transistor having a single gate structure. [0234] Since connection portion 150E can refer to connection portion 150D shown in FIG. 6B, detailed description is omitted. [0235] á1-7. Manufacturing method of display device 1ñ Referring to Figures 10A to 22C, a manufacturing method of the transistor 100A, the transistor 200A, the capacitor 250A and the connecting portion 150A included in the display device of an embodiment of the present invention shown in Figures 1A, 1B and 1C is described. [0236] Figures 10A to 22C are cross-sectional views illustrating the manufacturing method of the display device. In the cross-sectional views of Figures 10A to 22C, the direction of the dotted line X1-X2 is the channel length direction of the transistor 200A, and the direction of the dotted line X3-X4 is the channel length direction of the transistor 100A. The direction of the dotted line Y1-Y2 is the channel width direction of the transistor 100A. [0237] First, a conductive film is formed on the substrate 102, and the conductive film is processed by a photolithography process and an etching process to form a conductive film 104 used as a first gate electrode of the transistor 100A, a conductive film 113 used as a wiring, a conductive film 204 used as a gate electrode of the transistor 200A, and a conductive film 213 used as a capacitor wiring. Then, an insulating film 106 used as a first gate insulating film is formed on the conductive film 104, the conductive film 113, the conductive film 213, the conductive film 204, and the substrate 102 (refer to FIGS. 10A, 10B, and 10C). The process of forming the conductive film 104, the conductive film 113, the conductive film 213 and the conductive film 204 is a first photolithography process. [0238] In this specification, etc., the photolithography process refers to a process of forming a pattern using a mask. [0239] In the present embodiment, a glass substrate is used as the substrate 102. As the conductive film 104, the conductive film 113, the conductive film 204 and the conductive film 213, a titanium film with a thickness of 50 nm and a copper film with a thickness of 200 nm are formed by a sputtering method. [0240] In the present embodiment, as the insulating film 106, a silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm are formed by a PECVD method. [0241] In addition, the silicon nitride film has a three-layer structure including a first silicon nitride film, a second silicon nitride film and a third silicon nitride film. The three-layer structure can be formed, for example, as shown below. [0242] A first silicon nitride film with a thickness of 50 nm can be formed under the following conditions: for example, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm and ammonia with a flow rate of 100 sccm are used as source gases, the source gas is supplied to the reaction chamber of the PECVD equipment, the pressure in the reaction chamber is controlled to 100 Pa, and a high-frequency power supply of 27.12 MHz is used to supply a power of 2000 W. [0243] A second silicon nitride film with a thickness of 300 nm can be formed under the following conditions: silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia with a flow rate of 2000 sccm are used as source gases, the source gases are supplied into the reaction chamber of the PECVD equipment, the pressure in the reaction chamber is controlled to 100 Pa, and a high-frequency power supply of 27.12 MHz is used to supply 2000 W of power. [0244] For example, a third silicon nitride film with a thickness of 50 nm can be formed under the following conditions: using silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia with a flow rate of 100 sccm as source gases, supplying the source gases into the reaction chamber of the PECVD equipment, controlling the pressure in the reaction chamber to 100 Pa, and using a 27.12 MHz high-frequency power supply to supply a power of 2000 W. [0245] In addition, the substrate temperature when forming the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be set to be below 350°C. [0246] By adopting the above-mentioned three-layer structure as the silicon nitride film, for example, when a conductive film containing copper is used as one or more of the conductive film 104, the conductive film 113, the conductive film 204 and the conductive film 213, the following effects can be exerted. [0247] The first silicon nitride film can suppress the diffusion of copper from the conductive film 104, the conductive film 113, the conductive film 204 and the conductive film 213. The second silicon nitride film has a function of releasing hydrogen and can improve the withstand voltage of the insulating film used as a gate insulating film. The third silicon nitride film is a film that releases less hydrogen and can suppress the diffusion of hydrogen released from the second silicon nitride film. [0248] Next, a metal oxide film 108a and a metal oxide film 108b are formed on the insulating film 106 (refer to FIGS. 12A, 12B and 12C). [0249] FIGS. 11A, 11B and 11C are schematic cross-sectional views of the film forming device when the metal oxide film 108a and the metal oxide film 108b are formed on the insulating film 106. FIGS. 11A, 11B and 11C schematically illustrate: a sputtering device as a film forming device; a target material 191 provided in the sputtering device; and plasma 192 formed below the target material 191. [0250] In FIGS. 11A, 11B and 11C, oxygen or excess oxygen added to the insulating film 106 is schematically indicated by a dotted arrow. For example, when oxygen gas is used when forming the metal oxide film 108a, oxygen can be effectively added to the insulating film 106. [0251] First, the metal oxide film 108a is formed on the insulating film 106. The thickness of the metal oxide film 108a can be greater than 1nm and less than 25nm, preferably greater than 5nm and less than 20nm. In addition, the metal oxide film 108a is formed using either or both of an inert gas (typically, Ar gas) and an oxygen gas. In addition, the ratio of oxygen gas to the total deposition gas when forming the metal oxide film 108a (hereinafter, also referred to as the oxygen flow ratio) is greater than 0% and less than 30%, preferably greater than 5% and less than 15%. [0252] By forming the metal oxide film 108a with an oxygen flow rate ratio within the above range, the crystallinity of the metal oxide film 108a can be made lower than the crystallinity of the metal oxide film 108b. [0253] Then, the metal oxide film 108b is formed on the metal oxide film 108a. When the metal oxide film 108b is formed, plasma discharge is performed in an atmosphere containing oxygen gas. At this time, oxygen is added to the metal oxide film 108a which becomes the formed surface of the metal oxide film 108b. The oxygen flow rate ratio when forming the metal oxide film 108b is greater than 30% and less than 100%, preferably greater than 50% and less than 100%, and more preferably greater than 70% and less than 100%. [0254] The thickness of the metal oxide film 108b is greater than 20nm and less than 100nm, preferably greater than 20nm and less than 50nm. [0255] As described above, the oxygen flow rate ratio used to form the metal oxide film 108b is preferably higher than the oxygen flow rate ratio used to form the metal oxide film 108a. In other words, the metal oxide film 108a is preferably formed under a lower oxygen partial pressure than the metal oxide film 108b. [0256] The substrate temperature when forming the metal oxide film 108a and the metal oxide film 108b can be greater than room temperature (25°C) and less than 200°C, preferably greater than room temperature and less than 130°C. The substrate temperature in the above range is suitable for use in the case of using a large area glass substrate (for example, the above-mentioned 8th to 10th generation glass substrates). In particular, by setting the substrate temperature during the formation of the metal oxide film 108a and the metal oxide film 108b to room temperature, deformation or bending of the substrate can be suppressed. In addition, in the case where it is desired to improve the crystallinity of the metal oxide film 108b, it is preferable to increase the substrate temperature during the formation of the metal oxide film 108b. [0257] By continuously forming the metal oxide film 108a and the metal oxide film 108b in a vacuum, it is possible to prevent impurities from mixing into each interface, which is more preferable. [0258] In addition, it is necessary to highly purify the sputtering gas. For example, as the oxygen gas or argon gas used as the sputtering gas, a high-purity gas having a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less, and further preferably -120°C or less is used, thereby preventing moisture and the like from being mixed into the metal oxide film as much as possible. [0259] In addition, when forming a metal oxide film by sputtering, it is preferred to use an adsorption vacuum pump such as a cryogenic pump to evacuate the processing chamber of the sputtering device to a high vacuum (evacuate to 5°C or less).-7 Pa to 1´10-4 Pa) to remove water and other impurities to the metal oxide film as much as possible. In particular, when the sputtering device is on standby, the temperature in the processing chamber is equivalent to H2 The partial pressure of O gas molecules (equivalent to gas molecules with m/z=18) is preferably 1´10- 4 Pa or less, preferably 5´10- 5 Pa or less. [0260] In the present embodiment, the metal oxide film 108a is formed by a sputtering method using an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). In addition, the substrate temperature when forming the metal oxide film 108a is set to room temperature, and an argon gas with a flow rate of 180sccm and an oxygen gas with a flow rate of 20sccm (oxygen flow ratio of 10%) are used as deposition gases. [0261] In addition, the metal oxide film 108b is formed by a sputtering method using an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). In addition, the substrate temperature when forming the metal oxide film 108b is set to room temperature, and an oxygen gas with a flow rate of 200sccm (oxygen flow ratio of 100%) is used as deposition gas. [0262] By making the oxygen flow rate ratio when forming the metal oxide film 108a different from the oxygen flow rate ratio when forming the metal oxide film 108b, a stacked film with different crystallinity can be formed. [0263] Although the manufacturing method using the sputtering method is described here, it is not limited to this, and pulsed laser deposition (PLD) method, plasma enhanced chemical vapor deposition (PECVD) method, thermal CVD (Chemical Vapor Deposition) method, ALD (Atomic Layer Deposition) method, vacuum evaporation method, etc. can also be used. As an example of the thermal CVD method, the MOCVD (Metal Organic Chemical Vapor Deposition) method can be cited. [0264] After forming the metal oxide film 108a and the metal oxide film 108b, the metal oxide film 108a and the metal oxide film 108b may be exposed to plasma containing oxygen. As a result, oxygen can be added to the surface of the metal oxide film 108a and the metal oxide film 108b, and the oxygen defects of the metal oxide film 108a and the metal oxide film 108b can be reduced. In particular, by reducing the oxygen defects on the side surfaces of the metal oxide film 108a and the metal oxide film 108b, the occurrence of the leakage current of the transistor can be suppressed, so it is preferable. [0265] In addition, it is preferable to perform heat treatment (hereinafter referred to as the first heat treatment) after forming the metal oxide film 108a and the metal oxide film 108b. By performing the first heat treatment, hydrogen, water, etc. contained in the metal oxide film 108a and the metal oxide film 108b can be reduced. In addition, the heat treatment for the purpose of reducing hydrogen, water, etc. can also be performed after the metal oxide films 108a and 108b are processed into islands. Note that the first heat treatment is one of the highly purified treatments of the metal oxide film. [0266] The temperature of the first heat treatment is, for example, above 150°C and below the strain point of the substrate, preferably above 200°C and below 450°C, and more preferably above 250°C and below 350°C. [0267] The first heat treatment can be performed using an electric furnace, an RTA (Rapid Thermal Anneal) device, or the like. By using an RTA device, the heat treatment can be performed at a temperature above the strain point of the substrate for only a short time. Thus, the heating time can be shortened. The first heat treatment can be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of less than 20 ppm, preferably less than 1 ppm, and more preferably less than 10 ppb) or a rare gas (argon, helium, etc.). The above-mentioned nitrogen, oxygen, ultra-dry air or rare gas is preferably free of hydrogen, water, etc. In addition, after the heat treatment is performed in a nitrogen or rare gas atmosphere, it can also be heated in an oxygen or ultra-dry air atmosphere. As a result, while hydrogen, water, etc. in the metal oxide film can be separated, oxygen can be supplied to the metal oxide film. As a result, oxygen defects in the metal oxide film can be reduced. [0268] Next, a conductive film 112 is formed on the metal oxide film 108a and the metal oxide film 108b. Next, a photoresist mask 251, a photoresist mask 253, a photoresist mask 151, and a photoresist mask 153 are formed on the conductive film 112 by a second photolithography process (refer to FIGS. 13A, 13B, and 13C). The process of forming the photoresist mask 251, the photoresist mask 253, the photoresist mask 151, and the photoresist mask 153 is a second photolithography process. [0269] In the present embodiment, a titanium film with a thickness of 30 nm, a copper film with a thickness of 200 nm, and a titanium film with a thickness of 10 nm are sequentially formed as the conductive film 112 by a sputtering method. [0270] The photoresist mask 253 has a region 255 where the thickness of the photoresist is thin in the region overlapping with the conductive film 204. The region 255 may also be referred to as a recess. The photoresist mask 151 has a region 155 where the thickness of the photoresist is thin in the region overlapping with the conductive film 104. The region 155 can also be called a recess. In the present embodiment, when forming the photoresist mask, exposure using a multi-tone (high grayscale) mask is adopted. By using a multi-tone (high grayscale) mask, a photoresist mask with different thicknesses of the photoresist can be formed. [0271] The exposure using a multi-tone (high grayscale) mask is explained. [0272] First, a photoresist for forming the photoresist mask is formed. As the photoresist, a positive photoresist or a negative photoresist can be used. Here, a positive photoresist is used. The photoresist can be formed by a spin coating method or selectively formed by an inkjet method. When a photoresist is selectively formed by an inkjet method, it is possible to prevent the photoresist from being formed in unnecessary portions, thereby reducing waste of materials. [0273] Next, a multi-tone mask is used as a photomask, and light is irradiated onto the photoresist to expose the photoresist. [0274] A multi-tone mask refers to a mask that can be exposed at three levels (an exposed portion, an intermediate exposed portion, and an unexposed portion), and is a mask that allows the transmitted light to have a variety of intensities. By performing a single exposure and development process, a photoresist mask having regions of a variety of thicknesses can be formed. Therefore, by using a multi-tone mask, the number of photolithography processes can be reduced, thereby simplifying the process. [0275] As typical examples of multi-tone masks, there are a gray tone mask 10a as shown in FIG. 46A and a half tone mask 10b as shown in FIG. 46C. [0276] As shown in FIG. 46A, the gray tone mask 10a includes a light-transmitting substrate 13 and a light-shielding film 15 provided on the light-transmitting substrate 13. In addition, the gray tone mask 10a includes a light-shielding portion 17 provided with a light-shielding film, a diffraction grating portion 18 provided by a pattern of the light-shielding film, and a transmission portion 19 without a light-shielding film. [0277] As the light-transmitting substrate 13, a light-transmitting substrate such as quartz can be used. The light-shielding film 15 can be formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. [0278] FIG. 46B shows the light transmittance TR when the gray tone mask 10a is irradiated with exposure light. As shown in FIG. 46B , the light transmittance 21 of the light shielding portion 17 is 0%. The light transmittance 21 of the transparent portion 19 is approximately 100%. In addition, in the diffraction grating portion 18, the light transmittance 21 can be adjusted within a range of 10% to 70%. In the diffraction grating portion 18, the intervals of the light transmitting portions such as slits, dots, and meshes are set to intervals below the resolution limit of the light used for exposure. In addition, by adjusting the intervals and grating pitch of the slits, dots, and meshes, the light transmittance of the diffraction grating portion 18 can be controlled. The diffraction grating portion 18 can use periodic or non-periodic slits, dots, and meshes. [0279] As shown in FIG. 46C, the half-tone mask 10b includes a light-transmitting substrate 13 and a light-shielding film 25 and a semi-transparent film 23 provided on the light-transmitting substrate 13. In addition, the half-tone mask 10b includes a light-shielding portion 27 provided with the light-shielding film 25 and the semi-transparent film 23, a semi-transparent portion 28 provided with the semi-transparent film 23 but without the light-shielding film 25, and a transparent portion 29 provided with the semi-transparent film 23 but without the light-shielding film 25. [0280] FIG. 46D shows the light transmittance when the half-tone mask 10b is irradiated with exposure light. As shown in FIG. 46D, the light transmittance 31 of the light-shielding portion 27 is 0%. The light transmittance 31 of the transparent portion 29 is approximately 100%. In addition, in the semi-transparent portion 28, the light transmittance 31 can be adjusted within a range of more than 10% and less than 70%. In the semi-transparent portion 28, the light transmittance can be controlled according to the material of the semi-transparent film 23. [0281] As the semi-transparent film 23, MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. As the light-shielding film 25, a light-shielding material that absorbs light, such as chromium or chromium oxide, can be used. [0282] By developing after exposing using a multi-tone mask, a photoresist mask having areas with different thicknesses as shown in Figures 13A, 13B, and 13C can be formed. [0283] Note that although an example in which the thickness of the photoresist is two kinds is shown as the multi-tone mask, an embodiment of the present invention is not limited to this. By using a diffraction grating portion 18 or a semi-transparent film 23 having multiple light transmittances, a photoresist having three or more thicknesses can be formed. [0284] Next, the conductive film 112, the metal oxide film 108a, and a portion of the metal oxide film 108b are removed using the photoresist mask 251, the photoresist mask 253, the photoresist mask 151, and the photoresist mask 153 as masks to form the conductive film 215, the conductive film 212A, the conductive film 112A, the conductive film 115, the metal oxide film 228, the metal oxide film 208, the metal oxide film 108, and the metal oxide film 128 (refer to Figures 14A, 14B, and 14C). [0285] When processing the conductive film 112, a wet etching method can be used. However, the processing method is not limited to this, and for example, a dry etching method can also be used. When processing the metal oxide film 108b, a wet etching method can be used. However, the processing method is not limited thereto, and for example, dry etching may also be used. [0286] Different etching methods may be used when processing the conductive film 112, the metal oxide film 108a, and the metal oxide film 108b. For example, dry etching may be used when processing the conductive film 112, and wet etching may be used when processing the metal oxide film 108a and the metal oxide film 108b. [0287] Next, the photoresist mask 251, the photoresist mask 253, the photoresist mask 151, and a portion of the photoresist mask 153 are removed to reduce the area of the photoresist mask. By reducing the area of the photoresist mask, photoresist mask 251a, photoresist mask 253a, photoresist mask 253b, photoresist mask 151a, photoresist mask 151b and photoresist mask 153a are formed (refer to Figures 15A, 15B and 15C). [0288] When removing a portion of the photoresist mask, an ashing device can be used. Through the ashing process, while the area of the photoresist mask is reduced, the thickness of the photoresist mask is sometimes reduced. [0289] For example, as an ashing process, a photoexcited ashing process can be used, in which light such as ultraviolet rays is irradiated on a gas such as oxygen or ozone to cause a chemical reaction between the gas and organic matter to remove the organic matter. In addition, plasma ashing can also be used as an ashing process, in which a gas such as oxygen or ozone is plasmatized by high frequency, and the plasma is used to remove organic matter. [0290] The photoresist in the thin region 255 of the photoresist mask 253 and the thin region 155 of the photoresist mask 151 is removed by the above-mentioned ashing process, thereby separating the photoresist masks from each other as shown in Figures 15A, 15B and 15C. By removing a part of the photoresist mask, the photoresist mask in the region 255a overlapping with the conductive film 204 is removed to expose the conductive film 212A in the region 255a. In addition, the photoresist mask in the region 155a overlapping with the conductive film 104 is removed to expose the conductive film 112A in the region 155a. [0291] The end of the photoresist mask 251a is located inside the end of the conductive film 215. The ends of the photoresist mask 253a and the photoresist mask 253b are located inside the end of the conductive film 212A. The ends of the photoresist mask 151a and the photoresist mask 151b are located inside the end of the conductive film 112A. The end of the photoresist mask 153a is located inside the end of the conductive film 115. [0292] Next, using photoresist mask 251a, photoresist mask 253a, photoresist mask 253b, photoresist mask 151a, photoresist mask 151b, and photoresist mask 153a as masks, a portion of conductive film 215, conductive film 212A, conductive film 112A, and conductive film 115 are removed to form conductive film 215a, conductive film 212a, conductive film 212b, conductive film 112a, conductive film 112b, and conductive film 115a (refer to Figures 16A, 16B, and 16C). [0293] The end of conductive film 215a is located on the inner side of the end of metal oxide film 228. The end of conductive film 212a and conductive film 212b are located on the inner side of the end of metal oxide film 208. The ends of the conductive film 112a and the conductive film 112b are located on the inner side of the end of the metal oxide film 108. The end of the conductive film 115a is located on the inner side of the end of the metal oxide film 128. [0294] Next, the photoresist mask 251a, the photoresist mask 253a, the photoresist mask 253b, the photoresist mask 151a, the photoresist mask 151b, and the photoresist mask 153a are removed. [0295] After removing the photoresist mask, the surface (back channel side) of the metal oxide film 108, the metal oxide film 128, the metal oxide film 208, and the metal oxide film 228 (more specifically, the metal oxide film 108_2, the metal oxide film 128_2, the metal oxide film 208_2, and the metal oxide film 228_2) may also be washed. As a washing method, for example, washing using a chemical solution such as phosphoric acid can be cited. By washing using a chemical solution such as phosphoric acid, impurities (for example, elements contained in the conductive films 112a, 112b, 212a, and 212b) attached to the surfaces of the metal oxide films 108_2, 128_2, 208_2, and 228_2 can be removed. Note that this washing is not necessarily required and may not be performed depending on circumstances. [0296] In addition, in the formation process of the conductive film 112a, the conductive film 112b, the conductive film 212a, and the conductive film 212b and/or the above-mentioned washing process, the region of the metal oxide film 108 and the metal oxide film 208 exposed from the conductive film 112a, the conductive film 112b, the conductive film 212a, and the conductive film 212b sometimes becomes thinner. [0297] In addition, the region of the metal oxide film 108 and the metal oxide film 208 exposed, that is, the metal oxide film 108_2 and the metal oxide film 208_2 is preferably a metal oxide film whose crystallinity is improved. The highly crystalline metal oxide film has a structure in which impurities (especially constituent elements used for the conductive film 112a, the conductive film 112b, the conductive film 212a, and the conductive film 212b) are not easily diffused into the film. Therefore, a highly reliable transistor can be manufactured. [0298] In addition, in FIG. 16A, FIG. 16B and FIG. 16C, although the surfaces of the metal oxide film 108, the metal oxide film 128, the metal oxide film 208, and the metal oxide film 228 exposed from the conductive film 112a, the conductive film 112b, the conductive film 115a, the conductive film 212a, the conductive film 212b, and the conductive film 215a are shown, that is, the metal oxide film 108_2, the metal oxide film 128_2, The surfaces of the metal oxide film 208_2 and the metal oxide film 228_2 have recesses, but the present invention is not limited to this. The surfaces of the metal oxide film 108, the metal oxide film 128, the metal oxide film 208, and the metal oxide film 228 exposed from the conductive film 112a, the conductive film 112b, the conductive film 115a, the conductive film 212a, the conductive film 212b, and the conductive film 215a may not have recesses. [0299] Next, insulating film 114, insulating film 116 and insulating film 118 are formed on insulating film 106, metal oxide film 108, metal oxide film 128, metal oxide film 208, metal oxide film 228, conductive film 215a, conductive film 212a, conductive film 212b, conductive film 112a, conductive film 112b and conductive film 115a (refer to FIGS. 17A, 17B and 17C). [0300] Here, it is preferable to continuously form insulating film 116 after forming insulating film 114 without exposing to the atmosphere. By adjusting one or more of the flow rate, pressure, high-frequency power and substrate temperature of the source gas to continuously form the insulating film 116 in a manner not to be exposed to the atmosphere after the insulating film 114 is formed, the impurity concentration from the atmospheric components at the interface between the insulating film 114 and the insulating film 116 can be reduced. [0301] For example, as the insulating film 114, an oxynitride silicon film can be formed by the PECVD method. At this time, as the source gas, it is preferred to use a deposition gas containing silicon and an oxidizing gas. Typical examples of deposition gases containing silicon are silane, disilane, trisilane, silane fluoride, etc. As oxidizing gases, there are nitrous oxide, nitrogen dioxide, etc. In addition, the flow rate of the oxidizing gas relative to the above-mentioned deposition gas flow rate is more than 20 times and less than 500 times, preferably more than 40 times and less than 100 times. [0302] In the present embodiment, as the insulating film 114, the oxynitride silicon film is formed by the PECVD method under the following conditions: the temperature of the substrate 102 is maintained at 220°C, silane with a flow rate of 50sccm and nitrous oxide with a flow rate of 2000sccm are used as the source gas, the pressure in the processing chamber is 20Pa, and the high-frequency power supplied to the parallel plate electrode is 13.56MHz, 100W (power density is 1.6´10- 2 W/cm2[0303] As the insulating film 116, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the temperature of the substrate in the processing chamber of the PECVD equipment which is vacuum evacuated is maintained at 180°C or higher and 350°C or lower, the source gas is introduced into the processing chamber and the pressure in the processing chamber is set to 100Pa or higher and 250Pa or lower, preferably 100Pa or higher and 200Pa or lower, and 0.17W/cm2 is supplied to the electrode in the processing chamber.2 Above and 0.5W/cm2 Below, preferably 0.25W/cm2 Above and 0.35W/cm2[0304] During the formation of the insulating film 116, the high-frequency power having the above-mentioned power density is supplied to the reaction chamber having the above-mentioned pressure, thereby improving the decomposition efficiency of the source gas in the plasma, increasing the oxygen free radicals, and promoting the oxidation of the source gas, so that the oxygen content in the insulating film 116 exceeds the stoichiometric composition. On the other hand, in the film formed at the above-mentioned substrate temperature, since the bonding force between silicon and oxygen is weak, part of the oxygen in the film is released by the heat treatment of the subsequent process. As a result, an oxide insulating film can be formed in which the oxygen content exceeds the stoichiometric composition and part of the oxygen is released due to heating. [0305] In the process of forming the insulating film 116, the insulating film 114 is used as a protective film for the metal oxide films 108 and 208. Therefore, the insulating film 116 can be formed using a high-frequency power with a high power density while reducing damage to the metal oxide films 108 and 208. [0306] In addition, in the formation of the insulating film 116, the amount of defects in the insulating film 116 can be reduced by increasing the flow rate of the deposition gas containing silicon relative to the oxidizing gas. Typically, an oxide insulating film with a small amount of defects can be formed, in which the spin density of the signal caused by the silicon dangling bond and appearing at g=2.001 measured by ESR is less than 6´1017 spins/cm3 , preferably 3´1017 spins/cm3 Below, preferably 1.5´1017 spins/cm3 Below. As a result, the reliability of the transistors 100A and 200A can be improved. [0307] It is preferred to perform heat treatment (hereinafter referred to as the second heat treatment) after forming the insulating films 114 and 116. By the second heat treatment, the nitrogen oxide contained in the insulating films 114 and 116 can be reduced. By the second heat treatment, a part of the oxygen contained in the insulating films 114 and 116 can be moved to the metal oxide films 108 and 208 to reduce the oxygen defects in the metal oxide films 108 and 208. [0308] The temperature of the second heat treatment is typically set to less than 400°C, preferably less than 375°C, and further preferably above 150°C and below 350°C. The second heat treatment can be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of less than 20 ppm, preferably less than 1 ppm, and preferably less than 10 ppb) or a rare gas (argon, helium, etc.). It is preferred that the nitrogen, oxygen, ultra-dry air or rare gas does not contain hydrogen, water, etc. The heat treatment can be performed using an electric furnace, an RTA device, etc. [0309] The insulating film 118 contains one or both of hydrogen and nitrogen. As the insulating film 118, for example, a silicon nitride film is preferably used. The insulating film 118 can be formed, for example, by a sputtering method or a PECVD method. For example, when the insulating film 118 is formed by the PECVD method, the substrate temperature is set to be lower than 400°C, preferably lower than 375°C, and more preferably above 180°C and below 350°C. By setting the substrate temperature during the formation of the insulating film 118 to the above range, a dense film can be formed, which is preferred. In addition, by setting the substrate temperature during the formation of the insulating film 118 to the above range, oxygen or excess oxygen in the insulating films 114 and 116 can be moved to the metal oxide film 108. [0310] For example, when a silicon nitride film is formed as the insulating film 118 by the PECVD method, it is preferred to use a deposition gas containing silicon, nitrogen, and ammonia as source gases. By using less ammonia than nitrogen, ammonia is dissociated in plasma to generate active species. The active species will include the bond between silicon and hydrogen in the deposition gas containing silicon and the three-bond severance between nitrogen molecules. As a result, the bonding between silicon and nitrogen can be promoted, and a silicon nitride film with less bonding between silicon and hydrogen, fewer defects and a dense structure can be formed. On the other hand, when the amount of ammonia is greater than the amount of nitrogen, the decomposition of the deposition gas containing silicon and nitrogen does not progress, and the bonding between silicon and hydrogen will remain, resulting in an increased number of defects and a non-dense silicon nitride film. Therefore, in the source gas, the nitrogen flow rate ratio relative to ammonia is set to be more than 5 times and less than 50 times, preferably more than 10 times and less than 50 times. [0311] In this embodiment, as an insulating film 118, a silicon nitride film with a thickness of 50 nm is formed by using PECVD equipment and using silane, nitrogen and ammonia as source gases. The flow rate of silane is 50 sccm, the flow rate of nitrogen is 5000 sccm, and the flow rate of ammonia is 100 sccm. The pressure of the processing chamber is set to 100 Pa, the substrate temperature is set to 350°C, and a high-frequency power of 1000 W is supplied to the parallel plate electrode with a high-frequency power of 27.12 MHz. The PECVD equipment has an electrode area of 6000 cm2 Parallel plate PECVD equipment, and the power supplied is converted into power per unit area (power density) of 1.7´10- 1 W/cm2[0312] Here, it is preferred to continuously form the insulating film 118 without exposing it to the atmosphere after forming the insulating film 116. By continuously forming the insulating film 118 by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas without exposing it to the atmosphere after forming the insulating film 116, the impurity concentration from the atmospheric components at the interface between the insulating film 116 and the insulating film 118 can be reduced. [0313] In addition, a heat treatment equivalent to the above-mentioned first heat treatment and second heat treatment (hereinafter referred to as the third heat treatment) can be performed after forming the insulating film 118. [0314] By performing the third heat treatment, oxygen contained in the insulating film 116 moves to the metal oxide films 108 and 208, and fills oxygen defects in the metal oxide films 108 and 208. [0315] Next, a conductive film 130 is formed on the insulating film 118 (see FIGS. 18A, 18B, and 18C). [0316] A light-transmitting conductive film can be used for the conductive film 130. The light-transmitting conductive film can be formed using, for example, a conductive material such as indium tin oxide, indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide containing silicon oxide. [0317] In addition, when a conductive film is formed using an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) as the conductive film 130, when the insulating film 118 is formed, hydrogen and/or nitrogen contained in the insulating film 118 sometimes enters the conductive film 130. At this time, hydrogen and/or nitrogen bonds to oxygen defects in the conductive film 130 to reduce the resistance of the conductive film 130. Thus, a low-resistance conductive film 130 can be formed. The low-resistance conductive film is an oxide conductive film. [0318] A sputtering device can be used when forming the conductive film 130. When forming the conductive film 130, plasma discharge is performed in an atmosphere containing oxygen gas. At this time, oxygen is added to the insulating film 118 that is formed into the conductive film 130. The atmosphere when forming the conductive film 130 may be mixed with an inert gas (for example, helium, argon, xenon, etc.) in addition to oxygen gas. [0319] The oxygen gas may be at least contained in the deposition gas when forming the conductive film 130, and the ratio of oxygen gas in the entire deposition gas when forming the conductive film 130 is higher than 0% and lower than 100%, preferably higher than 10% and lower than 100%, and more preferably higher than 30% and lower than 100%. [0320] In the present embodiment, the conductive film 130 is formed by a sputtering method using an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). Alternatively, the conductive film 130 may be formed by a sputtering method using an ITO target and 100% oxygen gas as a deposition gas. [0321] Note that although the present embodiment shows a method of adding oxygen to the insulating film 116 when forming the conductive film 130, it is not limited to this. For example, oxygen may be added to the insulating film 116 after the conductive film 130 is formed. [0322] In order to add oxygen to the insulating film 116, for example, an oxide (In-Sn-Si oxide, also referred to as ITSO) target containing indium, tin, and silicon may be used.2 O3 ：SnO2 ：SiO2=85:10:5 [wt%]) to form an ITSO film with a thickness of 5 nm. At this time, when the thickness of the ITSO film is greater than 1 nm and less than 20 nm, or greater than 2 nm and less than 10 nm, it is better because oxygen can be properly transmitted and the release of oxygen can be suppressed. Then, oxygen is added to the insulating film 116 through the ITSO film. As a method for adding oxygen, ion doping, ion implantation, plasma treatment, etc. can be cited. When adding oxygen, oxygen can be effectively added to the insulating film 116 by applying a bias to one side of the substrate. When applying a bias, for example, using an ashing device, the power density of the bias applied to the substrate side of the ashing device can be set to 1 W/cm2 Above and 5W/cm2 below. In addition, by setting the substrate temperature when adding oxygen to be above room temperature and below 300°C, preferably above 100°C and below 250°C, oxygen can be efficiently added to the insulating film 116. [0323] Then, the conductive film 130 is processed into a desired shape to form a conductive film 130a (refer to Figures 19A, 19B and 19C). The process for forming the conductive film 130a is a third photolithography process. [0324] In the present embodiment, a wet etching method is used to form the conductive film 130a. When forming the conductive film 130a, a dry etching method can also be used. [0325] Then, an insulating film 119 is formed on the insulating film 118 and the conductive film 130a (refer to Figures 20A, 20B and 20C). The insulating film 119 has an opening 242 in a region overlapping with the conductive film 212b. The insulating film 119 has an opening 142 in a region overlapping with the conductive film 113. The insulating film 119 has an opening 144 in a region overlapping with the conductive film 115a. The insulating film 119 has an opening 146 in a region not overlapping with the conductive film 130a and overlapping with the conductive film 104. The insulating film 119 has an opening 148 in a region overlapping with the conductive film 130a. [0326] The insulating film 119 can be formed by coating a photosensitive resin on the insulating film 118 and the conductive film 130a, and then performing exposure and development. Alternatively, a non-photosensitive resin is coated on the insulating film 118 and the conductive film 130a and then fired. Next, a photoresist mask is formed and the fired non-photosensitive resin is etched using the photoresist mask to form the insulating film 119. The process for forming the insulating film 119 is the fourth photolithography process. [0327] Next, using the insulating film 119 as a mask, a portion of the insulating film 106, the insulating film 114, the insulating film 116 and the insulating film 118 are removed (refer to Figures 21A, 21B and 21C). The insulating film 114, the insulating film 116, and the insulating film 118 in the region overlapping with the opening 242 are removed to expose the conductive film 212b, thereby forming the opening 242a. The insulating film 106, the insulating film 114, the insulating film 116, and the insulating film 118 in the region overlapping with the opening 142 are removed to expose the conductive film 113, thereby forming the opening 142a. The insulating film 114, the insulating film 116, and the insulating film 118 in the region overlapping with the opening 144 are removed to expose the conductive film 115a, thereby forming the opening 144a. The insulating film 106, the insulating film 114, the insulating film 116, and the insulating film 118 in the area overlapping with the opening 146 are removed to expose the conductive film 104 to form the opening 146a. The conductive film 130a in the area overlapping with the opening 148 is not removed to form the opening 148a. [0328] When forming the opening 242a, the opening 142a, the opening 144a, the opening 146a, and the opening 148a, dry etching can be used. Alternatively, wet etching can be used. Dry etching and wet etching can also be combined. [0329] When forming the openings 242a, 142a, 144a, 146a, and 148a, it is preferred that the etching rates of the insulating films 106, 114, 116, and 118 be high, while the etching rates of the conductive films 212b, 113, 115a, and 130a be low. In addition, the etching rate of the insulating film 119 is preferably low. [0330] When forming the openings 242a, 142a, 144a, 146a, and 148a, the thickness of the insulating film 119 is sometimes thinned. The film thickness when forming the insulating film 119 may be set in consideration of the thinned thickness. [0331] Next, a conductive film is formed on the insulating film 119, the opening 242a, the opening 142a, the opening 144a, the opening 146a, and the opening 148a, and the conductive film will become the conductive film 220, the conductive film 120a used as the fourth wiring, and the conductive film 120b used as the first wiring. [0332] The conductive film is processed by using a photolithography process and an etching process to form the conductive film 220, the conductive film 120a used as the fourth wiring, and the conductive film 120b used as the first wiring (refer to Figures 22A, 22B, and 22C). By providing the conductive film 120a, the conductive film 113 is electrically connected to the conductive film 115a. By providing the conductive film 120b, the conductive film 130a is electrically connected to the conductive film 104. [0333] The process of forming the conductive film 220, the conductive film 120a used as the fourth wiring, and the conductive film 120b used as the first wiring is the fifth photolithography process. [0334] In this way, by performing five photolithography processes, the display device shown in Figures 1A, 1B and 1C can be manufactured. [0335] In one embodiment of the present invention, the display device can be manufactured by fewer (five) photolithography processes. By reducing the number of photolithography processes, the area for configuring the pattern can be reduced, and miniaturization of the transistor and high definition of the display device can be achieved. In addition, by reducing the number of photolithography processes, simplification of the process and improvement of the yield can be achieved. In addition, by reducing the number of photolithography processes, the mask cost can be reduced. [0336] á1-8. Manufacturing method of display device 2ñ Referring to Figures 23A to 29C, a manufacturing method of the transistor 100B, the transistor 200B, the capacitor 250B and the connecting portion 150B in the display device of an embodiment of the present invention shown in Figures 3A, 3B and 3C is described. [0337] Figures 23A to 29C are cross-sectional views illustrating the manufacturing method of the display device. In the cross-sectional views of FIGS. 23A to 29C , the direction of dotted line X1-X2 is the channel length direction of transistor 200B, and the direction of dotted line X3-X4 is the channel length direction of transistor 100B. The direction of dotted line Y1-Y2 is the channel width direction of transistor 100B. [0338] In the display device shown in FIGS. 3A , 3B and 3C , the process is performed to form conductive film 215, conductive film 212a, conductive film 212b, conductive film 112a, conductive film 112b and conductive film 115a in the same manner as the display device shown in FIGS. 1A , 1B and 1C . [0339] Next, insulating film 114 and insulating film 116 are formed on conductive film 215a, conductive film 212a, conductive film 212b, conductive film 112a, conductive film 112b and conductive film 115a (refer to FIGS. 23A, 23B and 23C). [0340] Next, conductive film 132 is formed on insulating film 116 (refer to FIGS. 25A, 25B and 25C). [0341] As conductive film 132, a conductive film can be formed using an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). When the insulating film 118 is formed on the conductive film 132, hydrogen and/or nitrogen contained in the insulating film 118 sometimes enter the conductive film 132. At this time, hydrogen and/or nitrogen bond to oxygen defects in the conductive film 132 to reduce the resistance of the conductive film 132. Thus, a low-resistance conductive film 132 can be formed. The low-resistance conductive film is an oxide conductive film. [0342] Figures 24A, 24B and 24C are cross-sectional schematic diagrams inside a film forming device when a conductive film 132 is formed on the insulating film 116. Figures 24A, 24B and 24C schematically illustrate: a sputtering device as a film forming device; a target 193 set in the sputtering device; and plasma 194 formed below the target 193. [0343] First, when forming the conductive film 132, plasma discharge is performed in an atmosphere containing oxygen gas. At this time, oxygen is added to the insulating film 116 on which the conductive film 132 is formed. The atmosphere when forming the conductive film 132 may be mixed with an inert gas (for example, helium, argon, xenon, etc.) in addition to oxygen gas. [0344] Oxygen gas may be at least contained in the deposition gas when forming the conductive film 132, and the proportion of oxygen gas in the entire deposition gas when forming the conductive film 132 is higher than 0% and lower than 100%, preferably higher than 10% and lower than 100%, and more preferably higher than 30% and lower than 100%. [0345] In FIG. 24A, FIG. 24B and FIG. 24C, the oxygen or excess oxygen added to the insulating film 116 is schematically indicated by a dotted arrow. [0346] In the present embodiment, the conductive film 132 is formed by a sputtering method using an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). Alternatively, the conductive film 132 may be formed by a sputtering method using an ITO target and 100% oxygen gas as a deposition gas. [0347] Note that although the present embodiment shows a method of adding oxygen to the insulating film 116 when forming the conductive film 132, it is not limited to this. For example, oxygen may be added to the insulating film 116 after the conductive film 132 is formed. [0348] In order to add oxygen to the insulating film 116, for example, an oxide target (In-Sn-Si oxide, also referred to as ITSO) containing indium, tin, and silicon can be used.2 O3 ：SnO2 ：SiO2=85:10:5 [wt%]) to form an ITSO film with a thickness of 5nm. At this time, when the thickness of the ITSO film is greater than 1nm and less than 20nm, or greater than 2nm and less than 10nm, it is better because oxygen can be properly transmitted and the release of oxygen can be suppressed. Then, oxygen is added to the insulating film 116 through the ITSO film. As a method for adding oxygen, ion doping, ion implantation, plasma treatment, etc. can be cited. When adding oxygen, oxygen can be effectively added to the insulating film 116 by applying a bias to one side of the substrate. When applying a bias, for example, using an ashing device, the power density of the bias applied to the substrate side of the ashing device can be set to 1W/cm2 Above and 5W/cm2 Below. In addition, by setting the substrate temperature when adding oxygen to above room temperature and below 300°C, preferably above 100°C and below 250°C, oxygen can be efficiently added to the insulating film 116. [0349] Then, the conductive film 132 is processed into a desired shape to form a conductive film 132a (refer to Figures 26A, 26B and 26C). The process for forming the conductive film 132a is a third photolithography process. [0350] In the present embodiment, a wet etching method is used to form the conductive film 132a. When forming the conductive film 132a, a dry etching method can also be used. [0351] Then, an insulating film 118 is formed on the insulating film 116 and the conductive film 132a. [0352] Next, an insulating film 119 is formed on the insulating film 118 (see FIGS. 27A, 27B, and 27C). The insulating film 119 has an opening 242 in a region overlapping with the conductive film 212b. The insulating film 119 has an opening 142 in a region overlapping with the conductive film 113. The insulating film 119 has an opening 144 in a region overlapping with the conductive film 115a. The insulating film 119 has an opening 146 in a region not overlapping with the conductive film 132a and overlapping with the conductive film 104. The insulating film 119 has an opening 148 in a region overlapping with the conductive film 132a. [0353] A photosensitive resin is coated on the insulating film 118 and the conductive film 132a, and then exposed and developed to form the insulating film 119. Alternatively, a non-photosensitive resin is coated on the insulating film 118 and the conductive film 132a, and then fired. Next, a photoresist mask is formed, and the fired non-photosensitive resin is etched using the photoresist mask to form the insulating film 119. The process for forming the insulating film 119 is the fourth photolithography process. [0354] Next, using the insulating film 119 as a mask, a portion of the insulating film 106, the insulating film 114, the insulating film 116, and the insulating film 118 is removed (see FIGS. 28A, 28B, and 28C). The insulating film 114, the insulating film 116, and the insulating film 118 in the area overlapping with the opening 242 are removed to expose the conductive film 212b, thereby forming the opening 242b. The insulating film 106, the insulating film 114, the insulating film 116, and the insulating film 118 in the area overlapping with the opening 142 are removed to expose the conductive film 113, thereby forming the opening 142b. The insulating film 114, the insulating film 116, and the insulating film 118 in the area overlapping with the opening 144 are removed to expose the conductive film 115a to form the opening 144b. The insulating film 106, the insulating film 114, the insulating film 116, and the insulating film 118 in the area overlapping with the opening 146 are removed to expose the conductive film 104 to form the opening 146b. The insulating film 118 in the area overlapping with the opening 148 is removed to expose the conductive film 132a to form the opening 148b. [0355] When forming the opening 242b, the opening 142b, the opening 144b, the opening 146b, and the opening 148b, a dry etching method can be used. In addition, wet etching may also be used. Dry etching and wet etching may also be combined. [0356] When forming opening 242b, opening 142b, opening 144b, opening 146b and opening 148b, it is preferred that the etching rate of insulating film 106, insulating film 114, insulating film 116 and insulating film 118 is high, while the etching rate of conductive film 212b, conductive film 113, conductive film 115a and conductive film 132a is low. In addition, the etching rate of insulating film 119 is preferably low. [0357] When the opening 242b, the opening 142b, the opening 144b, the opening 146b, and the opening 148b are formed, the thickness of the insulating film 119 may become thinner. The film thickness when forming the insulating film 119 may be set in consideration of the thinned thickness. [0358] Next, a conductive film is formed on the insulating film 119, the opening 242b, the opening 142b, the opening 144b, the opening 146b, and the opening 148b, and the conductive film will become the conductive film 220, the conductive film 120a used as the fourth wiring, and the conductive film 120b used as the first wiring. [0359] The above-mentioned conductive film is processed by using a photolithography process and an etching process to form a conductive film 220, a conductive film 120a used as a fourth wiring, and a conductive film 120b used as a first wiring (refer to Figures 29A, 29B and 29C). By forming the conductive film 120a, the conductive film 113 is electrically connected to the conductive film 115a. By forming the conductive film 120b, the conductive film 132a is electrically connected to the conductive film 104. [0360] The process of forming the conductive film 220, the conductive film 120a used as the fourth wiring, and the conductive film 120b used as the first wiring is the fifth photolithography process. [0361] In this way, by performing five photolithography processes, the display device shown in Figures 3A, 3B and 3C can be manufactured. [0362] In one embodiment of the present invention, a display device can be manufactured by fewer (five) photolithography processes. By reducing the number of photolithography processes, the area for configuring the pattern can be reduced, and the miniaturization of transistors and the high definition of the display device can be achieved. In addition, by reducing the number of photolithography processes, the process can be simplified and the yield can be improved. In addition, by reducing the number of photolithography processes, the mask cost can be reduced. [0363] á1-9. Manufacturing method of display device 3ñ Referring to Figures 30A to 32C, a manufacturing method of the transistor 100C, the transistor 200C, the capacitor 250C and the connecting portion 150C included in the display device of an embodiment of the present invention shown in Figures 4A, 4B and 4C is described. In the display device shown in Figures 4A, 4B and 4C, the process up to the formation of the insulating film 118 is carried out in the same manner as the display device shown in Figures 1A, 1B and 1C. [0364] Next, an insulating film 119 is formed on the insulating film 118 (refer to Figures 30A, 30B and 30C). The insulating film 119 has an opening 242 in a region overlapping with the conductive film 212b. The insulating film 119 has an opening 142 in the area overlapping with the conductive film 113. The insulating film 119 has an opening 144 in the area overlapping with the conductive film 115a. [0365] The insulating film 119 can be formed by coating a photosensitive resin on the insulating film 118, and then exposing and developing. Alternatively, a non-photosensitive resin is coated on the insulating film 118 and then fired. Next, a photoresist mask is formed, and the fired non-photosensitive resin is etched using the photoresist mask to form the insulating film 119. The process for forming the insulating film 119 is a third photolithography process. [0366] Next, using the insulating film 119 as a mask, a portion of the insulating film 106, the insulating film 114, the insulating film 116, and the insulating film 118 is removed (see FIGS. 31A, 31B, and 31C). The insulating film 114, the insulating film 116, and the insulating film 118 in the area overlapping with the opening 242 are removed to expose the conductive film 212b to form the opening 242c. The insulating film 106, the insulating film 114, the insulating film 116, and the insulating film 118 in the area overlapping with the opening 142 are removed to expose the conductive film 113 to form the opening 142c. The insulating film 114, the insulating film 116, and the insulating film 118 in the area overlapping the opening 144 are removed to expose the conductive film 115a, thereby forming the opening 144c. [0367] When forming the opening 242c, the opening 142c, and the opening 144c, dry etching can be used. Alternatively, wet etching can be used. Dry etching and wet etching can also be combined. [0368] When forming the openings 242c, 142c, and 144c, it is preferred that the etching rates of the insulating films 106, 114, 116, and 118 be high, while the etching rates of the conductive films 212b, 113, 115a, and 132a be low. In addition, the etching rate of the insulating film 119 is preferably low. [0369] When forming the openings 242c, 142c, and 144c, the thickness of the insulating film 119 may become thinner. The film thickness when forming the insulating film 119 may be set in consideration of the thinned thickness. [0370] Next, a conductive film is formed on the insulating film 119, the opening 242c, the opening 142c, and the opening 144c. The conductive film will become the conductive film 220, the conductive film 120a used as the fourth wiring, and the conductive film 120b used as the first wiring. [0371] The conductive film is processed by using a photolithography process and an etching process to form the conductive film 220, the conductive film 120a used as the fourth wiring, and the conductive film 120b used as the first wiring (refer to Figures 32A, 32B, and 32C). By forming the conductive film 120a, the conductive film 113 is electrically connected to the conductive film 115a. [0372] The process of forming the conductive film 220, the conductive film 120a used as the fourth wiring, and the conductive film 120b used as the first wiring is a fourth photolithography process. [0373] In this way, by performing four photolithography processes, the display device shown in Figures 4A, 4B, and 4C can be manufactured. [0374] In addition, in the present embodiment, the metal oxide film 228, the metal oxide film 208, the metal oxide film 108, the metal oxide film 128, the conductive film 215a, the conductive film 212a, the conductive film 212b, the conductive film 112a, the conductive film 112b, and the conductive film 115a are formed by a single photolithography process. The formation of the metal oxide film 228, the metal oxide film 208, the metal oxide film 108 and the metal oxide film 128 and the formation of the conductive film 215a, the conductive film 212a, the conductive film 212b, the conductive film 112a, the conductive film 112b and the conductive film 115a can also be performed by different photolithography processes. When they are formed by different photolithography processes, the display device shown in Figures 4A, 4B and 4C can be formed by five photolithography processes. [0375] In one embodiment of the present invention, a display device can be manufactured by fewer (four or five) photolithography processes. By reducing the number of photolithography processes, the area for configuring the pattern can be reduced, and miniaturization of transistors and high definition of the display device can be achieved. In addition, by reducing the number of photolithography processes, the process can be simplified and the yield can be improved. In addition, by reducing the number of photolithography processes, the mask cost can be reduced. [0376] á1-10. Manufacturing method of display device 4ñ Referring to Figures 33A to 41C, a manufacturing method of the transistor 100D, the transistor 200D, the capacitor 250D and the connecting portion 150D included in the display device of an embodiment of the present invention shown in Figures 6A, 6B and 6C is described. [0377] Figures 33A to 41C are cross-sectional views illustrating the manufacturing method of the display device. In the cross-sectional views of FIGS. 33A to 41C , the direction of dotted line X1-X2 is the channel length direction of transistor 200D, and the direction of dotted line X3-X4 is the channel length direction of transistor 100D. The direction of dotted line Y1-Y2 is the channel width direction of transistor 100D. [0378] In the display device shown in FIGS. 6A , 6B and 6C , the process is performed until the metal oxide film 108 a and the metal oxide film 108 b are formed in the same manner as the display device shown in FIGS. 1A , 1B and 1C . [0379] Next, the metal oxide film 108 and the insulating film 106 are processed by a photolithography process and an etching process to form an opening 160 in the area overlapping with the conductive film 113 (refer to Figures 33A, 33B and 33C). In the opening 160, the conductive film 113 is exposed. The process of forming the opening 160 is a second photolithography process. [0380] Next, the conductive film 112 is formed on the metal oxide 108. Next, a photoresist mask 251, a photoresist mask 253, a photoresist mask 151 and a photoresist mask 153 are formed on the conductive film 112 by a third photolithography process (refer to Figures 34A, 34B and 34C). The process of forming the photoresist mask 251, the photoresist mask 253, the photoresist mask 151 and the photoresist mask 153 is a third photolithography process. [0381] In the present embodiment, as the conductive film 112, a titanium film with a thickness of 30 nm, a copper film with a thickness of 200 nm, and a titanium film with a thickness of 10 nm are sequentially formed by a sputtering method. [0382] The photoresist mask 253 has a region 255 where the thickness of the photoresist is thin in the region overlapping with the conductive film 204. The region 255 can also be referred to as a recess. The photoresist mask 151 has a region 155 where the thickness of the photoresist is thin in the region overlapping with the conductive film 104. The region 155 can also be referred to as a recess. In the present embodiment, exposure using a multi-tone (high grayscale) mask is used when forming a photoresist mask. By using a multi-tone (high grayscale) mask, a photoresist mask having different thicknesses of the photoresist can be formed. [0383] By developing after exposure using a multi-tone mask, a photoresist mask having areas of different thicknesses as shown in FIGS. 34A, 34B, and 34C can be formed. [0384] Note that although an example in which two types of photoresist thicknesses are shown as a multi-tone mask, an embodiment of the present invention is not limited to this. By using a diffraction grating portion 18 or a semi-transparent film 23 having multiple light transmittances, a photoresist having three or more thicknesses can be formed. [0385] Next, the conductive film 112 and a portion of the metal oxide film 108 are removed using the photoresist mask 251, the photoresist mask 253, the photoresist mask 151, and the photoresist mask 153 as masks to form the conductive film 215, the conductive film 212A, the conductive film 112A, the conductive film 115, the metal oxide film 228, the metal oxide film 208, the metal oxide film 108, and the metal oxide film 128 (refer to Figures 35A, 35B, and 35C). [0386] When processing the conductive film 112, wet etching can be used. However, the processing method is not limited to this, and for example, dry etching can also be used. When processing the metal oxide film 108b, wet etching can be used. However, the processing method is not limited to this, and for example, dry etching can also be used. [0387] Different etching methods may be used when processing the conductive film 112, the metal oxide film 108a, and the metal oxide film 108b. For example, dry etching may be used when processing the conductive film 112, while wet etching may be used when processing the metal oxide film 108a and the metal oxide film 108b. [0388] Next, the photoresist mask 251, the photoresist mask 253, the photoresist mask 151, and a portion of the photoresist mask 153 are removed to reduce the area of the photoresist mask. By reducing the area of the photoresist mask, photoresist mask 251a, photoresist mask 253a, photoresist mask 253b, photoresist mask 151a, photoresist mask 151b and photoresist mask 153a are formed (refer to Figures 36A, 36B and 36C). [0389] When removing a portion of the photoresist mask, an ashing device can be used. Through the ashing process, while the area of the photoresist mask is reduced, the thickness of the photoresist mask is sometimes reduced. [0390] For example, as an ashing process, a photoexcited ashing process can be used, in which light such as ultraviolet rays is irradiated on a gas such as oxygen or ozone to cause a chemical reaction between the gas and organic matter to remove the organic matter. In addition, plasma ashing can be used as an ashing process, in which a gas such as oxygen or ozone is plasmatized by high frequency or the like, and the plasma is used to remove organic matter. [0391] The photoresist in the thin region 255 of the photoresist mask 253 and the thin region 155 of the photoresist mask 151 are removed by the above-mentioned ashing process, thereby separating the photoresist masks from each other as shown in Figures 36A, 36B and 36C. By removing a part of the photoresist mask, the photoresist mask in the region 255a overlapping with the conductive film 204 is removed to expose the conductive film 212A in the region 255a. In addition, the photoresist mask in the region 155a overlapping with the conductive film 104 is removed to expose the conductive film 112A in the region 155a. [0392] The end of the photoresist mask 251a is located inside the end of the conductive film 215. The ends of the photoresist mask 253a and the photoresist mask 253b are located inside the end of the conductive film 212A. The ends of the photoresist mask 151a and the photoresist mask 151b are located inside the end of the conductive film 112A. The end of the photoresist mask 153a is located inside the end of the conductive film 115. [0393] Next, using photoresist mask 251a, photoresist mask 253a, photoresist mask 253b, photoresist mask 151a, photoresist mask 151b, and photoresist mask 153a as masks, a portion of conductive film 215, conductive film 212A, conductive film 112A, and conductive film 115 are removed to form conductive film 215a, conductive film 212a, conductive film 212b, conductive film 112a, conductive film 112b, and conductive film 115a (refer to FIGS. 37A, 37B, and 37C). [0394] The end of conductive film 215a is located on the inner side of the end of metal oxide film 228. The end of conductive film 212a and conductive film 212b are located on the inner side of the end of metal oxide film 208. The ends of the conductive film 112a and the conductive film 112b are located on the inner side of the end of the metal oxide film 108. The end of the conductive film 115a is located on the inner side of the end of the metal oxide film 128. [0395] Next, the photoresist mask 251a, the photoresist mask 253a, the photoresist mask 253b, the photoresist mask 151a, the photoresist mask 151b, and the photoresist mask 153a are removed. [0396] After removing the photoresist mask, the surface (back channel side) of the metal oxide film 108, the metal oxide film 128, the metal oxide film 208, and the metal oxide film 228 (more specifically, the metal oxide film 108_2, the metal oxide film 128_2, the metal oxide film 208_2, and the metal oxide film 228_2) may also be washed. As a washing method, for example, washing using a chemical solution such as phosphoric acid can be cited. By washing using a chemical solution such as phosphoric acid, impurities (for example, elements contained in the conductive films 112a, 112b, 212a, and 212b) attached to the surfaces of the metal oxide films 108_2, 128_2, 208_2, and 228_2 can be removed. Note that this washing is not necessarily required and may not be performed depending on circumstances. [0397] In addition, in the formation process of the conductive film 112a, the conductive film 112b, the conductive film 212a, and the conductive film 212b and/or the above-mentioned washing process, the region of the metal oxide film 108 and the metal oxide film 208 exposed from the conductive film 112a, the conductive film 112b, the conductive film 212a, and the conductive film 212b sometimes becomes thinner. [0398] In addition, the region of the metal oxide film 108 and the metal oxide film 208 exposed, that is, the metal oxide film 108_2 and the metal oxide film 208_2 is preferably a metal oxide film whose crystallinity is improved. The highly crystalline metal oxide film has a structure in which impurities (especially constituent elements used for the conductive film 112a, the conductive film 112b, the conductive film 212a, and the conductive film 212b) are not easily diffused into the film. Therefore, a highly reliable transistor can be manufactured. [0399] In addition, in FIG. 37A, FIG. 37B, and FIG. 37C, although the surfaces of the metal oxide film 108, the metal oxide film 128, the metal oxide film 208, and the metal oxide film 228 exposed from the conductive film 112a, the conductive film 112b, the conductive film 115a, the conductive film 212a, the conductive film 212b, and the conductive film 215a are shown, that is, the metal oxide film 108_2, the metal oxide film 128_2, The surfaces of the metal oxide film 208_2 and the metal oxide film 228_2 have recesses, but the present invention is not limited to this. The surfaces of the metal oxide film 108, the metal oxide film 128, the metal oxide film 208, and the metal oxide film 228 exposed from the conductive film 112a, the conductive film 112b, the conductive film 115a, the conductive film 212a, the conductive film 212b, and the conductive film 215a may not have recesses. [0400] Next, insulating films 114, 116, and 118 are formed on insulating film 106, metal oxide film 108, metal oxide film 128, metal oxide film 208, metal oxide film 228, conductive film 215a, conductive film 212a, conductive film 212b, conductive film 112a, conductive film 112b, and conductive film 115a (see FIGS. 38A, 38B, and 38C). [0401] Since the method for forming insulating film 114, insulating film 116, and insulating film 118 can refer to the above description, detailed description is omitted. [0402] Here, it is preferred to continuously form the insulating film 116 without exposing it to the atmosphere after forming the insulating film 114. By continuously forming the insulating film 116 by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas without exposing it to the atmosphere after forming the insulating film 114, the impurity concentration from the atmospheric components at the interface between the insulating film 114 and the insulating film 116 can be reduced. [0403] Here, it is preferred to continuously form the insulating film 118 without exposing it to the atmosphere after forming the insulating film 116. By continuously forming the insulating film 118 by adjusting one or more of the flow rate, pressure, high-frequency power and substrate temperature of the source gas in a manner that is not exposed to the atmosphere after forming the insulating film 116, it is possible to reduce the concentration of impurities from atmospheric components at the interface between the insulating film 116 and the insulating film 118. [0404] In addition, a heat treatment equivalent to the above-mentioned first heat treatment and second heat treatment (hereinafter referred to as the third heat treatment) may be performed after forming the insulating film 118. [0405] By performing the third heat treatment, the oxygen contained in the insulating film 116 moves to the metal oxide films 108 and 208, filling the oxygen defects in the metal oxide films 108 and 208. [0406] Next, an insulating film 119 is formed on the insulating film 118 by a fourth photolithography process (see FIGS. 39A, 39B, and 39C). The insulating film 119 includes an opening 242 in a region overlapping with the conductive film 212b. The insulating film 119 includes a thin region 157 in a region overlapping with the conductive film 104 and the metal oxide film 108. The region 157 may also be referred to as a recess. The insulating film 119 includes an opening 146 in a region overlapping with the conductive film 104 and not overlapping with the metal oxide film 108. In the present embodiment, when forming the insulating film 119, exposure using a multi-tone (high grayscale) mask is employed. By using a multi-tone (high grayscale) mask, an insulating film 119 including regions of different thicknesses can be formed. [0407] A photosensitive resin is applied to the insulating film 118, and then exposed and developed to form the insulating film 119. Alternatively, a non-photosensitive resin is applied to the insulating film 118 and then fired. Next, a photoresist mask is formed, and the fired non-photosensitive resin is etched using the photoresist mask to form the insulating film 119. [0408] Next, using the insulating film 119 as a mask, a portion of the insulating film 106, the insulating film 114, the insulating film 116, and the insulating film 118 is removed (see FIGS. 40A, 40B, and 40C). The insulating film 114, the insulating film 116, and the insulating film 118 in the region overlapping with the opening 242 are removed to expose the conductive film 212b, thereby forming an opening 242d. The insulating film 106, the insulating film 114, the insulating film 116, and the insulating film 118 in the region overlapping with the opening 146 are removed to expose the conductive film 104, thereby forming an opening 146d. When a portion of the insulating film 106, the insulating film 114, the insulating film 116, and the insulating film 118 are removed, a portion of the insulating film 119 is also removed. The insulating film 119 in the region 157 is removed to expose the insulating film 118 to form the opening 142d. [0409] When forming the opening 242d, the opening 142d, and the opening 146d, a dry etching method may be used. Alternatively, a wet etching method may be used. A combination of the dry etching method and the wet etching method may also be used. [0410] When forming the openings 242d, 142d, and 146d, it is preferred that the etching rates of the insulating films 106, 114, 116, and 118 be higher, while the etching rates of the conductive films 212b, 113, and 115a be lower. [0411] When forming the openings 242d, 142d, and 146d, the thickness of the insulating film 119 may become thinner. The film thickness of the insulating film 119 may be set in consideration of the thinned thickness when forming the insulating film 119. [0412] When removing the insulating film 119 in the region 157, an ashing process may be used. By ashing, the area of the insulating film 119 is reduced and the thickness of the insulating film 119 is sometimes reduced. The film thickness when forming the insulating film 119 can be set in consideration of the thinned thickness. [0413] Next, a conductive film is formed on the insulating film 119, the opening 242a, the opening 142d and the opening 146d. The conductive film is processed into a desired shape to form a conductive film 220 and a conductive film 130d (refer to Figures 41A, 41B and 41C). The process for forming the conductive film 220 and the conductive film 130d is a fifth light lithography process. [0414] The conductive film 220 and the conductive film 130d can use a light-transmitting conductive film. The light-transmitting conductive film can be formed using conductive materials such as indium tin oxide, indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide containing silicon oxide. [0415] In addition, when the conductive film 220 and the conductive film 130d are formed using an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]), when the insulating film 118 is formed, hydrogen and/or nitrogen contained in the insulating film 118 sometimes enter the conductive film 220 and the conductive film 130d. At this time, hydrogen and/or nitrogen are bonded to oxygen defects in the conductive film 220 and the conductive film 130d to reduce the resistance of the conductive film 220 and the conductive film 130d. Thus, a low-resistance conductive film 220 and a conductive film 130d can be formed. The low-resistance conductive film is an oxide conductive film. [0416] A sputtering device can be used when forming the conductive film 220 and the conductive film 130d. When forming the conductive film 220 and the conductive film 130d, plasma discharge is performed in an atmosphere containing oxygen gas. At this time, oxygen is added to the insulating film 118 in which the conductive film 220 and the conductive film 130d are formed. The atmosphere when forming the conductive film 220 and the conductive film 130d can be mixed with an inert gas (for example, helium gas, argon gas, xenon gas, etc.) in addition to oxygen gas. [0417] The oxygen gas is at least contained in the deposition gas when forming the conductive film 220 and the conductive film 130d, and the ratio of the oxygen gas in the entire deposition gas when forming the conductive film 220 and the conductive film 130d is higher than 0% and lower than 100%, preferably higher than 10% and lower than 100%, and more preferably higher than 30% and lower than 100%. [0418] In the present embodiment, the conductive film 220 and the conductive film 130d are formed by a sputtering method using an In-Ga-Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). In addition, the conductive film 220 and the conductive film 130d can also be formed by a sputtering method using an ITO target and 100% oxygen gas as the deposition gas. [0419] Note that although the present embodiment shows a method of adding oxygen to the insulating film 116 when forming the conductive film 220 and the conductive film 130d, the present invention is not limited to this. For example, oxygen may be added to the insulating film 116 after the conductive film 220 and the conductive film 130d are formed. [0420] In order to add oxygen to the insulating film 116, for example, an oxide target (In-Sn-Si oxide, also referred to as ITSO) containing indium, tin, and silicon may be used.2 O3 ：SnO2 ：SiO2=85:10:5 [wt%]) to form an ITSO film with a thickness of 5nm. At this time, when the thickness of the ITSO film is greater than 1nm and less than 20nm, or greater than 2nm and less than 10nm, it is better because oxygen can be properly transmitted and the release of oxygen can be suppressed. Then, oxygen is added to the insulating film 116 through the ITSO film. As a method for adding oxygen, ion doping, ion implantation, plasma treatment, etc. can be cited. When adding oxygen, oxygen can be effectively added to the insulating film 116 by applying a bias to one side of the substrate. When applying a bias, for example, using an ashing device, the power density of the bias applied to the substrate side of the ashing device can be set to 1W/cm2 Above and 5W/cm2 Below. In addition, by setting the substrate temperature when adding oxygen to be above room temperature and below 300°C, preferably above 100°C and below 250°C, oxygen can be efficiently added to the insulating film 116. [0421] In the present embodiment, wet etching is used to form the conductive film 220 and the conductive film 130d. When forming the conductive film 220 and the conductive film 130d, dry etching can also be used. [0422] In this way, by performing five photolithography processes, the display device shown in Figures 6A, 6B and 6C can be manufactured. [0423] In one embodiment of the present invention, a display device can be manufactured by fewer (five) photolithography processes. By reducing the number of photolithography processes, the area for configuring the pattern can be reduced, and miniaturization of transistors and high definition of display devices can be achieved. In addition, by reducing the number of photolithography processes, simplification of the process and improvement of the yield can be achieved. In addition, by reducing the number of photolithography processes, the mask cost can be reduced. In addition, in the connection portion, by directly connecting the conductive film 113 used as the first wiring and the conductive film 115d used as the second wiring, good contact can be achieved, and the contact resistance can be reduced. [0424] á1-11. Manufacturing method of display device 5ñ Referring to Figures 42A to 44C, a manufacturing method of the transistor 100E, the transistor 200E, the capacitor 250E and the connecting portion 150E included in the display device of an embodiment of the present invention shown in Figures 8A, 8B and 8C is described. In the display device shown in Figures 8A, 8B and 8C, the process is performed until the insulating film 118 is formed in the same manner as the display device shown in Figures 6A, 6B and 6C. [0425] Then, an insulating film 119 is formed on the insulating film 118 by a fourth photolithography process (refer to Figures 42A, 42B and 42C). The insulating film 119 includes an opening 242 in the area overlapping with the conductive film 212b. [0426] The insulating film 119 can be formed by coating a photosensitive resin on the insulating film 118, and then exposing and developing. Alternatively, a non-photosensitive resin can be coated on the insulating film 118 and then fired. Then, a photoresist mask is formed, and the fired non-photosensitive resin is etched using the photoresist mask to form the insulating film 119. [0427] Next, using the insulating film 119 as a mask, a portion of the insulating film 114, the insulating film 116, and the insulating film 118 is removed (refer to Figures 43A, 43B, and 43C). The insulating film 114, the insulating film 116, and the insulating film 118 in the area overlapping the opening 242 are removed to expose the conductive film 212b to form the opening 242e. [0428] When forming the opening 242e, dry etching can be used. Alternatively, wet etching can be used. Dry etching and wet etching can also be combined. [0429] When forming the opening 242e, it is preferred that the etching rate of the insulating film 114, the insulating film 116 and the insulating film 118 is high, while the etching rate of the conductive film 212b is low. In addition, the etching rate of the insulating film 119 is preferably low. [0430] When forming the opening 242e, the thickness of the insulating film 119 sometimes becomes thinner. The film thickness when forming the insulating film 119 can be set in consideration of the thinned thickness. [0431] Next, a conductive film is formed on the insulating film 119 and the opening 242e. The conductive film is processed into a desired shape to form a conductive film 220 (refer to Figures 44A, 44B and 44C). The process for forming the conductive film 220 is a fifth light lithography process. [0432] The conductive film 220 can use a light-transmitting conductive film. The light-transmitting conductive film can be formed using conductive materials such as indium tin oxide, indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide containing silicon oxide. [0433] In the present embodiment, the conductive film 220 is formed using a wet etching method. When forming the conductive film 220, a dry etching method can also be used. [0434] In this way, by performing five photolithography processes, the display device shown in Figures 8A, 8B and 8C can be manufactured. [0435] In one embodiment of the present invention, a display device can be manufactured by fewer (five) photolithography processes. By reducing the number of photolithography processes, the area for configuring the pattern can be reduced, and the miniaturization of the transistor and the high definition of the display device can be achieved. In addition, by reducing the number of photolithography processes, the process can be simplified and the yield can be improved. In addition, by reducing the number of photolithography processes, the mask cost can be reduced. In addition, in the connecting portion, by directly connecting the conductive film 113 used as the first wiring and the conductive film 115a used as the second wiring, good contact can be achieved and the contact resistance can be reduced. [0436] At least a portion of the present embodiment can be implemented in combination with other embodiments described in the present specification as appropriate. [0437] Embodiment 2 In the present embodiment, a metal oxide film of an embodiment of the present invention is described with reference to Figures 47 to 50C. [0438] Structure of CAC-OS The following describes the details of a metal oxide with a CAC structure that can be used in a transistor disclosed in an embodiment of the present invention. Here, CAC-OS is used as a typical example of a metal oxide with a CAC structure for description. [0439] For example, as shown in Figure 47, in CAC-OS, the elements contained in the metal oxide are unevenly distributed, and regions 001 and 002 having each element as a main component are mixed to form or disperse in a mosaic shape. In other words, CAC-OS is a structure in which the elements contained in the metal oxide are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than 0.5nm and less than 10nm, preferably greater than 0.5nm and less than 3nm or a similar size. [0440] The physical properties of the region containing a specific element that is unevenly distributed are determined by the properties of the element. For example, a region containing an element that is more likely to become an insulator among the unevenly distributed elements contained in the metal oxide becomes a dielectric region. On the other hand, a region containing an element that is more likely to become a conductor among the unevenly distributed elements contained in the metal oxide becomes a conductor region. When the conductor region and the dielectric region are mixed in a mosaic shape, the material has the function of a semiconductor. [0441] In other words, the metal oxide in one embodiment of the present invention is a matrix composite or a metal matrix composite in which materials having different physical properties are mixed. [0442] The oxide semiconductor preferably contains at least indium. In particular, it is preferably containing indium and zinc. In addition, it may also contain element M (M is one or more selected from gallium, aluminum, silicon, boron, yttrium, copper, vanadium, curium, titanium, iron, nickel, germanium, zirconium, molybdenum, ruthenium, neodymium, uranium, tungsten and magnesium). For example, CAC-OS in In-Ga-Zn oxide (in CAC-OS, In-Ga-Zn oxide can be referred to as CAC-IGZO in particular) means that the material is divided into indium oxide (hereinafter referred to as InOX1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter referred to as InX2 ZnY2 OZ2 (X2, Y2 and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter referred to as GaOX3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as GaX4 ZnY4 OZ4 (X4, Y4 and Z4 are real numbers greater than 0)) etc. to form a mosaic, and the mosaic-shaped InOX1 or InX2 ZnY2 OZ2 A structure uniformly distributed in the film (hereinafter also referred to as a cloud shape). [0444] In other words, CAC-OS is a GaOX3 areas with In as the main componentX2 ZnY2 OZ2 or InOX1 is a composite oxide semiconductor composed of regions with as the main components. In this specification, for example, when the atomic number ratio of In to element M in the first region is greater than the atomic number ratio of In to element M in the second region, the In concentration in the first region is higher than that in the second region. [0445] Note that IGZO is a general term and sometimes refers to a compound containing In, Ga, Zn and O. As a typical example, InGaO3 (ZnO)m1 (m1 is a natural number) or In(1+x0) Ga(1-x0) O3 (ZnO)m0 (-1 ≤x0≤1, m0 is an arbitrary number). [0446] The above-mentioned crystalline compound has a single crystal structure, a polycrystalline structure or a CAAC structure. The CAAC structure is a crystal structure in which multiple IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the a-b plane. [0447] On the other hand, CAC-OS is related to the material composition of oxide semiconductors. CAC-OS refers to the following composition: in a material composition containing In, Ga, Zn and O, nanoparticle-like regions with Ga as the main component are observed in a part, and nanoparticle-like regions with In as the main component are observed in a part, and these regions are randomly dispersed in a mosaic shape. Therefore, in CAC-OS, the crystal structure is a secondary factor. [0448] CAC-OS does not include a stacked structure of two or more films with different compositions. For example, a structure consisting of two layers of a film containing In as a main component and a film containing Ga as a main component is not included. [0449] Note that sometimes no GaO is observed.X3 areas with In as the main componentX2 ZnY2 OZ2 or InOX1 is a clear boundary between regions with In as the main component. [0450] When CAC-OS includes one or more selected from aluminum, silicon, boron, yttrium, copper, vanadium, curium, titanium, iron, nickel, germanium, zirconium, molybdenum, lumber, arsenic, neodymium, tungsten, and magnesium instead of gallium, CAC-OS refers to a structure in which nanoparticle-like regions with the element as the main component are observed in one part, and nanoparticle-like regions with In as the main component are observed in another part, and these regions are randomly dispersed in a mosaic shape. [0451] áAnalysis of CAC-OSñ Next, the results of measuring the oxide semiconductor formed on the substrate using various measurement methods are described. [0452] Structure and manufacturing method of samples áá Nine samples of an embodiment of the present invention are described below. Each sample differs in substrate temperature and oxygen gas flow ratio when forming an oxide semiconductor. Each sample includes a substrate and an oxide semiconductor on the substrate. [0453] The manufacturing method of each sample is described. [0454] A glass substrate is used as a substrate. A sputtering device is used to form an In-Ga-Zn oxide with a thickness of 100 nm as an oxide semiconductor on the glass substrate. The film forming conditions are as follows: the pressure in the processing chamber is set to 0.6 Pa, and an oxide target (In:Ga:Zn=4:2:4.1 [atomic number ratio]) is used as a target. In addition, 2500 W of AC power is supplied to the oxide target set in the sputtering device. [0455] Nine samples were manufactured under the following conditions when forming oxides: the substrate temperature was set to a temperature when no intentional heating was performed (hereinafter, also referred to as room temperature or R.T.), 130°C or 170°C. In addition, the flow ratio of oxygen gas to the mixed gas of Ar and oxygen (hereinafter, also referred to as oxygen gas flow ratio) was set to 10%, 30% or 100%. [0456] ááX-ray Diffraction Analysisññ In this section, the results of X-ray diffraction (XRD) measurement of nine samples are described. As the XRD device, D8 ADVANCE manufactured by Bruker was used. The measurement conditions are as follows: q/2q scanning is performed using the Out-of-plane method, the scanning range is 15 degrees to 50 degrees, the step width is 0.02 degrees, and the scanning speed is 3.0 degrees per minute. [0457] FIG. 48 shows the results of measuring the XRD spectrum using the Out-of-plane method. In FIG. 48, the top row shows the measurement results of the sample whose substrate temperature during film formation is 170 degrees Celsius, the middle row shows the measurement results of the sample whose substrate temperature during film formation is 130 degrees Celsius, and the bottom row shows the measurement results of the sample whose substrate temperature during film formation is R.T. In addition, the leftmost column shows the measurement results of the sample with an oxygen gas flow ratio of 10%, the middle column shows the measurement results of the sample with an oxygen gas flow ratio of 30%, and the rightmost column shows the measurement results of the sample with an oxygen gas flow ratio of 100%. [0458] In the XRD spectrum shown in Figure 48, the higher the substrate temperature during film formation or the higher the oxygen gas flow ratio during film formation, the greater the peak intensity near 2q=31°. In addition, it is known that the peak near 2q=31° originates from a crystalline IGZO compound (also called CAAC (c-axis aligned crystalline)-IGZO) having a c-axis orientation in a direction approximately perpendicular to the formed surface or top surface. [0459] In addition, as shown in the XRD spectrum of Figure 48, the lower the substrate temperature during film formation or the lower the oxygen gas flow ratio, the less obvious the peak. Therefore, it can be seen that in samples in which the substrate temperature during film formation is low or the oxygen gas flow ratio is low, the orientation in the a-b plane direction and the c-axis direction of the measured area cannot be observed. [0460] áá Electron Microscope Analysisññ In this section, the results of observation and analysis using HAADF-STEM (High-Angle Annular Dark Field Scanning Transmission Electron Microscope) of samples manufactured under the conditions of a substrate temperature of R.T. during film formation and an oxygen gas flow ratio of 10% are described (hereinafter, images obtained using HAADF-STEM will also be referred to as TEM images). [0461] The results of image analysis of planar images (hereinafter, also referred to as planar TEM images) and cross-sectional images (hereinafter, also referred to as cross-sectional TEM images) obtained using HAADF-STEM are described. TEM images were observed using the spherical aberration correction function. When acquiring HAADF-STEM images, an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd. was used, the accelerating voltage was set to 200 kV, and an electron beam with a diameter of approximately 0.1 nm was irradiated. [0462] FIG. 49A is a planar TEM image of a sample produced under the conditions of a substrate temperature of R.T. and an oxygen gas flow ratio of 10% during film formation. FIG. 49B is a cross-sectional TEM image of a sample produced under the conditions of a substrate temperature of R.T. and an oxygen gas flow ratio of 10% during film formation. [0463] Analysis of electron diffraction pattern In this section, the results of obtaining electron diffraction pattern by irradiating a sample manufactured under the conditions of substrate temperature of R.T. and oxygen gas flow rate of 10% during film formation with an electron beam (also called nanobeam) having a diameter of 1 nm are described. [0464] The electron diffraction patterns of black dots a1, a2, a3, a4, and a5 in the planar TEM image of the sample manufactured under the conditions of substrate temperature of R.T. and oxygen gas flow rate of 10% during film formation shown in FIG. 49A are observed. The observation of the electron diffraction pattern is performed by irradiating the electron beam at a fixed speed for 35 seconds. FIG49C shows the result of black spot a1, FIG49D shows the result of black spot a2, FIG49E shows the result of black spot a3, FIG49F shows the result of black spot a4, and FIG49G shows the result of black spot a5. [0465] In FIG49C, FIG49D, FIG49E, FIG49F and FIG49G, a circle-like (ring-shaped) area with high brightness is observed. In addition, a plurality of spots are observed in the ring-shaped area. [0466] The electron diffraction patterns of black spot b1, black spot b2, black spot b3, black spot b4 and black spot b5 in the cross-sectional TEM image of the sample manufactured under the conditions of the substrate temperature of R.T. during film formation and the oxygen gas flow ratio of 10% shown in FIG49B are observed. FIG49H shows the result of black dot b1, FIG49I shows the result of black dot b2, FIG49J shows the result of black dot b3, FIG49K shows the result of black dot b4, and FIG49L shows the result of black dot b5. [0467] In FIG49H, FIG49I, FIG49J, FIG49K, and FIG49L, a ring-shaped area with high brightness is observed. In addition, a plurality of spots are observed in the ring-shaped area. [0468] For example, when the InGaZnO4 When a 300nm diameter electron beam is incident on the crystallized CAAC-OS in a direction parallel to the sample surface, the4 Diffraction pattern of spots on the (009) plane of the crystal. In other words, CAAC-OS has a c-axis orientation, and the c-axis is oriented approximately perpendicular to the direction of the formed surface or top surface. On the other hand, when an electron beam with a diameter of 300nm is incident on the same sample in a direction perpendicular to the sample surface, a ring-shaped diffraction pattern is confirmed. In other words, CAAC-OS does not have an a-axis orientation and a b-axis orientation. [0469] When electron diffraction is performed on an oxide semiconductor having microcrystals (nano crystalline oxide semiconductor, hereinafter referred to as nc-OS) using an electron beam with a large diameter (for example, 50nm or more), a diffraction pattern similar to a halo pattern is observed. In addition, when nanobeam electron diffraction is performed on nc-OS using an electron beam of a small diameter (for example, less than 50 nm), bright spots (spots) are observed. In addition, in the nanobeam electron diffraction pattern of nc-OS, a high brightness area such as a circle (annular) is sometimes observed. Moreover, multiple bright spots are sometimes observed in the annular area. [0470] The electron diffraction pattern of the sample manufactured under the conditions of the substrate temperature of R.T. during film formation and the oxygen gas flow ratio of 10% has an annular high brightness area and multiple bright spots appear in the annular area. Therefore, the sample manufactured under the conditions of the substrate temperature being R.T. during film formation and the oxygen gas flow ratio being 10% exhibits an electron diffraction pattern similar to that of nc-OS, and has no orientation in the plane direction and the cross-sectional direction. [0471] As described above, the properties of oxide semiconductors manufactured under the conditions of low substrate temperature or low oxygen gas flow ratio during film formation are significantly different from those of oxide semiconductor films with an amorphous structure and oxide semiconductor films with a single crystal structure. [0472] ááElemental Analysisññ In this section, the results of elemental analysis of samples manufactured under the conditions of the substrate temperature being R.T. during film formation and the oxygen gas flow ratio being 10% are described by obtaining and evaluating EDX surface analysis images using energy dispersive X-ray spectroscopy (EDX). In the EDX measurement, an energy dispersive X-ray analyzer JED-2300T manufactured by JEOL Ltd. is used as an elemental analysis device. When detecting X-rays emitted from a sample, a silicon drift detector is used. [0473] In the EDX measurement, an electron beam is irradiated to each point in the target area of analysis of the sample, and the energy and frequency of the characteristic X-rays of the sample generated at this time are measured to obtain an EDX spectrum corresponding to each point. In the present embodiment, the peak of the EDX spectrum at each point is attributed to the electron transition to the L shell layer in the In atom, the electron transition to the K shell layer in the Ga atom, the electron transition to the K shell layer in the Zn atom, and the electron transition to the K shell layer in the O atom, and the ratio of each atom at each point is calculated. By performing the above steps in the analysis target area of the sample, an EDX surface analysis image showing the ratio distribution of each atom can be obtained. [0474] Figures 50A, 50B and 50C show EDX surface analysis images of a cross-section of a sample manufactured under the conditions that the substrate temperature during film formation is R.T. and the oxygen gas flow ratio is 10%. FIG. 50A shows an EDX surface analysis image of Ga atoms (the ratio of Ga atoms to all atoms is 1.18 to 18.64 [atomic%]). FIG. 50B shows an EDX surface analysis image of In atoms (the ratio of In atoms to all atoms is 9.28 to 33.74 [atomic%]). FIG. 50C shows an EDX surface analysis image of Zn atoms (the ratio of Zn atoms to all atoms is 6.69 to 24.99 [atomic%]). In addition, FIG. 50A, FIG. 50B and FIG. 50C show the same region in the cross section of a sample produced under the conditions that the substrate temperature during film formation is R.T. and the oxygen gas flow ratio is 10%. In the EDX surface analysis image, the ratio of elements is represented by light and dark: the more the measured element in the region, the brighter the region, and the less the measured element, the darker the region. The EDX surface analysis images shown in FIG50A, FIG50B and FIG50C have a magnification of 7.2 million times. [0475] In the EDX surface analysis images shown in FIG50A, FIG50B and FIG50C, the relative distribution of light and dark is confirmed, and it is confirmed that each atom has a distribution in the sample manufactured under the conditions that the substrate temperature during film formation is R.T. and the oxygen gas flow ratio is 10%. Here, the focus is on the areas surrounded by solid lines and the areas surrounded by dotted lines shown in FIG50A, FIG50B and FIG50C. [0476] In FIG50A, there are more relatively dark areas in the area surrounded by solid lines, and there are more relatively bright areas in the area surrounded by dotted lines. In addition, in FIG. 50B , there are more relatively bright areas in the area surrounded by solid lines, and there are more relatively dark areas in the area surrounded by dotted lines. [0477] In other words, the area surrounded by solid lines is an area with relatively more In atoms, and the area surrounded by dotted lines is an area with relatively fewer In atoms. In FIG. 50C , in the area surrounded by solid lines, the right side is a relatively bright area, and the left side is a relatively dark area. Therefore, the area surrounded by solid lines is an area with relatively more In atoms.X2 ZnY2 OZ2 or InOX1 areas with GaO as the main components. [0478] In addition, the area surrounded by the solid line is an area with relatively fewer Ga atoms, and the area surrounded by the dotted line is an area with relatively more Ga atoms. In FIG50C, in the area surrounded by the dotted line, the upper left area is a relatively bright area, and the lower right area is a relatively dark area. Therefore, the area surrounded by the dotted line is a region with GaOX3 or GaX4 ZnY4 OZ4 areas with InO as the main components. [0479] As shown in FIG. 50A, FIG. 50B and FIG. 50C, the distribution of In atoms is more uniform than that of Ga atoms, with InOX1 areas with InX2 ZnY2 OZ2 areas with the main components connected to each other.X2 ZnY2 OZ2 or InOX1 areas with GaO as the main component are formed in a cloud-like shape. [0480] In this way, theX3 areas with In as the main componentsX2 ZnY2 OZ2 or InOX1 In-Ga-Zn oxides in which the main components are unevenly distributed in the region and mixed are called CAC-OS. [0481] The crystal structure of CAC-OS has an nc structure. In the electron diffraction pattern of CAC-OS having an nc structure, in addition to the bright spots (spots) caused by IGZO containing a single crystal, polycrystalline or CAAC structure, multiple bright spots (spots) appear. Alternatively, the crystal structure is defined as a ring-shaped high brightness area in addition to the multiple bright spots (spots). [0482] In addition, as shown in Figures 50A, 50B and 50C, the GaOX3 areas with In as the main componentsX2 ZnY2 OZ2 or InOX1 as the main component is greater than 0.5nm and less than 10nm or greater than 1nm and less than 3nm. In the EDX surface analysis image, the diameter of the region with each element as the main component is preferably greater than 1nm and less than 2nm. [0483] As described above, the structure of CAC-OS is different from that of IGZO compounds in which metal elements are uniformly distributed, and it has different properties from IGZO compounds. In other words, CAC-OS has a GaOX3 areas with In as the main componentsX2 ZnY2 OZ2 or InOX1 areas with In as the main component are separated from each other and the areas with each element as the main component are in a mosaic-like structure.X2 ZnY2 OZ2 or InOX1The conductivity of the area with GaO as the main component is higher than that of the area with GaO as the main component.X3In other words, when carriers flow through a region with InX2 ZnY2 OZ2 or InOX1 as the main component, it exhibits the conductivity of an oxide semiconductor.X2 ZnY2 OZ2 or InOX1 When the region with GaO as the main component is distributed in a cloud-like manner in an oxide semiconductor, a high field-effective mobility (m) can be achieved. [0485] On the other hand,X3 The insulation of the area with In as the main component is higher than that of the area with InX2 ZnY2 OZ2 or InOX1In other words, when GaOX3 When the region with GaO as the main component is distributed in the oxide semiconductor, the leakage current can be suppressed and good switching operation can be achieved. [0486] Therefore, when CAC-OS is used in semiconductor devices, theX3 Insulation and its origin in InX2 ZnY2 OZ2 or InOX1The complementary effect of the conductivity can achieve high on-state current (Ion ) and high field-effect mobility (m). [0487] In addition, semiconductor elements using CAC-OS have high reliability. Therefore, CAC-OS is suitable for various semiconductor devices such as displays. [0488] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification as appropriate. [0489] Transistor having a metal oxide film ñ The following describes the case where the above-mentioned metal oxide film is used for a transistor. [0490] By using the above-mentioned metal oxide film for a transistor, a transistor with high carrier mobility and high switching characteristics can be realized. In addition, a transistor with high reliability can be realized. [0491] In addition, it is preferred to use a metal oxide film with a low carrier density for the transistor. For example, the carrier density of the metal oxide film can be lower than 8´1011 /cm3 , preferably less than 1´1011 /cm3 , preferably less than 1´1010 /cm3 and 1´10-9 /cm3 The above. [0492] In the case of reducing the carrier density of the metal oxide film, the impurity concentration in the metal oxide film is reduced to reduce the defect state density. In this specification, etc., the state of low impurity concentration and low defect state density is referred to as "high purity nature" or "substantially high purity nature". Since the carrier generation sources of the metal oxide film of high purity nature or substantially high purity nature are fewer, it is possible to reduce the carrier density. In addition, since the metal oxide film of high purity nature or substantially high purity nature has a lower defect state density, it is possible to have a lower trap state density. [0493] In addition, it takes a long time for the charges captured by the trap energy level of the metal oxide film to disappear, and sometimes it behaves like a fixed charge. Therefore, the electrical characteristics of a transistor having a channel region formed in an oxide semiconductor having a high trap state density are sometimes unstable. [0494] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide film. In order to reduce the impurity concentration in the metal oxide film, it is better to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkali earth metals, iron, nickel, silicon, etc. [0495] Here, the influence of each impurity in the metal oxide film is explained. [0496] When the metal oxide film contains silicon or carbon, which is one of the Group 14 elements, a defect energy level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor or near the interface of the oxide semiconductor (measured by secondary ion mass spectrometry (SIMS)) is 2´1018 atoms/cm3 Below, preferably 2´1017 atoms/cm3[0497] In addition, when the metal oxide film contains an alkali metal or an alkali earth metal, a defect energy level is sometimes formed to form a carrier. Therefore, a transistor using a metal oxide film containing an alkali metal or an alkali earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of the alkali metal or the alkali earth metal in the metal oxide film. Specifically, the concentration of the alkali metal or the alkali earth metal in the metal oxide film measured by SIMS analysis is 1´1018 atoms/cm3 Below, preferably 2´1016 atoms/cm3 Below. [0498] When the metal oxide film contains nitrogen, electrons as carriers are generated, and the carrier density increases, and the oxide semiconductor is easily converted to n-type. As a result, the oxide semiconductor containing nitrogen is used for a semiconductor transistor and is likely to have a normally-on characteristic. Therefore, it is preferable to reduce the nitrogen in the oxide semiconductor as much as possible, for example, the nitrogen concentration in the oxide semiconductor measured by SIMS analysis is less than 5´1019 atoms/cm3 , preferably 5´1018 atoms/cm3 Below, preferably 1´1018 atoms/cm3 Below, further preferred is 5'1017 atoms/cm3 Below. [0499] Hydrogen contained in the metal oxide film reacts with oxygen bonded to the metal atom to generate water, thereby sometimes forming oxygen vacancies (Vo ). When hydrogen enters the oxygen vacancy (Vo ), sometimes electrons are generated as carriers. In addition, sometimes electrons are generated as carriers because part of the hydrogen bonds with oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is better to reduce the hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS analysis is less than 1´1020 atoms/cm3 , preferably less than 1´1019 atoms/cm3 , preferably less than 5´1018 atoms/cm3 , preferably less than 1´1018 atoms/cm3[0500] By introducing oxygen into the metal oxide film, the oxygen defects (VoIn other words, when the oxygen vacancies (Vo ) is filled with oxygen, the oxygen vacancy (Vo ) disappears. Therefore, by diffusing oxygen into the metal oxide film, the oxygen vacancies (Vo ), thereby improving the reliability of the transistor. [0501] As a method of introducing oxygen into a metal oxide film, for example, an oxide containing oxygen exceeding the stoichiometric composition can be provided in contact with an oxide semiconductor. That is, it is preferred to form a region containing oxygen exceeding the stoichiometric composition (hereinafter, also referred to as an oxygen excess region) in the above-mentioned oxide. In particular, when a metal oxide film is used for a transistor, by providing an oxide having an oxygen excess region on a base film or an interlayer film near the transistor, the oxygen deficiency of the transistor can be reduced, thereby improving the reliability of the transistor. [0502] By using a metal oxide film with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics. [0503] At least a portion of this embodiment can be implemented in appropriate combination with other embodiments described in this specification. [0504] Embodiment 3 In this embodiment, an example of a display device including the transistor illustrated in the previous embodiment is described using FIGS. 51 to 63. [0505] FIG. 51 is a top view showing an example of a display device. The display device 700 shown in FIG. 51 includes: a pixel portion 702 provided on a first substrate 701; a source drive circuit portion 704 and a gate drive circuit portion 706 provided on the first substrate 701; a sealant 712 provided so as to surround the pixel portion 702, the source drive circuit portion 704, and the gate drive circuit portion 706; and a second substrate 705 provided so as to be opposed to the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed by the sealant 712. That is, the pixel portion 702, the source drive circuit portion 704, and the gate drive circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Note that, although not shown in FIG. 51, a display element is provided between the first substrate 701 and the second substrate 705. [0506] In addition, in the display device 700, an FPC (Flexible printed circuit) terminal portion 708 electrically connected to the pixel portion 702, the source drive circuit portion 704, and the gate drive circuit portion 706, respectively, is provided in an area on the first substrate 701 that is not surrounded by the sealant 712. In addition, the FPC terminal portion 708 is connected to the FPC 716, and various signals are supplied to the pixel portion 702, the source drive circuit portion 704, and the gate drive circuit portion 706 via the FPC 716. In addition, the pixel portion 702, the source drive circuit portion 704, the gate drive circuit portion 706, and the FPC terminal portion 708 are each connected to the signal line 710. Various signals supplied by the FPC 716 are supplied to the pixel portion 702, the source drive circuit portion 704, the gate drive circuit portion 706, and the FPC terminal portion 708 via the signal line 710. [0507] In addition, a plurality of gate drive circuit portions 706 may be provided in the display device 700. In addition, although the display device 700 shows an example in which the source drive circuit portion 704 and the gate drive circuit portion 706 are formed on the same first substrate 701 as the pixel portion 702, the present invention is not limited to this structure. For example, only the gate drive circuit portion 706 may be formed on the first substrate 701, or only the source drive circuit portion 704 may be formed on the first substrate 701. In this case, a structure in which a substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) having a source drive circuit or a gate drive circuit formed thereon is formed on the first substrate 701 may also be adopted. In addition, there is no particular limitation on the connection method of the separately formed drive circuit substrate, and a COG (Chip On Glass) method, a wire bonding method, etc. can be adopted. [0508] In addition, the pixel portion 702, the source drive circuit portion 704, and the gate drive circuit portion 706 included in the display device 700 include a plurality of transistors, and transistors of a semiconductor device of an embodiment of the present invention can be applied. [0509] In addition, the display device 700 can include various elements. As such an element, for example, there can be cited electroluminescent (EL) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (transistors that emit light in response to an electric current), electron emission elements, liquid crystal elements, electronic ink elements, electrophoretic elements, electrowetting elements, plasma display panels (PDPs), MEMS (micro-electromechanical systems), displays (such as gate valves (GLVs), digital micromirror devices (DMDs), digital microshutter (DMS) elements), piezoelectric ceramic displays, etc. [0510] In addition, as an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron-emitting element, there are field emission displays (FED) or SED flat-panel displays (SED: Surface-conduction Electron-emitter Display). As an example of a display device using a liquid crystal element, there are liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, and projection liquid crystal displays). As an example of a display device using an electronic ink element or an electrophoretic element, there are electronic paper. Note that when a semi-transmissive liquid crystal display or a reflective liquid crystal display is realized, part or all of the pixel electrode is made to function as a reflective electrode. For example, part or all of the pixel electrode is made to contain aluminum, silver, or the like. In addition, at this time, a memory circuit such as SRAM can also be set under the reflective electrode. Thus, power consumption can be further reduced. [0511] As a display mode of the display device 700, a progressive scanning mode or an interlaced scanning mode can be adopted. In addition, as a color element controlled in a pixel when performing color display, it is not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, it can be composed of four pixels of R pixel, G pixel, B pixel and W (white) pixel. Alternatively, as in the PenTile arrangement, a color element can also be composed of two colors in RGB, and two different colors can be selected according to the color element to form it. Alternatively, one or more colors such as yellow, cyan, magenta, etc. can be added to RGB. In addition, the size of the display area of each color element point can be different. However, the disclosed invention is not limited to a display device for color display, but can also be applied to a display device for black and white display. [0512] In addition, in order to use white light (W) for backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) so that the display device can display in full color, a color layer (also called a filter) can also be used. As a color layer, for example, red (R), green (G), blue (B), yellow (Y), etc. can be used in appropriate combination. By using a color layer, the color reproducibility can be further improved compared to the case where a color layer is not used. At this time, by setting an area including a color layer and an area not including a color layer, the white light in the area not including a color layer can be directly used for display. By partially providing an area that does not include a color layer, when displaying a bright image, the reduction in brightness caused by the color layer can sometimes be reduced, thereby reducing power consumption by about 20% to 30%. However, when a full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W can also be emitted from an element having each luminous color. By using a self-luminous element, power consumption can sometimes be further reduced compared to the case of using a color layer. [0513] In addition, as a colorization method, in addition to a method of converting a portion of the luminescence from the above-mentioned white light into red, green, and blue through a color filter (color filter method), a method of using red, green, and blue luminescence separately (three-color method) and a method of converting a portion of blue light into red or green (color conversion method or quantum dot method) can also be used. [0514] In the present embodiment, a structure using a liquid crystal element and an EL element as a display element is described using FIGS. 52 to 55 are cross-sectional views along the dotted line Q-R shown in FIG. 51, and are structures using a liquid crystal element as a display element. In addition, FIGS. 56 and 57 are cross-sectional views along the dotted line Q-R shown in FIG. 51, and are structures using an EL element as a display element. [0515] Below, the common parts shown in FIGS. 52 to 57 are first described, and then the different parts are described. [0516] á3-1. Description of the common parts of the display deviceñ The display device 700 shown in FIGS. 52 to 57 includes: a lead wiring portion 711; a pixel portion 702; a source drive circuit portion 704; and an FPC terminal portion 708. In addition, the lead wiring portion 711 includes a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor (not shown). In addition, the source drive circuit portion 704 includes a transistor 752. [0517] The transistor 750 has the same structure as the above-mentioned transistor 200A. The transistor 752 has the same structure as the above-mentioned transistor 100A. The transistor 750 and the transistor 752 may also have the structure of other transistors shown in the above-mentioned embodiment. [0518] The transistor used in the present embodiment includes a highly purified metal oxide film in which the formation of oxygen defects is suppressed. The transistor can reduce the off-state current. Therefore, the retention time of electrical signals such as image signals can be extended, and the write interval can also be extended in the power supply state. Therefore, the frequency of the update operation can be reduced, thereby achieving the effect of suppressing power consumption. [0519] In addition, the transistor used in the present embodiment can obtain a higher field-effect mobility and can therefore be driven at high speed. For example, by using such a transistor capable of high-speed driving in a liquid crystal display device, a switching transistor of a pixel portion and a driving transistor for a driving circuit can be formed on the same substrate. In other words, since a semiconductor device formed of a silicon wafer or the like does not need to be used separately as a driving circuit, the number of components of the semiconductor device can be reduced. In addition, a high-quality image can also be provided in the pixel portion by using a transistor capable of high-speed driving. [0520] In FIGS. 52 to 57, it is shown that the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source drive circuit portion 704 use the same structure of transistors, but the present invention is not limited to this. For example, the pixel portion 702 and the source drive circuit portion 704 may also use different transistors. Specifically, it is possible to cite a structure in which the pixel portion 702 uses a staggered transistor and the source drive circuit portion 704 uses the inverse staggered transistor structure shown in Embodiment 1, or a structure in which the pixel portion 702 uses the inverse staggered transistor structure shown in Embodiment 1 and the source drive circuit portion 704 uses a staggered transistor structure, etc. In addition, the source drive circuit portion 704 can also be replaced with a gate drive circuit portion. [0521] The signal line 710 is formed in the same process as the conductive film used as the source electrode and the drain electrode of the transistors 750 and 752. For example, when the signal line 710 is formed using a material containing a copper element, the signal delay caused by the wiring resistance is less, and a large screen display can be achieved. [0522] In addition, the FPC terminal portion 708 includes a connecting electrode 760, an anisotropic conductive film 780 and an FPC716. The connecting electrode 760 is formed in the same process as the conductive film used as the source electrode and the drain electrode of the transistors 750 and 752. In addition, the connecting electrode 760 and the terminal included in the FPC 716 are electrically connected via the anisotropic conductive film 780. [0523] In addition, as the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. In addition, as the first substrate 701 and the second substrate 705, a flexible substrate can also be used. As the flexible substrate, for example, a plastic substrate can be cited. [0524] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film, and is used to control the distance between the first substrate 701 and the second substrate 705 (the cell gap). In addition, as the structure 778, a spherical spacer can also be used. [0525] In addition, on the side of the second substrate 705, a light shielding film 738 used as a black matrix, a color film 736 used as a color filter, and an insulating film 734 in contact with the light shielding film 738 and the color film 736 are provided. [0526] á3-2. Structural example of a display device using a liquid crystal elementñ The display device 700 shown in Figures 52 and 53 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the side of the second substrate 705 and is used as a counter electrode. The display device 700 shown in FIG. 52 and FIG. 53 can display an image by changing the alignment state of the liquid crystal layer 776 by applying a voltage between the conductive film 772 and the conductive film 774, thereby controlling the transmission and non-transmission of light. [0527] The conductive film 772 is electrically connected to the conductive film used as the source electrode and the drain electrode of the transistor 750. The conductive film 772 is formed on the gate insulating film of the transistor 750 and is used as a pixel electrode, that is, an electrode of the display element. In addition, the conductive film 772 is used as a reflective electrode. The display device 700 shown in FIG. 52 and FIG. 53 is a so-called reflective color liquid crystal display device in which the conductive film 772 reflects external light and displays it through the color film 736. [0528] In addition, as the conductive film 772, a conductive film that is translucent to visible light or a conductive film that is reflective to visible light can be used. As the conductive film that is translucent to visible light, for example, it is preferable to use a material containing one selected from indium (In), zinc (Zn), and tin (Sn). As the conductive film that is reflective to visible light, for example, it is preferable to use a material containing aluminum or silver. In the present embodiment, a conductive film that is reflective to visible light is used as the conductive film 772. [0529] As shown in Figures 52 and 53, the insulating film 770 is used as a planarizing film. In addition, a conductive film 772 is formed on the insulating film 770. [0530] In addition, the display device 700 shown in Figures 52 and 53 shows a reflective color liquid crystal display device, but is not limited to this. For example, a transmissive color liquid crystal display device can be realized by using a conductive film that is transmissive to visible light as the conductive film 772. In addition, a so-called semi-transmissive color liquid crystal display device that combines a reflective color liquid crystal display device and a transmissive color liquid crystal display device can be realized. [0531] Here, Figures 54 and 55 show a transmissive color liquid crystal display device. Figures 54 and 55 are cross-sectional views along the dotted line Q-R shown in Figure 51, and Figures 54 and 55 show a structure using a liquid crystal element as a display element. In addition, the display device 700 shown in FIG. 54 and FIG. 55 is an example of a structure that uses a horizontal electric field method (for example, FFS (Fringe Field Switching) mode) as a driving method of a liquid crystal element. In the case of the structure shown in FIG. 54 and FIG. 55, an insulating film 773 is provided on a conductive film 772 used as a pixel electrode, and a conductive film 774 is provided on the insulating film 773. At this time, the conductive film 774 has a function of a common electrode, and the alignment state of the liquid crystal layer 776 can be controlled by the electric field generated between the conductive film 772 and the conductive film 774 via the insulating film 773. [0532] Note that, although not shown in FIGS. 52 to 55 , an alignment film may be provided on the side of the conductive film 772 and/or the conductive film 774 that contacts the liquid crystal layer 776, respectively. In addition, although not shown in FIGS. 52 to 55 , optical components (optical substrates) such as polarization components, phase difference components, and anti-reflection components may be appropriately provided. For example, circular polarization using a polarization substrate and a phase difference substrate may also be used. In addition, as a light source, a backlight, a side light, etc. may also be used. [0533] In the case of using a liquid crystal element as a display element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. may be used. These liquid crystal materials exhibit a cholesteric phase, a lamellar phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc., depending on the conditions. In addition, when adopting the lateral electric field mode, it is also possible to use a liquid crystal that does not use an alignment film and exhibits a blue phase. The blue phase is a kind of liquid crystal phase, and refers to the phase that appears before the temperature of the cholesterol-type liquid crystal is changed from the cholesterol phase to the homogeneous phase when the temperature is raised. Because the blue phase only appears in a narrow temperature range, a liquid crystal composition in which a chiral reagent more than a few wt% is mixed is used in the liquid crystal layer to expand the temperature range. Because the response speed of the liquid crystal composition comprising the liquid crystal exhibiting the blue phase and the chiral reagent is fast, and it has optical isotropy. Thus, the liquid crystal composition comprising the liquid crystal exhibiting the blue phase and the chiral reagent does not need an alignment process. In addition, since there is no need to set an alignment film and no need for friction treatment, electrostatic damage caused by friction treatment can be prevented, thereby reducing defects and damage to the liquid crystal display device in the process. In addition, the viewing angle dependence of the liquid crystal material showing a blue phase is small. [0535] In addition, when a liquid crystal element is used as a display element, the following modes can be used: TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS mode, ASM (Axially Symmetric aligned Micro-cell: Axially symmetrically arranged micro-cell) mode, OCB (Optical Compensated Birefringence: Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal: Ferroelectric Liquid Crystal) mode and AFLC (AntiFerroelectric Liquid Crystal: AntiFerroelectric Liquid Crystal) mode, etc. [0536] In addition, the display device 700 may also use a normally black liquid crystal display device, such as a transmissive liquid crystal display device using a vertical alignment (VA) mode. As the vertical alignment mode, several examples can be cited, such as an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, etc. [0537] á3-3. Display device using a light-emitting elementñ The display device 700 shown in Figures 56 and 57 includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 772, an EL layer 786, and a conductive film 788. The display device 700 shown in Figures 56 and 57 can display an image by causing the EL layer 786 included in the light-emitting element 782 to emit light. As materials that can be used for organic compounds, fluorescent materials or phosphorescent materials can be cited. In addition, as materials that can be used for quantum dots, colloidal quantum dot materials, alloy-type quantum dot materials, core-shell quantum dot materials, core-type quantum dot materials, etc. can be cited. In addition, materials containing element groups of the 12th and 16th families, the 13th and 15th families, or the 14th and 16th families can also be used. Alternatively, quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can be used. [0539] In the display device 700 shown in Figures 56 and 57, an insulating film 730 is provided on the transistor 750. The insulating film 730 covers a portion of the conductive film 772. The light-emitting element 782 adopts a top emission structure. Therefore, the conductive film 788 has light transmittance and allows the light emitted by the EL layer 786 to pass through. Note that although the top emission structure is illustrated in this embodiment, it is not limited to this. For example, it can also be applied to a bottom emission structure that emits light to one side of the conductive film 772 or a double-sided emission structure that emits light to both the side of the conductive film 772 and the side of the conductive film 788. [0540] In addition, a color film 736 is provided at a position overlapping with the light-emitting element 782, and a light-shielding film 738 is provided at a position overlapping with the insulating film 730, in the lead wiring portion 711, and in the source drive circuit portion 704. The color film 736 and the light-shielding film 738 may also be covered with an insulating film. The space between the light-emitting element 782 and the color film 736 is filled with a sealing film 732. Note that although a structure in which the color film 736 is provided in the display device 700 shown in FIG. 56 is illustrated, it is not limited to this. For example, when the EL layer 786 is formed by separate coating, a structure in which the color film 736 is not provided may also be adopted. [0541] As the insulating film 730, a heat-resistant organic material such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, epoxy resin, etc. can be used. In addition, the insulating film 730 can also be formed by stacking a plurality of insulating films formed using the above materials. [0542] á3-4. Structural example of providing an input-output device in a display deviceñ In addition, an input-output device can also be provided in the display device 700 shown in Figures 52 to 57. As the input-output device, for example, a touch panel can be cited. [0543] FIGS. 58 to 63 show a structure in which a touch panel 791 is provided for the display device 700 shown in FIGS. 52 to 57. [0544] FIGS. 58 to 63 are cross-sectional views showing that the touch panel 791 is provided in the display device 700 shown in FIGS. 52 to 57. [0545] First, the touch panel 791 shown in FIGS. 58 to 63 will be described below. [0546] The touch panel 791 shown in FIGS. 58 to 63 is a so-called In-Cell type touch panel provided between the substrate 705 and the color film 736. The touch panel 791 may be formed on one side of the substrate 705 before the color film 736 is formed. [0547] The touch panel 791 includes a light shielding film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. For example, when a detection object such as a finger or a stylus pen approaches the touch panel, a change in mutual capacitance between the electrode 793 and the electrode 794 can be detected. [0548] In addition, the intersection of the electrode 793 and the electrode 794 is shown above the transistor 750 shown in Figures 58 to 63. The electrode 796 is electrically connected to the two electrodes 793 sandwiching the electrode 794 through an opening provided in the insulating film 795. In addition, in Figures 58 to 63, a structure is shown in which the region where the electrode 796 is provided is provided in the pixel portion 702, but it is not limited to this, and for example, it can also be formed in the source drive circuit portion 704. [0549] The electrode 793 and the electrode 794 are provided in the region overlapping with the light shielding film 738. In addition, as shown in Figures 62 and 63, the electrode 793 is preferably provided in a manner not to overlap with the light-emitting element 782. In addition, as shown in Figures 58 to 61, the electrode 793 is preferably provided in a manner not to overlap with the liquid crystal element 775. In other words, the electrode 793 has an opening in the region overlapping with the light-emitting element 782 and the liquid crystal element 775. That is, the electrode 793 has a grid shape. By adopting this structure, the electrode 793 can have a structure that does not block the light emitted by the light-emitting element 782. Alternatively, the electrode 793 can also have a structure that does not block the light passing through the liquid crystal element 775. Therefore, since the brightness reduction caused by the configuration of the touch panel 791 is extremely small, a display device with high visibility and reduced power consumption can be achieved. In addition, the electrode 794 can also have the same structure. [0550] Since the electrode 793 and the electrode 794 do not overlap with the light-emitting element 782, the electrode 793 and the electrode 794 can use a metal material with low visible light transmittance. Alternatively, since the electrodes 793 and 794 do not overlap with the liquid crystal element 775, the electrodes 793 and 794 can use a metal material with low visible light transmittance. [0551] Therefore, compared with electrodes using oxide materials with high visible light transmittance, the resistance of the electrodes 793 and 794 can be reduced, thereby improving the sensor sensitivity of the touch panel. [0552] For example, the electrodes 793, 794, and 796 can also use conductive nanowires. The average diameter of the nanowire can be greater than 1nm and less than 100nm, preferably greater than 5nm and less than 50nm, and more preferably greater than 5nm and less than 25nm. In addition, as the above-mentioned nanowires, metal nanowires such as Ag nanowires, Cu nanowires, and Al nanowires, or carbon nanotubes, etc. can be used. For example, when Ag nanowires are used as any one or all of the electrodes 793, 794, and 796, a visible light transmittance of more than 89% and a sheet resistance of more than 40 W/square and less than 100 W/square can be achieved. [0553] Although the structure of the In-Cell touch panel is shown in Figures 58 to 63, it is not limited to this. For example, a so-called On-Cell touch panel formed on the display device 700 or a so-called Out-Cell touch panel that is attached to the display device 700 and used can also be used. [0554] In this way, a display device of an embodiment of the present invention can be used in combination with various types of touch panels. [0555] At least a portion of the present embodiment may be implemented in combination with other embodiments described in the present specification as appropriate. [0556] Embodiment 4 In the present embodiment, a display device including a semiconductor device according to an embodiment of the present invention is described with reference to FIG. 64A, FIG. 64B, and FIG. 64C. [0557] á4. Circuit structure of display deviceñ The display device shown in FIG. 64A includes: a region having pixels of display elements (hereinafter referred to as pixel portion 502); a circuit portion arranged outside the pixel portion 502 and having a circuit for driving the pixels (hereinafter referred to as driving circuit portion 504); a circuit having a function of protecting the element (hereinafter referred to as protection circuit 506); and a terminal portion 507. In addition, the protection circuit 506 may not be provided. [0558] A part or all of the driving circuit portion 504 is preferably formed on the same substrate as the pixel portion 502. This can reduce the number of components and the number of terminals. When a part or all of the driving circuit portion 504 is not formed on the same substrate as the pixel portion 502, a part or all of the driving circuit portion 504 can be mounted by COG or TAB (Tape Automated Bonding). [0559] The pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number greater than or equal to 2) and Y columns (Y is a natural number greater than or equal to 2), and the driving circuit portion 504 includes a driving circuit such as a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving the display element in the pixel (hereinafter referred to as a source driver 504b). [0560] The gate driver 504a includes a shift register and the like. The gate driver 504a receives a signal for driving the shift register via a terminal portion 507 and outputs the signal. For example, the gate driver 504a receives an activation pulse signal, a clock signal, etc. and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of the wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which the scanning signal is supplied. In addition, a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be controlled individually by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, this is not limited to this, and the gate driver 504a may also supply other signals. [0561] The source driver 504b has a shift register, etc. The source driver 504b receives a signal for driving the shift register and a signal (image signal) from which a data signal is derived through the terminal portion 507. The source driver 504b has a function of generating a data signal written to the pixel circuit 501 based on the image signal. In addition, the source driver 504b has a function of controlling the output of the data signal according to a pulse signal generated by the input of a start pulse signal, a clock signal, etc. In addition, the source driver 504b has a function of controlling the potential of the wiring (hereinafter referred to as data lines DL_1 to DL_Y) supplied with the data signal. Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited thereto, and the source driver 504b may supply other signals. [0562] The source driver 504b is configured, for example, using a plurality of analog switches. The source driver 504b can output a signal obtained by time-dividing an image signal as a data signal by sequentially turning on the plurality of analog switches. In addition, the source driver 504b may also be configured using a shift register or the like. [0563] The pulse signal and the data signal are input to each of the plurality of pixel circuits 501 via one of the plurality of scan lines GL supplied with the scan signal and one of the plurality of data lines DL supplied with the data signal, respectively. In addition, the gate driver 504a controls the writing and holding of the data signal in each of the plurality of pixel circuits 501. For example, the pulse signal is input from the gate driver 504a to the pixel circuit 501 in the mth row and nth column via the scan line GL_m (m is a natural number less than X), and the data signal is input from the source driver 504b to the pixel circuit 501 in the mth row and nth column via the data line DL_n (n is a natural number less than Y) according to the potential of the scan line GL_m. [0564] The protection circuit 506 shown in FIG. 64A is connected to the scan line GL which is a wiring between the gate driver 504a and the pixel circuit 501, for example. Alternatively, the protection circuit 506 is connected to a data line DL which is a wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504b and the terminal portion 507. In addition, the terminal portion 507 refers to a portion where terminals for inputting power, control signals, and image signals from an external circuit to the display device are provided. [0565] The protection circuit 506 is a circuit that causes conduction between the wiring connected thereto and other wirings when a potential outside a certain range is supplied to the wiring. [0566] As shown in FIG. 64A, by providing a protection circuit 506 for the pixel portion 502 and the driver circuit portion 504, the resistance of the display device to overcurrents caused by ESD (Electro Static Discharge) and the like can be improved. However, the structure of the protection circuit 506 is not limited thereto, and for example, a structure in which the gate driver 504a is connected to the protection circuit 506 or a structure in which the source driver 504b is connected to the protection circuit 506 may be adopted. Alternatively, a structure in which the terminal portion 507 is connected to the protection circuit 506 may be adopted. [0567] In addition, although an example in which the driver circuit portion 504 is formed by a gate driver 504a and a source driver 504b is shown in FIG64A, the present invention is not limited to this. For example, only the gate driver 504a may be formed and a substrate (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) on which a separately prepared source driver circuit is formed may be mounted. [0568] In addition, the plurality of pixel circuits 501 shown in FIG64A may, for example, adopt the structure shown in FIG64B. [0569] The pixel circuit 501 shown in FIG64B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor shown in the previous embodiment may be used for the transistor 550. [0570] The potential of one of a pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set according to the data to be written. In addition, a common potential may be supplied to one of a pair of electrodes of the liquid crystal element 570 possessed by each of the plurality of pixel circuits 501. In addition, the potential supplied to one of a pair of electrodes of the liquid crystal element 570 possessed by the pixel circuit 501 in one row may be different from the potential supplied to one of a pair of electrodes of the liquid crystal element 570 possessed by the pixel circuit 501 in another row. [0571] For example, as a driving method of the display device including the liquid crystal element 570, the following modes can also be used: TN mode; STN mode; VA mode; ASM (Axially Symmetric aligned Micro-cell: axially symmetrically arranged micro-cell) mode; OCB (Optically Compensated Birefringence: optically compensated birefringence) mode; FLC (Ferroelectric Liquid Crystal: ferroelectric liquid crystal) mode; AFLC (Anti Ferroelectric Liquid Crystal: antiferroelectric liquid crystal) mode; MVA mode; PVA (Patterned Vertical Alignment: vertical alignment configuration) mode; IPS mode; FFS mode or TBA (Transverse Bend Alignment: transverse bend alignment) mode, etc. In addition, as a driving method of the display device, in addition to the above-mentioned driving method, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest-host mode, etc. However, it is not limited to this, and various liquid crystal elements and driving methods can be used as liquid crystal elements and their driving methods. [0572] In the pixel circuit 501 of the mth row and nth column, one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other of the source electrode and the drain electrode is electrically connected to the other electrode of a pair of electrodes of the liquid crystal element 570. The gate electrode of transistor 550 is electrically connected to the scanning line GL_m. Transistor 550 has a function of controlling the writing of data of a data signal by becoming an on state or an off state. [0573] One of a pair of electrodes of capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other electrode is electrically connected to the other electrode of a pair of electrodes of liquid crystal element 570. In addition, the potential of potential supply line VL is appropriately set according to the specifications of pixel circuit 501. Capacitor 560 has a function of a storage capacitor for storing written data. [0574] For example, in a display device including the pixel circuit 501 shown in FIG. 64B, the pixel circuit 501 of each row is selected in turn by the gate driver 504a shown in FIG. 64A, and the transistor 550 is turned on to write the data signal. [0575] When the transistor 550 is turned off, the pixel circuit 501 to which the data is written becomes a hold state. By performing the above steps in turn row by row, an image can be displayed. [0576] The multiple pixel circuits 501 shown in FIG. 64A can adopt the structure shown in FIG. 64C, for example. [0577] The pixel circuit 501 shown in FIG. 64C includes transistors 552, 554, a capacitor 562, and a light-emitting element 572. The transistor shown in the previous embodiment can be applied to the transistor 552 and/or the transistor 554. [0578] One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n) to which a data signal is supplied. Furthermore, the gate electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied. [0579] The transistor 552 has a function of controlling the writing of data of a data signal by becoming an on state or an off state. [0580] One of a pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is supplied (hereinafter, referred to as a potential supply line VL_a), and the other electrode is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. [0581] The capacitor 562 has a function as a storage capacitor for storing written data. [0582] One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Furthermore, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. [0583] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554. [0584] As the light-emitting element 572, for example, an organic electroluminescent element (also referred to as an organic EL element) or the like can be used. Note that the light-emitting element 572 is not limited to the organic EL element, and an inorganic EL element made of an inorganic material can also be used. [0585] In addition, one of the potential supply line VL_a and the potential supply line VL_b is supplied with a high power potential VDD, and the other is supplied with a low power potential VSS. [0586] For example, in a display device including the pixel circuit 501 shown in FIG. 64C, the pixel circuit 501 of each row is selected in turn by the gate driver 504a shown in FIG. 64A, and the transistor 552 is turned on to write the data signal. [0587] When the transistor 552 is turned off, the pixel circuit 501 into which the data is written becomes a hold state. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light-emitting element 572 emits light at a brightness corresponding to the amount of current flowing. By performing the above steps in turn row by row, an image can be displayed. [0588] At least a portion of the present embodiment can be implemented in appropriate combination with other embodiments described in this specification. [0589] Embodiment 5 FIG. 65 is a block diagram showing a structural example of a display device 800. The display device 800 includes a display unit 810, a touch sensor unit 820, a controller IC 815, and a main body 840. In addition, a light sensor 843 and an open/close sensor 844 may also be provided in the display device 800 as needed. The display unit 810 includes a pixel portion 502, a gate driver 504a, and a source driver 504b. [0590] ááController ICññ In FIG. 65, the controller IC815 includes an interface 850, a frame memory 851, a decoder 852, a sensor controller 853, a controller 854, a clock generation circuit 855, an image processing portion 860, a memory 870, a timing controller 873, a register 875, and a touch sensor controller 884. [0591] The communication between the controller IC815 and the main body 840 is performed through the interface 850. Image data, various control signals, etc. are sent from the main body 840 to the controller IC815. In addition, information such as the touch position obtained by the touch sensor controller 884 is sent from the controller IC 815 to the main body 840. In addition, each circuit included in the controller IC 815 is appropriately selected according to the specifications of the main body 840, the specifications of the display device 800, etc. [0592] The frame memory 851 is a memory used to store image data input to the controller IC 815. When compressed image data is sent from the main body 840, the frame memory 851 can store the compressed image data. The decoder 852 is a circuit that decompresses the compressed image data. When it is not necessary to decompress the image data, the decoder 852 does not process it. Alternatively, the decoder 852 may be arranged between the frame memory 851 and the interface 850. [0593] The image processing unit 860 has a function of performing various image processing on the image data. For example, the image processing unit 860 includes a gamma correction circuit 861, a dimming circuit 862, and a color adjustment circuit 863. [0594] In addition, when a display element that utilizes the flow of electric current to emit light, such as an organic EL or LED, is used as the display element of the display device 800, the image processing unit 860 may also include a correction circuit 864. In this case, the source driver 504b preferably includes a circuit that detects the current flowing through the display element. The correction circuit 864 has a function of adjusting the brightness of the display element according to the signal sent from the source driver 504b. [0595] The image data processed in the image processing unit 860 is output to the source driver 504b via the memory 870. The memory 870 is a memory for temporarily storing image data. The source driver 504b has the function of processing the input image data and writing the image data to the source line of the pixel unit 502. Note that there is no limit to the number of source drivers 504b, and it can be set according to the number of pixels in the pixel unit 502. [0596] The timing controller 873 has the function of generating timing signals used in the source driver 504b, the touch sensor controller 884, and the gate driver 504a. [0597] The touch sensor controller 884 has a function of controlling the driving circuit of the touch sensor unit 820. The signal including the touch information read from the touch sensor unit 820 is processed by the touch sensor controller 884 and sent to the main body 840 through the interface 850. The main body 840 generates image data reflecting the touch information and sends it to the controller IC815. In addition, a structure in which the touch information is reflected in the image data using the controller IC815 can also be adopted. [0598] The clock generation circuit 855 has a function of generating a clock signal used in the controller IC815. The controller 854 has a function of processing various control signals sent from the main body 840 through the interface 850 and controlling various circuits in the controller IC815. In addition, the controller 854 has a function of controlling the power supply to various circuits in the controller IC815. Hereinafter, the technology of temporarily stopping the power supply to the circuit that is not in use is referred to as power gating. In FIG. 65 , the power supply line is omitted. [0599] The register 875 stores data used for the operation of the controller IC815. The data stored in the register 875 include parameters used when the image processing unit 860 performs correction processing, parameters used when the timing controller 873 generates waveforms of various timing signals, and the like. The register 875 has a scanner chain register composed of a plurality of registers. [0600] The sensor controller 853 is electrically connected to the photo sensor 843. The photo sensor 843 detects light 845 and generates a detection signal. The sensor controller 853 generates a control signal based on the detection signal. The control signal generated by the sensor controller 853 is output to the controller 854, for example. [0601] The image processing unit 860 can adjust the brightness of the pixel based on the brightness of the light 845 measured using the light sensor 843 and the sensor controller 853. In other words, in an environment where the brightness of the light 845 is low, the brightness of the pixel is reduced to reduce glare and reduce power consumption. In addition, in an environment where the brightness of the light 845 is high, a display quality with high visibility is obtained by increasing the brightness of the pixel. The above adjustment can be performed based on the brightness set by the user. The above adjustment is referred to as dimming or dimming processing. In addition, the circuit that performs this processing is referred to as a dimming circuit. [0602] In addition, the photo sensor 843 and the sensor controller 853 may also have the function of measuring the color tone of the light 845 to correct the color tone. For example, in a red environment at dusk, the eyes of the user of the display device 800 perceive red as white due to color adaptation. In this case, the color displayed by the display device 800 appears pale, so the color tone correction can be performed by emphasizing the R (red) component of the display device 800. The above correction is called color adjustment or color adjustment processing. In addition, the circuit that performs this processing is called a color adjustment circuit. [0603] The image processing unit 860 sometimes includes other processing circuits such as an RGB-RGBW conversion circuit according to the specifications of the display device 800. The RGB-RGBW conversion circuit is a circuit having a function of converting RGB (red, green, blue) image data into RGBW (red, green, blue, white) image data. That is, when the display device 800 includes pixels of four colors, RGBW, power consumption can be reduced by using W (white) pixels to display the W (white) component of the image data. Note that, in the case where the display device 800 includes pixels of four colors, RGBY (red, green, blue, yellow), for example, an RGB-RGBY conversion circuit can be used. [0604] á Parameters ñ Image correction processing such as gamma correction, dimming, and color adjustment is equivalent to processing for generating output correction data Y based on input image data X. The parameters used in the image processing unit 860 are parameters used to convert image data X into correction data Y. [0605] There are two methods for setting parameters: a table method and a function approximation method. In the table method shown in FIG66A, the correction data Yn for the image data Xn is stored in a table as a parameter. In the table method, a plurality of registers are required to store the parameters corresponding to the table, but the flexibility of the correction is high. On the other hand, when the correction data Y for the image data X can be empirically predetermined, as shown in FIG66B, a structure using the function approximation method is effective. a1, a2, b2, etc. are parameters. Here, a method of linear approximation in each region is shown, but a method of approximation with a nonlinear function can also be adopted. In the function approximation method, the flexibility of the correction is low, but there are fewer registers for storing the parameters defining the function. [0606] The parameters used in the timing controller 873 represent, for example, the timing at which the generated signal of the timing controller 873 becomes "L" (or "H") with respect to the reference signal as shown in FIG. 66C. The parameter Ra (or Rb) represents how many clock cycles are equivalent to the timing at which the reference signal becomes "L" (or "H"). [0607] The above-mentioned parameters for correction can be stored in the register 875. In addition, as parameters other than the above-mentioned parameters that can be stored in the register 875, there are the brightness, hue, energy saving setting (the time until the display dims or turns off the display) of the display device 800, the sensitivity of the touch sensor controller 884, and the like. [0608] Power gating When the image data transmitted from the main body 840 does not change, the controller 854 may perform power gating on a portion of the circuits in the controller IC 815. Specifically, for example, the circuits in the area 890 (frame memory 851, decoder 852, image processing unit 860, memory 870, timing controller 873, register 875) may be temporarily stopped. In addition, a structure may be adopted in which a control signal indicating that the image data does not change is transmitted from the main body 840 to the controller IC 815, and when the controller 854 detects the control signal, power gating is performed. [0609] When the image data does not change, for example, by incorporating a timer function in the controller 854, the timing for restarting the power supply to the circuits in the area 890 can be determined based on the time measured by the timer. [0610] In addition to the circuits in the area 890, the above-mentioned power gating can also be performed on the source driver 504b. [0611] In the structure of FIG. 65, the source driver 504b can also be included in the controller IC 815. In other words, the source driver 504b and the controller IC 815 can also be set on the same chip. [0612] Next, a specific circuit structure example of the frame memory 851 and the register 875 is described. [0613] á Frame memory 851ñ FIG67A shows a structural example of the frame memory 851. The frame memory 851 includes a control unit 902, a cell array 903, and a peripheral circuit 908. The peripheral circuit 908 includes a sense amplifier circuit 904, a driver 905, a main amplifier 906, and an input-output circuit 907. [0614] The control unit 902 has a function of controlling the frame memory 851. For example, the control unit 902 controls the driver 905, the main amplifier 906, and the input-output circuit 907. [0615] The driver 905 is electrically connected to a plurality of wirings WL and CSEL. The driver 905 generates a signal that is output to the plurality of wirings WL and CSEL. [0616] The cell array 903 includes a plurality of memory cells 909. The memory cell 909 is electrically connected to wirings WL, LBL (or LBLB), and BGL. The wiring WL is a word line, and the wirings LBL and LBLB are local bit lines. In the example of FIG67A, the structure of the cell array 903 is a folded bit line method, and may also be an open bit line method. [0617] FIG67B shows an example of the structure of the memory cell 909. The memory cell 909 includes a transistor NW1 and a capacitor CS1. The memory cell 909 has the same circuit structure as a memory cell of a DRAM (dynamic random access memory). Here, the transistor NW1 is a transistor including a back gate. The back gate of transistor NW1 is electrically connected to wiring BGL. Voltage Vbg_w1 is input to wiring BGL. [0618] Transistor NW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, by forming memory cell 909 with OS transistors, the charge leakage from capacitor CS1 can be suppressed, so the frequency of updating operation of frame memory 851 can be reduced. In addition, even if the power supply is stopped, frame memory 851 can retain image data for a long time. In addition, by making voltage Vbg_w1 a negative voltage, the critical voltage of transistor NW1 can drift toward the positive potential side, and the retention time of memory cell 909 can be extended. [0619] Here, "off-state current" refers to the current flowing between the source and the drain when the transistor is in the off state. In the case of an n-channel transistor, for example, when the critical voltage is about 0V to 2V, the current flowing between the source and the drain when the voltage of the gate with respect to the source is a negative voltage can be called the off-state current. In addition, "the off-state current is extremely small" means that, for example, the off-state current per channel width of 1mm is 100zA (z: medium, 10-twenty one ) or less. Since the off-state current is as small as possible, the standardized off-state current is preferably less than 10zA/mm or less than 1zA/mm, and more preferably 10yA/mm (y: 10-twenty four ) or less. [0620] Since the transistors NW1 of the multiple memory cells 909 included in the cell array 903 are OS transistors, the transistors of other circuits can be, for example, Si transistors formed on a silicon wafer. Thus, the cell array 903 can be stacked on the sense amplifier circuit 904. Therefore, the circuit area of the frame memory 851 can be reduced, thereby achieving miniaturization of the controller IC 815. [0621] The cell array 903 is stacked on the sense amplifier circuit 904. The sense amplifier circuit 904 includes a plurality of sense amplifiers SA. The sense amplifier SA is electrically connected to the adjacent wirings LBL, LBLB (local bit line pairs), wirings GBL, GBLB (global bit line pairs), and a plurality of wirings CSEL. The sense amplifier SA has a function of amplifying the potential difference between the wiring LBL and the wiring LBLB. [0622] In the sense amplifier circuit 904, one wiring GBL is provided for each of the four wirings LBL, and one wiring GBLB is provided for each of the four wirings LBLB, but the structure of the sense amplifier circuit 904 is not limited to the structural example of FIG. 67A. [0623] The main amplifier 906 is connected to the sense amplifier circuit 904 and the input/output circuit 907. The main amplifier 906 has a function of amplifying the potential difference between the wiring GBL and the wiring GBLB. In addition, the main amplifier 906 can be omitted. [0624] The input-output circuit 907 has the following functions: outputting the potential corresponding to the written data to the wiring GBL and the wiring GBLB or the main amplifier 906; and reading the potential of the wiring GBL and the wiring GBLB or the output potential of the main amplifier 906, and outputting the potential as data to the outside. The sense amplifier SA for reading data and the sense amplifier SA for writing data can be selected according to the signal of the wiring CSEL. Therefore, since the input-output circuit 907 does not require a selection circuit such as a multiplexer, the circuit structure can be simplified and the occupied area can be reduced. [0625] á Register 875ñ Figure 68 is a block diagram showing an example of the structure of the register 875. The register 875 includes a scanner chain register section 875A and a register section 875B. The scanner chain register section 875A includes a plurality of registers 930. The scanner chain register is constituted by a plurality of registers 930. The register section 875B includes a plurality of registers 931. [0626] The register 930 is a non-volatile register in which data does not disappear even when power is stopped. Since the register 930 is a non-volatile register, the register 930 includes a holding circuit using an OS transistor. [0627] On the other hand, the register 931 is a volatile register. There is no particular restriction on the circuit structure of the register 931. It can be any circuit capable of storing data, and can also be composed of a latch circuit, a flip-flop circuit, etc. The image processing unit 860 and the timing controller 873 access the register unit 875B and extract data from the corresponding register 931. Alternatively, the image processing unit 860 and the timing controller 873 control the processing content according to the data supplied from the register unit 875B. [0628] When the data stored in the register 875 is updated, the data of the scanner chain register unit 875A is first changed. After rewriting the data of each register 930 of the scanner chain register section 875A, the data of each register 930 of the scanner chain register section 875A is simultaneously loaded into each register 931 of the register section 875B. [0629] Thus, the image processing section 860 and the timing controller 873 can use the data updated at the same time to perform various processes. Since the update of the data is synchronized, the stable operation of the controller IC 815 can be achieved. By setting the scanner chain register section 875A and the register section 875B, the data of the scanner chain register section 875A can also be updated during the operation of the image processing section 860 and the timing controller 873. [0630] When the power supply of the controller IC 815 is gated, the data is stored (saved) in the holding circuit of the register 930 and then the power supply is stopped. After the power supply is restarted, the data in the register 930 is restored (loaded) into the register 931 and normal operation is restarted. In addition, when the data stored in the register 930 and the data stored in the register 931 are inconsistent, it is preferable to store the data in the holding circuit of the register 930 again after storing the data in the register 931 in the register 930. For example, when the update data is inserted into the scanner chain register section 875A, a data mismatch occurs. [0631] FIG. 69 shows an example of a circuit structure of registers 930 and 931. FIG. 69 shows two stages of registers 930 of the scanner chain register section 875A and two registers 931 corresponding to these registers 930. Register 930 receives a signal Scan In and outputs a signal Scan Out. [0632] Register 930 includes a holding circuit 947, a selector 948, and a flip-flop circuit 949. The selector 948 and the flip-flop circuit 949 constitute a scan flip-flop circuit. The selector 948 receives a signal SAVE1. [0633] The holding circuit 947 receives signals SAVE2 and LOAD2. The holding circuit 947 includes transistors T1 to T6 and capacitors C4 and C6. Transistors T1 and T2 are OS transistors. Transistors T1 and T2 may also be OS transistors including a back gate like transistor NW1 of the memory cell 909 (see FIG. 67B ). [0634] A three-transistor gain unit is formed by transistors T1, T3, T4 and capacitor C4. Similarly, a three-transistor gain unit is formed by transistors T2, T5, T6 and capacitor C6. The two gain units store complementary data held by the flip-flop circuit 949. Since transistors T1 and T2 are OS transistors, the holding circuit 947 can retain data for a long time even when power is stopped. In the register 930, transistors other than transistors T1 and T2 can be formed of Si transistors. [0635] The holding circuit 947 stores the complementary data held by the flip-flop circuit 949 according to the signal SAVE2, and loads the held data into the flip-flop circuit 949 according to the signal LOAD2. [0636] The input terminal of the flip-flop circuit 949 is electrically connected to the output terminal of the selector 948, and the data output terminal is electrically connected to the input terminal of the register 931. The flip-flop circuit 949 includes inverters 950 to 955 and analog switches 957 and 958. The conduction state of the analog switches 957 and 958 is controlled by a scan clock signal (referred to as Scan Clock). The flip-flop circuit 949 is not limited to the circuit structure of FIG. 69, and various flip-flop circuits 949 can be used. [0637] One of the two input terminals of the selector 948 is electrically connected to the output terminal of the register 931, and the other is electrically connected to the output terminal of the flip-flop circuit 949 of the previous stage. In addition, the input terminal of the selector 948 of the first stage of the scanner chain register section 875A inputs data from the outside of the register 875. [0638] The register 931 includes inverters 961 to 963, a clock inverter 964, an analog switch 965, and a buffer 966. The register 931 loads the data of the flip-flop circuit 949 according to the signal LOAD1. The transistor of the register 931 can be formed of a Si transistor. [0639] ááWorking Exampleññ The working examples of the controller IC 815 and the register 875 of the display device 800 are described by being classified into before shipment, when the electronic device including the display device 800 is started, and during normal operation. [0640] áBefore Shipmentñ Before shipment, parameters related to the specifications of the display device 800 are stored in the register 875. These parameters include, for example, the number of pixels, the number of touch sensors, and the parameters used by the timing controller 873 to generate various timing signal waveforms. When the image processing unit 860 includes the correction circuit 864, the correction data is stored as a parameter in the register 875. In addition to being stored in the register 875, these parameters may also be stored in a dedicated ROM. [0641] At startup When the electronic device including the display device 800 is started, parameters such as user settings sent from the main body 840 are stored in the register 875. These parameters include, for example, display brightness or color tone, touch sensor sensitivity, energy saving settings (time until the display dims or turns off the display), gamma correction curves or tables, etc. In addition, when the parameters are stored in the register 875, a scanning clock signal and data equivalent to the parameters synchronized with the scanning clock signal are sent from the controller 854 to the register 875. [0642] Normal operation Normal operation can be divided into a state of displaying a dynamic image, a state of displaying a static image (a state in which IDS driving can be performed), and a state of not displaying, etc. In the state of displaying a dynamic image, etc., the image processing unit 860 and the timing controller 873, etc. work, but the data change of the register 875 is performed on the scanner chain register unit 875A, so it does not affect the image processing unit 860, etc. After the data of the scanner chain register unit 875A is changed, the data of the scanner chain register unit 875A is loaded into the register unit 875B at the same time, and the data change of the register 875 is completed. In addition, the operation of the image processing unit 860 and the like is switched to an operation corresponding to the data. [0643] In a state where a static image is displayed and IDS driving is possible, for example, the power gate of the register 875 can be performed in the same manner as other circuits in the area 890. At this time, before the power gate is performed, the complementary data held by the flip-flop circuit 949 is stored in the holding circuit 947 in the register 930 included in the scanner chain register unit 875A according to the signal SAVE2. [0644] When recovering from power gating, the data held by the holding circuit 947 is loaded into the flip-flop circuit 949 according to the signal LOAD2, and the data of the flip-flop circuit 949 is loaded into the register 931 according to the signal LOAD1. In this way, the data of the register 875 is valid in the same state as before the power gating. In addition, even in the power gating state, when the main body 840 requires the parameter of the register 875 to be changed, the power gating of the register 875 can be released and the parameter can be changed. [0645] In a state where no display is performed, for example, the circuit in the area 890 (including the register 875) can be power gated. At this time, the main body 840 sometimes stops working, but since the frame memory 851 and the buffer 875 are non-volatile, when recovering from the power gating, the display (static image) before the power gating can be performed without waiting for the recovery of the main body 840. [0646] For example, when the display device 800 is used as the display part of the foldable information terminal, when the information terminal is folded and the display surface of the display device 800 is not used, the sensor controller 853 and the touch sensor controller 884 can be powered off except for the circuit in the area 890. [0647] When the information terminal is folded, the main body 840 sometimes stops working according to the specifications of the main body 840. When the information terminal is unfolded again in the state where the main body 840 stops working, since the frame memory 851 and the register 875 are non-volatile, the image data in the frame memory 851 can be displayed before the image data, various control signals, etc. are sent from the main body 840. [0648] In this way, by providing the scanner chain register section 875A and the register section 875B in the register 875, the data of the scanner chain register section 875A can be changed, and the data can be changed smoothly without affecting the image processing section 860 and the timing controller 873. In addition, each register 930 of the scanner chain register section 875A includes a holding circuit 947, so that it can smoothly transfer to the power gate state and restore from the power gate state. [0649] This embodiment can be implemented in combination with other embodiments as appropriate. [0650] Embodiment 6 In this embodiment, a display module and an electronic device including a semiconductor device of an embodiment of the present invention are described with reference to Figures 70A to 76D. [0651] á6-1. Display moduleñ A display module that can be manufactured using an embodiment of the present invention is described. [0652] The display module 6000 shown in FIG. 70A includes a display panel 6006 connected to an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002. [0653] For example, a display device manufactured using an embodiment of the present invention can be used for the display panel 6006. Thus, the display module can be manufactured with a high yield. [0654] The upper cover 6001 and the lower cover 6002 can appropriately change their shapes or sizes according to the size of the display panel 6006. [0655] In addition, a touch panel can also be provided in a manner overlapping with the display panel 6006. The touch panel can be a resistive film touch panel or an electrostatic capacitance touch panel, and can be formed in a manner overlapping with the display panel 6006. In addition, the display panel 6006 can also have the function of a touch panel without providing the touch panel. [0656] In addition to the function of protecting the display panel 6006, the frame 6009 also has the function of an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 6010. In addition, the frame 6009 can also have the function of a heat sink. [0657] The printed circuit board 6010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or a power source using a separately provided battery 6011 can be used. When a commercial power source is used, the battery 6011 can be omitted. [0658] In addition, components such as a polarizing plate, a phase difference plate, and a prism can also be provided in the display module 6000. [0659] FIG. 70B is a cross-sectional schematic diagram of a display module 6000 having an optical touch sensor. [0660] The display module 6000 includes a light-emitting portion 6015 and a light-receiving portion 6016 provided on a printed circuit board 6010. In addition, a pair of light-guiding portions (light-guiding portion 6017a, light-guiding portion 6017b) are provided in an area surrounded by the upper cover 6001 and the lower cover 6002. [0661] For example, plastic can be used as the upper cover 6001 and the lower cover 6002. The thickness of the upper cover 6001 and the lower cover 6002 can be thin (for example, not less than 0.5 mm and not more than 5 mm). Therefore, the weight of the display module 6000 can be made extremely light. In addition, the upper cover 6001 and the lower cover 6002 can be manufactured with very little material, thereby reducing the manufacturing cost. [0662] The display panel 6006 overlaps with the printed circuit board 6010 and the battery 6011 via the frame 6009. The display panel 6006 and the frame 6009 are fixed to the light guiding portion 6017a and the light guiding portion 6017b. [0663] The light 6018 emitted from the light emitting portion 6015 passes through the light guiding portion 6017a, the top of the display panel 6006, and the light guiding portion 6017b to reach the light receiving portion 6016. For example, when light 6018 is blocked by a detection object such as a finger or a stylus, a touch operation can be detected. [0664] For example, a plurality of light-emitting portions 6015 are provided along two adjacent sides of the display panel 6006. A plurality of light-receiving portions 6016 are arranged at positions opposite to the light-emitting portions 6015. Thus, information on the position of the touch operation can be obtained. [0665] As the light-emitting portion 6015, for example, a light source such as an LED element can be used. In particular, as the light-emitting portion 6015, it is preferable to use a light source that emits infrared rays that are invisible to the user and harmless to the user. [0666] As the light-receiving portion 6016, a photoelectric element that receives the light emitted by the light-emitting portion 6015 and converts it into an electrical signal can be used. It is preferable to use a photodiode that can receive infrared rays. [0667] As the light guiding portion 6017a and the light guiding portion 6017b, a component that at least transmits light 6018 can be used. By using the light guiding portion 6017a and the light guiding portion 6017b, the light emitting portion 6015 and the light receiving portion 6016 can be arranged on the lower side of the display panel 6006, and it is possible to prevent external light from reaching the light receiving portion 6016 and causing erroneous operation of the touch sensor. In particular, it is preferable to use a resin that absorbs visible light and transmits infrared rays. In this way, erroneous operation of the touch sensor can be more effectively suppressed. [0668] FIG6-2. Electronic device 1ñ Figures 71A to 71E show an example of an electronic device. [0669] Figure 71A is an external view of a camera 8000 equipped with a viewfinder 8100. [0670] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, and the like. In addition, the camera 8000 is equipped with a detachable lens 8006. [0671] Here, the camera 8000 has a structure that allows the lens 8006 to be removed from the housing 8001 and exchanged, and the lens 8006 and the housing may be formed as one body. [0672] By pressing the shutter button 8004, the camera 8000 can take an image. In addition, the display unit 8002 is used as a touch panel, and imaging can also be performed by touching the display unit 8002. [0673] The housing 8001 of the camera 8000 includes an embedder having an electrode, and can be connected to a flash device, etc. in addition to the viewfinder 8100. [0674] The viewfinder 8100 includes the housing 8101, a display unit 8102, and a button 8103, etc. [0675] The housing 8101 includes an embedder that is embedded in the embedder of the camera 8000, and the viewfinder 8100 can be mounted on the camera 8000. In addition, the embedder includes an electrode, and an image, etc. received from the camera 8000 using the electrode can be displayed on the display unit 8102. [0676] The button 8103 is used as a power button. By using the button 8103, the display or non-display of the display unit 8102 can be switched. [0677] The display device of one embodiment of the present invention can be used for the display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100. [0678] In addition, in FIG. 71A, the camera 8000 and the viewfinder 8100 are separate and detachable electronic devices, but a viewfinder with a display device can also be built into the housing 8001 of the camera 8000. [0679] FIG. 71B is an external view of the head-mounted display 8200. [0680] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display unit 8204, a cable 8205, and the like. In addition, a battery 8206 is built into the mounting portion 8201. [0681] Electric power is supplied from the battery 8206 to the main body 8203 via the cable 8205. The main body 8203 is equipped with a wireless receiver, etc., and can display image information such as received image data on the display portion 8204. In addition, by using a camera provided in the main body 8203 to capture the movement of the user's eyeballs and eyelids, and calculating the coordinates of the user's viewpoint based on the information, the user's viewpoint can be used as an input method. [0682] In addition, a plurality of electrodes can be provided at the position of the mounting portion 8201 that is touched by the user. The main body 8203 can also have a function of recognizing the user's viewpoint by detecting the current flowing through the electrodes according to the movement of the user's eyeballs. In addition, the main body 8203 may have a function of monitoring the user's pulse by detecting the current flowing through the electrode. The mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, and may have a function of displaying the user's biological information on the display portion 8204. In addition, the main body 8203 may also detect the movement of the user's head, etc., and change the image displayed on the display portion 8204 in synchronization with the movement of the user's head, etc. [0683] The display device of one embodiment of the present invention can be used for the display portion 8204. [0684] FIG. 71C, FIG. 71D, and FIG. 71E are external views of a head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display portion 8302, a belt-shaped fixing tool 8304, and a pair of lenses 8305. [0685] The user can see the display on the display portion 8302 through the lenses 8305. Preferably, the display portion 8302 is configured in a bent configuration. By configuring the display portion 8302 in a bent configuration, the user can experience a high sense of reality. Note that in this embodiment, a structure in which one display portion 8302 is provided is exemplified, but the present invention is not limited thereto. For example, a structure in which two display portions 8302 are provided may also be adopted. At this time, when each display unit is arranged on the side of each eye of the user, three-dimensional display using parallax can be performed. [0686] A display device of an embodiment of the present invention can be used for the display unit 8302. Because the display device of an embodiment of the present invention has an extremely high resolution, even if it is enlarged using the lens 8305 as shown in FIG71E, a more realistic image can be displayed without the user seeing the pixels. [0687] á6-3. Electronic device 2ñ Next, FIGS. 72A to 72G show an example of an electronic device different from the electronic device shown in FIGS. 71A to 71E. [0688] The electronic device shown in Figures 72A to 72G includes a housing 9000, a display portion 9001, a speaker 9003, an operating key 9005 (including a power switch or an operating switch), a connecting terminal 9006, a sensor 9007 (the sensor has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared), a microphone 9008, etc. [0689] The electronic device shown in Figures 72A to 72G has various functions. For example, the following functions may be provided: a function of displaying various information (still images, moving images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of controlling processing by using various software (programs); a function of wireless communication; a function of connecting to various computer networks by using a wireless communication function; a function of sending or receiving various data by using a wireless communication function; a function of reading a program or data stored in a storage medium and displaying it on a display unit; etc. Note that the functions that the electronic device shown in FIGS. 72A to 72G may have are not limited to the above functions, but may have various functions. In addition, although not shown in FIGS. 72A to 72G , the electronic device may include a plurality of display units. In addition, a camera or the like may be provided in the electronic device so that it has the following functions: a function of shooting still images; a function of shooting moving images; a function of storing the shot images in a storage medium (an external storage medium or a storage medium built into the camera); a function of displaying the shot images on a display unit; etc. [0690] At least a portion of the present embodiment may be implemented in combination with other embodiments described in this specification as appropriate. [0691] Next, a broadcasting system using the electronic device is described. Here, in particular, a system for transmitting broadcast signals is described. [0692] á Broadcasting systemñ Figure 73 is a block diagram schematically showing an example of the structure of a broadcasting system. The broadcasting system 1500 includes a camera 1510, a transmitter 1511, and an electronic device system 1501. The electronic device system 1501 includes a receiver 1512 and a display device 1513. The camera 1510 includes an image sensor 1520 and an image processor 1521. The transmitter 1511 includes an encoder 1522 and a modulator 1523. [0693] The receiver 1512 and the display device 1513 are composed of an antenna, a demodulator, a decoder, a logic circuit, an image processor, and a display unit included in the electronic device system 1501. Specifically, for example, the receiver 1512 includes an antenna, a demodulator, a decoder, and a logic circuit. The display device 1513 includes an image processor and a display unit. In addition, the decoder and the logic circuit may not be included in the receiver 1512, but included in the display device 1513. [0694] In the case where the camera 1510 is capable of shooting 8K video, the image sensor 1520 includes a number of pixels capable of shooting 8K color images. For example, when a pixel is composed of one red (R) sub-pixel, two green (G) sub-pixels, and one blue (B) sub-pixel, the image sensor 1520 requires at least 7680×4320×4 [R, G+G, B] pixels, and in the case of a 4K camera, the number of pixels of the image sensor 1520 is at least 3840×2160×4, and in the case of a 2K camera, the number of pixels is at least 1920×1080×4. [0695] The image sensor 1520 generates unprocessed Raw data 1540. The image processor 1521 performs image processing (noise removal, interpolation processing, etc.) on the Raw data 1540 and generates video data 1541. The video data 1541 is output to the transmitter 1511. [0696] The transmitter 1511 processes the video data 1541 to generate a broadcast signal 1543 (sometimes referred to as a carrier) suitable for a broadcast band. The encoder 1522 processes the video data 1541 to generate encoded data 1542. The encoder 1522 performs a process of encoding the video data 1541, a process of adding broadcast control data (e.g., authentication data) to the video data 1541, an encryption process, and an interference process (data sorting process for spread spectrum), etc. [0697] In the broadcast system 1500 of FIG. 73, a semiconductor device can be used for the encoder 1522. In addition, a dedicated IC or processor (e.g., GPU, CPU) etc. may be combined to constitute the encoder 1522. In addition, the encoder 1522 may be integrated into a dedicated IC chip. [0698] The modulator 1523 generates and outputs a broadcast signal 1543 by performing IQ modulation (quadrature amplitude modulation) on the encoded data 1542. The broadcast signal 1543 is a composite signal of data having an I (in-phase) component and a Q (quadrature component) component. The TV broadcast station obtains the video data 1541 and supplies the broadcast signal 1543. [0699] The receiver 1512 included in the electronic device system 1501 receives the broadcast signal 1543. [0700] FIG. 74 shows a broadcast system 1500A including other electronic device systems. [0701] The broadcasting system 1500A includes a camera 1510, a transmitter 1511, an electronic device system 1501A, and an image generating device 1530. The electronic device system 1501A includes a receiver 1512 and a display device 1513. The camera 1510 includes an image sensor 1520 and an image processor 1521. The transmitter 1511 includes an encoder 1522A, an encoder 1522B, and a modulator 1523. [0702] The receiver 1512 and the display device 1513 are composed of an antenna, a demodulator, a decoder, an image processor, and a display unit included in the electronic device system 1501A. Specifically, for example, the receiver 1512 includes an antenna, a demodulator and a decoder, and the display device 1513 includes an image processor and a display unit. In addition, the decoder may not be included in the receiver 1512, but included in the display device 1513. [0703] Regarding the camera 1510, the image sensor 1520 and the image processor 1521 included in the camera 1510, refer to the above description. The image processor 1521 generates video data 1541A. The video data 1541A is output to the transmitter 1511. [0704] The image generating device 1530 is a device that generates image data such as text, graphics, patterns, etc. that are attached to the image data generated in the image processor 1521. Image data such as text, graphics or patterns are sent to the transmitter 1511 as video data 1541B. [0705] The transmitter 1511 processes the video data 1541A and the video data 1541B to generate a broadcast signal 1543 (sometimes referred to as a carrier) suitable for the broadcast band. The encoder 1522A processes the video data 1541A to generate encoded data 1542A. In addition, the encoder 1522B processes the video data 1541B to generate encoded data 1542B. Encoder 1522A and encoder 1522B perform processing for encoding video data 1541A and video data 1541B, processing for adding broadcast control data (e.g., authentication data) to video data 1541A and video data 1541B, encryption processing, and interference processing (data sorting processing for spread spectrum), etc. [0706] In addition, broadcast system 1500A may also process video data 1541A and video data 1541B by one encoder as in broadcast system 1500 shown in FIG. 73. [0707] Coded data 1542A and coded data 1542B are sent to modulator 1523. The modulator 1523 generates and outputs a broadcast signal 1543 by performing IQ modulation on the coded data 1542A and the coded data 1542B. The broadcast signal 1543 is a composite signal of data having an I component and a Q component. The TV broadcast station obtains the video data 1541 and supplies the broadcast signal 1543. [0708] The receiver 1512 included in the electronic device system 1501A receives the broadcast signal 1543. [0709] Figure 75 schematically shows data transmission in the broadcast system. Figure 75 shows the path of the radio wave (broadcast signal) transmitted from the broadcast station 1561 to the television (TV) 1560 in each household. The TV 1560 has a receiver 1512 and a display device 1513. As artificial satellite 1562, for example, a CS satellite and a BS satellite can be cited. As antenna 1564, for example, a BS/110° CS antenna and a CS antenna can be cited. As antenna 1565, for example, an ultra-high frequency (UHF: Ultra High Frequency) antenna can be cited. [0710] Radio waves 1566A and 1566B are satellite broadcast signals. After receiving radio wave 1566A, artificial satellite 1562 transmits radio wave 1566B to the ground. By receiving radio wave 1566B with antenna 1564, each household can watch satellite TV broadcasts with TV 1560. Alternatively, the antenna of another radio station receives radio wave 1566B and uses a receiver in the radio station to process it into a signal that can be transmitted via an optical cable. The radio station uses an optical cable network to send broadcast signals to the input unit of TV 1560 in each household. Radio waves 1567A and 1567B are terrestrial broadcast signals. Radio tower 1563 amplifies the received radio wave 1567A and transmits radio wave 1567B. By using antenna 1565 to receive radio wave 1567B, each household can watch terrestrial TV broadcasts on TV 1560. [0711] The video transmission system of the present embodiment is not limited to a TV broadcast system. In addition, the transmitted video data can be dynamic image data or static image data. [0712] Figures 76A, 76B, 76C and 76D show examples of receiver modes. TV 1560 can receive broadcast signals through a receiver and display them on TV 1560. Figure 76A shows a case where a receiver 1571 is set on the outside of TV 1560. In addition, as another example, Figure 76B shows a case where data is transmitted between antennas 1564, 1565 and TV 1560 via wireless devices 1572 and 1573. In this case, wireless device 1572 or wireless device 1573 also has the function of a receiver. In addition, TV 1560 can also have a built-in wireless device 1573 (see Figure 76C). [0713] The receiver can be made small enough to be carried around. The receiver 1574 shown in FIG. 76D includes a connector portion 1575. When electronic devices such as display devices and information terminals (e.g., personal computers, smart phones, mobile phones, tablet terminals, etc.) have terminals that can be connected to the connector portion 1575, satellite broadcasts or terrestrial broadcasts can be viewed using these electronic devices. [0714] At least a portion of this embodiment can be appropriately combined with other embodiments described in this specification and implemented.

[0715]10a‧‧‧灰色調遮罩10b‧‧‧半色調遮罩13‧‧‧透光基板15‧‧‧遮光膜17‧‧‧遮光部18‧‧‧繞射光柵部19‧‧‧透過部21‧‧‧穿透率23‧‧‧半透過膜25‧‧‧遮光膜27‧‧‧遮光部28‧‧‧半透過部29‧‧‧透過部31‧‧‧穿透率100A‧‧‧電晶體100B‧‧‧電晶體100C‧‧‧電晶體100D‧‧‧電晶體100E‧‧‧電晶體102‧‧‧基板104‧‧‧導電膜106‧‧‧絕緣膜108‧‧‧金屬氧化物膜108a‧‧‧金屬氧化物膜108b‧‧‧金屬氧化物膜108_1‧‧‧金屬氧化物膜108_2‧‧‧金屬氧化物膜112‧‧‧導電膜112a‧‧‧導電膜112A‧‧‧導電膜112b‧‧‧導電膜113‧‧‧導電膜114‧‧‧絕緣膜115‧‧‧導電膜115a‧‧‧導電膜115d‧‧‧導電膜116‧‧‧絕緣膜118‧‧‧絕緣膜119‧‧‧絕緣膜120a‧‧‧導電膜120b‧‧‧導電膜128‧‧‧金屬氧化物膜128_1‧‧‧金屬氧化物膜128_2‧‧‧金屬氧化物膜130‧‧‧導電膜130a‧‧‧導電膜130d‧‧‧導電膜132‧‧‧導電膜132a‧‧‧導電膜142‧‧‧開口142a‧‧‧開口142b‧‧‧開口142c‧‧‧開口142d‧‧‧開口144‧‧‧開口144a‧‧‧開口144b‧‧‧開口144c‧‧‧開口146‧‧‧開口146a‧‧‧開口146b‧‧‧開口146d‧‧‧開口148‧‧‧開口148a‧‧‧開口148b‧‧‧開口150A‧‧‧連接部150B‧‧‧連接部150C‧‧‧連接部150D‧‧‧連接部150E‧‧‧連接部151‧‧‧光阻遮罩151a‧‧‧光阻遮罩151b‧‧‧光阻遮罩153‧‧‧光阻遮罩153a‧‧‧光阻遮罩155‧‧‧區域155a‧‧‧區域157‧‧‧區域160‧‧‧開口191‧‧‧靶材192‧‧‧電漿193‧‧‧靶材194‧‧‧電漿200A‧‧‧電晶體200B‧‧‧電晶體200C‧‧‧電晶體200D‧‧‧電晶體200E‧‧‧電晶體204‧‧‧導電膜208‧‧‧金屬氧化物膜208_1‧‧‧金屬氧化物膜208_2‧‧‧金屬氧化物膜228‧‧‧金屬氧化物膜228_1‧‧‧金屬氧化物膜228_2‧‧‧金屬氧化物膜212a‧‧‧導電膜212A‧‧‧導電膜212b‧‧‧導電膜213‧‧‧導電膜215‧‧‧導電膜215a‧‧‧導電膜220‧‧‧導電膜242‧‧‧開口242a‧‧‧開口242b‧‧‧開口242c‧‧‧開口242d‧‧‧開口242e‧‧‧開口250A‧‧‧電容器250B‧‧‧電容器250C‧‧‧電容器250D‧‧‧電容器250E‧‧‧電容器251‧‧‧光阻遮罩251a‧‧‧光阻遮罩253‧‧‧光阻遮罩253a‧‧‧光阻遮罩253b‧‧‧光阻遮罩255‧‧‧區域255a‧‧‧區域501‧‧‧像素電路502‧‧‧像素部504‧‧‧驅動電路部504a‧‧‧閘極驅動器504b‧‧‧源極驅動器506‧‧‧保護電路507‧‧‧端子部550‧‧‧電晶體552‧‧‧電晶體554‧‧‧電晶體560‧‧‧電容器562‧‧‧電容器570‧‧‧液晶元件572‧‧‧發光元件700‧‧‧顯示裝置701‧‧‧基板702‧‧‧像素部704‧‧‧源極驅動電路部705‧‧‧基板706‧‧‧閘極驅動電路部708‧‧‧FPC端子部710‧‧‧信號線711‧‧‧佈線部712‧‧‧密封劑716‧‧‧FPC730‧‧‧絕緣膜732‧‧‧密封膜734‧‧‧絕緣膜736‧‧‧彩色膜738‧‧‧遮光膜750‧‧‧電晶體752‧‧‧電晶體760‧‧‧連接電極770‧‧‧絕緣膜772‧‧‧導電膜773‧‧‧絕緣膜774‧‧‧導電膜775‧‧‧液晶元件776‧‧‧液晶層778‧‧‧結構體780‧‧‧異方性導電膜782‧‧‧發光元件786‧‧‧EL層788‧‧‧導電膜791‧‧‧觸控面板792‧‧‧絕緣膜793‧‧‧電極794‧‧‧電極795‧‧‧絕緣膜796‧‧‧電極797‧‧‧絕緣膜800‧‧‧顯示裝置815‧‧‧控制器IC843‧‧‧感測器844‧‧‧感測器845‧‧‧光853‧‧‧控制器854‧‧‧控制器873‧‧‧控制器884‧‧‧控制器890‧‧‧區域1500‧‧‧廣播系統1500A‧‧‧廣播系統1510‧‧‧攝影機1511‧‧‧發送器1512‧‧‧接收器1513‧‧‧顯示裝置1520‧‧‧影像感測器1521‧‧‧影像處理器1522‧‧‧編碼器1522A‧‧‧編碼器1522B‧‧‧編碼器1523‧‧‧調變器1530‧‧‧影像生成裝置1540‧‧‧Raw資料1541‧‧‧視頻資料1541A‧‧‧視頻資料1541B‧‧‧視頻資料1542‧‧‧編過碼的資料1542A‧‧‧編過碼的資料1542B‧‧‧編過碼的資料1543‧‧‧廣播信號1560‧‧‧電視機(TV)1561‧‧‧廣播電臺1562‧‧‧人造衛星1563‧‧‧電波塔1564‧‧‧天線1565‧‧‧天線1566A‧‧‧電波1566B‧‧‧電波1567A‧‧‧電波1567B‧‧‧電波1571‧‧‧接收器1572‧‧‧無線裝置1573‧‧‧無線裝置1574‧‧‧接收器1575‧‧‧連接器部6000‧‧‧顯示模組6001‧‧‧上蓋6002‧‧‧下蓋6005‧‧‧FPC6006‧‧‧顯示面板6009‧‧‧框架6010‧‧‧印刷電路板6011‧‧‧電池6015‧‧‧發光部6016‧‧‧受光部6017a‧‧‧導光部6017b‧‧‧導光部6018‧‧‧光8000‧‧‧攝影機8001‧‧‧外殼8002‧‧‧顯示部8006‧‧‧鏡頭8101‧‧‧外殼8102‧‧‧顯示部8202‧‧‧透鏡8204‧‧‧顯示部8205‧‧‧電纜8206‧‧‧電池8301‧‧‧外殼8302‧‧‧顯示部8305‧‧‧透鏡9000‧‧‧外殼9001‧‧‧顯示部9003‧‧‧揚聲器9005‧‧‧操作鍵9006‧‧‧連接端子9007‧‧‧感測器[0715]10a‧‧‧Gray tone mask10b‧‧‧Half tone mask13‧‧‧Transparent substrate15‧‧‧Light shielding film17‧‧‧Light shielding portion18‧‧‧Diffraction grating portion19‧‧‧Transparent portion21‧‧‧Transmittance23‧‧‧Semi-transparent film25‧‧‧Light shielding film27‧‧‧Light shielding portion28‧‧‧Semi-transparent portion29‧‧‧Transparent portion31‧‧‧Transmittance100A‧‧‧Transistor100B‧‧‧Transistor100C‧ ‧‧Transistor 100D‧‧‧Transistor 100E‧‧‧Transistor 102‧‧‧Substrate 104‧‧‧Conductive film 106‧‧‧Insulating film 108‧‧‧Metal oxide film 108a‧‧‧Metal oxide film 108b‧‧‧Metal oxide film 108_1‧‧‧Metal oxide film 108_2‧‧‧Metal oxide film 112‧‧‧Conductive film 112a‧‧‧Conductive film 112A‧‧‧Conductive film 112b‧‧‧Conductive film Conductive film 113‧‧‧Conductive film 114‧‧‧Insulating film 115‧‧‧Conductive film 115a‧‧‧Conductive film 115d‧‧‧Conductive film 116‧‧‧Insulating film 118‧‧‧Insulating film 119‧‧‧Insulating film 120a‧‧‧Conductive film 120b‧‧‧Conductive film 128‧‧‧Metal oxide film 128_1‧‧‧Metal oxide film 128_2‧‧‧Metal oxide film 130‧‧‧Conductive film 130a‧‧‧Conductive film Film 130d‧‧‧Conductive film 132‧‧‧Conductive film 132a‧‧‧Conductive film 142‧‧‧Opening 142a‧‧‧Opening 142b‧‧‧Opening 142c‧‧‧Opening 142d‧‧‧Opening 144 ‧‧‧Opening 144a‧‧‧Opening 144b‧‧‧Opening 144c‧‧‧Opening 146‧‧‧ Opening 146a‧‧‧Opening 146b‧‧‧Opening 146d‧‧‧Opening 148‧‧‧Opening 14 8a‧‧‧Opening 148b‧‧‧Opening 150A‧‧‧Connecting portion 150B‧‧‧Connecting portion 150C‧‧‧Connecting portion 150D‧‧‧Connecting portion 150E‧‧‧Connecting portion 151‧‧‧Light blocking mask 151a‧‧‧Light blocking mask 151b‧‧‧Light blocking mask 153‧‧‧Light blocking mask 153a‧‧‧Light blocking mask 155‧‧‧Region 155a‧‧‧Region 157‧‧‧Region 160‧‧‧Opening 19 1‧‧‧Target 192‧‧‧Plasma 193‧‧‧Target 194‧‧‧Plasma 200A‧‧‧Transistor 200B‧‧‧Transistor 200C‧‧‧Transistor 200D‧‧‧Transistor 200E‧‧‧Transistor 204‧‧‧Conductive film 208‧‧‧Metal oxide film 208_1‧‧‧Metal oxide film 208_2‧‧‧Metal oxide film 228‧‧‧Metal oxide film 228_1‧‧‧Metal oxide Film 228_2‧‧‧Metal oxide film 212a‧‧‧Conductive film 212A‧‧‧Conductive film 212b‧‧‧Conductive film 213‧‧‧Conductive film 215‧‧‧Conductive film 215a‧‧‧Conductive film 220‧‧‧Conductive film 242‧‧‧Opening 242a‧‧‧Opening 242b‧‧‧Opening 242c‧‧‧Opening 242d‧‧‧Opening 242e‧‧‧Opening 250A‧‧‧Capacitor 250B‧‧‧Capacitor Device 250C‧‧‧Capacitor 250D‧‧‧Capacitor 250E‧‧‧Capacitor 251‧‧‧Photoresist mask 251a‧‧‧Photoresist mask 253‧‧‧Photoresist mask 253a‧‧‧Photoresist mask 253b‧‧‧Photoresist mask 255‧‧‧Region 255a‧‧‧Region 501‧‧‧Pixel circuit 502‧‧‧Pixel portion 504‧‧‧Drive circuit portion 504a‧‧‧Gate driver 504b‧‧‧Source driver Device 506‧‧‧Protection circuit 507‧‧‧Terminal portion 550‧‧‧Transistor 552‧‧‧Transistor 554‧‧‧Transistor 560‧‧‧Capacitor 562‧‧‧Capacitor 570‧‧‧Liquid crystal element 572‧‧‧Light-emitting element 700‧‧‧Display device 701‧‧‧Substrate 702‧‧‧Pixel portion 704‧‧‧Source drive circuit portion 705‧‧‧Substrate 706‧‧‧Gate drive circuit portion 708‧‧‧FP C terminal portion 710 ‧‧‧Signal line 711 ‧‧‧Wiring portion 712 ‧‧‧Sealing agent 716 ‧‧‧FPC 730 ‧‧‧Insulating film 732 ‧‧‧Sealing film 734 ‧‧‧Insulating film 736 ‧‧‧Colored film 738 ‧‧‧Light shielding film 750 ‧‧‧Transistor 752 ‧‧‧Transistor 760 ‧‧‧Connecting electrode 770 ‧‧‧Insulating film 772 ‧‧‧Conductive film 773 ‧‧‧Insulating film 774 ‧‧‧Conductive film 775 ‧‧ ‧Liquid crystal element776‧‧‧Liquid crystal layer778‧‧‧Structural body780‧‧‧Anisotropic conductive film782‧‧‧Light-emitting element786‧‧‧EL layer788‧‧‧Conductive film791‧‧‧Touch panel792‧‧‧Insulating film793‧‧‧Electrode794‧‧‧Electrode795‧‧‧Insulating film796‧‧‧Electrode797‧‧‧Insulating film800‧‧‧Display device815‧‧‧Controller IC843‧‧‧Sensor 844‧‧‧Sensor845‧‧‧Light853‧‧‧Controller854‧‧‧Controller873‧‧‧Controller884‧‧‧Controller890‧‧‧Region1500‧‧‧Broadcasting system1500A‧‧‧Broadcasting system1510‧‧‧Camera1511‧‧‧Transmitter1512‧‧‧Receiver1513‧‧‧Display device1520‧‧‧Image sensor1521‧‧‧Image processor1522‧‧ ‧Encoder 1522A‧‧‧Encoder 1522B‧‧‧Encoder 1523‧‧‧Modulator 1530‧‧‧Image generating device 1540‧‧‧Raw data 1541‧‧‧Video data 1541A‧‧‧Video data 1541B‧‧‧Video data 1542‧‧‧Encoded data 1542A‧‧‧Encoded data 1542B‧‧‧Encoded data 1543‧‧‧Broadcast signal 1560‧‧ ‧TV 1561‧‧‧Broadcasting station 1562‧‧‧Satellite 1563‧‧‧Radio tower 1564‧‧‧Antenna 1565‧‧‧Antenna 1566A‧‧‧Radio wave 1566B‧‧‧Radio wave 1567A‧‧‧Radio wave 1567B‧‧‧Radio wave 1571‧‧‧Receiver 1572‧‧‧Wireless device 1573‧‧‧Wireless device 1574‧‧‧Receiver 1575‧‧‧Connector unit 600 0‧‧‧Display module6001‧‧‧Upper cover6002‧‧‧Lower cover6005‧‧‧FPC6006‧‧‧Display panel6009‧‧‧Frame6010‧‧‧Printed circuit board6011‧‧‧Battery6015‧‧‧Light emitting unit6016‧‧‧Light receiving unit6017a‧‧‧Light guiding unit6017b‧‧‧Light guiding unit6018‧‧‧Light8000‧‧‧Camera8001‧‧‧Casing8002‧‧‧Display Display unit8006‧‧‧Lens8101‧‧‧Casing8102‧‧‧Display unit8202‧‧‧Lens8204‧‧‧Display unit8205‧‧‧Cable8206‧‧‧Battery8301‧‧‧Casing8302‧‧‧Display unit8305‧‧‧Lens9000‧‧‧Casing9001‧‧‧Display unit9003‧‧‧Speaker9005‧‧‧Operation key9006‧‧‧Connection terminal9007‧‧‧Sensor

[0028] 在圖式中： 圖1A至圖1C是說明顯示裝置的剖面圖； 圖2A和圖2B是說明顯示裝置的俯視圖； 圖3A至圖3C是說明顯示裝置的剖面圖； 圖4A至圖4C是說明顯示裝置的剖面圖； 圖5A和圖5B是說明顯示裝置的俯視圖； 圖6A至圖6C是說明顯示裝置的剖面圖； 圖7A和圖7B是說明顯示裝置的俯視圖； 圖8A至圖8C是說明顯示裝置的剖面圖； 圖9A和圖9B是說明顯示裝置的俯視圖； 圖10A至圖10C是說明顯示裝置的製造方法的剖面圖； 圖11A至圖11C是說明顯示裝置的製造方法的剖面圖； 圖12A至圖12C是說明顯示裝置的製造方法的剖面圖； 圖13A至圖13C是說明顯示裝置的製造方法的剖面圖； 圖14A至圖14C是說明顯示裝置的製造方法的剖面圖； 圖15A至圖15C是說明顯示裝置的製造方法的剖面圖； 圖16A至圖16C是說明顯示裝置的製造方法的剖面圖； 圖17A至圖17C是說明顯示裝置的製造方法的剖面圖； 圖18A至圖18C是說明顯示裝置的製造方法的剖面圖； 圖19A至圖19C是說明顯示裝置的製造方法的剖面圖； 圖20A至圖20C是說明顯示裝置的製造方法的剖面圖； 圖21A至圖21C是說明顯示裝置的製造方法的剖面圖； 圖22A至圖22C是說明顯示裝置的製造方法的剖面圖； 圖23A至圖23C是說明顯示裝置的製造方法的剖面圖； 圖24A至圖24C是說明顯示裝置的製造方法的剖面圖； 圖25A至圖25C是說明顯示裝置的製造方法的剖面圖； 圖26A至圖26C是說明顯示裝置的製造方法的剖面圖； 圖27A至圖27C是說明顯示裝置的製造方法的剖面圖； 圖28A至圖28C是說明顯示裝置的製造方法的剖面圖； 圖29A至圖29C是說明顯示裝置的製造方法的剖面圖； 圖30A至圖30C是說明顯示裝置的製造方法的剖面圖； 圖31A至圖31C是說明顯示裝置的製造方法的剖面圖； 圖32A至圖32C是說明顯示裝置的製造方法的剖面圖； 圖33A至圖33C是說明顯示裝置的製造方法的剖面圖； 圖34A至圖34C是說明顯示裝置的製造方法的剖面圖； 圖35A至圖35C是說明顯示裝置的製造方法的剖面圖； 圖36A至圖36C是說明顯示裝置的製造方法的剖面圖； 圖37A至圖37C是說明顯示裝置的製造方法的剖面圖； 圖38A至圖38C是說明顯示裝置的製造方法的剖面圖； 圖39A至圖39C是說明顯示裝置的製造方法的剖面圖； 圖40A至圖40C是說明顯示裝置的製造方法的剖面圖； 圖41A至圖41C是說明顯示裝置的製造方法的剖面圖； 圖42A至圖42C是說明顯示裝置的製造方法的剖面圖； 圖43A至圖43C是說明顯示裝置的製造方法的剖面圖； 圖44A至圖44C是說明顯示裝置的製造方法的剖面圖； 圖45A和圖45B是示出擴散到金屬氧化物膜中的氧或過量氧的擴散路徑的示意圖； 圖46A至圖46D是多色調遮罩的剖面圖及說明光穿透率的圖； 圖47是金屬氧化物的構成的示意圖； 圖48是說明樣本的XRD譜的測定結果的圖； 圖49A至圖49L是說明樣本的TEM影像及電子束繞射圖案的圖； 圖50A至圖50C是樣本的EDX面分析影像； 圖51是示出顯示裝置的一個實施方式的俯視圖； 圖52是示出顯示裝置的一個實施方式的剖面圖； 圖53是示出顯示裝置的一個實施方式的剖面圖； 圖54是示出顯示裝置的一個實施方式的剖面圖； 圖55是示出顯示裝置的一個實施方式的剖面圖； 圖56是示出顯示裝置的一個實施方式的剖面圖； 圖57是示出顯示裝置的一個實施方式的剖面圖； 圖58是示出顯示裝置的一個實施方式的剖面圖； 圖59是示出顯示裝置的一個實施方式的剖面圖； 圖60是示出顯示裝置的一個實施方式的剖面圖； 圖61是示出顯示裝置的一個實施方式的俯視圖； 圖62是示出顯示裝置的一個實施方式的剖面圖； 圖63是示出顯示裝置的一個實施方式的剖面圖； 圖64A至圖64C是說明顯示裝置的方塊圖及電路圖； 圖65是示出控制器IC的結構實例的方塊圖； 圖66A至圖66C是說明參數的圖； 圖67A和圖67B是示出圖框記憶體的結構實例的圖； 圖68是示出暫存器的結構實例的方塊圖； 圖69是示出暫存器的結構實例的電路圖； 圖70A和圖70B是說明顯示模組的結構例子的圖； 圖71A至圖71E是說明電子裝置的圖； 圖72A至圖72G是說明電子裝置的圖； 圖73是示出廣播系統的結構實例的方塊圖； 圖74是示出廣播系統的結構實例的方塊圖； 圖75是示出廣播系統的資料傳輸的示意圖； 圖76A至圖76D是示出接收器的結構實例的圖。[0028] In the drawings: FIGS. 1A to 1C are cross-sectional views illustrating a display device; FIGS. 2A and 2B are top views illustrating a display device; FIGS. 3A to 3C are cross-sectional views illustrating a display device; FIGS. 4A to 4C are cross-sectional views illustrating a display device; FIGS. 5A and 5B are top views illustrating a display device; FIGS. 6A to 6C are cross-sectional views illustrating a display device; FIGS. 7A and 7B are top views illustrating a display device; FIGS. 8A to 8C are cross-sectional views illustrating a display device; FIGS. 9A and 9B are top views illustrating a display device; FIGS. 10A to 10C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 11A to 11C are cross-sectional views illustrating a method for manufacturing a display device; 12A to 12C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 13A to 13C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 14A to 14C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 15A to 15C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 16A to 16C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 17A to 17C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 18A to 18C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 19A to 19C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 20A to 20C are cross-sectional views illustrating a method for manufacturing a display device; 21A to 21C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 22A to 22C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 23A to 23C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 24A to 24C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 25A to 25C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 26A to 26C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 27A to 27C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 28A to 28C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 29A to 29C are cross-sectional views illustrating a method for manufacturing a display device; 30A to 30C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 31A to 31C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 32A to 32C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 33A to 33C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 34A to 34C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 35A to 35C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 36A to 36C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 37A to 37C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 38A to 38C are cross-sectional views illustrating a method for manufacturing a display device; FIGS. 39A to 39C are cross-sectional views for explaining a method for manufacturing a display device; FIGS. 40A to 40C are cross-sectional views for explaining a method for manufacturing a display device; FIGS. 41A to 41C are cross-sectional views for explaining a method for manufacturing a display device; FIGS. 42A to 42C are cross-sectional views for explaining a method for manufacturing a display device; FIGS. 43A to 43C are cross-sectional views for explaining a method for manufacturing a display device; FIGS. 44A to 44C are cross-sectional views for explaining a method for manufacturing a display device; FIGS. 45A and 45B are schematic diagrams showing diffusion paths of oxygen or excess oxygen diffused into a metal oxide film; FIGS. 46A to 46D are cross-sectional views of a multi-tone mask and diagrams for explaining light transmittance; FIG. 47 is a schematic diagram of the composition of a metal oxide; FIG. 48 is a diagram illustrating the measurement result of the XRD spectrum of the sample; FIG. 49A to FIG. 49L are diagrams illustrating the TEM images and electron beam diffraction patterns of the sample; FIG. 50A to FIG. 50C are EDX surface analysis images of the sample; FIG. 51 is a top view showing an embodiment of the display device; FIG. 52 is a cross-sectional view showing an embodiment of the display device; FIG. 53 is a cross-sectional view showing an embodiment of the display device; FIG. 54 is a cross-sectional view showing an embodiment of the display device; FIG. 55 is a cross-sectional view showing an embodiment of the display device; FIG. 56 is a cross-sectional view showing an embodiment of the display device; FIG. 57 is a cross-sectional view showing an embodiment of the display device; FIG. 58 is a cross-sectional view showing an embodiment of the display device; FIG. 59 is a cross-sectional view showing an embodiment of a display device; FIG. 60 is a cross-sectional view showing an embodiment of a display device; FIG. 61 is a top view showing an embodiment of a display device; FIG. 62 is a cross-sectional view showing an embodiment of a display device; FIG. 63 is a cross-sectional view showing an embodiment of a display device; FIGS. 64A to 64C are block diagrams and circuit diagrams illustrating a display device; FIG. 65 is a block diagram showing a structural example of a controller IC; FIGS. 66A to 66C are diagrams illustrating parameters; FIGS. 67A and 67B are diagrams showing a structural example of a frame memory; FIG. 68 is a block diagram showing a structural example of a register; FIG. 69 is a circuit diagram showing a structural example of a register; Figures 70A and 70B are diagrams illustrating a structural example of a display module; Figures 71A to 71E are diagrams illustrating an electronic device; Figures 72A to 72G are diagrams illustrating an electronic device; Figure 73 is a block diagram showing a structural example of a broadcasting system; Figure 74 is a block diagram showing a structural example of a broadcasting system; Figure 75 is a schematic diagram showing data transmission of the broadcasting system; Figures 76A to 76D are diagrams showing a structural example of a receiver.

100A‧‧‧電晶體 100A‧‧‧Transistor

102‧‧‧基板 102‧‧‧Substrate

104‧‧‧導電膜 104‧‧‧Conductive film

106‧‧‧絕緣膜 106‧‧‧Insulation film

108‧‧‧金屬氧化物膜 108‧‧‧Metal oxide film

108_1‧‧‧金屬氧化物膜 108_1‧‧‧Metal oxide film

108_2‧‧‧金屬氧化物膜 108_2‧‧‧Metal oxide film

112a‧‧‧導電膜 112a‧‧‧Conductive film

112b‧‧‧導電膜 112b‧‧‧Conductive film

113‧‧‧導電膜 113‧‧‧Conductive film

114‧‧‧絕緣膜 114‧‧‧Insulation film

115a‧‧‧導電膜 115a‧‧‧Conductive film

116‧‧‧絕緣膜 116‧‧‧Insulation film

118‧‧‧絕緣膜 118‧‧‧Insulation film

119‧‧‧絕緣膜 119‧‧‧Insulation film

120a‧‧‧導電膜 120a‧‧‧conductive film

128‧‧‧金屬氧化物膜 128‧‧‧Metal oxide film

128_1‧‧‧金屬氧化物膜 128_1‧‧‧Metal oxide film

128_2‧‧‧金屬氧化物膜 128_2‧‧‧Metal oxide film

130a‧‧‧導電膜 130a‧‧‧Conductive film

142a‧‧‧開口 142a‧‧‧Opening

144a‧‧‧開口 144a‧‧‧Opening

150A‧‧‧連接部 150A‧‧‧Connection section

Claims (8)

一種顯示裝置，包括： 像素部；以及 驅動該像素部的驅動電路， 其中，該像素部包括： 第一電晶體； 在該第一電晶體上的第一絕緣膜；以及 在該第一絕緣膜上的像素電極，該像素電極與該第一電晶體電連接， 該驅動電路包括： 第二電晶體； 在該第二電晶體上的該第一絕緣膜；以及 連接部， 該第二電晶體包括： 第一閘極電極； 與該第一閘極電極重疊的金屬氧化物膜； 與該金屬氧化物膜重疊的第二閘極電極； 在該金屬氧化物膜上並與其接觸的源極電極及汲極電極；以及 在該第一絕緣膜上的第一佈線，該第一佈線藉由形成在該第一絕緣膜中的第一開口和第二開口使該第一閘極電極和該第二閘極電極連接， 該源極電極的外端部及該汲極電極的外端部位於該金屬氧化物膜的端部的內側， 該連接部包括： 與該第一閘極電極相同的表面上的第二佈線； 與該源極電極及該汲極電極相同的表面上的第三佈線；以及 使該第二佈線和該第三佈線連接的第四佈線， 並且，該像素電極、該第一佈線、及該第四佈線包括相同的層。 A display device includes: a pixel portion; and a driving circuit for driving the pixel portion, wherein the pixel portion includes: a first transistor; a first insulating film on the first transistor; and a pixel electrode on the first insulating film, the pixel electrode being electrically connected to the first transistor, the driving circuit includes: a second transistor; the first insulating film on the second transistor; and a connecting portion, the second transistor includes: a first gate electrode; a metal oxide film overlapping the first gate electrode; a second gate electrode overlapping the metal oxide film; a source electrode and a drain electrode on and in contact with the metal oxide film; and a first wiring on the first insulating film, the first wiring connecting the first gate electrode and the second gate electrode via a first opening and a second opening formed in the first insulating film, an outer end of the source electrode and an outer end of the drain electrode are located inside the end of the metal oxide film, the connecting portion includes: a second wiring on the same surface as the first gate electrode; a third wiring on the same surface as the source electrode and the drain electrode; and a fourth wiring connecting the second wiring and the third wiring, Furthermore, the pixel electrode, the first wiring, and the fourth wiring include the same layer. 一種顯示裝置，包括： 像素部；以及 驅動該像素部的驅動電路， 其中，該像素部包括： 第一電晶體； 在該第一電晶體上的第一絕緣膜，該第一絕緣膜具有平坦表面；以及 在該第一絕緣膜的該平坦表面上的像素電極，該像素電極與該第一電晶體電連接， 該驅動電路包括： 第二電晶體； 在該第二電晶體上的該第一絕緣膜；以及 連接部， 該第二電晶體包括： 金屬氧化物膜； 隔著該金屬氧化物膜彼此相對的第一閘極電極及第二閘極電極； 在該金屬氧化物膜上並與其接觸的源極電極及汲極電極；以及 在該第一絕緣膜的該平坦表面上的第一佈線，該第一佈線藉由形成在該第一絕緣膜中的第一開口和第二開口使該第一閘極電極和該第二閘極電極連接， 該源極電極的端部及該汲極電極的端部未延伸超過該金屬氧化物膜的端部， 該連接部包括： 位於與該第一閘極電極相同的表面上的第二佈線； 位於與該源極電極及該汲極電極相同的表面上的第三佈線，以及 在該第一絕緣膜的該平坦表面上的第四佈線，該第四佈線使該第二佈線和該第三佈線連接， 並且，該像素電極、該第一佈線、及該第四佈線包括相同的層。 A display device includes: a pixel portion; and a driving circuit for driving the pixel portion, wherein the pixel portion includes: a first transistor; a first insulating film on the first transistor, the first insulating film having a flat surface; and a pixel electrode on the flat surface of the first insulating film, the pixel electrode being electrically connected to the first transistor, the driving circuit includes: a second transistor; the first insulating film on the second transistor; and a connecting portion, the second transistor includes: a metal oxide film; a first gate electrode and a second gate electrode facing each other across the metal oxide film; a source electrode and a drain electrode on and in contact with the metal oxide film; and A first wiring on the flat surface of the first insulating film, the first wiring connecting the first gate electrode and the second gate electrode through a first opening and a second opening formed in the first insulating film, The end of the source electrode and the end of the drain electrode do not extend beyond the end of the metal oxide film, The connecting portion includes: A second wiring located on the same surface as the first gate electrode; A third wiring located on the same surface as the source electrode and the drain electrode, and A fourth wiring on the flat surface of the first insulating film, the fourth wiring connecting the second wiring and the third wiring, Furthermore, the pixel electrode, the first wiring, and the fourth wiring include the same layer. 根據申請專利範圍第1或2項中任一項之顯示裝置，其中該金屬氧化物膜包括第一金屬氧化物層及在該第一金屬氧化物層上的第二金屬氧化物層。A display device according to any one of item 1 or 2 of the patent application scope, wherein the metal oxide film includes a first metal oxide layer and a second metal oxide layer on the first metal oxide layer. 根據申請專利範圍第1或2項中任一項之顯示裝置，其中該金屬氧化物膜包含銦、鋅及氧。A display device according to any one of item 1 or 2 of the patent application scope, wherein the metal oxide film contains indium, zinc and oxygen. 根據申請專利範圍第4項之顯示裝置，其中該金屬氧化物膜還包含元素M，該元素M為鎵、鋁、矽、硼、釔、錫、銅、釩、鈹、鈦、鐵、鎳、鍺、鋯、鉬、鑭、鈰、釹、鉿、鉭、鎢和鎂中的一種或多種。According to the display device of item 4 of the patent application scope, the metal oxide film also contains element M, and the element M is one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, curium, titanium, iron, nickel, germanium, zirconium, molybdenum, lumber, barium, neodymium, uranium, tungsten and magnesium. 根據申請專利範圍第5項之顯示裝置，其中該金屬氧化物膜包括： 銦的含量佔據銦、該元素M和鋅原子的總和的40%以上且50%以下的區域；以及 該元素M的含量佔據銦、該元素M和鋅原子的該總和的5%以上且30%以下的區域。 According to the display device of item 5 of the patent application, the metal oxide film includes: A region in which the content of indium accounts for more than 40% and less than 50% of the total of indium, the element M and zinc atoms; and A region in which the content of the element M accounts for more than 5% and less than 30% of the total of indium, the element M and zinc atoms. 根據申請專利範圍第5項之顯示裝置，其中在該金屬氧化物膜中，銦、該元素M及鋅的原子數比為4：x：y，其中x為1.5以上且2.5以下，y為2以上且4以下。According to the display device of item 5 of the patent application scope, in the metal oxide film, the atomic number ratio of indium, the element M and zinc is 4:x:y, wherein x is greater than 1.5 and less than 2.5, and y is greater than 2 and less than 4. 一種電子裝置，包括： 申請專利範圍第1或2項中任一項之顯示裝置；以及 接收器。 An electronic device comprising: a display device of any one of item 1 or 2 of the patent application scope; and a receiver.
TW106133312A 2016-10-07 2017-09-28 Display device and electronic device TWI880886B (en)

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