TWI880619B - Semiconductor device and memory device with 3d package thereof - Google Patents

Abstract

The present application is related to a semiconductor device and a memory device with 3D package thereof. The semiconductor device comprises an electronic component layer, a first connection pad layer, a second connection pad layer and a plurality of first connectors. The first connection pad layer comprises a first connection pad for connecting to electronic components. The second connection pad layer comprises a second connection pad for connecting to the first connection pad. The first connectors are disposed in the electronic component layer or disposed on the second connection pad layer and are away from the electronic component layer. One of the first connectors is electrically connected to the second connection pad. Thus, the semiconductor device of the present application can be packaged by Wafer-on-Wafer technology through the first connection pad layer, the second connection pad layer and the plurality of first connectors and is compatible with existing 2D package technology. Therefore, the effect of improving the convenience of electronic device package is achieved.

Description

Semiconductor device and 3D packaged memory device

The present application relates to a semiconductor device, and more particularly to a semiconductor device and a 3D packaged memory device thereof.

Semiconductor devices are electronic devices that use semiconductor materials to implement electronic circuit components. For example, a sequencer/deserializer (SerDes) chip is a semiconductor device that can meet the transmission speed requirements of data transmission interfaces such as HDMI (High Definition Multimedia Interface), DDR (Double Data Rate), and MIPI (Mobile Industry Processor Interface) to perform high-speed data transmission.

At the same time, in order to meet the requirements of electronic products for performance and overall volume, a wafer stacking technology (Wafer-on-Wafer, WoW) to achieve 3D packaging technology has been proposed. However, existing semiconductor devices are limited by their architecture design and can only be applied to products with 2D packaging structures, and cannot be directly applied to electronic products made with wafer stacking technology (Wafer-on-Wafer, WoW).

Therefore, how to propose a novel semiconductor device that is suitable for wafer stacking technology is one of the problems that this field wants to solve.

In order to solve the above-mentioned technical problems, the present application proposes a semiconductor device and a 3D packaged memory device embodiment thereof, which allows the existing semiconductor device to be directly packaged with other chips using wafer stacking technology by setting connection pads and connectors, and is also compatible with the existing 2D packaging technology, thereby achieving the purpose of improving the convenience of electronic device packaging.

In order to achieve the above-mentioned purpose, the present application proposes a semiconductor device embodiment, including an electronic component layer, a first connection pad layer, a second connection pad layer and a plurality of first connectors. The electronic component layer includes an electronic component. The first connection pad layer is arranged on the electronic component layer, including a first connection pad, and the first connection pad is electrically connected to the electronic component. The second connection pad layer is arranged on the first connection pad layer, including a second connection pad, and the second connection pad is electrically connected to the first connection pad. The first connectors are arranged in the electronic component layer or on the second connection pad layer and away from the electronic component layer, and one of the first connectors is electrically connected to the second connection pad.

In order to achieve the above-mentioned purpose, the present application proposes a 3D packaged memory device, including an intermediate layer and a high-speed data exchange layer. The high-speed data exchange layer is arranged on the intermediate layer, and includes a semiconductor device. The semiconductor device includes an electronic component layer, a first connection pad layer, a second connection pad layer and a plurality of silicon through vias. The electronic component layer includes an electronic component. The first connection pad layer is arranged on the electronic component layer, and includes a first connection pad, and the first connection pad is electrically connected to the electronic component. The second connection pad layer is arranged on the first connection pad layer, and includes a second connection pad, and the second connection pad is electrically connected to the first connection pad. A plurality of through silicon vias are disposed in the electronic component layer, and one of the through silicon vias is electrically connected to the second connection pad.

Through the above content, the semiconductor device of the present application and the memory device embodiment of the 3D package thereof are provided with a second connection pad and a first connector, and the first connector can be arranged in the electronic component layer, so that the electronic components of the electronic component layer can be electrically connected to the first connector through the second connection pad, so that the wafer stacking technology can be used to package with other chips. At the same time, the first connector can also be arranged on a side of the semiconductor device away from the electronic component layer, so that the semiconductor device can be compatible with the existing 2D packaging technology. Thereby, the present application can not only be packaged with other chips by wafer stacking technology, but also be compatible with the existing 2D packaging technology, so as to achieve the purpose of improving the convenience of electronic device packaging.

Please refer to FIG. 1 and FIG. 2 , which are schematic diagrams of a semiconductor device embodiment of the present application. The semiconductor device 1000 includes an electronic component layer 100 ( 100 a ) and a connection layer 200 , and the connection layer 200 is disposed on the electronic component layer 100 .

In the embodiment of FIG. 1 and FIG. 2 , the electronic component layer 100a has an upper surface 101 and a lower surface 102, and the lower surface 102 is provided with a plurality of connection pads (layer) 130. The electronic component layer 100a includes a plurality of connectors 110 and a plurality of electronic components 120. In this embodiment, the plurality of electronic components 120 are transistor components.

In the embodiments of FIG. 1 and FIG. 2 , a plurality of connectors 110 are disposed in the electronic component layer 100a, so that the upper surface 101 and the lower surface 102 of the electronic component layer 100a are connected through the plurality of connectors 110. One end of each connector 110 is electrically connected to a connection pad (layer) 130. In this embodiment, the connector 110a is electrically connected to the connection pad (layer) 130a, the connector 110b is electrically connected to the connection pad (layer) 130b, and the connector 110c is electrically connected to the connection pad (layer) 130c. In this embodiment, the plurality of connectors 110 are disposed on one side of the plurality of electronic components 120. In this embodiment, the plurality of connectors 110 are used to provide the voltage level or signal required by the plurality of electronic components 120. For example, the connector 110a receives an input signal through the connection pad (layer) 130a, the connector 110b receives a first voltage level through the connection pad (layer) 130b, and the connector 110c receives a second voltage level through the connection pad (layer) 130c, wherein the input signal is, for example, an input voltage level, the voltage value of the second voltage level is greater than the voltage value of the first voltage level, the second voltage level is, for example, a power voltage, and the first voltage level is, for example, a ground voltage. In this embodiment, the plurality of connectors 110 are through silicon vias (TSV).

In the embodiment of FIG. 1 and FIG. 2 , the connection layer 200 includes a first connection pad layer 210, and the first connection pad layer 210 is disposed on the electronic component layer 100a. The first connection pad layer 210 is provided with a plurality of first connection pads (layer) 211 and a plurality of connection pads (layer) 212. The plurality of first connection pads (layer) 211 are electrically connected to the plurality of electronic components 120. The plurality of connection pads (layer) 212 are electrically connected to the plurality of connectors 110.

In the embodiment of FIG. 1 and FIG. 2 , the connection layer 200 includes a first connection column layer 220, and the first connection column layer 220 is disposed on the first connection pad layer 210. The first connection column layer 220 is provided with a plurality of first connection columns (vias) 221 and a plurality of connection columns (vias) 222. The plurality of first connection columns (vias) 221 are electrically connected to the plurality of first connection pads (layer) 211. The plurality of connection columns (vias) 222 are electrically connected to the plurality of connection pads (layer) 212.

In the embodiment of FIG. 1 and FIG. 2 , the connection layer 200 includes a second connection pad layer 230, and the second connection pad layer 230 is disposed on the first connection column layer 220. The second connection pad layer 230 is provided with a plurality of second connection pads (layers) 231 and a connection pad (layer) 232. The connection pad (layer) 232 is electrically connected to the connection column (via) 222. The plurality of second connection pads (layers) 231 are electrically connected to the plurality of first connection columns (via) 221. At least one second connection pad (layer) 231 is further electrically connected to the connection column (via) 222. For example, the second connection pad 231a is further electrically connected to the connection column (via) 222, and the second connection pad 231b is further electrically connected to the connection column (via) 222. Thus, the connector 110b can provide a first voltage level to the electronic component 120 through the second connection pad (layer) 231b, and the connector 110c can provide a second voltage level to another electronic component 120 through the second connection pad (layer) 231a.

In the embodiment of FIG. 1 and FIG. 2 , the connection layer 200 includes a second connection column layer 240, and the second connection column layer 240 is disposed on the second connection pad layer 230. The second connection column layer 240 is provided with a plurality of second connection columns (vias) 241 and a connection column (via) 242. The plurality of second connection columns (vias) 241 are electrically connected to the plurality of second connection pads (layer) 231. The connection column (via) 242 is electrically connected to the connection pad (layer) 232.

In the embodiment of FIG. 1 and FIG. 2 , the connection layer 200 includes a third connection pad layer 250, and the third connection pad layer 250 is disposed on the second connection column layer 240. The third connection pad layer 250 includes a third connection pad (layer) 251 and a connection pad (layer) 252. The third connection pad (layer) 251 is electrically connected to a plurality of second connection columns (vias) 241. The connection pad (layer) 252 is electrically connected to the connection columns (vias) 242.

In the embodiment of FIG. 1 and FIG. 2 , the connection layer 200 includes a third connection column layer 260, and the third connection column layer 260 is disposed on the third connection pad layer 250. The third connection column layer 260 is provided with a third connection column (via) 261 and a connection column (via) 262. The third connection column (via) 261 is electrically connected to the third connection pad (layer) 251. The connection column (via) 262 is electrically connected to the connection pad (layer) 252.

In the embodiment of FIG. 1 and FIG. 2 , the connection layer 200 includes a fourth connection pad layer 270, and the fourth connection pad layer 270 is disposed on the third connection column layer 260. The fourth connection pad layer 270 includes a fourth connection pad (layer) 271 and a connection pad (layer) 272. The fourth connection pad (layer) 271 is electrically connected to the third connection column (via) 261. The connection pad (layer) 272 is electrically connected to the connection column (via) 262.

In the embodiment of FIG. 1 and FIG. 2 , the connection layer 200 includes a fourth connection column layer 280, and the fourth connection column layer 280 is disposed on the fourth connection pad layer 270. The fourth connection column layer 280 is provided with a fourth connection column (via) 281 and a connection column (via) 282. The fourth connection column (via) 281 is electrically connected to the fourth connection pad (layer) 271. The connection column (via) 282 is electrically connected to the connection pad (layer) 272.

In the embodiment of FIG. 1 and FIG. 2 , the connection layer 200 includes a top connection layer 290, and the top connection layer 290 is disposed on the fourth connection column layer 280. The top connection layer 290 is provided with a top connection pad (layer) 291, and the top connection pad (layer) 291 is electrically connected to the fourth connection column (via) 281 and the connection column (via) 282. Thus, the connector 110a can provide an input signal to the electronic element 120 through the top connection pad (layer) 291.

In this embodiment, the number of connection pad layers and connection column layers is only an example. The number and configuration of the connection pad layers and connection column layers can be adjusted according to actual needs, that is, this application is not limited to the number shown in Figures 1 and 2.

In this embodiment, the semiconductor device 1000 is provided with a connector 110 on the electronic component layer 100a, and the electronic component 120 is electrically connected to the connector 110 through the connection pads of the connection layer 200 (e.g., the second connection pad (layer) 231, the third connection pad (layer) 251), so that the semiconductor device 1000 can be packaged with other chips through the connector 110 and the connection pad (layer) by wafer stacking technology. At the same time, in this embodiment, the existing semiconductor device can be packaged with other chips by wafer stacking technology without changing the internal structure of the existing semiconductor device (e.g., area A). Therefore, the embodiment of the present application can achieve the purpose of improving the convenience of electronic device packaging.

Please refer to Figures 3 and 4, which are another schematic diagram of the semiconductor device embodiment of the present application. In this embodiment, the semiconductor device 1000 includes an electronic component layer 100 (100b), a connection layer 300 and a connector connection layer 400, wherein the connection layer 300 is disposed on the electronic component layer 100, and the connector connection layer 400 is disposed on the connection layer 300.

In the embodiment of FIG. 3 and FIG. 4 , the difference between the electronic component layer 100 b and the electronic component layer 100 a is that the electronic component layer 100 b is not provided with the aforementioned connector 110 .

In the embodiment shown in FIG. 3 and FIG. 4 , the connection layer 300 includes a first connection pad layer 310 , which is disposed on the electronic component layer 100 b . The first connection pad layer 310 includes a plurality of first connection pads (layers) 311 . The plurality of first connection pads (layers) 311 are electrically connected to the plurality of electronic components 120 .

In the embodiment shown in FIG3 and FIG4 , the connection layer 300 includes a first connection column layer 320 , and the first connection column layer 320 is disposed on the first connection pad layer 310 . The first connection column layer 320 is provided with a plurality of first connection columns (vias) 321 . The plurality of first connection columns (vias) 321 are electrically connected to the plurality of first connection pads (layers) 311 .

In the embodiment shown in FIG. 3 and FIG. 4 , the connection layer 300 includes a second connection pad layer 330 , which is disposed on the first connection column layer 320 . The second connection pad layer 330 includes a plurality of second connection pads (layers) 331 . The plurality of second connection pads (layers) 331 are electrically connected to the plurality of first connection columns (vias) 321 .

In the embodiment of FIG. 3 and FIG. 4 , the connection layer 300 includes a second connection column layer 340, and the second connection column layer 340 is disposed on the second connection pad layer 330. The second connection column layer 340 is provided with a plurality of second connection columns (vias) 341 and connection columns (vias) 342. The plurality of second connection columns (vias) 341 are electrically connected to the plurality of second connection pads (layers) 331. The connection columns (vias) 342 are electrically connected to a portion of the plurality of second connection pads (layers) 331. For example, the connection column (via) 342a is electrically connected to the second connection pad (layer) 331a, and the connection column (via) 342b is electrically connected to the second connection pad (layer) 331b.

In the embodiment of FIG. 3 and FIG. 4 , the connection layer 300 includes a third connection pad layer 350, and the third connection pad layer 350 is disposed on the second connection column layer 340. The third connection pad layer 350 is provided with a third connection pad (layer) 351 and a connection pad (layer) 352. The third connection pad (layer) 351 is electrically connected to a plurality of second connection columns (vias) 341. The connection pad (layer) 352 is electrically connected to the connection columns (vias) 342.

In the embodiment of FIG. 3 and FIG. 4 , the connection layer 300 includes a third connection column layer 360, and the third connection column layer 360 is disposed on the third connection pad layer 350. The third connection column layer 360 is provided with a third connection column (via) 361 and a connection column (via) 362. The third connection column (via) 361 is electrically connected to the third connection pad (layer) 351. The connection column (via) 362 is electrically connected to the connection pad (layer) 352.

In the embodiment of FIG. 3 and FIG. 4 , the connection layer 300 includes a fourth connection pad layer 370, and the fourth connection pad layer 370 is disposed on the third connection column layer 360. The fourth connection pad layer 370 includes a fourth connection pad (layer) 371 and a connection pad (layer) 372. The fourth connection pad (layer) 371 is electrically connected to the third connection column (via) 361. The connection pad (layer) 372 is electrically connected to the connection column (via) 362.

In the embodiment of FIG. 3 and FIG. 4 , the connection layer 300 includes a fourth connection column layer 380, and the fourth connection column layer 380 is disposed on the fourth connection pad layer 370. The fourth connection column layer 380 is provided with a fourth connection column (via) 381 and a connection column (via) 382. The fourth connection column (via) 381 is electrically connected to the fourth connection pad (layer) 371. The connection column (via) 382 is electrically connected to the connection pad (layer) 372.

In the embodiment of FIG. 3 and FIG. 4 , the connection layer 300 includes a top connection layer 390, and the top connection layer 390 is disposed on the fourth connection column layer 380. The top connection layer 390 is provided with a top connection pad (layer) 391 and a connection pad (layer) 392. The top connection pad (layer) 391 is electrically connected to the fourth connection column (via) 381. The connection pad (layer) 392 is electrically connected to the connection column (via) 382.

In the embodiment of FIG. 3 and FIG. 4 , the connector connection layer 400 includes a first connection layer 410, which is disposed on the top connection layer 390. The first connection layer 410 is provided with a plurality of connection posts (vias) 411, and the plurality of connection posts (vias) 411 are electrically connected to the top connection pad (layer) 391 and the connection pad (layer) 392, respectively.

In the embodiment of FIG. 3 and FIG. 4 , the connector connection layer 400 includes a second connection layer 420, and the second connection layer 420 is disposed on the first connection layer 410. The second connection layer 420 is provided with a plurality of connection pads (layers) 421, and some of the connection pads (layers) 421 are electrically connected to the connection pillars (vias) 411. For example, the connection pads (layers) 421a and the connection pads (layers) 421c are electrically connected to the connection pillars (vias) 411, respectively. In this embodiment, the connection pads (layers) 421b are used to be electrically connected to the corresponding connection pads (layers) 372 through other stacked layers (not shown).

In the embodiment of FIG. 3 and FIG. 4 , the connector connection layer 400 includes a third connection layer 430, and the third connection layer 430 is disposed on the second connection layer 420. The third connection layer 430 is provided with a plurality of connection pads (layer) 431, and the plurality of connection pads (layer) 431 are electrically connected to the connection pad (layer) 421, respectively, to form the connector 450 of the embodiment of the present application. That is, in this embodiment, the connector 450 is realized by the electrically connected connection pad (layer) 431 and the connection pad (layer) 421. For example, the connector 450a is realized by the connection pad (layer) 431a and the connection pad (layer) 421a.

In the embodiment of FIG. 3 and FIG. 4 , a plurality of connection pads 440 are disposed on the upper surface 401 of the connector connection layer 400 , and each connection pad 440 is electrically connected to the connection pad 431 , respectively. Thus, the plurality of connectors 450 can receive the voltage level or signal required by the plurality of electronic components 120 through the connection pads 440 . For example, connector 450a receives a first voltage level through connecting pad (layer) 440a, connector 450b receives an input signal through connecting pad (layer) 440b, and connector 450c receives a second voltage level through connecting pad (layer) 440c, wherein the voltage value of the second voltage level is greater than the voltage value of the first voltage level, the second voltage level is, for example, a power supply voltage, and the first voltage level is, for example, a ground voltage.

In this embodiment, the number of connection pad layers and connection column layers is only an example. The number and configuration of the connection pad layers and connection column layers can be adjusted according to actual needs, that is, this application is not limited to the number shown in Figures 3 and 4.

In this embodiment, the semiconductor device 1000 electrically connects the electronic element 120 to the connector 450 through the connection pad of the connection layer 300, so that the semiconductor device 1000 can be packaged with other chips through the connector 450 and the connection pad using the 2D chip packaging technology. At the same time, in this embodiment, the semiconductor device 1000 can be provided with the connection pad without changing the internal structure of the existing semiconductor device (area A in FIG. 4 ), so that the existing semiconductor device is not only applicable to the wafer stacking technology, but also can be packaged using the existing 2D chip packaging technology. Therefore, the embodiment of the present application can achieve the purpose of improving the convenience of electronic device packaging.

Please refer to FIG. 5, which is another schematic diagram of a semiconductor device embodiment of the present application. In this embodiment, the semiconductor device 1000 can be implemented in combination with the embodiments of FIG. 1 to FIG. 4, and the elements are the same as the elements of FIG. 1 to FIG. 4, so they are not repeated here. Therefore, in this embodiment, the semiconductor device 1000 includes both the connector 110 and the connector 450.

In this embodiment, the semiconductor device 1000 of the present application embodiment can be applied to both 2D chip packaging technology and wafer stacking technology, and can further achieve the purpose of improving the convenience of electronic device packaging.

Please refer to FIG. 6 and FIG. 7, which are another schematic diagram of the semiconductor device embodiment of the present application. The difference between the embodiment of FIG. 6 and FIG. 7 and the embodiment of FIG. 5 is that the connector 110 and the connector 450 may not be electrically connected to each other. For example, in the embodiment of FIG. 6, the connector 450 may not be electrically connected to the top connection layer (290 or 390), the third connection pad layer (250 or 350) and the second connection pad layer 230 by not providing a connection column (via) and/or a connection pad (layer), so that the connector 110 and the connector 450 are not electrically connected to each other. For example, in the embodiment of FIG. 7 , by not providing a connection column (via) and/or a connection pad (layer), the connector 110 is not electrically connected to the top connection layer (290 or 390), the third connection pad layer (250 or 350), and the second connection pad layer 230, so the connector 110 and the connector 450 are not electrically connected to each other. In other embodiments, part of the connector 110 and the connector 450 can also be electrically connected to the top connection layer (290 or 390), the third connection pad layer (250 or 350), and the second connection pad layer 230 as required. That is, the connector 110 and the connector 450 of the present application are not limited to the electrical connection method of Figures 1 to 7. The connector 110 and the connector 450 of the present application can be electrically connected to the top connection layer (290 or 390), the third connection pad layer (250 or 350) and the second connection pad layer 230 as needed.

Please refer to FIG8 , which is another schematic diagram of a semiconductor device embodiment of the present application. The semiconductor device 1000 includes an electronic component layer 100 ( 100 c ) and a connection layer 500 , wherein the connection layer 500 is disposed on the electronic component layer 100 .

In the embodiment shown in FIG. 8 , the difference between the electronic component layer 100 c and the electronic component layer 100 a is that the connector 110 a is disposed between two electronic components 120 .

In the embodiment of FIG. 8 , the connection layer 500 includes a first connection pad layer 510, and the first connection pad layer 510 is disposed on the electronic component layer 100c. The first connection pad layer 510 is provided with a plurality of first connection pads (layer) 511 and a plurality of connection pads (layer) 512. The plurality of first connection pads (layer) 511 are electrically connected to the plurality of electronic components 120. The plurality of connection pads (layer) 512 are electrically connected to a portion of the connectors 110. For example, the plurality of connection pads (layer) 512 are electrically connected to the connectors 110b and the connectors 110c, respectively. In this embodiment, since the connector 110a is disposed between two electronic components 120, in order to prevent the connector 110a from affecting the electrical properties of the electronic components 120, the connection pad (layer) 512 is not electrically connected to the connector 110a.

In the embodiment of FIG. 8 , the connection layer 500 includes a first connection column layer 520, and the first connection column layer 520 is disposed on the first connection pad layer 510. The first connection column layer 520 is provided with a plurality of first connection columns (vias) 521 and a plurality of connection columns (vias) 522. The plurality of first connection columns (vias) 521 are electrically connected to the plurality of first connection pads (layer) 511. The plurality of connection columns (vias) 522 are electrically connected to the plurality of connection pads (layer) 512.

In the embodiment of FIG. 8 , the connection layer 500 includes a second connection pad layer 530, and the second connection pad layer 530 is disposed on the first connection column layer 520. The second connection pad layer 530 is provided with a plurality of second connection pads (layers) 531. The plurality of second connection pads (layers) 531 are electrically connected to the plurality of first connection columns (vias) 521. At least one second connection pad (layer) 531 is further electrically connected to the connection column (via) 522. For example, the second connection pad (layer) 531a is further electrically connected to the connection column (via) 522, and the second connection pad (layer) 531b is further electrically connected to the connection column (via) 522. Thereby, the connector 110b can provide a first voltage level to the electronic component 120 through the second connection pad (layer) 531b, and the connector 110c can provide a second voltage level to another electronic component 120 through the second connection pad (layer) 531a.

In the embodiment of FIG8 , the connection layer 500 includes a second connection column layer 540 , and the second connection column layer 540 is disposed on the second connection pad layer 530 . The second connection column layer 540 is provided with a plurality of second connection columns (vias) 541 . The plurality of second connection columns (vias) 541 are electrically connected to the plurality of second connection pads (layer) 531 .

In the embodiment of FIG. 8 , the connection layer 500 includes a third connection pad layer 550, and the third connection pad layer 550 is disposed on the second connection column layer 540. The third connection pad layer 550 is provided with a third connection pad (layer) 551. The third connection pad (layer) 551 is electrically connected to a plurality of second connection columns (vias) 541. In this embodiment, the third connection pad (layer) 551 is electrically connected to the connector 110a through other stacked layers (e.g., other connection column layers and connection pad layers). Thereby, the connector 110a can provide the received input signal to the electronic element 120 through the third connection pad (layer) 551.

In this embodiment, the number of connection pad layers and connection column layers is only an example. The number and configuration of the connection pad layers and connection column layers can be adjusted according to actual needs, that is, this application is not limited to the number shown in FIG. 8 .

In this embodiment, since the connector 110a of the semiconductor device 1000 is disposed between two electronic components 120, the transmission distance between the connector 110a and the third connection pad (layer) 551 is greatly reduced, and the area occupied by the connector 110 is reduced. Therefore, compared with the embodiments of FIG. 1 and FIG. 2, the semiconductor device 1000 of this embodiment can not only be packaged by wafer stacking technology, but also the overall area of the semiconductor device 1000 can be further reduced, and the transmission rate between the connector 110a and the third connection pad (layer) 551 can be improved, so as to achieve the purpose of improving the convenience of electronic device packaging.

Please refer to Figures 9 and 10, which are another schematic diagram of the semiconductor device embodiment of the present application. In this embodiment, the semiconductor device 1000 includes an electronic component layer 100 (100d), a connection layer 600 and a connector connection layer 700, wherein the connection layer 600 is disposed on the electronic component layer 100, and the connector connection layer 700 is disposed on the connection layer 600.

In the embodiments of FIG. 9 and FIG. 10 , the difference between the electronic component layer 100 d and the electronic component layer 100 c is that the electronic component layer 100 d is not provided with the aforementioned connector 110 .

In the embodiment of FIG. 9 and FIG. 10 , the connection layer 600 includes a first connection pad layer 610 , which is disposed on the electronic component layer 100 d . The first connection pad layer 610 includes a plurality of first connection pads (layers) 611 . The plurality of first connection pads (layers) 611 are electrically connected to the plurality of electronic components 120 .

In the embodiment of FIG9 and FIG10 , the connection layer 600 includes a first connection column layer 620 , and the first connection column layer 620 is disposed on the first connection pad layer 610 . The first connection column layer 620 is provided with a plurality of first connection columns (vias) 621 . The plurality of first connection columns (vias) 621 are electrically connected to the plurality of first connection pads (layers) 611 .

In the embodiment shown in FIG9 and FIG10 , the connection layer 600 includes a second connection pad layer 630 , which is disposed on the first connection column layer 620 . The second connection pad layer 630 includes a plurality of second connection pads (layers) 631 . The plurality of second connection pads (layers) 631 are electrically connected to the plurality of first connection columns (vias) 621 .

In the embodiment of FIG. 9 and FIG. 10 , the connection layer 600 includes a second connection column layer 640, and the second connection column layer 640 is disposed on the second connection pad layer 630. The second connection column layer 640 is provided with a plurality of second connection columns (vias) 641 and a plurality of connection columns (vias) 642. The plurality of second connection columns (vias) 641 are electrically connected to the plurality of second connection pads (layer) 631. The plurality of connection columns (vias) 642 are electrically connected to a portion of the second connection pads (layer) 631. For example, the plurality of connection columns (vias) 642 are electrically connected to the second connection pads (layer) 631a and the second connection pads (layer) 631b, respectively.

In the embodiment of FIG. 9 and FIG. 10 , the connection layer 600 includes a third connection pad layer 650, and the third connection pad layer 650 is disposed on the second connection column layer 640. The third connection pad layer 650 is provided with a third connection pad (layer) 651 and a plurality of connection pads (layer) 652. The third connection pad (layer) 651 is electrically connected to a plurality of second connection columns (vias) 641. The plurality of connection pads (layer) 652 are electrically connected to the connection columns (vias) 642, respectively.

In the embodiment of FIG9 and FIG10, the connection layer 600 includes a third connection column layer 660, and the third connection column layer 660 is disposed on the third connection pad layer 650. The third connection column layer 660 is provided with a plurality of connection columns (vias) 661. The plurality of connection columns (vias) 661 are electrically connected to the third connection pad (layer) 651 and the connection pad (layer) 652, respectively.

In the embodiment shown in FIG9 and FIG10 , the connection layer 600 includes a fourth connection pad layer 670 , which is disposed on the third connection column layer 660 . The fourth connection pad layer 670 includes a plurality of connection pads (layers) 671 . The connection pads (layers) 671 are electrically connected to the plurality of connection columns (vias) 661 .

In the embodiment of FIG9 and FIG10 , the connector connection layer 700 includes a first connection layer 710 , and the first connection layer 710 is disposed on the fourth connection pad layer 670 . The first connection layer 710 is provided with a plurality of connection posts (vias) 711 . The plurality of connection posts (vias) 711 are electrically connected to the plurality of connection pads (layers) 671 .

In the embodiment of FIG9 and FIG10 , the connector connection layer 700 includes a second connection layer 720 , which is disposed on the first connection layer 710 . The second connection layer 720 is provided with a plurality of connection pads (layers) 721 , which are electrically connected to the connection posts (vias) 711 .

In the embodiment of FIG. 9 and FIG. 10 , the connector connection layer 700 includes a third connection layer 730, and the third connection layer 730 is disposed on the second connection layer 720. The third connection layer 730 is provided with a plurality of connection pads (layer) 731, and the plurality of connection pads (layer) 731 are electrically connected to the connection pad (layer) 721. In this embodiment, the connector 750 is implemented by the electrically connected connection pad (layer) 731 and the connection pad (layer) 721. For example, the connector 750a is implemented by the connection pad (layer) 731a and the connection pad (layer) 721a.

In the embodiment of FIG9 and FIG10 , a plurality of connection pads 740 are disposed on the upper surface 701 of the connector connection layer 700 , and each connection pad 740 is electrically connected to the connection pad 731 , respectively. Thus, the plurality of connectors 750 can receive the voltage level required by the plurality of electronic components 120 through the connection pads 740 . For example, connector 750a receives an input signal through connection pad (layer) 740a, connector 750b receives a first voltage level through connection pad (layer) 740b, and connector 750c receives a second voltage level through connection pad (layer) 740c, wherein the voltage value of the second voltage level is greater than the voltage value of the first voltage level, the second voltage level is, for example, a power supply voltage, and the first voltage level is, for example, a ground voltage.

In this embodiment, the number of connection pad layers and connection column layers is only an example. The number and configuration of the connection pad layers and connection column layers can be adjusted according to actual needs, that is, this application is not limited to the number shown in Figures 9 and 10.

In this embodiment, the semiconductor device 1000 electrically connects the electronic element 120 to the connector 750 through the connection pad of the connection layer 600, so that the semiconductor device 1000 can be packaged with other chips through the connector 750 and the connection pad using the 2D chip packaging technology. At the same time, in this embodiment, the semiconductor device 1000 is provided with a connection pad, so that the semiconductor device embodiment of the present application is not only applicable to the wafer stacking technology, but can also be packaged using the existing 2D chip packaging technology. Therefore, the embodiment of the present application can achieve the purpose of improving the convenience of electronic device packaging.

Please refer to FIG. 11, which is another schematic diagram of a semiconductor device embodiment of the present application. In this embodiment, the semiconductor device 1000 can be combined with the embodiments of FIG. 8 to FIG. 10, and the components are the same as the components of FIG. 8 to FIG. 10, so they are not repeated here. Therefore, in this embodiment, the semiconductor device 1000 includes both the connector 110 and the connector 750.

Therefore, in this embodiment, the semiconductor device 1000 of the embodiment of the present application can be applied to both 2D chip packaging technology and wafer stacking technology, and can further achieve the purpose of improving the convenience of electronic device packaging.

Please refer to Figures 12 and 13, which are another schematic diagram of the semiconductor device embodiment of the present application. The difference between the embodiments of Figures 12 and 13 and the embodiment of Figure 11 is that the connector 110 and the connector 750 may not be electrically connected to each other. For example, in the embodiment of Figure 12, the connector 750 is not electrically connected to the third connection pad layer 650 and the connection pad layer 530, so the connector 110 and the connector 750 are not electrically connected to each other. For example, in the embodiment of Figure 13, the connector 110 is not electrically connected to the third connection pad layer 650 and the connection pad layer 530, so the connector 110 and the connector 750 are not electrically connected to each other.

Please refer to Fig. 14, which is a schematic diagram of a memory device embodiment of the present application. In the embodiment of Fig. 14, the memory device 1 includes a high-speed interface chip 10, an intermediate layer 20, a high-speed data exchange layer 30, a first processor 40, a second processor 50 and a memory crystal layer 60.

In the embodiment of FIG. 14 , the high-speed data exchange layer 30, the first processor 40 and the second processor 50 are disposed on the interposer 20, wherein the high-speed data exchange layer 30 includes the aforementioned high-speed interface chip 10, and the high-speed interface chip 10 can be implemented by the semiconductor device 1000 of FIG. 1 , FIG. 2 , FIG. 5 , FIG. 6 , FIG. 8 , FIG. 11 or FIG. 12 , and the memory crystal layer 60 is stacked and disposed on the high-speed data exchange layer 30. Therefore, in this embodiment, the memory device 1 is a memory device that implements 3D packaging using wafer stacking technology.

In summary, the semiconductor device of the present application and the memory device embodiment of the 3D package thereof are provided with connection pads and connectors, and the connectors can be arranged in the electronic component layer, so that the electronic components of the electronic component layer can be electrically connected to the connectors through the connection pads, so that the wafer stacking technology can be used to package with other chips. At the same time, the connectors can also be arranged on a side of the semiconductor device away from the electronic component layer, so that the semiconductor device can be compatible with the existing 2D packaging technology. Thereby, the present application can not only be packaged with other chips by wafer stacking technology, but also be compatible with the existing 2D packaging technology, so as to achieve the purpose of improving the convenience of electronic device packaging.

1  Memory device 10 High-speed interface chip 20 Interposer 30 High-speed data exchange layer 40 First processor 50 Second processor 60 Memory crystal layer 100, 100a, 100b, 100c, 100d     Electronic component layer 101     Upper surface 102     Lower surface 110, 110a, 110b, 110c   Connector 120     Electronic component 130, 130a, 130b, 130c   Connecting pad 200     Connecting layer 210     First connecting pad layer 211     First connecting pad 212     Connecting pad 220    First connecting column layer 221     First connecting column 222     Connecting column 230     Second connecting pad layer 231, 231a, 231b  Second connecting pad 232     Connecting pad 240     Second connecting column layer 241     Second connecting column 242     Connecting column 250     Third connecting pad layer 251     Third connecting pad 252     Connecting pad 260     Third connecting column layer 261     Third connecting column 262     Connecting column 270     Fourth connecting pad layer 271     Fourth connecting pad 272     Connecting pad 280     Fourth connecting column layer 281    Fourth connecting column 282     Connecting column 290     Top connecting layer 291     Top connecting pad 300     Connecting layer 310     First connecting pad layer 311     First connecting pad 320     First connecting column layer 321     First connecting column 330     Second connecting pad layer 331, 331a, 331b  Second connecting pad 340     Second connecting column layer 341     Second connecting column 342, 342a, 342b  Connecting column 350     Third connecting pad layer 351     Third connecting pad 352     Connecting pad 360     Third connecting column layer 361     Third connecting column 362     Connecting column 370     Fourth connecting pad layer 371     Fourth connecting pad 372     Connecting pad 380     Fourth connecting column layer 381     Fourth connecting column 382     Connecting column 390     Top connecting layer 391     Top connecting pad 392     Connecting pad 400     Connector connecting layer 401     Upper surface 410     First connecting layer 411     Connecting column 420     Second connecting layer 421, 421a, 421b, 421c   Connecting pad 430     Third connecting layer 431, 431a Connecting pad 440, 440a, 440b, 440c   Connecting pad 450, 450a Connecting piece 500     Connecting layer 510     First connecting pad layer 511     First connecting pad 512     Connecting pad 520     First connecting column layer 521     First connecting column 522     Connecting column 530     Connecting pad layer 531, 531a, 531b  Second connecting pad 540     Second connecting column layer 541     Second connecting column 550     Third connecting pad layer 551     Third connecting pad 600     Connecting layer 610     First connecting pad layer 611     First connecting pad 620     First connecting column layer 621     First connecting column 630     Second connecting pad layer 631, 631a, 631b  Second connecting pad 640     Second connecting column layer 641     Second connecting column 642     Connecting column 650     Third connecting pad layer 651     Third connecting pad 652     Connecting pad 660     Third connecting column layer 661     Connecting column 670     Fourth connecting pad layer 671     Connecting pad 700     Connecting layer 701     Upper surface 710     First connecting layer 711     Connecting column 720    Second connection layer 721, 721a connection pad 730     Third connection layer 731, 731a connection pad 740, 740a, 740b, 740c   connection pad 750, 750a, 750b, 750c   connector 1000   semiconductor device A  region

Figure 1 is a schematic diagram of the first embodiment of the semiconductor device of the present application; Figure 2 is a schematic diagram of the first embodiment of the semiconductor device of the present application; Figure 3 is a schematic diagram of the second embodiment of the semiconductor device of the present application; Figure 4 is a schematic diagram of the second embodiment of the semiconductor device of the present application; Figure 5 is a schematic diagram of the third embodiment of the semiconductor device of the present application; Figure 6 is a schematic diagram of the fourth embodiment of the semiconductor device of the present application; Figure 7 is a schematic diagram of the fifth embodiment of the semiconductor device of the present application; Figure 8 is a schematic diagram of the sixth embodiment of the semiconductor device of the present application; Figure 9 is a schematic diagram of the seventh embodiment of the semiconductor device of the present application; Figure 10 is a schematic diagram of the seventh embodiment of the semiconductor device of the present application; Figure 11 is a schematic diagram of the eighth embodiment of the semiconductor device of the present application; FIG. 12 is a schematic diagram of the ninth embodiment of the semiconductor device of the present application; FIG. 13 is a schematic diagram of the tenth embodiment of the semiconductor device of the present application; and FIG. 14 is a schematic diagram of the memory device embodiment of the present application.

1000:Semiconductor devices

100, 100a: electronic component layer

101: Upper surface

102: Lower surface

110, 110a, 110b, 110c: Connectors

120: Electronic components

130, 130a, 130b, 130c: connection pads

200: Connection layer

210: First connection pad layer

220: First connecting column layer

230: Second connection pad layer

240: Second connecting column layer

250: Third connection pad layer

260: Third connecting column layer

270: Fourth connection pad layer

280: Fourth connecting column layer

290: Top connection layer

Claims (11)

A semiconductor device has a first side and a second side opposite to the first side, comprising: A plurality of connection pads disposed on the first side and the second side of the semiconductor device; An electronic component layer comprising an electronic component electrically connected to the connection pads disposed on the first side of the semiconductor device; A first connection pad layer disposed on the electronic component layer, comprising a first connection pad electrically connected to the electronic component; A second connection pad layer disposed on the first connection pad layer, comprising a second connection pad electrically connected to the first connection pad; A plurality of first connectors, disposed in the electronic component layer, one of the first connectors being electrically connected to the second connection pad, and one of the first connectors being electrically connected to the connection pads disposed on the first side of the semiconductor device; and A plurality of second connectors, the second connectors being disposed on the second connection pad layer and away from the electronic component layer, the second connectors being electrically connected to the connection pads disposed on the second side of the semiconductor device, and one of the second connectors being electrically connected to the second connection pad. A semiconductor device as described in claim 1, wherein the semiconductor device includes a third connection pad layer, which is disposed on the second connection pad layer, and includes a third connection pad, and the third connection pad is electrically connected to the electronic component through the first connection pad layer and the second connection pad layer. A semiconductor device as described in claim 2, wherein the semiconductor device includes a top connection layer disposed on the third connection pad layer, including a top connection pad, the top connection pad is electrically connected to the third connection pad, and is electrically connected to one of the first connection members. A semiconductor device as described in claim 2, wherein one of the first connectors is electrically connected to the third connection pad. A semiconductor device as described in claim 2, wherein the semiconductor device includes a fourth connection pad layer, which is arranged on the third connection pad layer and includes a plurality of connection pads, one of the connection pads of the fourth connection pad layer is electrically connected to the third connection pad and one of the first connection members, and another one of the connection pads of the fourth connection pad layer is electrically connected to the second connection pad and another one of the first connection members. A semiconductor device as described in claim 1, wherein the first connecting members are a through silicon via. A semiconductor device as described in claim 1, wherein the first connecting members are not arranged between two of the electronic components. A semiconductor device as described in claim 1, wherein one of the first connectors is disposed between two of the electronic components. A semiconductor device as described in claim 2, wherein one of the first connectors and one of the second connectors are electrically connected to the third connection pad. A semiconductor device as described in claim 5, wherein one of the first connectors and one of the second connectors are electrically connected to one of the connection pads of the fourth connection pad layer. A 3D packaged memory device, comprising: an interposer; and a high-speed data exchange layer disposed on the interposer, comprising the semiconductor device as described in claim 1.

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