TWI880562B - Display device - Google Patents

Abstract

A display device includes a substrate on which a plurality of light-emitting elements is disposed; a transistor on the substrate; a plurality of signal lines on the substrate; a plurality of link lines below the substrate; and a plurality of upper pads on the substrate and connected to the plurality of signal lines, in which the plurality of upper pads is disposed to overlap with at least one of the plurality of signal lines and the plurality of transistors. Therefore, it is possible to implement the high-resolution display device with zero bezel by reducing the bezel area of the display device.

Description

Display device

The present invention relates to a display device, in particular to a display device having a narrow border area.

As display devices used in computer monitors, televisions, mobile phones, etc., such as organic light-emitting displays (OLED) for self-luminescence and liquid crystal displays (LCD) that require independent light sources.

The application range of display devices is diverse, ranging from computer monitors and televisions to personal mobile devices, and research on display devices having a wide display area and having a reduced size and weight is ongoing.

Furthermore, recently, a display device including an inorganic light emitting diode (LED) such as a micro light emitting diode has attracted attention as a next-generation display device. Since LEDs are made of inorganic materials rather than organic materials, LEDs are more reliable and have a longer lifespan than liquid crystal display devices or organic light emitting display devices.

Furthermore, LEDs can be turned on or off quickly, have excellent luminous efficiency, high impact resistance, and good stability, and can display high-brightness images.

The present invention provides a display device having a narrow border area.

More specifically, the present invention provides a display device having a narrow bezel area, which can implement high resolution.

The present invention also provides a display device that reduces the problem of multiple pads being disconnected from each other.

Furthermore, the present invention provides a display device that solves the problem that the material constituting the side wiring is not properly placed on the side surface of the substrate of the display device.

The present invention is not limited to the above-mentioned and other features not mentioned above, and a person with ordinary knowledge in the relevant field can clearly understand the present invention through the following description.

According to one aspect of the present invention, a display device includes a substrate on which a plurality of light-emitting elements are disposed; a transistor located on the substrate; a plurality of signal lines located on the substrate; a plurality of connection lines under the substrate; and a plurality of upper pads located on the substrate and connected to the plurality of signal lines, wherein the plurality of upper pads are arranged to overlap with at least one of the plurality of signal lines and the plurality of transistors. Therefore, a high-resolution display device with zero border (or minimized border) can be implemented by reducing the border area of the display device.

Further details of the embodiments are included in the detailed description and drawings.

According to the present invention, the pad can be configured to overlap with at least one of a plurality of signal lines and a plurality of transistors, thereby reducing the border area of the display device.

According to the present invention, a high-resolution display device can be implemented by reducing the border area.

According to the present invention, the problem of disconnecting multiple pads by physical impact can be solved.

According to the present invention, the side circuits arranged on the side surface of the substrate can be arranged uniformly.

The effects according to the present invention are not limited to the above exemplary contents, and more various effects are included in the present invention.

100: Display device

101: First substrate

102: Second substrate

110: Substrate

111: Buffer layer

112: Gate insulation layer

113: Interlayer insulation layer

114: Passivation layer

115a: first planarization layer

115b: Second planarization layer

115c: Third planarization layer

117: Reflective layer

118: Second adhesive layer

119: Embankment

121: First adhesive layer

140: Side line

150: Lateral insulating layer

400: Display device

402: Second substrate

410: Substrate

440: Side line

450: Lateral insulation layer

500: Display device

AA: Display area

ACT: Active layer

CE1: First electrode

CE2: Second electrode

DE: Drain electrode

DL: Data Line

DL1: First data line

DL2: Second data line

DL3: Third data line

DL2-1: First layer

DL2-2: Second layer

DL2-3: The third layer

EL: Active layer

GE: Gate electrode

GR:Grinding machine

L1: First Line

LED: light-emitting element

LED1: first light-emitting element

LED2: The second light-emitting element

LED3: The third light-emitting element

LS: Light blocking layer

NA: Non-display area

NE:n-type electrode

NL:n-type layer

P: Pixels

PE: p-type electrode

PL: p-type layer

PAD: Upper pad

PAD1,PAD2: Upper pad

RL: Reference Line

SC: Storage capacitor

SC1: first capacitor electrode

SC2: Second capacitor electrode

SE: Source electrode

SL: Scan line

SP: Sub-pixel

SP1,SP2,SP3: sub-pixel

TR: Transistor

VDDL: high voltage line

VSSL: low voltage line

X: Area

II-II ' , III-III ' : line

The above and other aspects, features and other advantages of the present invention will be more clearly understood through the following detailed description and the attached drawings.

FIG. 1 is a schematic plan view (or top view) of a display device according to the first embodiment; FIG. 2A is a schematic plan view of the display device before a process of grinding the display device is performed according to the first embodiment; FIG. 2B is a schematic cross-sectional view of the display device along line II-II' in FIG. 2A; FIG. 3A is a schematic plan view of the display device after a process of grinding the display device is performed according to the first embodiment; FIG. 3B is a cross-sectional schematic diagram of the display device along line III-III' in FIG. 3A; FIG. 4A is a cross-sectional schematic diagram of the display device in a state before performing a process of grinding the display device according to the second embodiment; FIG. 4B is a cross-sectional schematic diagram of the display device in a state after performing a process of grinding the display device according to the second embodiment; and FIG. 5 is a cross-sectional schematic diagram of the display device according to the third embodiment.

The advantages and features of the present invention and its implementation will be described in detail with reference to the following embodiments and the attached drawings. However, the present invention is not limited to the embodiments described herein and can be implemented in various forms. The embodiments are only examples so that those with common knowledge in the relevant technical field can fully understand the disclosure of the present invention and the scope of the present invention.

The shapes, sizes, proportions, angles and quantities disclosed in the drawings used to describe the embodiments are examples only, and the present invention is not limited thereto. Throughout the text, similar reference numerals generally indicate similar elements. Furthermore, in the following description of the present invention, detailed explanations of known related technologies may be omitted so as not to unnecessarily obscure the subject matter of the present invention. Unless a term such as "only" is used, terms such as "including", "having" and "consisting of..." described in this description are generally intended to allow for the addition of other elements. Unless otherwise expressly stated, a singular description may include a plural description.

Even if not explicitly stated, components are interpreted as including a normal tolerance range.

When describing a positional relationship, when the positional relationship is described between two components, for example, using "on", "above", "below", "next to", one or more other components may be disposed between the two components, unless further qualifying terms are used, such as "immediately" or "directly".

When a component or layer is disposed "on" another component or layer, another layer or another component may be inserted directly on or between other components.

Although the terms "first", "second", etc. may be used herein to describe various different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, in the technical concept of the present invention, the first element mentioned below may be the second element.

Throughout the text, similar reference numbers generally refer to similar components.

The size and thickness of each component shown in the figure are shown for the convenience of description, and the present invention is not limited to the size and thickness of the components shown.

The features of the various aspects of the present invention may be partially or entirely bonded to or combined with each other, and may be technically interlocked and operated in various ways, and these aspects may be performed independently or in relation to each other.

In this article, the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a plan view (or top view) of a display device according to the first embodiment. For the convenience of description, FIG. 1 only shows a substrate 110, a data line DL, a scanning line SL, a plurality of sub-pixels SP, and an upper pad PAD of the display device 100. Furthermore, the region X in FIG. 1 will be described with reference to FIG. 2A.

Referring to FIG. 1 , it can be seen that the substrate 110 can be a substrate, for example, an insulating substrate that supports a component disposed on an upper portion of the display device 100. For example, the substrate 110 can be made of glass, resin, etc. Furthermore, the substrate 110 can include a polymer or plastic. In many embodiments, the substrate 110 can be made of a flexible plastic material.

The substrate 110 may have a display area AA and a non-display area NA surrounding the display area AA.

The display area AA is an area of the display device 100 that displays an image. The display area AA may include a plurality of sub-pixels SP constituting a plurality of pixels, and a circuit for operating the plurality of sub-pixels SP.

The plurality of sub-pixels SP are the smallest units constituting the display area AA. Light-emitting elements, thin film transistors for operating the light-emitting elements, etc. may be disposed in each of the plurality of sub-pixels SP. The plurality of sub-pixels SP will be described in detail with reference to FIGS. 2A to 3B.

A plurality of signal lines for transmitting various forms of signals to a plurality of sub-pixels SP are arranged in the display area AA. For example, the plurality of signal lines may include a plurality of data lines DL for providing data voltages to a plurality of sub-pixels SP and a plurality of scanning lines SL for providing scanning voltages to a plurality of sub-pixels SP. The plurality of signal lines will be described in detail below with reference to FIGS. 2A to 3B.

The non-display area NA may be defined as an area where no image is displayed, i.e., an area surrounding the display area AA. The non-display area NA may include connection lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA. Alternatively, or in addition, the non-display area NA may include a driver integrated circuit such as a gate driver integrated circuit and a data driver integrated circuit.

Multiple upper pads PAD1 for transmitting various forms of signals to multiple sub-pixels SP on the substrate 110 are arranged in the non-display area NA. The multiple upper pads PAD1 are arranged to overlap with multiple signal lines and will be described below. Furthermore, the multiple upper pads PAD1 can be electrically connected to the side lines and multiple signal lines in the display area AA, and provide signals received from multiple flexible films and printed circuit boards arranged on the rear surface of the substrate 110 to the multiple sub-pixels SP. The multiple upper pads PAD1 will be described in more detail with reference to Figures 2A to 3B.

The embodiments are not limited to overlapping upper pads of signal lines. That is, the upper pad may not overlap the signal line. The signal line and the upper pad may be arranged alternately (for example, the signal line is arranged between multiple upper pads). In this arrangement, for example, if the side line extends along the width to cover the end of the upper pad and the end of the signal line, the upper pad can still be connected to the signal line via the side line.

Meanwhile, in the present invention, a configuration has been described in which the display area AA and the non-display area NA are defined as the front surface of the display device 100. However, the present invention is not limited thereto. The non-display area NA may not be defined as the front surface of the display device 100. When a plurality of display devices 100 according to the first embodiment are connected to implement an assembled display having a large screen, the interval between the outermost peripheral sub-pixels SP of the display device 100 and the outermost peripheral sub-pixels SP of another display device 100 adjacent to the one display device 100 may be implemented to be the same as the interval between the plurality of sub-pixels SP in one display device 100, so that a zero border may be implemented in which the border area is not substantially presented. Therefore, the display area AA in which only the image is displayed may be defined as the front surface of the display device 100. However, the present invention is not limited thereto.

FIG. 2A is a schematic plan view of a display device in a state before the process of grinding the display device according to the first embodiment. FIG. 2B is a schematic cross-sectional view of the display device along line II-II' in FIG. 2A. FIG. 2A is an enlarged plan view of region X shown in FIG. 1. FIG. 2A only shows a plurality of upper pads PAD1 of a substrate 110, a plurality of signal lines, a plurality of light-emitting elements LED, and a plurality of pixels P.

Please refer to Figure 2A, multiple display modules include multiple signal lines and multiple pixels P.

The plurality of pixels P may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be sub-pixels that emit light of different colors. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be a red sub-pixel for emitting red light, a green sub-pixel for emitting green light, and a blue sub-pixel for emitting blue light, respectively. However, the present invention is not limited thereto. For example, the plurality of pixels P may further include a white sub-pixel for emitting white light.

Each of the plurality of sub-pixels SP1, SP2, and SP3 may include a light-emitting region and a circuit region. An area where light emitted from the light-emitting element LED can propagate to the outside may be defined as a light-emitting region. A light-emitting region is an area that can independently emit light by a single color light type. The light-emitting element LED may be disposed in the light-emitting region. For example, a first light-emitting element LED1 for emitting red light may be disposed on a first sub-pixel SP1. A second light-emitting element LED2 for emitting green light may be disposed on a second sub-pixel SP2. A third light-emitting element LED3 for emitting blue light may be disposed on a third sub-pixel SP3.

The circuit area is the remaining area excluding the light-emitting area. A driving circuit for operating a plurality of light-emitting elements LED can be arranged in the circuit area. For example, a driving circuit including a transistor TR and a storage capacitor SC can be arranged in the circuit area.

A plurality of signal lines are disposed on the substrate 110. The side surfaces of each of the plurality of signal lines can be disposed in a plane indicated by the first line L1 in FIG. 2A and FIG. 2B, wherein the plane is located at the end of the process of grinding the substrate 110.

The plurality of signal lines may be lines for transmitting various forms of signals to the driving circuit, and include a scanning line SL, a data line DL, a high potential voltage line VDDL, a reference line RL, a low potential voltage line VSSL, etc. However, the present invention is not limited thereto.

Each data line DL is a line for transmitting a data signal to a respective sub-pixel SP1, SP2 or SP3. A plurality of data lines DL can be arranged to extend along a row direction between a plurality of sub-pixels SP1, SP2, SP3, and include a first data line DL1, a second data line DL2, and a third data line DL3. The first data line DL1, the second data line DL2, and the third data line DL3 can transmit data voltages to sub-pixels SP1, SP2, SP3, respectively. For example, the first data line DL1 can transmit a data voltage to the first sub-pixel SP1, the second data line DL2 can transmit a data voltage to the second sub-pixel SP2, and the third data line DL3 can transmit a data voltage to the third sub-pixel SP3.

The multiple high-potential voltage lines VDDL are used to transmit high-potential power voltage to multiple sub-pixels SP1, SP2, SP3. The multiple high-potential voltage lines VDDL can extend along the row direction.

Multiple sub-pixels SP1, SP2, and SP3 can share a single high-potential voltage line VDDL. For example, the single high-potential voltage line VDDL can be set between the first sub-pixel SP1 and the third sub-pixel SP3, and provide a high-potential power voltage to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

The multiple reference lines RL include lines extending along the row direction and transmitting reference voltages to the multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 can share a single reference line RL. For example, the single reference line RL can be set between the third sub-pixel SP3 and the first sub-pixel SP1, and transmit reference voltages to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

The low potential voltage line VSSL is a line for applying a low potential power voltage to a plurality of sub-pixels SP1, SP2, and SP3. The low potential voltage line VSSL may extend along the row direction. Sub-pixels SP1, SP2, and SP3 may share a single low potential voltage line VSSL. For example, the single low potential voltage line VSSL may be disposed between the first sub-pixel SP1 and the third sub-pixel SP3, and provide a low potential power voltage to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

In this article, various components of the display device 100 will be described in more detail with reference to FIG. 2B .

Referring to FIG. 2B , a substrate 110 for supporting various components disposed on the display device 100 may be disposed on the display device 100.

The substrate 110 may include a first substrate 101 and a second substrate 102.

The first substrate 101 may be a substrate, for example, an insulating substrate supporting constituent elements disposed on an upper portion of the display device 100. For example, the first substrate 101 may be made of glass, resin, etc. Alternatively, or in addition, the first substrate 101 may include a polymer or plastic.

The second substrate 102 is disposed below the first substrate 101. The second substrate 102 may be a substrate, for example, an insulating substrate that supports constituent elements disposed on a lower portion of the display device 100. For example, the second substrate 102 may be made of glass, resin, or the like. Alternatively, or in addition, the second substrate 102 may include a polymer or plastic. The second substrate 102 may be made of the same material as the first substrate 101.

The first adhesive layer 121 is disposed between the first substrate 101 and the second substrate 102. The first adhesive layer 121 can be made of a material that can be cured by various curing methods to bond the first substrate 101 and the second substrate 102. The first adhesive layer 121 can be disposed on a partial area or the entire area between the first substrate 101 and the second substrate 102.

Please refer to FIG. 2B , the light blocking layer LS can be disposed on the first substrate 101.

The light blocking layer LS may be provided to overlap with the first active layer ACT of the transistor TR and to block light from entering the first active layer ACT. If light is emitted to the first active layer ACT, a leakage current may be generated that may degrade the reliability of the transistor TR, which is a driving transistor. In this case, when the light blocking layer LS made of an opaque electrically conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) and alloys thereof is provided to overlap with the first active layer ACT, the light blocking layer LS may block light from entering the first active layer ACT from the lower portion of the substrate 110, thereby improving the reliability of the transistor TR.

The buffer layer 111 is disposed on the first substrate 101 and the light blocking layer LS. The buffer layer 111 can reduce the penetration of water vapor or impurities through the first substrate 101. For example, the buffer layer 111 can be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present invention is not limited thereto. Furthermore, the buffer layer 111 can be excluded to be consistent with the form of the first substrate 101 or the form of the transistor TR. However, the present invention is not limited thereto.

The transistor TR is disposed on the buffer layer 111 of each of the multiple sub-pixels SP1, SP2, and SP3.

The transistor TR includes a first active layer ACT, a gate electrode GE, a source electrode SE and a drain electrode DE.

The first active layer ACT is disposed on the buffer layer 111. The first active layer ACT may be made of a semiconductive material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the present invention is not limited thereto. For example, when the first active layer ACT is made of an oxide semiconductor, the first active layer ACT may include a channel region, a source region, and a drain region, and the source region and the drain region may be conductive regions. However, the present invention is not limited thereto.

The gate insulating layer 112 is disposed on the first active layer ACT. The gate insulating layer 112 can be used to insulate the gate electrode GE and the layer of the first active layer ACT, and is made of an insulating material. For example, the gate insulating layer 112 can be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present invention is not limited thereto.

The gate insulating layer 112 may be formed in the same pattern as the gate electrode GE. However, the present invention is not limited thereto. The gate insulating layer 112 may be formed on the front surface (or upper surface) of the first substrate 101.

The gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be disposed to overlap the gate insulating layer 112. The gate electrode GE may be made of an electrically conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof. However, the present invention is not limited thereto.

The interlayer insulating layer 113 is disposed on the gate electrode GE and the buffer layer 111. The interlayer insulating layer 113 may be a layer for insulating the gate electrode GE, the source electrode SE, and the drain electrode DE. The interlayer insulating layer 113 may be made of an inorganic material like the gate insulating layer 112. For example, the interlayer insulating layer 113 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present invention is not limited thereto.

The source electrode SE and the drain electrode DE are disposed on the interlayer insulating layer 113 and separated from each other. The source electrode SE and the drain electrode DE can be electrically connected to the first active layer ACT through a through hole formed in the interlayer insulating layer 113. The source electrode SE and the drain electrode DE can be disposed on the same layer and made of an electrically conductive material like the gate electrode GE. However, the present invention is not limited thereto. For example, the source electrode SE and the drain electrode DE can each be made of an electrically conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof. However, the present invention is not limited thereto.

The drain electrode DE is electrically connected to the low potential voltage line VSSL. For example, the drain electrode DE of each second sub-pixel SP2 and the third sub-pixel SP3 can be electrically connected to the low potential voltage line VSSL disposed on the left side of the first sub-pixel SP1.

The source electrode SE can be electrically connected to the light blocking layer LS through a through hole formed in the interlayer insulating layer 113 and the buffer layer 111. If the light blocking layer LS floats, the threshold voltage of the transistor TR changes, which can affect the operation of the display device 100. Therefore, the light blocking layer LS can be electrically connected to the source electrode SE, so that a voltage can be applied to the light blocking layer LS, and the operation of the transistor TR can be unaffected. However, the present invention is not limited to this. Both the first active layer ACT and the source electrode SE can directly contact the light blocking layer LS. Multiple signal lines can be set on the interlayer insulating layer 113. For example, the plurality of signal lines may include a plurality of scanning lines SL, a plurality of high potential voltage lines VDDL, a plurality of data lines DL, and a plurality of reference lines RL. However, the present invention is not limited thereto. The plurality of signal lines may be disposed on the same layer on the first substrate 101 and may be made of the same electrically conductive material. The plurality of scanning lines SL, the plurality of high potential voltage lines VDDL, the plurality of data lines DL, and the plurality of reference lines RL may each be made of an electrically conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present invention is not limited thereto. The plurality of signal lines may be disposed on different layers on the first substrate 101 and may be made of different electrically conductive materials. Furthermore, the plurality of signal lines can be made of the same material as the drain electrode DE and the source electrode SE. At the same time, the plurality of signal lines can be arranged on different layers of the first substrate 101 and made of different electrically conductive materials. In this case, the plurality of signal lines can be arranged on the same layer and made of the same material as any constituent element constituting the transistor TR.

The storage capacitor SC is disposed in the circuit area of each of the plurality of sub-pixels SP1, SP2, and SP3. The storage capacitor SC can store the voltage between the gate electrode GE and the source electrode SE of the transistor TR so that the light-emitting element LED can continuously maintain the same state within a single frame. The storage capacitor SC includes a first capacitor electrode SC1 and a second capacitor electrode SC2.

The first capacitor electrode SC1 is disposed between the first substrate 101 and the buffer layer 111 in each of the plurality of sub-pixels SP. The first capacitor electrode SC1 may be disposed to be closest to the first substrate 101 among the conductor components disposed on the first substrate 101. The first capacitor electrode SC1 may be formed as a single body with the light blocking layer LS and may be electrically connected to the source electrode SE through the light blocking layer LS.

The buffer layer 111 and the gate insulating layer 112 are disposed on the first capacitor electrode SC1, and the second capacitor electrode SC2 is disposed on the buffer layer 111 and the gate insulating layer 112. The second capacitor electrode SC2 may be disposed to overlap with the first capacitor electrode SC1. The second capacitor electrode SC2 may be made of the same material as the gate electrode GE. For example, the gate electrode GE and the second capacitor electrode SC2 may be formed by forming a semiconductive material on the gate insulating layer 112 and patterning a portion of the semiconductive material.

The passivation layer 114 is disposed on the transistor TR and the storage capacitor SC. The passivation layer 114 is an insulating layer for protecting the components disposed on the lower portion of the passivation layer 114. For example, the passivation layer 114 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present invention is not limited thereto. Furthermore, the passivation layer 114 may be excluded to be consistent with some embodiments.

A plurality of reflective layers 117 are disposed on the passivation layer 114. The reflective layer 117 may be disposed to overlap with a light-emitting region including a light-emitting element LED. The reflective layer 117 reflects light entering from the light-emitting element LED and toward the upper portion of the light-emitting element LED, thereby improving the light-emitting efficiency of the display device 100. However, when the display device 100 is a back-lighting type display device, the reflective layer 117 may be excluded or disposed on the upper portion of the light-emitting element LED.

The second adhesive layer 118 covering the reflective layer 117 is disposed on the reflective layer 117. The second adhesive layer 118 is an adhesive layer for bonding the light-emitting element LED to the reflective layer 117. The second adhesive layer 118 can be insulated from the reflective layer 117 and the light-emitting element LED, each made of a metal material. The second adhesive layer 118 can be made of a thermosetting or light-hardenable material. However, the present invention is not limited thereto. FIG. 2B shows that the second adhesive layer 118 is disposed to cover only the reflective layer 117. However, the arrangement position of the second adhesive layer 118 is not limited thereto.

A plurality of light-emitting element LEDs are disposed on the second adhesive layer 118. The plurality of light-emitting element LEDs are disposed to overlap with the plurality of reflective layers 117. Each of the plurality of light-emitting element LEDs may be a micro light-emitting diode including an inorganic active layer. The plurality of light-emitting element LEDs each include an n-type layer, an active layer, a p-type layer, an n-type electrode, and a p-type electrode. A light-emitting element LED having a lateral structure is used as a configuration of the light-emitting element LED as described below. The n-type electrode or the p-type electrode may be disposed on the top of the light-emitting element LED. The n-type electrode and the p-type electrode may be disposed to be horizontally separated. However, the structure of the light-emitting element LED is not limited thereto.

Specifically, the n-type layer NL of the light-emitting element LED is disposed on the second adhesive layer 118. The n-type layer NL can be formed by injecting n-type impurities into gallium nitride having excellent crystallinity. The second active layer EL is disposed on the n-type layer NL. The second active layer EL can be located in the light-emitting layer of the light-emitting element LED and used to emit light. The second active layer EL can be made of a nitride semiconductor such as indium gallium nitride. The p-type layer PL is disposed on the second active layer EL. The p-type layer PL can be formed by injecting p-type impurities into gallium nitride. However, the constituent materials of the n-type layer NL, the second active layer EL, and the p-type layer PL are not limited thereto.

The p-type electrode PE is disposed on the p-type layer PL of the light-emitting element LED. Furthermore, the n-type electrode NE is disposed on the n-type layer NL of the light-emitting element LED. The n-type electrode NE is disposed to be separated from the p-type electrode PE. Specifically, the light-emitting element LED can be manufactured by stacking the n-type layer NL, the active layer EL, and the p-type layer PL, etching predetermined portions of the active layer EL and the p-type layer PL, and forming the n-type electrode NE and the p-type electrode PE in this order. In this case, the predetermined portion is a space for separating the n-type electrode NE and the p-type electrode PE. The predetermined portion can be etched to expose a portion of the n-type layer NL. In other words, the surface of the light-emitting element LED on which the n-type electrode NE and the p-type electrode PE are to be disposed may be a surface having different height levels rather than a flattened surface. Therefore, the p-type electrode PE is disposed on the p-type layer PL, and the n-type electrode NE is disposed on the n-type layer NL. The p-type electrode PE and the n-type electrode NE are disposed to be separated from each other at different height levels. Therefore, the n-type electrode NE may be disposed closer to the second adhesive layer 118 than the p-type electrode PE. Furthermore, the n-type electrode NE and the p-type electrode PE may be made of an electrically conductive material such as a transparent conductive oxide. Furthermore, the n-type electrode NE and the p-type electrode PE may be made of the same material. However, the present invention is not limited thereto.

The first planarization layer 115a is disposed on the transistor TR. The first planarization layer 115a may be disposed in a region excluding a region where the light emitting element LED is disposed. The first planarization layer 115a planarizes the upper surface of the transistor TR.

The first planarization layer 115a may be configured as a single layer or multiple layers made of an organic material such as polyimide or photoacrylic. However, the present invention is not limited thereto.

The second planarization layer 115b is provided on the first planarization layer 115a and the light-emitting element LED. The second planarization layer 115b is a layer for planarizing the upper surface of the transistor TR and the upper surface of the light-emitting element LED. FIG. 2B shows that the first planarization layer 115a and the second planarization layer 115b are provided. However, the present invention is not limited thereto. A single planarization layer can be formed. When a single planarization layer is provided, an excessive increase in the time required for the process can be suppressed. Furthermore, two or more planarization layers can be provided. The second planarization layer 115b can be made of the same material as the first planarization layer 115a. However, the present invention is not limited thereto.

The first electrode CE1 is an electrode electrically connected to the transistor TR and the light-emitting element LED. The first electrode CE1 is connected to the n-type electrode NE of the light-emitting element LED through a through hole formed in the second planarization layer 115b. Furthermore, the first electrode CE1 is connected to the source electrode SE of the transistor TR through a through hole formed in the first planarization layer 115a, the second planarization layer 115b and the passivation layer 114. However, the present invention is not limited thereto. The first electrode CE1 can be connected to the drain electrode DE of the transistor TR to be consistent with the form of the transistor TR.

The second electrode CE2 is an electrode electrically connected to the light-emitting element LED and the high potential voltage line VDDL. Specifically, the second electrode CE2 is connected to the high potential voltage line VDDL through the through-holes formed in the first planarization layer 115a, the second planarization layer 115b and the passivation layer 114. The second electrode CE2 is connected to the p-type electrode PE of the light-emitting element LED through the through-holes formed in the second planarization layer 115b. Therefore, the high potential voltage line VDDL and the p-type electrode PE of the light-emitting element LED are electrically connected.

The first electrode CE1 and the second electrode CE2 are separated from each other. Specifically, the first electrode CE1 may be surrounded by the first planarization layer 115a, the second planarization layer 115b, and the third planarization layer 115c. The second electrode CE2 may be surrounded by the first planarization layer 115a, the second planarization layer 115b, and the third planarization layer 115c. The second planarization layer 115b and the third planarization layer 115c may contact each other in the region between the first electrode CE1 and the second electrode CE2. The third planarization layer 115c may be disposed between the first electrode CE1 and the second electrode CE2. Therefore, the first electrode CE1 and the second electrode CE2 are electrically insulated from each other.

The embankment 119 is disposed on the second planarization layer 115b, the first electrode CE1, and the second electrode CE2. The embankment 119 is an insulating layer that defines the light-emitting area. The embankment 119 may be made of an organic insulating material. The embankment 119 may be made of the same material as the first planarization layer 115a and the second planarization layer 115b. Furthermore, the embankment 119 may be used to include a light-absorbing material such as a black material to suppress color mixing caused when light emitted from the light-emitting element LED is transmitted to adjacent sub-pixels SP1, SP2, SP3. The embankment 119 may have a slope. Specifically, multiple side surfaces of the embankment 119 may be formed as inclined surfaces having specific slopes. Furthermore, the embankment 119 may overlap with the upper pad PAD1 or the lower pad PAD2. The bank 119 may cover the area where the upper pad PAD1 and the lower pad PAD2 are provided.

The third planarization layer 115c is disposed on the bank 119. The third planarization layer 115c can planarize the upper portion of the first substrate 101 and protect the components disposed under the third planarization layer 115c. The third planarization layer 115c can be configured as a single layer or multiple layers made of an organic material such as polyimide or photoacrylic. However, the present invention is not limited thereto.

Please refer to FIG. 2B , multiple signal lines are disposed on the first substrate 101 and disposed at the end of the first substrate 101. The multiple signal lines may include multiple scanning lines SL, multiple high potential voltage lines VDDL, multiple low potential voltage lines VSSL, multiple data lines DL, and multiple reference lines RL. For the convenience of description, FIG. 2B shows the second data line DL2 among the multiple signal lines.

The second data line DL2 may include a first layer DL2-1, a second layer DL2-2, and a third layer DL2-3. The second data line DL2 may have a jumping line structure through the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3. In other words, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 may function as a jumping line. The first layer DL2-1, the second layer DL2-2, the third layer DL2-3, and the upper pad PAD1 may be electrically connected to each other in parallel through holes in a plurality of insulating layers disposed therebetween. Therefore, the resistance of the second data line DL2 may be reduced.

More generally, each of the plurality of signal lines includes at least two overlapping signal line layers connected in parallel to each other. An insulating layer may be disposed between each of a pair of adjacent signal line layers in the at least two overlapping signal line layers. The insulating layer may include a plurality of through holes that receive corresponding connection portions connecting the adjacent pair of signal line layers. The signal line may be electrically connected to the upper pad, optionally wherein the signal line is electrically connected to the upper pad in parallel. The insulating layer may be disposed between the upper pad and the signal line. The insulating layer includes through holes that receive connection portions of the signal line and the upper pad.

The first layer DL2-1 can be disposed on the same layer as the light blocking layer LS and made of the same electrical conductive material as the light blocking layer LS. However, the present invention is not limited thereto.

The buffer layer 111 and the second layer DL2-2 can be disposed on the first layer DL2-1.

The second layer DL2-2 can be disposed on the same layer as the gate electrode GE and made of the same electrical conductive material as the gate electrode GE. However, the present invention is not limited thereto.

The outer end of the second layer DL2-2 may be disposed on the same plane as the outer end of the first layer DL2-1 (e.g., the plane indicated by the line L1 in FIG. 2A and FIG. 2B ). Furthermore, the second layer DL2-2 may be disposed to overlap with the first layer DL2-1 disposed on the lower portion of the second layer DL2-2 (i.e., disposed below the second layer DL2-2). FIG. 2B shows that the second layer DL2-2 is disposed to overlap with a portion of the first layer DL2-1. However, the present invention is not limited thereto. For example, the second layer DL2-2 may be disposed to completely overlap with the first layer DL2-1. The second layer DL2-2 may be disposed to overlap with the front (or upper) surface of the first layer DL2-1.

The second layer DL2-2 can be electrically connected to the first layer DL2-1 through a contact hole formed in the buffer layer 111. Therefore, the second layer DL2-2 can implement a structure that is parallel connected to the first layer DL2-1, thereby reducing the resistance of the second data line DL2.

The interlayer insulating layer 113 and the third layer DL2-3 are disposed on the second layer DL2-2. The third layer DL2-3 may be disposed to overlap with a plurality of upper pads PAD1 disposed on the upper portion of the third layer DL2-3 (ie, disposed on the third layer DL2-3).

The third layer DL2-3 can be disposed on the same layer as the source electrode SE and the drain electrode DE, and made of the same electrical conductive material as the source electrode SE and the drain electrode DE. However, the present invention is not limited thereto.

The outer end of the third layer DL2-3 may be disposed on the same plane as the end of the first layer DL2-1 and the end of the second layer DL2-2 (e.g., the plane indicated by the line L1 in FIG. 2A and FIG. 2B ). Furthermore, the third layer DL2-3 may be disposed to overlap with the second layer DL2-2 and the first layer DL2-1. FIG. 2B shows that the inner end of the third layer DL2-3 (i.e., the end farthest from the line L1) is disposed between the inner end of the second layer DL2-2 and the inner end of the first layer DL2-1. However, the position of the inner end of the third layer DL2-3 is not limited thereto.

The third layer DL2-3 can be electrically connected to the second layer DL2-2 through a contact hole formed in the interlayer insulating layer 113. Therefore, the second layer DL2-2 and the third layer DL2-3 can be implemented as a structure connected in parallel to each other, thereby reducing the resistance of the second data line DL2.

At the same time, an electrostatic discharge circuit can be disposed on the substrate 110 to overlap with the plurality of upper pads PAD1. The electrostatic discharge circuit is disposed in an area between the plurality of upper pads PAD1 and the display area AA. The electrostatic discharge circuit can be electrically connected to the second data line DL2. When static electricity is introduced through the second data line DL2, the electrostatic discharge circuit can be turned on and release the static electricity to the ground line, thereby blocking (reducing or eliminating) the static electricity. In other words, the electrostatic discharge unit can be electrically connected to the ground line and electrically connected to the signal line (e.g., the second data line DL2), and vice versa. Therefore, the electrostatic discharge circuit can suppress damage to the display device 100 by blocking or releasing the flow of overcurrent caused by static electricity. The electrostatic discharge circuit can be electrically connected to the signal line via the side line 140.

The electrostatic discharge circuit can be overlapped on the upper pad PAD1 and/or the lower pad PAD2, thereby providing a tighter arrangement at the edge of the display device, thereby reducing or eliminating the bezel.

The bank 119 may be disposed on the electrostatic discharge circuit to partially or completely overlap the electrostatic discharge circuit. The bank may extend to the edge of the display device. The bank 119 may include a light absorbing material (e.g., a black material). Therefore, the bank may prevent external light from being irradiated onto the electrostatic discharge circuit and reflected from the electrostatic discharge circuit. Furthermore, the edge of the display and the area between the plurality of sub-pixels may have the same appearance.

The passivation layer 114 and one of the upper pads PAD1 are disposed on the third layer DL2-3.

The side surfaces of each of the plurality of upper pads PAD1 may be disposed on the same plane as the side surfaces of each of the plurality of signal lines including the second data line DL2 (for example, the plane indicated by the line L1 in FIG. 2A and FIG. 2B ).

Meanwhile, FIG. 2B shows that the upper pad PAD1 overlaps only with the second data line DL2 as a signal line. However, each of the plurality of upper pads PAD1 may be configured to overlap with at least one of the plurality of signal lines and or at least one of the plurality of transistors TR.

The upper pad PAD1 can overlap with the signal line DL2 or the TFT, or both. The technical effect is to reduce the size of the area between the edge of the display panel and the LED, thereby reducing the size of the frame or completely eliminating the frame (for example, making the distance between the edge of the display panel and the LED half the distance between adjacent multiple LEDs).

At the edge of the display device, the bank 119 may partially or completely overlap the signal line (e.g., the second data line DL2) and/or the upper pad PAD1 and/or the lower pad PAD2. The bank 119 may include a light blocking material (e.g., a black material) and may extend to the edge of the substrate 110. Therefore, the bank may prevent external light from being irradiated onto the upper pad PAD1 and/or the signal line (e.g., the second data line DL2) and reflected therefrom. Furthermore, the edge of the display device may have the same appearance as the area between multiple sub-pixels.

Multiple upper pads PAD1 (disposed on the front surface or top side of the substrate 110) can be electrically connected to the side lines 140 described below and multiple signal lines in the display area AA, and provide signals received from multiple flexible films and printed circuit boards disposed on the rear surface (i.e., bottom side) of the substrate 110 to multiple sub-pixels SP.

A plurality of lower pads PAD2 are disposed on the lower surface (i.e., the rear surface or the bottom side) of the second substrate 102.

The multiple lower pads PAD2 can transmit the signals received from the driver disposed on the rear surface of the second substrate 102 to the multiple side lines 140 and further to the multiple upper pads PAD1 and multiple signal lines. The multiple lower pads PAD2 can be disposed at the end of the second substrate 102 in the non-display area NA and electrically connected to the side lines 140 covering (or disposed on) the side surface of the second substrate 102 (and the side surfaces of other layers at the edge of the display device).

Multiple lower pads PAD2 can be arranged at a position where multiple lower pads PAD2 overlap with multiple upper pads PAD1. Multiple upper pads PAD1 and multiple lower pads PAD2 overlap with each other and are electrically connected to each other through the side line 140. Multiple lower pads PAD2 and signal lines can also overlap with each other and are electrically connected to each other through the side line 140. At the same time, although not shown in FIG. 2B, multiple connection lines, multiple flexible films, printed circuit boards, etc. can be arranged under the second substrate 102.

The plurality of connection lines may provide various signals and voltages received from the driving part to the plurality of signal lines of the display device 100. For example, the plurality of connection lines may include a plurality of gate connection lines, a plurality of data connection lines, a plurality of high potential voltage connection lines, a plurality of low potential voltage connection lines, and a reference voltage connection line according to their connection with the corresponding signal lines. However, the present invention is not limited thereto. Here, the driving part may include a plurality of flexible films and a printed circuit board. However, the present invention is not limited thereto. The connection lines may electrically connect the driving part to the side lines directly or via other components such as the lower pad or the upper pad.

Multiple flexible films supply signals to multiple sub-pixels SP. Multiple flexible films are configured so that various types of components such as gate driver integrated circuits and data driver integrated circuits are arranged on a flexible base film. The printed circuit board is electrically connected to multiple flexible films and supplies signals to the components of the driver integrated circuit. Various types of components for providing various signals such as drive signals and data signals to the driver integrated circuit can be arranged on the printed circuit board. Multiple lower pads PAD2 can be electrically connected to multiple flexible films or printed circuit boards through multiple connection lines.

For example, multiple lower pads PAD2 can be electrically connected to multiple flexible films through multiple connection lines. Multiple flexible films can provide various forms of signals to multiple side lines 140, multiple upper pads PAD1, multiple signal lines, and multiple sub-pixels SP through multiple lower pads PAD2 and multiple connection lines. Therefore, the signal received from the driver can be transmitted to multiple sub-pixels SP and the signal line on the front surface of the first substrate 101 through multiple lower pads PAD2 of the second substrate 102, the side lines 140 and multiple upper pads PAD1 of the first substrate 101. More generally, a signal from a driver on the bottom side (or rear surface or lower surface) of the substrate 110 may be transmitted to a plurality of sub-pixels SP on the top side (or front surface or upper surface) via a side line 140. The side line 140 is connected to the driver via a lower pad PAD2 and is connected to the sub-pixels SP via a signal line and an upper pad PAD1. The side line 140 may be directly connected to the signal line and/or may be connected to the signal line via an upper pad PAD1.

Referring to FIG. 2B , after the first substrate 101 and the second substrate 102 are bonded together by the first adhesive layer 121 , the first substrate 101 and the second substrate 102 can be polished (for example, using mechanical polishing means) to the plane indicated by the first line L1 .

The grinder GR disposed outside the first substrate 101 and the second substrate 102 can grind the side surfaces of the first substrate 101 and the second substrate 102 while rotating around the rotation axis. The grinder GR can grind the side surfaces of the first substrate 101 and the second substrate 102 while moving to the first line L1 overlapping with the side surfaces of multiple signal lines and multiple pads PAD including the upper pad PAD1 and the lower pad PAD2. Therefore, the grinding surface can be formed on the side surfaces of the first substrate 101 and the second substrate 102 by the grinder GR. However, the present invention is not limited thereto, and the portion of the substrate 110 protruding from the plane indicated by the line L1 can be removed by other methods such as cutting, sanding, or filing.

For ease of description, the figure shows that the plurality of pads PADs remaining on the substrate 110 after the grinding process have a large area. However, when substantially reducing the bezel area and implementing the assembly of the display, the area of the plurality of pads PADs remaining on the substrate 110 can be very small to eliminate the unevenness between adjacent display devices 100. In other words, the entire end of the display can be ground back (or otherwise manufactured) to minimize the area containing the plurality of pads PADs. This allows the distance between the closest edge of the sub-pixel SP and the line L1 to be reduced to, for example, half the distance between the edges of adjacent sub-pixels, so that in a spliced display including one or more adjacent displays as shown in FIG. 2A and FIG. 2B (or FIG. 3A and FIG. 3B; or FIG. 4A and FIG. 4B; or FIG. 5), there is no discontinuity in the spacing of the sub-pixels on the spliced array at the connection between the adjacent displays. Therefore, the appearance and performance of the spliced display are improved.

The grinding surfaces of the first substrate 101 and the second substrate 102 formed by the grinding machine GR can have a straight line shape consistent with the shape of the grinding machine GR. In other words, the surface can be uniformly ground so that the final result is a flat grinding surface. In this article, the side surfaces of the first substrate 101 and the second substrate 102 will be described below with reference to Figures 3A and 3B.

FIG. 3A is a schematic plan view of a sub-pixel of a display device according to the first embodiment. FIG. 3B is a schematic cross-sectional view of the display device along line III-III' in FIG. 3A. FIG. 3A and FIG. 3B illustrate the state after the grinding process is completed. FIG. 3A illustrates a plurality of upper pads PAD1, a plurality of signal lines, a plurality of light-emitting elements LED, a plurality of side lines 140, and a plurality of pixels P on a substrate 110. Because the display device 100 in the state after the grinding process is completed is substantially the same as the display device in the state before the grinding process is performed (e.g., the display device of FIG. 2A and FIG. 2B ), except for adding a plurality of side lines 140 and a side insulating layer 150 and excluding the removed portion of the substrate 110 , the repeated description of the components, features, and arrangements described with reference to FIG. 1 , FIG. 2A , and FIG. 2B will be omitted.

Referring to FIG. 3A and FIG. 3B , the side surfaces of the first substrate 101 and the second substrate 102 of the display device 100 are arranged in a straight line shape (i.e., a plane). The side surfaces of the first substrate 101 and the second substrate 102 are arranged on the same plane as the side surfaces of the components of the display device 100 arranged on the upper part and the lower part of the substrate 110. For example, the side surface of the first substrate 101 can be arranged on the same plane as the side surfaces of multiple signal lines and multiple upper pads PAD1, and on the same plane as the side surfaces of multiple insulating layers arranged on the first substrate 101. The side surface of the second substrate 102 can also be arranged on the same plane as the side surfaces of multiple lower pads PAD2 arranged under the second substrate 102.

After the removal (e.g., grinding) process, a plurality of side lines 140 are disposed on the side surfaces of the first substrate 101 and the second substrate 102. The plurality of side lines 140 can electrically connect a plurality of upper pads PAD1 formed on the upper surface of the first substrate 101 and a plurality of lower pads PAD2 formed on the lower surface of the second substrate 102, and further connect a plurality of signal lines formed on the upper surface of the first substrate 101 and a plurality of connection lines formed on the rear surface of the second substrate 102 (i.e., located on the back, bottom, below, or below the second substrate 102). However, the present invention is not limited to including the lower pad, and the connection line can be directly connected to the side line without the lower pad.

A plurality of side lines 140 may be provided to surround the side surface of the display device 100. The plurality of side lines may be separated from each other. The plurality of side lines 140 may respectively contact the side surfaces of the plurality of upper pads PAD1 provided at the end of the first substrate 101, the side surfaces of the plurality of signal lines, the side surface of the first substrate 101, the side surface of the second substrate 102, and the side surfaces of the plurality of lower pads PAD2 provided at the end of the second substrate 102. In this case, when the side surface of the substrate 110 is provided in a plane perpendicular to the plane of the upper surface of the substrate 110, the plurality of side lines 140 may also be provided in a direction perpendicular to the upper surface of the substrate 110.

The plurality of side lines 140 can be formed by pad printing using a conductive ink containing, for example, silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), etc.

The side insulating layer 150 is provided to cover the plurality of side wirings 140. The side insulating layer 150 may be formed to cover the side wirings 140 on the upper surface of the first substrate 101, the side surface of the first substrate 101, the side surface of the second substrate 102, and the rear surface of the second substrate 102. In other words, the side insulating layer 150 may cover the upper surface, the lower surface, and the side surface of the side wirings 140. The side insulating layer 150 may protect the plurality of side wirings 140.

Meanwhile, when the plurality of side wirings 140 are made of a metal material, external light is reflected by the plurality of side wirings 140, or light emitted by the self-light emitting element LED is reflected by the plurality of side wirings 140, and a problem of a user visually recognizing the light may occur. Therefore, the side insulating layer 150 may be used to include a black material to suppress the reflection of external light. For example, the side insulating layer 150 may be formed by a pad printing method using an insulating material including a black material such as black ink.

Meanwhile, although not shown in FIG. 3A and FIG. 3B , a sealing unit and an optical film covering the side insulating layer 150 may be additionally provided. The sealing unit may be provided to surround the side surface of the display device 100 and protect the display device 100 from external impact or moisture and oxygen. For example, the sealing unit may be made of materials such as polyimide (PI), polyurethane, epoxy, and acrylic. However, the present invention is not limited thereto.

The optical film may be disposed on the sealing unit, the side insulating layer 150, and the protective layer. The optical film may be a functional film that implements an image with higher image quality while protecting the display device 100. For example, the optical film may include an anti-glare film, an anti-reflection film, a low-reflection film, an OLED transmittance controllable film, or a polarization plate. However, the present invention is not limited thereto.

A plurality of pads are disposed on the upper and lower sides of a substrate in a non-display area of a display device to transmit various forms of signals to a plurality of sub-pixels. The plurality of pads may be connected between a plurality of side lines and a plurality of signal lines, and the plurality of pads provide signals received from a printed circuit board disposed under the substrate and a plurality of flexible films to a plurality of sub-pixels. In this case, the plurality of pads are disposed on an outer peripheral portion of the display device, that is, a frame area. Furthermore, the plurality of pads are disposed outside of a plurality of signal lines and a plurality of transistors, which requires separate areas for disposing the plurality of pads, thereby limiting the reduction of the frame of the display device.

At the same time, the spacing between the outermost peripheral light-emitting element LEDs of a panel and the outermost peripheral light-emitting element LEDs of another panel adjacent to the panel (and having the same edge structure and side wiring as any embodiment described herein) is implemented to be the same as the spacing between the light-emitting element LEDs in a panel, so that the assembled display is implemented by setting multiple panels in a tile shape. Therefore, due to the reduction of the size limit of multiple pads, when the border area of the display device is larger than the spacing between the light-emitting elements in a display panel, the boundaries between the display modules can be visually recognized by the user, which causes the interruption of the display image, and especially the limitation of the implementation of large-scale panels caused by tiling.

Therefore, in the display device 100 according to the first embodiment, a plurality of pads PAD are arranged to overlap with a plurality of signal lines and at least one of a plurality of transistors TR, so that a separate area for arranging the pads PAD can be eliminated from the design, and the bezel area of the display device 100 can be reduced.

Furthermore, in the display device 100 according to the first embodiment, the side line 140 is formed on the side surfaces of the first upper pad PAD1 and the plurality of lower pads PAD2, so that the side surface of the substrate 110 can be ground to form a straight line portion (i.e., a plane). That is, the plurality of side lines 140 can be formed without grinding the side surface of the substrate 110 at an angle, so as to more smoothly connect the plurality of signal lines (e.g., gate line GL, data line DL) disposed on the upper surface of the first substrate 101 and the plurality of connection lines on the rear surface of the second substrate 102, thereby simplifying the manufacturing process. When the term "side surface" is used to describe the surface of a feature, this can be understood to mean the surface of the terminal of the feature, such as at the edge of the display device.

Furthermore, in the display device 100 according to the first embodiment, the side surface of the substrate 110 is not grinded at an angle, which can reduce the problems caused when the side surface of the substrate 110 is grinded at an angle.

First, during the grinding process, defects that may occur in the side wiring and multiple pads can be suppressed. When the grinding process using a grinder is performed on the edges of the first substrate and the second substrate, multiple pads and side wiring provided on the upper and lower portions of the substrates are partially removed together with the substrates, causing the problem of disconnection of the side wiring and multiple pads. Furthermore, the problem of cracks starting to form on the ground side surface and spreading occurs. Therefore, in the display device 100 according to the first embodiment, the grinding process is not performed on the side surface of the substrate 110, which can suppress defects that may occur in the side wiring 140 and multiple pads PAD.

Furthermore, the side insulating layer 150 covering the plurality of side lines 140 may be applied from the bottom of the substrate 110 and filled to the upper surface of the substrate 110 along the direction of the side surface (i.e., along the direction in the plane of the side surface). Therefore, when the side surface of the substrate is grinded obliquely, the side insulating layer 150 may be unevenly formed on the side surface of the substrate due to the oblique surface formed on the side surface of the substrate. Therefore, the side insulating layer may not be filled at some points without covering a portion of the upper surface of the substrate or covering the entire side surface. Therefore, when the side wiring is exposed at a point where the side insulating layer is not filled, external light is reflected by multiple side wirings located at the corresponding point or light emitted from the light-emitting element is reflected by multiple side wirings, and a problem that the user visually recognizes the light may occur. Therefore, in the display device 100 according to the first embodiment, the inclined surface is not formed on the side surface of the substrate 110 by a grinding process. Therefore, the side insulating layer 150 can be uniformly disposed on the side surface of the substrate 110, and the external light can be suppressed from being reflected by the side wiring 140 located at a point where the side insulating layer 150 is not filled.

FIG. 4A is a cross-sectional schematic diagram of a display device according to the second embodiment in a state before the process of grinding the display device. FIG. 4B is a cross-sectional schematic diagram of a display device according to the second embodiment. Because the display device 400 according to the second embodiment is substantially the same as the display device 100 according to the first embodiment, except for the substrate 410, the plurality of side lines 440, and the plurality of pads PAD, the repeated description of the components, features, and arrangements described with reference to FIG. 1, FIG. 2A, FIG. 2B, FIG. 3A, and FIG. 3B will be omitted.

Referring to FIG. 4A , the side surfaces of the first substrate 101 and the second substrate 402 may be ground. The grinder GR may grind the side surfaces of the first substrate 101 and the second substrate 402 while moving to the first line L1. Therefore, a grinding surface may be formed on the side surfaces of the first substrate 101 and the second substrate 402 by the grinder GR. In this case, the grinding surface of the first substrate 101 formed by the grinder GR may be formed into a straight line shape according to the shape of the grinder GR. At the same time, the side surface of the second substrate 402 and the side surface of the first substrate 101 may be configured as different surfaces (for example, wherein the planes of the surfaces have different orientations).

In this article, the side surfaces of the first substrate 101 and the second substrate 402 will be described below with reference to FIG. 4B .

Referring to FIG. 4B , the substrate 410 of the display device 400 may include a side surface formed as an inclined surface that is inclined relative to the upper surface of the substrate 410. That is, a portion of the side surface of the substrate 410 may be an inclined surface that is inclined (obliquely) relative to the upper surface of the substrate 410.

First, the side surface of the first substrate 101 of the display device 400 is disposed on the same plane as the side surface of the components of the display device 400 disposed on the upper portion of the substrate 410. For example, the side surface of the first substrate 101 may be disposed on the same plane as the side surfaces of the plurality of signal lines and the plurality of upper pads PAD1, and disposed on the same plane as the side surfaces of the plurality of insulating layers disposed on the first substrate 101. In this case, the side surface of the first substrate 101 may be a surface perpendicular to the upper surface of the substrate 110.

The side surface of the second substrate 402 may include a side surface arranged in a direction (i.e., orientation) different from the direction (i.e., orientation) of the side surface of the component of the display device 400 arranged on the upper portion of the substrate 410. For example, a portion of the side surface of the second substrate 402 may include an inclined surface that is inclined (obliquely) relative to the upper surface of the substrate 110.

At the same time, the side surfaces of each of the multiple lower pads PAD2 and the multiple connection lines disposed on the lower portion of the second substrate 402 may include an inclined surface formed at the same angle (and in the same plane) as the side surface of the second substrate 402. Therefore, as shown in FIG. 4B , the ends of the multiple lower pads PAD2 and the multiple connection lines disposed on the lower portion of the second substrate 402 may be disposed within the ends of the substrate 410 (i.e., the ends are divided by the line L1).

Next, a plurality of side lines 440 are disposed on the side surfaces of the first substrate 101 and the second substrate 402. The plurality of side lines 440 may connect a plurality of upper pads PAD1 having a side surface in a straight line shape and a plurality of lower pads PAD2 including a side surface having an inclined surface. In this case, the plurality of side lines 440 may contact the side surface of the first substrate 101 and the inclined side surface of the second substrate 402. Therefore, when the plurality of lower pads PAD2 are disposed in the side surface of the second substrate 402, the plurality of side lines 440 may also contact the lower surface of the substrate 410.

The side insulating layer 450 is provided to cover the plurality of side wirings 440. The side insulating layer 450 may be formed to cover the side wirings 440 on the upper portion of the first substrate 101, the side surface of the first substrate 101, the side surface of the second substrate 402, and the lower portion of the second substrate 402. In other words, the side insulating layer 450 may cover the upper surface, the lower surface, and the side surface of the side wirings 440. The side insulating layer 450 may protect the plurality of side wirings 440.

In the display device 400 according to the second embodiment, each of the plurality of pads PAD is configured to overlap with at least one of the plurality of signal lines and/or at least one of the plurality of transistors TR, thereby reducing the frame area of the display device 400.

Furthermore, in the display device 400 according to the second embodiment, the side surface of the substrate 410 can be set as a (tilted) inclined surface, thereby reducing the contact resistance between the plurality of side lines 440 and the plurality of pads PAD. When the side surface of the substrate 410 is set at an inclined surface, the contact area between the plurality of pads PAD and the plurality of side lines 440 can be increased. Therefore, the overall resistance of the plurality of signal lines and the plurality of pads PAD can be reduced.

FIG5 is a cross-sectional schematic diagram of a display device according to the third embodiment. Because the display device 500 according to the third embodiment is substantially the same as the display device 100 according to the first embodiment, except for a plurality of side lines and a plurality of pads PAD, the repeated description of the components, features, and arrangements described with reference to FIG1, FIG2A, FIG2B, FIG3A, and FIG3B will be omitted.

Please refer to FIG. 5 , a plurality of signal lines are disposed on the first substrate 101 and disposed at the end of the first substrate 101 . For the convenience of description, FIG. 5 shows the second data line DL2 among the plurality of signal lines.

The second data line DL2 may include a first layer DL2-1, a second layer DL2-2, and a third layer DL2-3. The first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 are the same as the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 described with reference to FIGS. 1 to 3B.

The passivation layer 114 and the first planarization layer 115a are disposed on the third layer DL2-3.

At the same time, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 constituting the second data line DL2 can be electrically connected to the multiple lower pads PAD2 through the side line 140, and provide various forms of signals to the multiple sub-pixels SP. Therefore, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 constituting the second data line DL2 can be regarded as an upper pad, and each of the multiple upper pads can be a part of the corresponding multiple signal lines.

According to the display device 500 of the third embodiment, a plurality of side lines 140 can be formed without grinding the side surface of the substrate 110 at an angle, thereby simplifying the manufacturing process.

Furthermore, in the display device 500 according to the third embodiment, the side surface of the substrate 110 is not grinded obliquely. Therefore, the problem that some side lines 140 and a plurality of pads PAD are removed and the side lines 140 and a plurality of pads PAD are disconnected during the grinding process can be suppressed.

Furthermore, in the display device 500 according to the third embodiment, the inclined surface is not formed on the side surface of the substrate 110 by a grinding process. Therefore, the side insulating layer 150 can be uniformly disposed on the side surface of the substrate 110, and the external light can be suppressed from being reflected by the side line 140. Alternatively, the display device 500 can be configured as a display device described with reference to FIG. 4A and FIG. 4B (i.e., having an inclined surface of the second substrate), but without an upper pad, but having a direct connection between the side line 140 and one or more layers of the signal lines DL2-1, DL2-2, DL2-3 (as described in FIG. 5).

Furthermore, in the display device 500 according to the third embodiment, without providing a separate pad at the end of the display device 500, some of the plurality of signal lines can be used as pads. In the display device 500 according to the third embodiment, the plurality of side lines 140 can contact the side surfaces of the plurality of signal lines. Therefore, without providing a conductive material for forming the pad, the signal applied from the driving part to the plurality of pixels SP can be transmitted. Therefore, in the display device 500 according to the third embodiment, the process of forming a separate conductive material for forming the pad is not performed, thereby reducing the cost and simplifying the process of manufacturing the display device.

The embodiment can also be described as follows: According to one aspect of the present invention, the display device includes: a substrate on which a plurality of light-emitting elements are disposed; a transistor located on the substrate; a plurality of signal lines located on the substrate; a plurality of connection lines under the substrate; and a plurality of upper pads located on the substrate and connected to the plurality of signal lines, wherein the plurality of upper pads are arranged to overlap with at least one of the plurality of signal lines and the plurality of transistors.

The display device may further include a plurality of side lines that can connect to a plurality of signal lines and a plurality of connection lines. The plurality of upper pads and the plurality of signal lines can contact the plurality of side lines.

The side surfaces of the plurality of upper pads may be disposed on the same plane as the side surfaces of the plurality of signal lines.

Multiple side traces can contact the side surface as well as the lower surface of the substrate.

The display device may further include a plurality of lower pads on the lower surface of the substrate, and the lower pads are connected to a plurality of connection lines. The plurality of lower pads may be arranged to overlap with the plurality of upper pads.

A portion of the side surface of the substrate may be an inclined surface that is inclined relative to the upper surface of the substrate, and a plurality of side lines may partially cover the side surface and the lower surface of the substrate.

The substrate may include a first substrate and a second substrate below the first substrate. A side surface of a portion of the second substrate may be an inclined surface that is inclined relative to the upper surface of the substrate.

The display device may further include a plurality of lower pads on the lower surface of the substrate and connected to a plurality of connection lines. The ends of the plurality of lower pads may be disposed within the ends of the substrate.

The display device may further include a plurality of insulating layers located on the substrate and disposed on the upper portion or lower portion of the plurality of upper pads and the plurality of signal lines. The side surfaces of the plurality of insulating layers may be disposed on the same plane as the side surface of the substrate.

The side surfaces of the plurality of insulating layers may be disposed on the same plane as the side surfaces of the plurality of upper pads.

Each of the multiple upper pads can be part of each of the multiple signal lines.

The display device may further include an electrostatic discharge circuit located on the substrate to overlap with multiple upper pads.

Although the embodiments have been described in detail with reference to the attached drawings, the present invention is not limited thereto and can be embodied in many different forms. Therefore, the embodiments are for illustrative purposes only and are not intended to limit the technical concept of the present invention. It is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present invention. The scope of the present invention should be interpreted based on the following invention application patent scope and its equivalents.

This article also describes examples of the following numbers:

Example 1. A display device comprises: a substrate on which a plurality of light-emitting elements are disposed; a plurality of transistors disposed on the substrate; a plurality of signal lines disposed on the substrate; a plurality of connection lines disposed under the substrate; and a plurality of upper pads disposed on the substrate and connected to the signal lines, wherein the upper pads overlap with at least one of the signal lines and the transistors.

Example 2. The display device of Example 1 further includes a plurality of side lines connecting the signal lines and the connection lines, wherein the plurality of upper pads and the plurality of signal lines are in contact with the plurality of side lines.

Example 3. A display device as in Example 1 or 2, wherein the side surfaces of the plurality of upper pads and the side surfaces of the plurality of signal lines are arranged on the same plane.

Example 4. A display device as in Example 1, 2 or 3, wherein a plurality of side lines are in contact with the side surface and the lower surface of the substrate.

Example 5. The display device of Example 4 further includes a plurality of lower pads located on the lower surface of the substrate and connected to a plurality of connection lines, wherein the plurality of lower pads overlap with the plurality of upper pads.

Example 6. A display device as in Example 4 or 5, wherein a portion of the side surface of the substrate is an inclined surface that is inclined relative to the upper surface of the substrate, and wherein a plurality of side lines partially cover the side surface and the lower surface of the substrate.

Example 7. A display device as in any one of Examples 1 to 6, wherein the substrate includes a first substrate and a second substrate located below the first substrate, and wherein a portion of the side surface of the second substrate is an inclined surface that is inclined relative to the upper surface of the second substrate.

Example 8. A display device as in any one of Examples 1 to 7, further comprising a plurality of lower pads located on the lower surface of the substrate and connected to a plurality of connection lines, wherein the ends of the plurality of lower pads are disposed within the ends of the substrate.

Example 9. A display device as in any one of Examples 1 to 8, further comprising a plurality of insulating layers, the plurality of insulating layers being located on the substrate and disposed on the upper portion or lower portion of the plurality of signal lines and the plurality of upper pads, wherein the side surfaces of the plurality of insulating layers are disposed on the same plane as the side surface of the substrate.

Example 10. A display device as in Example 9, wherein the side surfaces of the plurality of insulating layers and the side surfaces of the plurality of upper pads are arranged on the same plane.

Example 11. A display device as in any one of Examples 1 to 10, wherein each of the plurality of upper pads is a portion of each of the plurality of signal lines.

Example 12. A display device as in any one of Examples 1 to 11, further comprising an electrostatic discharge circuit disposed on the substrate and overlapping with a plurality of upper pads.

Example 13. A display device, comprising: a plurality of scanning lines and a plurality of data lines, disposed on a first substrate; a light-emitting element, disposed between adjacent ones of the plurality of data lines; a transistor, disposed on the first substrate; a plurality of upper pads, disposed on the first substrate and connected to the plurality of scanning lines and the plurality of data lines; a plurality of lower pads, disposed on the second substrate and overlapping with the plurality of upper pads; and a plurality of side lines, disposed on the side surfaces of the first substrate and the second substrate and connected to the plurality of upper pads, the plurality of lower pads and the plurality of data lines.

Example 14. The display device of Example 13 further includes multiple insulating layers disposed on multiple signal lines and multiple bottom pads.

Example 15. The display device of Example 14, wherein the side surfaces of the plurality of insulating layers are arranged on the same plane as the side surfaces of the first substrate and the second substrate.

Example 16. A display device as in any one of Examples 13 to 15, wherein the second substrate has a side surface that is inclined relative to the second substrate.

Example 17. A display device as in any one of Examples 13 to 16, wherein the plurality of lower pads have ends disposed within the ends of the second substrate.

Example 18. A display device as in any one of Examples 13 to 17, wherein the plurality of upper pads have side surfaces disposed on the same plane as the side surfaces of the plurality of data lines.

Example 19. A display device as in any one of Examples 13 to 18, wherein a plurality of side lines are formed by pad printing using a conductive ink.

Example 20. A display device as in any one of Examples 13 to 16, further comprising an electrostatic discharge circuit disposed on the first substrate and overlapping with a plurality of upper pads.

This document also describes the following numbered items:

Item 1. A display device, comprising: a substrate; a plurality of light-emitting elements disposed on the substrate; a plurality of transistors disposed on the substrate; a plurality of signal lines disposed on the substrate, each signal line being electrically connected to one or more of the plurality of transistors; an electrostatic discharge circuit disposed on the substrate and arranged to selectively connect the signal line to the ground line.

Item 2. The display device of Item 1 further comprises: a plurality of connection lines disposed under the substrate; and a plurality of side lines disposed on the side surface of the substrate, each side line providing at least a portion of the electrical connection between a corresponding one of the plurality of connection lines and a corresponding one of the plurality of signal lines, wherein the electrostatic discharge circuit is electrically connected to the signal line via the side line.

Item 3. A display device as in Item 1 or 2, further comprising an upper pad disposed on the substrate, wherein the electrostatic discharge circuit overlaps the upper pad.

Item 4. A display device as in Item 1, 2 or 3, further comprising a lower pad disposed under the substrate, wherein the electrostatic discharge circuit overlaps the lower pad.

Item 5. A display device as in Item 1 or 2, further comprising an upper pad disposed on the substrate and a lower pad disposed below the substrate, wherein the upper pad overlaps the lower pad, and optionally wherein the electrostatic discharge circuit overlaps the upper pad and/or the lower pad.

Item 6. A display device as described in any one of Items 1 to 5, further comprising a bank disposed on the substrate, wherein the bank overlaps the electrostatic discharge circuit.

Item 7. A display device as in Item 6, wherein the bank comprises a light blocking material.

Item 8. A display device as in Item 7, wherein the bank comprises a black material.

Item 9. A display device as described in any one of Items 1 to 8, wherein each of the plurality of light-emitting elements is a micro-light-emitting diode comprising an inorganic active layer.

Item 10. A display device as described in any one of Items 1 to 9, wherein each of the plurality of light-emitting elements comprises: an n-type layer; an active layer located on the n-type layer; a p-type layer located on the active layer; an n-type electrode located on the n-type layer; and a p-type electrode located on the p-type layer, wherein the p-type electrode and the n-type electrode are disposed at different height levels to be separated from each other.

Item 11. The display device of Item 10 further comprises: a first electrode connected to the n-type electrode; and a second electrode connected to the p-type electrode.

Item 12. The display device of Item 11 further comprises: a first planarization layer; a second planarization layer located on the first planarization layer; and a third planarization layer located on the second planarization layer, wherein the first electrode and the second electrode are separated from each other, and the third planarization layer is disposed between the first electrode and the second electrode.

Item 13. A display device as in Item 12, wherein the second planarization layer and the third planarization layer contact each other in a region between the first electrode and the second electrode.

Item 14. A display device as in any one of items 11 to 13, further comprising: a bank located on the first electrode and the second electrode, and a plurality of upper pads disposed on the substrate, wherein the bank overlaps at least a portion of at least one of the plurality of upper pads, and optionally wherein the bank comprises a light blocking material, and optionally wherein the light blocking material is a black material.

Item 15. A display device as described in any one of Items 9 to 14, further comprising a reflective layer corresponding to each of the plurality of light-emitting elements, wherein the light-emitting elements overlap the reflective layer.

Item 16. A display device as described in any one of Items 1 to 15, further comprising a plurality of upper pads disposed on a substrate, wherein the electrostatic discharge circuit is disposed in an area between a display area where a light-emitting element is disposed and the upper pads.

Item 17. A display device as described in any one of Items 1 to 16, wherein each of the plurality of signal lines comprises at least two overlapping signal line layers connected in parallel to each other.

Item 18. A display device as described in any one of Items 1 to 17, further comprising a first insulating layer, wherein the first insulating layer is disposed between each of a pair of adjacent signal line layers in at least two overlapping signal line layers.

Item 19. A display device as in Item 18, wherein the first insulating layer includes a first through hole, wherein the first through hole receives a corresponding connection portion connecting a pair of adjacent signal line layers.

Item 20. A display device as described in any one of items 1 to 19, wherein the signal line is electrically connected to the upper pad, and optionally wherein the signal line is electrically connected to the upper pad in parallel.

Item 21. A display device as described in any one of Items 1 to 20, further comprising a second insulating layer disposed between the upper pad and the signal line.

Item 22. A display device as in Item 21, wherein the second insulating layer includes a second through hole, wherein the second through hole receives a connection portion connecting the signal line and the upper pad.

Item 23. A display device as described in any one of Items 1 to 22, further comprising a plurality of upper pads disposed on a substrate, wherein each of the plurality of upper pads overlaps: One of a plurality of signal lines; and/or one of a plurality of transistors.

Item 24. A display device as described in any one of items 1 to 23, wherein the edge of the display device includes at least one plane, and the substrate, the electrostatic discharge circuit, and the signal line terminate at the at least one plane.

Item 25. A display device as in Item 24, wherein at least one plane includes a first plane arranged perpendicular to the upper surface of the substrate.

Item 26. A display device as in Item 24 or 25, wherein at least one plane includes a second plane inclined relative to the upper surface of the substrate.

Item 27. A display device as in Item 24, 25 or 26, further comprising a plurality of side lines, wherein the plurality of side lines partially cover at least one plane, and optionally cover the lower surface of the substrate.

Item 28. A display device as in Item 27, wherein each side line is in contact with the electrostatic discharge circuit signal line and the corresponding one in the middle.

This article also describes the following numbered items:

Item 1. A display device, comprising: a substrate; a plurality of light-emitting elements disposed on the substrate; a plurality of transistors disposed on the substrate; a plurality of signal lines disposed on the substrate, each signal line being electrically connected to one or more of the plurality of transistors; an upper pad disposed on the substrate, wherein the upper pad is disposed at an edge region of the substrate, and a bank is disposed on the upper pad to overlap the upper pad.

Item 2. A display device as in Item 1, further comprising a plurality of lower pads disposed under the substrate, wherein the upper pads overlap the lower pads.

Item 3. A display device as in Item 1 or 2, wherein the bank comprises a light blocking material, optionally a black material.

Item 4. A display device as in any one of items 1 to 3, wherein the bank extends to the edge of the substrate.

Item 5. A display device as in any one of items 1 to 4, wherein the bank extends between the light-emitting element and the edge of the substrate.

Item 6. A display device as in any one of Items 1 to 5, wherein each of the plurality of signal lines comprises at least two overlapping signal line layers connected in parallel to each other.

Item 7. The display device of Item 6 further comprises a first insulating layer, wherein the first insulating layer is disposed between each of a pair of adjacent signal line layers in at least two overlapping signal line layers.

Item 8. A display device as in Item 7, wherein the first insulating layer includes a first through hole, wherein the first through hole receives a corresponding connection portion connecting a pair of adjacent signal line layers.

Item 9. A display device as in any one of items 1 to 8, wherein the signal line is electrically connected to the upper pad, optionally wherein the signal line is electrically connected to the upper pad in parallel.

Item 10. A display device as in any one of items 1 to 9, further comprising a second insulating layer disposed between the upper pad and the signal line.

Item 11. A display device as in Item 10, wherein the second insulating layer includes a second through hole, the second through hole receiving a connection portion of the signal line and the upper pad.

Item 12. A display device as described in any one of Items 1 to 11, wherein each of the plurality of light-emitting elements is a micro-light-emitting diode comprising an inorganic active layer.

Item 13. A display device as described in any one of items 1 to 12, wherein each of the plurality of light-emitting elements comprises: an n-type layer; an active layer located on the n-type layer; a p-type layer located on the active layer; an n-type electrode located on the n-type layer; and a p-type electrode located on the p-type layer, wherein the p-type electrode and the n-type electrode are disposed at different height levels to be separated from each other.

Item 14. The display device of Item 13 further comprises: a first electrode connected to the n-type electrode; and a second electrode connected to the p-type electrode.

Item 15. The display device of Item 14 further comprises: a first planarization layer; a second planarization layer located on the first planarization layer; and a third planarization layer located on the second planarization layer, wherein the first electrode and the second electrode are separated from each other, and the third planarization layer is disposed between the first electrode and the second electrode.

Item 16. A display device as in Item 15, wherein the second planarization layer and the third planarization layer contact each other in a region between the first electrode and the second electrode.

Item 17. A display device as described in any one of Items 14 to 16, wherein the bank is provided on the first electrode and the second electrode.

Item 18. A display device as in any one of items 1 to 17, further comprising a reflective layer corresponding to each of a plurality of light-emitting elements, wherein the light-emitting elements overlap the reflective layer.

Item 19. A display device as in any one of items 1 to 18, further comprising an electrostatic discharge circuit, the electrostatic discharge circuit being disposed on the substrate and arranged to selectively electrically connect the signal line to the ground line, wherein the bank is disposed on the electrostatic discharge circuit and overlaps the electrostatic discharge circuit.

Item 20. A display device as in any one of items 1 to 19, wherein the bank is arranged to overlap a plurality of signal lines.

Item 21. A display device as in any one of items 1 to 20, wherein the edge of the display device includes at least one plane, and the substrate and the signal line terminate at the at least one plane.

Item 22. A display device as in Item 21, wherein at least one plane includes a first plane arranged perpendicular to the upper surface of the substrate.

Item 23. A display device as in Item 21 or 22, wherein at least one plane includes a second plane inclined relative to the upper surface of the substrate.

Item 24. A display device as in Item 21, 22 or 23, further comprising a plurality of side lines, wherein the plurality of side lines partially cover at least one plane, and optionally cover the lower surface of the substrate.

Item 25. A display device as in Item 24, wherein each side line contacts a corresponding one of a plurality of signal lines.

This article also describes the following numbered embodiments:

Embodiment 1. A display device comprises: a substrate; a plurality of light-emitting elements disposed on the substrate; a plurality of transistors disposed on the substrate; a plurality of signal lines disposed on the substrate, each signal line being electrically connected to one or more of the plurality of transistors; a plurality of connection lines disposed under the substrate; and a plurality of side lines disposed on a side surface of the substrate, each side line providing at least a portion of an electrical connection between a corresponding one of the plurality of connection lines and a corresponding one of the plurality of signal lines.

Embodiment 2. A display device as in Embodiment 1, wherein the edge of the display device includes at least one plane, and the substrate and the signal line terminate at at least one plane.

Embodiment 3. A display device as in Embodiment 2, wherein at least one plane includes a first plane arranged perpendicular to the upper surface of the substrate.

Embodiment 4. A display device as in Embodiment 2 or 3, wherein at least one plane includes a second plane inclined relative to the upper surface of the substrate.

Embodiment 5. A display device as in Embodiment 2, 3 or 4, wherein a plurality of side lines partially cover at least one plane and optionally cover the lower surface of the substrate.

Embodiment 6. A display device as in any one of Embodiments 1 to 5, wherein each side line contacts a corresponding one of a plurality of signal lines.

Embodiment 7. A display device as in any one of Embodiments 1 to 6, wherein the substrate comprises a first substrate and a second substrate located below the first substrate, and wherein at least a portion of the side surface of the second substrate forms at least a portion of the second plane.

Embodiment 8. A display device as in any one of embodiments 1 to 7 further comprises a plurality of upper pads disposed on the substrate, each upper pad being electrically connected to a corresponding one of the plurality of signal lines.

Embodiment 9. A display device as in any one of Embodiments 1 to 8, further comprising a plurality of upper pads disposed on a substrate, wherein each of a plurality of sub-pixels comprises a transistor, and wherein each of the plurality of upper pads overlaps: one of a plurality of signal lines; and/or one of a plurality of transistors.

Embodiment 10. A display device as in Embodiment 8 or 9, wherein each side line contacts a corresponding one of a plurality of upper pads.

Embodiment 11. A display device as in Embodiment 8, 9 or 10, wherein the side surface of the upper pad and the side surface of the signal line are located in the same plane.

Embodiment 12. A display device as in any one of embodiments 8 to 11, further comprising a plurality of lower pads located on the lower surface of the substrate, each lower pad being electrically connected to a corresponding one of a plurality of connection lines, wherein each of the plurality of lower pads overlaps with a corresponding one of the plurality of upper pads.

Embodiment 13. A display device as in any one of embodiments 8 to 12, further comprising a plurality of insulating layers, the plurality of insulating layers being located on the substrate and disposed on the upper portion or lower portion of the plurality of upper pads and/or the upper portion or lower portion of the plurality of signal lines, wherein the side surface of the insulating layer is located in the same plane as the side surface of the substrate.

Embodiment 14. A display device as in Embodiment 13, wherein the side surface of the insulating layer is in the same plane as the side surface of the upper pad and/or the side surface of the signal line.

Embodiment 15. A display device as in any one of Embodiments 8 to 14, wherein each of the plurality of upper pads is a part of a corresponding one of the plurality of signal lines.

Embodiment 16. A display device as in any one of embodiments 8 to 15, further comprising an electrostatic discharge circuit disposed on the substrate and overlapping with a plurality of upper pads.

Embodiment 17. A display device as in any one of embodiments 1 to 16, further comprising a plurality of lower pads located on the lower surface of the substrate, each lower pad being electrically connected to a corresponding one of the plurality of connection lines, wherein the end of the lower pad is disposed within the end of the substrate.

Embodiment 18. A display device as in any one of embodiments 1 to 17, further comprising: a plurality of upper pads disposed on a substrate, each upper pad being connected to a corresponding one of a plurality of signal lines; and a plurality of lower pads disposed under the substrate, each lower pad overlapping a corresponding one of the plurality of upper pads, wherein the side line electrically connects the lower pad to: the upper pad; and/or a plurality of signal lines.

Embodiment 19. A display device as in any one of embodiments 1 to 18, further comprising a side insulating layer configured to cover a plurality of side lines, wherein the side insulating layer optionally comprises a light blocking material.

Embodiment 20. A display device as in any one of embodiments 1 to 19, wherein each of the plurality of signal lines comprises at least two overlapping signal line layers connected in parallel to each other.

Embodiment 21. A display device as in any one of Embodiments 1 to 20, further comprising a first insulating layer, wherein the first insulating layer is disposed between each of a pair of adjacent signal circuit layers in at least two overlapping signal circuit layers.

Embodiment 22. A display device as in Embodiment 21, wherein the first insulating layer includes a first through hole, wherein the first through hole receives a corresponding connection portion connecting a pair of adjacent signal line layers.

Embodiment 23. A display device as in any one of embodiments 1 to 22, further comprising a plurality of upper pads, wherein each signal line is electrically connected to a corresponding upper pad, and optionally connected in parallel with the corresponding upper pad.

Embodiment 24. A display device as in any one of embodiments 1 to 23, further comprising a second insulating layer disposed between the upper pad and the signal line, wherein the second insulating layer comprises a second through hole, and the second through hole receives a connection portion connecting the signal line and the upper pad.

Embodiment 25. A display device as in any one of embodiments 1 to 24, further comprising a bank disposed on the substrate, wherein the bank optionally comprises a light blocking material, optionally comprises a black material.

Embodiment 26. A display device as in any one of embodiments 1 to 25, wherein each of the plurality of light-emitting elements is a micro-light-emitting diode comprising an inorganic active layer.

Embodiment 27. A display device as in any one of embodiments 1 to 26, wherein each of the plurality of light-emitting elements comprises: an n-type layer; an active layer located on the n-type layer; a p-type layer located on the active layer; an n-type electrode located on the n-type layer; and a p-type electrode located on the p-type layer, wherein the p-type electrode and the n-type electrode are disposed at different height levels to be separated from each other.

Embodiment 28. The display device of Embodiment 27 further comprises: a first electrode connected to the n-type electrode; and a second electrode connected to the p-type electrode.

Embodiment 29. The display device of embodiment 28 further comprises: a first planarization layer; a second planarization layer located on the first planarization layer; and a third planarization layer located on the second planarization layer, wherein the first electrode and the second electrode are separated from each other, and the third planarization layer is disposed between the first electrode and the second electrode.

Embodiment 30. A display device as in Embodiment 29, wherein the second planarization layer and the third planarization layer contact each other in a region between the first electrode and the second electrode.

Embodiment 31. A display device as in any one of embodiments 28 to 30, further comprising: a bank located on the first electrode and the second electrode, and a plurality of upper pads disposed on the substrate, wherein the bank overlaps at least a portion of at least one of the plurality of upper pads, and optionally wherein the bank comprises a light blocking material, and optionally wherein the light blocking material is a black material.

Embodiment 32. A display device as in any one of embodiments 26 to 31, further comprising a reflective layer corresponding to each of a plurality of light-emitting elements, wherein the light-emitting elements overlap the reflective layer.

Embodiment 33. A display device as in any one of embodiments 1 to 32, further comprising: an electrostatic discharge circuit disposed on the substrate and arranged to selectively connect the signal line to the ground line, and wherein the electrostatic discharge circuit is electrically connected to the signal line via a side line, and optionally wherein the electrostatic discharge circuit is disposed in an area between the display area where the light-emitting element is disposed and the upper pad.

Embodiment 34. A method for manufacturing a display device, comprising: Providing a display panel, comprising: a substrate; a plurality of sub-pixels disposed on the substrate; a plurality of signal lines disposed on the substrate, each signal line being electrically connected to one or more of the plurality of sub-pixels; a plurality of connection lines disposed under the substrate, wherein a portion of the substrate protrudes beyond the ends of the plurality of signal lines, at least a portion of the substrate is removed to provide a flat side surface of the display panel, the display panel comprising a side surface of the substrate and a side surface of each of the plurality of signal lines located in the same plane as the side surface of the substrate; depositing the plurality of side lines on the side surface of the display panel.

Embodiment 35. A method as in Embodiment 34, wherein depositing a plurality of side lines comprises depositing a plurality of side lines by pad printing conductive ink.

Embodiment 36. A method as in Embodiment 34 or 35, wherein removing at least a portion of the substrate comprises grinding a protruding portion of the substrate, optionally further comprises grinding the substrate outside the protruding portion, and optionally further comprises grinding a signal line.

Embodiment 37. The method of embodiment 34 or 35 further comprises removing the end of the substrate other than the protruding portion, and optionally further comprises removing the end of the signal line.

100: Display device

101: First substrate

102: Second substrate

110: Substrate

111: Buffer layer

112: Gate insulation layer

113: Interlayer insulation layer

114: Passivation layer

115a: first planarization layer

115b: Second planarization layer

115c: Third planarization layer

117: Reflective layer

118: Second adhesive layer

119: Embankment

121: First adhesive layer

140: Side line

150: Lateral insulating layer

ACT: Active layer

CE1: First electrode

CE2: Second electrode

DE: Drain electrode

DL2: Second data line

DL2-1: First layer

DL2-2: Second layer

DL2-3: The third layer

EL: Active layer

GE: Gate electrode

LED: light-emitting element

LS: Light blocking layer

NE:n-type electrode

NL:n-type layer

PAD: Upper pad

PAD1,PAD2: Upper pad

PE: p-type electrode

PL: p-type layer

SC: Storage capacitor

SC1: first capacitor electrode

SC2: Second capacitor electrode

SE: Source electrode

TR: Transistor

Claims (19)

A display device includes: a substrate, a plurality of light-emitting elements disposed on the substrate; a plurality of transistors disposed on the substrate; a plurality of signal lines disposed on the substrate; a plurality of connection lines disposed under the substrate; a plurality of upper pads disposed on the substrate; and a plurality of side lines disposed on a side surface of the substrate, wherein each of the upper pads overlaps with one of the signal lines and/or one of the transistors, and wherein each of the side lines provides at least a portion of an electrical connection between a corresponding one of the connection lines and a corresponding one of the signal lines. A display device as described in claim 1, wherein an edge of the display device includes a plane, and the substrate and the signal line terminate on the plane. A display device as described in claim 1, wherein the side lines are in contact with a side surface of the substrate and optionally with a lower surface of the substrate. The display device as described in claim 3 further includes: a plurality of lower pads disposed under the substrate, each of the lower pads overlapping with a corresponding one of the upper pads, wherein the side lines electrically connect the lower pads to: the upper pads; and/or the signal lines. The display device as described in claim 4 further includes a side insulating layer configured to cover the side lines, optionally wherein the side insulating layer includes a light blocking material, optionally including a black material. A display device as described in claim 5, wherein a portion of the side surface of the substrate is an inclined surface inclined relative to an upper surface of the substrate, and wherein the side lines partially cover the side surface and optionally cover the lower surface of the substrate. A display device as described in claim 6, wherein the substrate includes a first substrate and a second substrate located below the first substrate, and wherein at least a portion of a side surface of the second substrate forms at least a portion of the inclined surface. A display device as described in claim 1, wherein each of the side lines contacts: a corresponding one of the upper pads, and/or a corresponding one of the signal lines. A display device as described in claim 1, wherein each of the upper pads is electrically connected to a corresponding one of the signal lines, and/or wherein multiple side surfaces of the upper pads and multiple side surfaces of the signal lines are located in the same plane. The display device as described in claim 1 further includes a plurality of lower pads located on a lower surface of the substrate, each of the lower pads being electrically connected to a corresponding one of the connecting lines, wherein each of the lower pads overlaps with a corresponding one of the upper pads, and/or wherein a plurality of ends of the lower pads are disposed within an end of the substrate. The display device as described in claim 1 further includes multiple insulating layers, which are located on the substrate and arranged on the upper part or lower part of the upper pads and/or the upper part or lower part of the signal lines, wherein multiple side surfaces of the insulating layer are located in the same plane as a side surface of the substrate and/or the side surfaces of the upper pads. A display device as described in claim 1, wherein each of the light-emitting elements is a micro-light-emitting diode comprising an inorganic active layer, and/or wherein each of the light-emitting elements comprises: an n-type layer; an active layer located on the n-type layer; a p-type layer located on the active layer; an n-type electrode located on the n-type layer; and a p-type electrode located on the p-type layer, wherein the p-type electrode and the n-type electrode are arranged to be separated from each other at different height levels. The display device as described in claim 12 further includes: a first electrode connected to the n-type electrode; and a second electrode connected to the p-type electrode. The display device as described in claim 13 further includes: a first planarization layer; a second planarization layer located on the first planarization layer; and a third planarization layer located on the second planarization layer, wherein the first electrode and the second electrode are separated from each other, and the third planarization layer is arranged between the first electrode and the second electrode, optionally wherein the second planarization layer and the third planarization layer are in contact with each other in a region between the first electrode and the second electrode. The display device as described in claim 13 further includes a dam located on the first electrode and the second electrode, wherein the dam overlaps at least a portion of at least one of the upper pads, optionally wherein the dam includes a light blocking material, optionally wherein the light blocking material is a black material. The display device as described in claim 12 further includes a plurality of reflective layers respectively corresponding to each of the light-emitting elements, wherein the light-emitting elements overlap the reflective layers. The display device as described in claim 1 further includes an electrostatic discharge circuit, which is disposed on the substrate and is arranged to selectively connect the signal lines to a ground line, wherein the electrostatic discharge circuit is disposed in an area between the upper pads and a display area where a plurality of sub-pixels are disposed, or wherein the electrostatic discharge circuit overlaps the upper pads. A display device as described in claim 1, wherein each of the signal lines includes at least two overlapping signal line layers connected in parallel to each other, and optionally wherein the display device further includes an insulating layer disposed between each of a pair of adjacent signal line layers among the at least two overlapping signal line layers, wherein the insulating layer includes a plurality of through holes, and the through holes receive corresponding plurality of connection portions that electrically connect the pair of adjacent signal line layers. A display device as described in claim 1, wherein each of the signal lines is electrically connected in parallel to a corresponding upper pad, and optionally wherein the display device further includes an insulating layer disposed between the upper pad and the signal line, wherein the insulating layer includes a through hole, and the through hole receives a connection portion electrically connecting the signal line and the upper pad.